ECEG-4221 VLSI Design

Addis Ababa Institute of Technology (AAIT) Department of Electrical and Computer

Engineering

AAIT, School of Electrical and Nebyu Yonas & Henok Teklewold 1

Computer Engineering
 Learning Outcomes

 At the end of the lecture, students should be

able to know about:
 Testing Digital Circuit
 Test vector generation

2 Adopted from Iman Basha

AAIT, School of Electrical

and Computer Engineering
Introduction

Tests fall into three main categories

functionality tests or logic verification (Design level)
Debug tests (tests are run on the first batch of chips that return
from fabrication)
manufacturing tests (before shipping to the customer to verify)

AAIT, School of Electrical and Nebyu Yonas & Henok Teklewold

Computer Engineering 3
 Introduction


In manufacturing process faults may occur

Dust particles

imperfections in starting material

missing connections

The goal of a manufacturing test procedure is to
determine which die are good and should be shipped to customers


Generate a test vectors

AAIT, School of Electrical and Nebyu Yonas & Henok Teklewold

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Introduction
• Objective: Reduce the amount of input test patterns with
acceptable level of fault coverage for testing purpose.
• The input stimulus - test pattern.
• The response at ->normal output pins, or
->some internal nodes–not accessible to user
• Response of the device compared to an expected response
generated from known good device, or by simulation.
• Passing a test => does not contain faults which are tested for.
• 100% test, is rarely possible in real life systems.

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Computer Engineering
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Introduction…
• Assumption - logically, the system performs its desired function, and that
any faults occur due to electrical problems associated with one or more of
its component parts.
• During the design, ensure means to set or reset key nodes in the system,
that is, to control them and the ability to see clearly the effects of the test
patterns applied.
• Key concepts:
– Controllability - Being able to set up known internal states.
– Observability - Being able to observe the effects of a state change as it occurs
(preferably at the system primary outputs).

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Computer Engineering
Test time
• In VLSI circuits, high ratio of logic gates to pins.
• No way of directly accessing the internals of devices.
• “Exhaustive Testing”
• 2^N possible input patterns, for N no. of inputs.
• out of hand for large input devices, only for very small number of inputs.
• most of the test patterns are actually redundant.
• need a method to determine significant test patterns, to obtain a minimum set
of patterns.
• Assuming tester capable of applying a test pattern every 100ns:

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Computer Engineering
Methods
• Popular methods:
 Boolean Differences
 D-Algorithm
 Sensitised Path Method.

 Critical Path (L.A.S.A.R)

 P.O.D.E.M

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Computer Engineering
Fault Models
• A Fault Model is a description of the effects of some fault or
combination of faults in the underlying circuitry.
• Stuck –at faults:
– Represent the effect of faults by making on or more nodes stuck at
logic levels “0”, aka stuck-at-0, or “1 ”, aka stuck-at-1.

• Bridging Fault
– Complex Model(beyond the scope of this course)

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 D-Algorithm(formal)-Terminology

• Singular Cover
• D-intersection
• Primitive D-cube of a fault (pdcf)
• Propagation D-cubes (pdf)

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Singular Cover
SC of a gate (or any circuit element) is
nothing but a compact version of the truth
table.
Example: SC of a AND gate with a and b as
inputs and c as output
a b c
0 X 0
X 0 0
1 1 1
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Computer Engineering
Singular Cover (contd.)
SC of a NOR gate with a and b as inputs and
c as output
a b c
1 X 0
X 1 0
0 0 1

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Computer Engineering
D-Intersection

0 1 X D D'
0 0 D' 0  
1 D 1 1  
X 0 1 X D D'
D   D D *
D'   D' * D'
 Primitive D-Cube of Fault (pdcf)
For generating a s-a-0 fault at node c, choose
a SC row which gives an o/p of 1 for the nor
gate and intersect with (X,X,0).
pdcf is (0, 0, D)

a
b c

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Computer Engineering
PDCF (contd.)
For generating a s-a-1 fault at node c, choose
a SC row which gives an o/p of 0 for the nor
gate and intersect with (X,X,1).
pdcf is (1, X, D) or (X, 1, D)

a c
b

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Computer Engineering
Propagation D-Cube (pdc)
• PDC consists of a table for each circuit element
which has entries for propagating faults on any one
of its inputs to the output.

• To generate PDC entry corresponding to any one

column, D-intersect any two rows of SC which have
opposite values (0 and 1) in that column.

• There can be multiple rows for one column

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PDC Example
PDC of a AND gate with a and b as inputs
and c as output

a b c
1 D D
D 1 D

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PDC Example (contd.)
PDC of a NOR gate with a and b as inputs
and c as output

a b c
0 D D’
D 0 D’

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D-Algorithm Steps
• Choose a stuck-at-fault at any of the nodes.
• Choose a pdcf for generating the fault.
• Choose an output and a path to the output and
propagate the fault to the output by choosing pdc
for all circuit elements on the path. (D-Drive)
• Use the SC of all unassigned circuit elements to
arrive at a consistent set of inputs. (back-
propagate or consistency check)

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 D-Algorithm: PDCF Example
i
a
4
b f
1
c h

d g
e 2

Choose a fault say g s-a-0. Choose pdcf of

gate 2 for generating this fault
(a b c d e f g h i ) = (X X X 0 0 X D X X)
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D-Algorithm: D-Drive Example
Propagate the fault to the o/p using pdc of gates 3 &4

a i
4
b f
c 1
h

3
0 D g
d
e 0 2 pdc 3 (X X X 0 0 1 D D’ X)
pdc 4 (0 X X 0 0 1 D D’ D’)

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 D-Algorithm: Consistency Example
Perform consistency operation for gate 1

a i
4
b f
c 1
h

3
0 D g
d
e 0 2 (X X X 0 0 1 D D’ X)
(0 1 1 0 0 1 D D’ D’)
Ans. Test Vectors (0 1 1 0 0 )
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