ECEG-4221-VLSI - Lec - 05 - Ratioed, Pass and Dynamic CMOS Logic

ECEG-4221 VLSI Design
Addis Ababa Institute of Technology (AAIT) Department of Electrical and

Computer Engineering
Learning Outcomes
 At the end of the lecture, students should

be able to know about:
 Ratioed Logic.
 Pass transistor logic.
 Dynamic Logic.
Nebyu Yonas & Henok

2 Teklewold
AAIT, School of Electrical
and Computer Engineering
Ratioed Logic
Ratioed logic is an attempt to reduce the number of
transistors required to implement a given logic function, at the
cost of reduced robustness and extra power dissipation.
VDD VDD VDD
Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
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Ratioed Logic
This results in reduced noise margins and more

importantly static power dissipation.
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Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
depletion load NMOS pseudo-NMOS
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Pseudo-NMOS
VOH = VDD (Similar to complementary CMOS)
Smaller area & load but static power dissipation!!!!

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Pseudo-NMOS Inverter VTC
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Pseudo-NMOS Inverter
Performance
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Pseudo-NMOS: Example
The static power dissipation of pseudo-NMOS
limits its use. However, pseudo-NMOS still finds
use in large fan-in circuits.
NOR
When area is most important, the reduced transistor count
compared to complimentary CMOS is quite attractive. NAND
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Improved Loads(How to Build Even Better Loads)
It is possible to create a ratioed logic style that completely eliminates static currents
and provides rail-to-rail swing. Such a gate combines two concepts: differential
logic and positive feedback.
VDD VDD
M1 M2
Out Out
A
A PDN1 PDN2
B
B
VSS VSS
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL Example
AND and NAND
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DCVSL Example(5 marks)
Analyze which logical operations OUT a (OUT)’ implement
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DCVSL Circuits
• The resulting circuit exhibits (positive side)
 a rail-to-rail swing, and
 the static power dissipation is eliminated: in steady
state, none of the stacked pull-down networks and
load devices are simultaneously conducting.
• The circuit
 Still ratioed
 increase complexity in design, this circuit style still
has a power-dissipation problem that is due to cross-
over currents.
 During the transition, there is a period of time when
PMOS and PDN are turned on simultaneously,
producing a short circuit path.
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DCVSL Circuits
• The DCVSL gate provides differential (or
complementary) outputs
 Both the output signal (Vout1) and its inverted value
(Vout2) are simultaneously available. (This is a distinct
advantage, as it eliminates the need for an extra inverter to
produce the complementary signal)
 For complex function may reduce the number of

gates required by a factor of two!
 the inverted signal is delayed with respect to the original

This causes timing problems, especially in very high-
speed designs. The differential output capability avoids
this problem
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Why not always DCVSL Circuits
• the differential nature virtually doubles the number of
wires that has to be routed, leading very often to
unwieldy designs. And
• the dynamic power dissipation is high.
Lets try another option

Pass-Transistor Logic !!
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Pass-Transistor Logic
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Pass-Transistor Logic
A popular and widely-used alternative to complementary CMOS is pass

transistor logic, which attempts to reduce the number of transistors
required to implement logic by allowing the primary inputs to drive gate
terminals as well as source/drain terminals.
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Example: AND Gate
B Fewer transistors are required
to implement a given function.
A
B
F = AB
0
B’ is essential to ensure that the gate is static, this is that a
low-impedance path exists to the supply rails under all
circumstances.
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Differential Pass Transistor Logic
 The basic idea (similar to DCVSL) is to accept
true and complementary inputs and produce true
and complementary outputs.
Example: Complementary pass Transistor Logic(CPL)
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NMOS-Only Logic
3.0
In
In
1.5 m/0.25 m Out
2.0
Voltage [V]
VDD x x
Out
0.5  m/0.25 m
0.5 m/0.25 m 1.0
0.0
0 0.5 1 1.5 2
Time [ns]
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NMOS-only Switch
C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1
VB does not pull up to 2.5V, but 2.5V - VTN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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Differential Pass Transistor Logic
 Unfortunately, differential pass-transistor logic,
like single-ended pass-transistor logic, suffers
from static power dissipation and reduced noise
margins, since the high input to the signal-
restoring inverter only charges up to VDD-VTn.
 There are several solutions proposed to deal with
this problem as outlined below
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NMOS Only Logic: Solution-
1(Level Restoring Transistor)
VDD
VDD
Level Restorer
Mr
B
M2
X
A Mn Out
M1
• Advantage: Full Swing

• Eliminates static power dissipation
• Ratio problem
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Restorer Sizing
3.0
2.0 • Upper limit on restorer size

Voltage [V]
W/Lr =1.75/0.25
• Pass-transistor pull-down can
W/L r =1.50/0.25
have several transistors in
1.0 stack
W/Lr =1.0/0.25 W/L r =1.25/0.25
0.0
0 100 200 300 400 500
Time [ps]
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Another Solution: Transmission
Gate
The most widely-used solution to deal with the voltage-drop problem is the
use of transmission gates.
The transmission gate combines the best of both device flavors by placing
a NMOS device in parallel with a PMOS device
C
C
A B A B
C
C C = 2.5 V
A = 2.5 V
B
CL
C=0V
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Transmission Gate
Transmission gate enables rail to rail switching.
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Transmission gate Example:
Inverting Multiplexer
• Transmission gates can be used to build some complex
gates very efficiently.
VDD
S
A
M2
S F
M1
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Delay in Transmission Gate
Networks
2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req

In
C CC C C CC C
(c)
The most common approach for dealing with the long delay is to break the chain
and by inserting buffers every m switches
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Delay Optimization
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CAUTION:
• Although many of the circuit styles discussed in the
previous sections sound very exciting, and might be
superior to static CMOS in many respects,
• none of them has the robustness and ease of design of
complementary CMOS. Therefore, use them sparingly and
with caution.
• For designs that have no extreme area, complexity, or
speed constraints, complementary CMOS is the
recommended design style.
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Quiz
Analyze which logical operations OUT implement, Hint: It is
one of the basic derived logic gate!
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Home Work
Analyze this circuit.
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Dynamic CMOS
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Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to either
GND or VDD via a low resistance path.
 Fan-in of n requires 2n (n N-type + n P-type)
devices.
 Dynamic circuits rely on the temporary storage of
signal values on the capacitance of high
impedance nodes.
 Requires on n + 2 (n+1 N-type + 1 P-type)
transistors.
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Dynamic Gate
It got two phases precharge and conditional evaluation phases.
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on
Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
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Conditions on Output
 Once the output of a dynamic gate is discharged,
it cannot be charged again until the next
precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.
 Output can be in the high impedance state during
and after evaluation (PDN off), state is stored on
CL.
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Properties of Dynamic Gates
 Logic function is implemented by the PDN only
 Number of transistors is N + 2 (versus 2N for static
complementary CMOS)
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect the logic
levels
 Faster switching speeds
 Reduced load capacitance due to lower input capacitance
(Cin)
 Reduced load capacitance due to smaller output loading
(Cout)
 No I , so all the current provided by PDN goes into
sc
discharging CL Nebyu Yonas & Henok
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Properties of Dynamic Gates
 Overall power dissipation usually higher than static
CMOS.
 No static current path ever exists between VDD and GND
(including Psc).
 No glitching (Dynamic hazard).
 Higher transition probabilities.
 Extra load on Clk.
 PDN starts to work as soon as the input signals
exceed VTn, so Set VM, VIH and VIL equal to VTn
 low noise margin (NML).
 Needs a precharge/evaluate clock.
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Issues in Dynamic Design 1:
Charge Leakage
CLK
VOut Evaluate
Precharge
Dominant component is subthreshold current

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Solution to Charge Leakage
During precharge, Out is VDD and inverter
out is GND, so keeper is on
Keeper
During evaluation if PDN is off, the keeper
compensates for drained charge due to Clk Mp Mkp
leakage.(by reducing the output impedance)
A Out
If PDN is on, there is a fight between the CL
PDN and the PUN - circuit is ratioed so PDN
B
wins, eventually
Note Psc during switching period when PDN Clk Me

and keeper are both on simultaneously
(Soln,the bleeder resistance is made high,
or, in other words, the device is kept small.)
Same approach as level restorer for pass-transistor logic

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40 Teklewold
Issues in Dynamic Design 2:
Charge Sharing
CA initially discharged
Clk Mp and CL fully charged.
Out
A CL
Charge stored originally
B=0 CA on CL is redistributed
Clk Me CB
(shared) over CL and CA
leading to reduced
robustness
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Solution to Charge Redistribution
Clk Mp Mkp Clk

Out
A
Clk Me
Precharge internal nodes using a clock-driven

transistor (at the cost of increased area and power)
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Issues in Dynamic Design 3: Clock
Feed Through
Coupling between Out and Clk input
Clk Mp of the precharge device due to the
Out gate to drain capacitance.
A CL
B So voltage of Out can rise above

VDD.
Clk Me
The fast rising (and falling edges) of
the clock couple to Out.
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Clock Feed Through
Clock feed through
Clk 2.5
Out
In1
1.5
Voltage
In2
In &
In3 0.5 Clk
Out
In4
-0.5
Clk
0 0.5 1
Time, ns
Clock feed through
More noise is generated as
a result of clock coupling
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Other Effects
 Capacitive coupling, Back gate coupling

 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)
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Cascading Dynamic Gates
Straightforward cascading of dynamic gates to create more complex
structures does not work!!!
V
Clk Mp
Clk Mp Clk
Out2
Out1
In
In
Clk Me Clk Me
VTn
Out1
V
Out2
t
Only 0  1 transitions allowed at inputs!
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Domino Logic
Domino logic module consists of an n-type dynamic logic block
followed by a static inverter.
Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5
Clk Me Clk Me
The introduction of the static inverter has the additional advantage that the fan-
out of the gate is driven by a static inverter with a low impedance output, which
increases noise immunity. The buffer furthermore reduces the capacitance of
the dynamic output node by separating internal and load capacitances.
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Why Domino?
During evaluation, the output of the first Domino block either stays at 0
or makes a 0 to 1 transition, affecting the second gate.
Change ripple through the whole chain, one after the other, similar to a
line of falling dominoes—hence the name Domino!
Clk
Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk
Like falling dominos!

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Properties of Domino Logic
 Only non-inverting logic can be implemented

 Very high speed
 Static inverter can be skewed, only L-H transition
 Input capacitance reduced – smaller logical effort.
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Domino Logic Design
To design using Domino-style
we need to create schematic that
uses non-inverting gates:
(1) look for CMOS gates followed by
inverter
(2) use Demorgan’s Law to create non-
inv gates
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Domino Logic Design (Cont’d)
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Designing with Domino Logic
VDD VDD
VDD
Clk Mp Clk Mp Mr
Out1
Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!
Clk Me Clk Me
Inputs = 0
during precharge
However, eliminating the evaluation device extends the precharge cycle:
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Footless Domino
VDD VDD VDD
Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0
The first gate in the chain needs a foot switch

Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
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Differential (Dual Rail) Domino
off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B
Clk Me
Solves the problem of non-inverting logic

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np-CMOS
Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
Mp
(to PDN)
Clk Me Clk
Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN
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NORA Logic
Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
Mp
(to PDN)
Clk Me Clk
to other to other
PDN’s PUN’s
WARNING: Very sensitive to noise!

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What to do this week?
 Reading assignment
 Read about Sequential circuits.
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57 Teklewold

ECEG-4221-VLSI - Lec - 05 - Ratioed, Pass and Dynamic CMOS Logic

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ECEG-4221 VLSI Design

Addis Ababa Institute of Technology (AAIT) Department of Electrical and

 At the end of the lecture, students should

Nebyu Yonas & Henok

Resistive Depletion PMOS

VSS VSS VSS

Nebyu Yonas & Henok

This results in reduced noise margins and more

depletion load NMOS pseudo-NMOS

Nebyu Yonas & Henok

VOH = VDD (Similar to complementary CMOS)

Smaller area & load but static power dissipation!!!!

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

 For complex function may reduce the number of

 the inverted signal is delayed with respect to the original

Lets try another option

Nebyu Yonas & Henok

Nebyu Yonas & Henok

A popular and widely-used alternative to complementary CMOS is pass

Example: Complementary pass Transistor Logic(CPL)

Nebyu Yonas & Henok

Nebyu Yonas & Henok

VB does not pull up to 2.5V, but 2.5V - VTN

Nebyu Yonas & Henok

Nebyu Yonas & Henok

• Advantage: Full Swing

2.0 • Upper limit on restorer size

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Req Req Req Req

Req Req Req Req Req Req

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Two phase operation

Nebyu Yonas & Henok

Dominant component is subthreshold current

Note Psc during switching period when PDN Clk Me

Same approach as level restorer for pass-transistor logic

Nebyu Yonas & Henok

Clk Mp Mkp Clk

Precharge internal nodes using a clock-driven

Nebyu Yonas & Henok

B So voltage of Out can rise above

Nebyu Yonas & Henok

 Capacitive coupling, Back gate coupling

Nebyu Yonas & Henok

Clk Mp Clk Mp Mkp

Ini PDN Ini PDN Ini PDN Ini PDN

Like falling dominos!

 Only non-inverting logic can be implemented

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Nebyu Yonas & Henok

Clk Mp Clk Mp Clk Mp

The first gate in the chain needs a foot switch