ECEG-4221 VLSI Design

Addis Ababa Institute of Technology (AAIT) Department of Electrical and

Computer Engineering
Learning Outcomes

 At the end of the lecture, students should

be able to know about:
 Sequential circuit design.

Nebyu Yonas & Henok

2 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK
Output not only depends upon the current values of the inputs,
but also upon preceding input values.

Nebyu Yonas & Henok

3 Teklewold
AAIT, School of Electrical
and Computer Engineering
Timing Definitions
CLK
t Register
tsu t hold D Q

D DATA CLK
STABLE t
tc q

Q DATA
STABLE t

 Set-up time - time before rising edge of clk that D

must be valid.
 Propagation delay - time for D to reach Q.
 Hold time - time D must be stable after rising edge of
clk. 4
Nebyu Yonas & Henok
Teklewold
AAIT, School of Electrical
and Computer Engineering
Maximum Clock Frequency

Also:
tcdreg + tcdlogic > thold

tcd: contamination delay =

T ≥ tclk-Q + tp,comb + tsetup minimum propagation delay

Clock period T, should be adjusted as given above for proper operation

of the sequential circuit.
Nebyu Yonas & Henok
5 Teklewold
AAIT, School of Electrical
and Computer Engineering
Naming Conventions
 In our text:
 a latch is level sensitive.

 a register is edge-triggered.

 There are many different naming

conventions
 For instance, many books call edge-

triggered elements flip-flops.

Nebyu Yonas & Henok

6 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Latches vs Registers
 Latches
 level sensitive circuit that passes inputs to Q when the
clock is high(or low) - transparent mode
 input sampled on the falling edge of the clock is held
stable at the output when clock is low(or high) - hold
mode
 Registers (edge-triggered)
 edge sensitive circuits that sample the inputs on a clock
transition
 positive edge-triggered: 0  1
 negative edge-triggered: 1  0
 built using latches (e.g., master-slave flip-flops)
Nebyu Yonas & Henok
7 Teklewold
AAIT, School of Electrical
and Computer Engineering
Latch vs. Register
 Latch stores data  Register stores data
when clock is high when clock edge rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q
Nebyu Yonas & Henok
8 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Latches
Positive Latch Negative Latch

In D Q Out In D Q Out
G G

CLK CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

Nebyu Yonas & Henok

9 Teklewold
AAIT, School of Electrical
and Computer Engineering
Positive Feedback: Bi-Stability
 Static memories use +ve
principle
feedback to create a bi-stable ckt Vi1 Vo1 = Vi2 Vo 2

Vo 2 = Vi 1

Nebyu Yonas & Henok

10 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Mux-Based Latches
Negative latch Positive latch
transparent when CLK= 0) (transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK CLK

Q  Clk  Q  Clk  D Q  Clk  Q  Clk  D

Nebyu Yonas & Henok
11 Teklewold
AAIT, School of Electrical
and Computer Engineering
Mux-Based Latch(Transistor level
implementation) CLK

CLK

CLK
 Similar functionality to SR-latch but advantage
that the sizing of the device
Nebyu Yonas & Henok
12 Teklewold
AAIT, School of Electrical
and Computer Engineering
(Positive Edge-Triggered) Register
 The most common approach for constructing an edge-
triggered register is to use a master-slave configuration
Slave
Master

0 Q D
1 QM
1
QM
D 0 Q

CLK
CLK

Two opposite latches trigger on edge Also called

master-slave latch pair
Nebyu Yonas & Henok
13 Teklewold
AAIT, School of Electrical
and Computer Engineering
Edge Triggered Register
Multiplexer-based latch pair(transistor level implementation )

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

Nebyu Yonas & Henok

14 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Storage Mechanisms
Static(+ve feedback)
• a cross-coupled inverter pair
produces a bi stable element
• a stored value remains valid as
long as the supply voltage is
applied to the circuit, hence the
name static.
CLK
Q
CLK
D
CLK
AAIT, School of Electrical
and Computer Engineering
Dynamic (charge-based)
• Charge stored on a capacitor can
be used to represent a logic signal.
The absence of charge denotes a 0,
while its presence stands for a
stored 1.
• A stored value can hence only be
kept for a limited amount of time,
typically in the range of
milliseconds.
CLK
D Q
CLK
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15 Teklewold
 Other Latches/Registers: C MOS(Clocked CMOS) Register 2

VDD VDD
• insensitive to
clock overlap M2 M6

CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7

M1 M5

Master Stage

• CLK = 0 (CLK’ = 1): The first tri-state driver is turned on, and the master stage acts
as an inverter sampling the inverted version of D on the internal node X. The master
stage is in the evaluation mode. Meanwhile, the slave section is in a high impedance
mode, or in a hold mode.
• Both transistors M7 and M8 are off, decoupling the output from the input. The output
Q retains its previous value stored on the output capacitor CL2
Nebyu Yonas & Henok
16 Teklewold
AAIT, School of Electrical
and Computer Engineering
 Pipelining

REG
REG a

REG

REG

REG
CLK log Out

REG
log Out

REG
CLK b CLK CLK CLK
REG

b CLK
CLK

CLK Pipelined
Reference

Pipelining is a technique to improve the resource utilization,

and increase the functional throughput.
Nebyu Yonas & Henok
17 Teklewold
AAIT, School of Electrical
and Computer Engineering
What to do this week?

 Reading assignment
 Read about ALU Design.

Nebyu Yonas & Henok

18 Teklewold
AAIT, School of Electrical
and Computer Engineering