VLSI Design : 2021-22

Lecture 11
Layout of Static CMOS Circuits

By Dr. Sanjay Vidhyadharan

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 Logical Effort

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 Logical Effort : Example
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort F = 45/8
Branching Effort B=3*2=6
Path Effort H = GBF = 125
3
Best Stage Effort ℎ= 𝐻=5
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22
In multiples of pinv (1)
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 Logical Effort : Example

• Work backward for sizes

y = 45 * (5/3) / 5 = 15 h = 5 = fg the gate effort
f = 5/g the gate effort
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3

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 Inverter Layout

VDD GND

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 Inverter Layout

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 Inverter Layout

VDD
VDD

M2
In Out

M1

Out
In

Inverter circuit

GND

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 Inverter Layout

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 Inverter Stick Diagram

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 Inverter Stick Diagram

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 Dual-Inverter Layout

Multi-Finger devices

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 2-Input NAND Layout

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 2-Input NAND Layout

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 2-Input NAND Layout

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 2-Input NOR Layout

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 2-Input NOR Stick Diagrams

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 4-Input NOR Stick Diagram

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 Euler Paths
See if you can “trace” transistor gates in same order, crossing each gate once, for N and P
networks independently Where “tracing” means path from source/drain of one to
source/drain of next Without “jumping” connections

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 Euler Paths

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 Euler Paths

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 Euler Paths

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 Area Estimation

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 Area Estimation

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 Area Estimation

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 Full Adder

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 Full Adder

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 Full Adder

𝐶𝑎𝑟𝑟𝑦 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵

𝑃𝑢𝑙𝑙 − 𝐷𝑜𝑤𝑛 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵

𝑃𝑢𝑙𝑙 − 𝑈𝑃 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴′ 𝐵′ + 𝐵′ 𝐶 ′ + 𝐶 ′ 𝐴′

= 𝐴′ 𝐵′ + 𝐶′(𝐴′ + 𝐵′ )

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 Full Adder

12 12 12

12 12

6 6

6 6 6

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 Thank you

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