M techThesisReport1

See discussions, stats, and author profiles for this publication at: https://www.researchgate.
net/publication/344808898
Design of LDO for Low Power Biomedical Applications
Thesis · October 2020
CITATIONS READS
0 1,010
1 author:
Rakesh Kumar Pothal

Indian Institute of Technology Gandhinagar
1 PUBLICATION 0 CITATIONS
SEE PROFILE
All content following this page was uploaded by Rakesh Kumar Pothal on 22 October 2020.
The user has requested enhancement of the downloaded file.

Design of LDO for Low Power Biomedical Applications
by
Rakesh Kumar Pothal
A dissertation submitted in partial fulfillment

of the requirements for the degree of
Master of Technology
in Electrical Engineering,
2020
Advisory Committee:
Prof. Nihar Ranjan Mohapatra (Supervisor)
Prof. Joycee Mekie (EE)
Prof. Sanjay Amrutiya (Mathematics)
CERTIFICATE
It is certified that the work contained in the thesis titled Design of LDO for Low Power
Biomedical Applications by RAKESH KUMAR POTHAL (18210107), has been
carried out under my supervision and that this work has not been submitted elsewhere
for a degree.
Imohapaomfg 2020 .
Prof. Nihar Ranjan Mohapatra (Supervisor)

Professor
Gandhinagar - 382355, India
©Rakesh Kumar Pothal
2020
D E D I C A T I O N
To my parents and those who inspired me
i
A C K N O W L E D G M E N T S
First of all, I sincerely thank my guide and advisor, Prof. Nihar Ran-
jan Mohapatra, for his valuable guidance and inputs throughout this
work.This work would not have been successful without his constant
support and motivation. His critical insightful suggestions and com-
ments have helped me to improve my understanding toward the topic.
I would also like to thank Neelam Surana for his insightful comments.
His advice on research inspired me to learn lot of new things. Again,
I would like to thank J Sujatha for her constant support throughout
the research. I am also grateful to my advisory committee for their
valuable insight into the problem.
I would like to thank my family for their immense love and support.
They have always encouraged me and put their trust in me and my
decisions. I thank all my colleagues for creating an excellent lab en-
vironment for research. A special thanks to Ravins Katiyar, Shubham
Jain, Piyush Dewangan and Shubham Patil for their support and use-
ful suggestions.
ii
TABLE OF CONTENTS
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Chapter
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Power Management ICs (PMICs) . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Role of PMICs . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Difference between PMICs and Power Electronics . . . . . . 5
1.1.3 Power Management of Smart Phone . . . . . . . . . . . . . . 5
1.2 Component of PMICs . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Low Dropout Regulator(LDO) . . . . . . . . . . . . . . . . . 6
1.3 Power Management and Transmission of Implantable Biomedical chip 7
1.3.1 Safety Considerations of Human Body . . . . . . . . . . . . 8
1.3.2 Block Diagram of Bio Implanted Chip . . . . . . . . . . . . . 9
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Basics of LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 LDO Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1 Pass Element . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Feedback Loop . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.4 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.5 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Working Principle of LDO . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Parameters of LDO Regulator . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.5 Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.6 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.7 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . 25
iii
2.4 Transient Response of LDO . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.1 Load Transient . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.2 Line Transient . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 Frequency Response of LDO . . . . . . . . . . . . . . . . . . . . . . 29
2.6 Compensation technique of LDO . . . . . . . . . . . . . . . . . . . . 31
2.6.1 Miller Compensation Technique . . . . . . . . . . . . . . . . 31
2.6.2 Buffer Technique . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 Capless LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7.1 Difference between Capacitor based and Capless LDO . . . . 33
3 Design of Low Power Biomedical LDO . . . . . . . . . . . . . . . . . . . . 34
3.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Selection of Components . . . . . . . . . . . . . . . . . . . . 35
3.2.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 Comparison of Techniques . . . . . . . . . . . . . . . . . . . . . . . 48
3.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Sources of Error in LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1 Error in Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 Mismatch in feedback resistor . . . . . . . . . . . . . . . . . . . . . 51
4.4 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.1 Offset cancellation . . . . . . . . . . . . . . . . . . . . . . . 51
5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
iv
LIST OF FIGURES
1.1 Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Power Electronic PCB Board (left) [14] and PMIC (right) [15] . . . . . . . 5
1.6 Exploded View of Samsung Galaxy S4 [16] . . . . . . . . . . . . . . . . . 5
1.7 Components of DC DC Switching Converter . . . . . . . . . . . . . . . . 6
1.8 Basic LDO Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.9 ECG Monitoring System by Wireless Power Transmission [17] . . . . . . 8
1.10 ECG Sensor Implanted Device . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Charge Pump based NMOS LDO (left) and PMOS based LDO (right) . . . 11
2.2 PMOS based LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Steps (a)(left), (b)(middle) and (c)(right) in LDO working . . . . . . . . . 13
2.4 Outpout Voltage vs. input voltage . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Analysis of Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 Small Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9 PMOS based LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.10 Typical LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.11 Negative Feedback of LDO . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.12 Calculating output impedance . . . . . . . . . . . . . . . . . . . . . . . . 19
2.13 PSRR in Low Frequency to Ultra-High Frequency Region . . . . . . . . . 21
2.14 PSRR in High Frequency Range . . . . . . . . . . . . . . . . . . . . . . . 22
2.15 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.16 Effect of COU T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17 Effect of RESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.18 LDO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
v
2.19 Equivalent Circuit of Cout . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.20 Time domain analysis for load transient response . . . . . . . . . . . . . . 26
2.21 Frequency Response of LDO . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.22 Pole Distribution of LDO without Cout . . . . . . . . . . . . . . . . . . . 31
2.23 Pole Distribution of LDO with Cout . . . . . . . . . . . . . . . . . . . . . 31
2.24 Pole Distribution of LDO with Buffer . . . . . . . . . . . . . . . . . . . . 32
3.1 Frequency and Signal Amplitude of Human Body . . . . . . . . . . . . . . 34

3.2 Power Transmission Efficiency in RF Link . . . . . . . . . . . . . . . . . 35
3.3 LDO Design process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4 Full transistor level diagram of telescopic based LDO . . . . . . . . . . . . 38
3.5 Load transient response of LDO . . . . . . . . . . . . . . . . . . . . . . . 39
3.6 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7 Line Regulation at full load . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8 Loop Gain at Full Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Loop Gain at No Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 PSRR at Full Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 PSRR at No Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Ripple Rejection at Full Load . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Ripple Rejection at No Load . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14 Block diagram of Buffer based LDO . . . . . . . . . . . . . . . . . . . . . 40
3.15 Full circuit diagram of Buffer based LDO . . . . . . . . . . . . . . . . . . 41
3.16 Load transient response of Buffer based LDO . . . . . . . . . . . . . . . . 41
3.17 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.21 PSRR at Full Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22 PSRR at No Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.24 Ripple Rejection at No Load . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.25 Block diagram of Current Amplifier based LDO . . . . . . . . . . . . . . 43
3.26 Vout undershoot vs. Cout . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.27 Pole Location when Auxiliary Loop is absent . . . . . . . . . . . . . . . . 44
3.28 Pole Location when Auxiliary Loop is present . . . . . . . . . . . . . . . . 45
3.29 Full circuit diagram of Current Amplifier based LDO . . . . . . . . . . . 45
vi
3.30 Load transient response of Current Amplifier based LDO . . . . . . . . . 46
3.31 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.35 PSRR at Full Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.36 PSRR at No Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.38 Temperature Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.39 Monte Carlo simulation of Load Transient . . . . . . . . . . . . . . . . . . 47
3.40 Process Corner Variation of Regulated Vout . . . . . . . . . . . . . . . . . 47
4.1 Mismatch in Feedback Resistor . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Output Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4 Offset cancellation in Comparator . . . . . . . . . . . . . . . . . . . . . . 53
vii
LIST OF ABBREVIATIONS
LDO Low Drop-out
PSRR Power Supply Rejection Ratio
SWRs Switching Regulators
PMICs Power Management Integrated Chips
SoC System on Chip
PCE Power Conversion Efficiency
RF Radio Frequency
SAR Specific Absorption Rate
BGR Band Gap Reference
ESR Effective Series Resistance
UGB Unit Gain Bandwidth
ECG Electrocardiography
EEG Electroencephalogram
EMG Electrocardiography
SCL Semiconductor Laboratory
PMOS P-Channel Metal Oxide Semiconductor
NMOS N-Channel Metal Oxide Semiconductor
viii
ABSTRACT
Low Drop Out (LDO) voltage regulator is a fantastic solution to provide a very
low ripple regulated power supply to the digital and analog blocks present in
System-on-Chips (SoCs). In this research work, we designed and analysed an
ultra-low-power (< 20µW ) LDO architecture for self-powered bio implanted
chips. This LDO receives the input power from the RF link and supplies the
regulated power to different blocks which are present on the chip. Also, we
simulated three designs, observed their responses and compared their perfor-
mance. We obtained 99.99% voltage accuracy, 99.99% current efficiency, 90%
power efficiency, and 100nW power dissipation. This work is done in SCL
180nm CMOS technology node. Finally, we discussed some sources of error
and how to minimise them which creates a venture for further studies.
Chapter 1
Introduction
The scaling down of MOS devices to nanometric dimensions results in various un-
desired impacts on both Physical and IC Design and especially on Analog IC Design.
The major issues being the Gate Tunneling Leakage Current (IGleak ) as transistors are
continuously shrinking, it can inject a low-frequency pole (fgate ) and deteriorate the
following:
• Stability of the system
• Transient Response Time (Tr )
• Variation of the Voltage ( V )
These are unwanted factors for any Analog ICs.

Over the preceding thirty years, the power management technology has become
more significant as compact cellular phones, tablets, laptops and wearable electronics
like watches, fitness trackers, smart jewelry, and implantable biomedical sensors have
become an element of our routine. These modern electronic devices accelerated the
improvement in:
• Battery usage lifetime
• Power-conversion efficiency (PCE)
• Lowering voltages
• Operating speed
• Operating lifespan
• Overall Performance
So, it is required to apprehend the comprehensive design of power management cir-

cuits. The Power Management IC (PMIC) design powers both low-voltage (LV) and
high-voltage (HV) devices. PMICs include linear regulators like Low Drop Out (LDO)
1
Chapter 1. Introduction
and non-linear regulators like switching regulators (SWRs) and switched-capacitor de-
sign. However, as compared to the non-linear, linear regulators are cheaper, less com-
plicated and less noisy.
This work aims to study the power management designs for an implantable biomed-
ical chip, which contains an LDO for power management. Moreover, the work is to
make the reader aware of the process trend and demand of today’s applications, as
listed in the List1 from the beginning.
1.1 Power Management ICs (PMICs)

We require efficient and reliable power delivering supply to operate any electronic
devices. Some devices require AC power, while some devices require DC power and
some devices even require both AC as well as DC power. So, according to the power
conversion, we can classify our Power Supply System as follows:
1. AC-DC / DC-AC converters (Rectifier and Inverter)
2. AC-AC converters (Transformer)
3. DC-DC converters (Voltage Regulator)
In this literature, we are mainly going to focus on the DC-DC converter (Voltage
Regulator).
1.1.1 Role of PMICs

The PMICs basically perform five tasks as classified below:
1. Power Conversion
2. Distribution
3. Control
4. Regulation
5. Monitoring and Reporting
1.1.1.1 Power Conversion
Our power source can be either a battery or a charger that provides an unregulated
supply voltage (as shown in Figure 1.1). Since we cannot feed this unregulated voltage
to the load directly, we require an optimal way/device to convert the power from source
2
to destination. A power converter circuit (Linear/Switching) converts this unregulated

supply voltage to regulated supply voltage. Now, this voltage can be safely fed to the
load.
There are several types of power converters available in the market, but it is essential
to use the correct type. Factors that need to be considered before-hand are- power
requirement, cost, efficiency and size.
Figure 1.1: Power Conversion
1.1.1.2 Distribution
When a system requires different voltage levels/rails (for e.g., 1V, 2V, 3V) cheaply
and with high efficiency, we can use Power Management Units. In Figure 1.2, a 3.7V
battery provides power to the Power Management Circuit. Now, our Power Manage-
ment Unit generates different voltage levels like 1.35V for Circuit A, 1.8V for Circuit
B and D, 2.8V for Circuit C and 2.5V for Circuit E.
Figure 1.2: Distribution
3
1.1.1.3 Control
Power Management Units introduce flexibility for controlling voltage, current, and
general performance (efficiency, and quiescent current) of the circuit.
1.1.1.4 Regulation
The tolerance towards the maximum and minimum value during operating condi-
tions is known as Regulation. It is an expected metric in operating conditions. As
shown in Figure 1.3, regulated output voltage settles down after some time. In any
design, one can see if settling time is in a bearable range or not. Similarly, voltage ac-
curacy (undershoot and overshoot) is also one of the most significant parameters during
operation.
Figure 1.3: Regulation
1.1.1.5 Monitoring/Reporting
Certain features and faults need to be monitored during operation and reported for
precautionary actions to be taken. If a system monitors and reports accurately, then one
can assess the faults and provide precise solutions. For e.g., in Figure 1.4, one can very
easily observe the battery life of electronic devices such as a cellular phone or a laptop
to decide whether to charge or not.
Figure 1.4: Monitoring
4
1.1.2 Difference between PMICs and Power Electronics

There are two approaches to generate regulated voltage sources. For high power
applications, one can opt for Power Electronics and for low power applications, PMICs
are relatively the better choice. In Power Electronics, discrete components are used
together on printed circuit boards (PCBs), which makes the system bulkier, whereas, in
PMICs, the entire circuitry is system on chip (SoC) in which everything is integrated
on a single chip.
Figure 1.5: Power Electronic PCB Board (left) [14] and PMIC (right) [15]
1.1.3 Power Management of Smart Phone

We can see in Figure 1.6 an internal structure of Samsung Galaxy S4. The PMICs
consist of DC-DC converter and LDO.
Figure 1.6: Exploded View of Samsung Galaxy S4 [16]
5
1.2 Component of PMICs

PMICs designed for DC Power applications mainly consist of a DC-DC Converter
and an LDO. The types and applications of DC-DC Converter are listed below:
1. DC-DC Converter
(a) Buck Converter (Step-Down)

(b) Boost Converter (Step-Up)
(c) Buck-Boost Converter (Step-Down and Step-Up)
2. LDO
1.2.1 DC-DC Converter

The DC-DC switching regulators are mainly used in PMICs due to their high effi-
ciency and high driving capacity. It consists of two switches and one low pass filter, as
shown in Figure 1.7.
Figure 1.7: Components of DC DC Switching Converter
1
fS =
TS
VOU T
D=
VIN
However, S1 and S2 are never switched ON simultaneously even for a brief time
period. Because if S1 and S2 are turned ON, then all the energy will flow from the input
to the ground, and huge amounts of power loss will occur.
1.2.2 Low Dropout Regulator(LDO)

Switching regulators (SWRs) convert the voltage through a non-linear switching
operation because of their large open-loop gain. Hence, they give output voltage with
ripples, whereas an LDO is a linear voltage regulator, i.e., it converts voltage through a
6
linear operation. As the output voltage has either little or no ripples, it provides a clean,
well-regulated output.
However, LDO regulators experience an intrinsic disadvantage, namely, poor PCE.
If the output voltage ratio to the input voltage is small, huge voltage stresses over the
Pass Transistor, causing notable power loss.
Hence, the LDO regulators are often employed in series combination with the SWRs
to overcome the undesired ripples. This process of overcoming the ripples created by
another more efficient regulator is known as post-regulation. It is a simple and efficient
power management module if the output voltage ratio to the input voltage and the open-
loop gain can remain large. The LDO regulator here is regarded as a voltage buffer as
it used for minimizing the voltage ripples at slightly decreased PCE.
Although the PCE is low, this regulator’s performance benefits include Iq and wide
bandwidth (BW), which results in a fast transient response. Also, LDO regulators are
extensively employed in compact electronic gadgets as they require very small areas
on-chip and printed circuit boards (PCBs). When one considers lesser area on-chip or
compactness on PCB or decreased discrete component expenses, an LDO regulator is
the only key that can afford all the metrics and a conversion function for regulated and
scaled-down voltages.
The block diagram of LDO is shown in Figure 1.8. The detailed discussion on the
LDO regulator will be done in forthcoming chapters.
Figure 1.8: Basic LDO Regulator
1.3 Power Management and Transmission of Implantable

Biomedical chip
Patient monitoring systems have a wide range of applications in hospitals, including
intensive care units. Once electronic equipment is connected to a communication net-
work, it creates a telemedicine system in which the patients can be monitored, and their
state can be controlled remotely, even over the Internet, thus indicating these instru-
ments’ portability. The multidisciplinary interaction between medicine and engineer-
ing, for e.g., microelectronics and biosensor materials, allows the development of di-
7
agnosing devices capable of monitoring and controlling pathogens and diseases. When
the entire device is placed or implanted, it becomes a lab-on-chip and point-of-care de-
vice. Since the implanted device becomes a component of biological data acquisition
system (biotelemetry), it must satisfy some essential constraints, such as reduced size,
low power consumption, and the possibility of being self-powered by an RF (Inductive)
link.
A typical self power biomedical implanted device (BID) is shown in Figure 1.9.
The system consists, basically, of a biological sensor, a transducer, the incorporated
electronics and signal processing units, and the RF link to establish a communication
with the central unit. Coupling the implanted device, the local wireless link, and a
communication network together results in a wireless biosensor network.
Figure 1.9: ECG Monitoring System by Wireless Power Transmission [17]
1.3.1 Safety Considerations of Human Body

For e.g., the user of an implantable ECG monitoring system is normally exposed
to RF radiation near the skin, and therefore, few safety measurements must be taken
into account. The main biohazards and risks are mainly due to the RF exposure and
the heating from the electromagnetic field distribution on biological tissues. [1] The
specific absorption rate (SAR) gives a quantitative measurement of both the electric
field and induced current density over the human tissue. The temperature variation over
time indicates the local heating factor.[1] Both relations are given by Equation 1.1 and
1.2.
|E|2
SAR = [W/Kg] (1.1)
⇢
dT SAR
= [ C/s] (1.2)
dt c
Here,
E = incident electric field intensity (RMS)
= conductivity
⇢ = human tissue mass density
8
c = the specific heat capacity

Based on Equations 1.1 and 1.2, a safe value for the power transferred by the RF link
can be calculated. In Figure 1.9, a full ECG sensor monitoring system can be seen.[1]
1.3.2 Block Diagram of Bio Implanted Chip

Implantable Biomedical chips typically consist of a heartbeat pulse microsensor
senses the pulse and convert it into an electrical signal, a signal conditioning circuit
that processes the signal, a transmitter, and finally, a linear voltage regulator (LDO)
which provides constant power to all the components.[1] An RF transmitter transmits
the power through the RF link. This signal is received and is converted into a DC signal
by a rectifier. The output of the rectifier feeds the linear regulator, which provides
constant operating voltage to all the elements with a very low ripple, as shown in Figure
1.10. The primary focus is to design this linear voltage regulator efficiently for this
purpose.[1]
Figure 1.10: ECG Sensor Implanted Device
1.4 Thesis Organization

Chapter 1 introduced the topic and some known facts to the readers. Chapter 2 re-
views about basic knowledge required while designing an LDO in which the structure,
working principle, crucial parameter, frequency response, and compensation schemes
are thoroughly discussed. In the end, a Capless and capacitor-based LDO is differen-
tiated. Chapter 3 discusses the extraction of specifications for low power biomedical
application and the design of the LDO in detail. Also, the simulation results are pro-
vided to arrive at the comparison, results, and discussion. Chapter 4 explains the sources
of error and ways to mitigate them. Chapter 5 provides insight into the whole work and
mentions the venture for future work.
9
Chapter 2
Basics of LDO
As we discussed in section 1.2.2, LDO is a linear regulator with low dropout voltage
(VIN -VOU T ). LDO is less expensive than switching regulators because of no discrete
components (Capless LDO) and smaller areas. Due to these reasons, LDO is the best
option to embed in the implantable biomedical chips to supply regulated power. [2]
2.1 LDO Structures

LDO mainly comprises of 5 blocks as listed below:
1. Pass Element
2. Error Amplifier
3. Feedback Loop
4. Reference voltage
5. Output Capacitor
2.1.1 Pass Element

The Pass Element supplies the regulated output voltage by taking the unregulated
input voltage. It comprises nothing but a transistor, either a current-driven Bipolar
Junction Transistor (BJT) or a voltage-driven Metal Oxide Semiconductor Field Effect
Transistor (MOSFET). BJT has advantages of large driving capacity due to larger cur-
rent gain, but it has two notable disadvantages: first, it requires high voltage across the
base-emitter junction (0.7V ) and base-collector junction to retain the BJT in the active
region. The second disadvantage is high Il eakage at the base terminal. So we use
MOSFET to avoid these two drawbacks, but it has a low driving capacity. LDO regula-
tors usually operate in saturation region as a voltage-controlled current source because
the channel has the smallest resistance and therefore dissipating less power. If the LDO
10
Chapter 2. Basics of LDO
regulator needs low dropout voltage and low Iq , then the PMOS is the most excellent
choice among the several configurations. However, the PMOS also has various draw-
backs. For example, it needs more area on-chip to counterbalance the lower mobility
µp than in the n-channel MOSFET (NMOS) µn . [2]
Moreover, the PMOS serves as a common source (CS) stage in an LDO regulator.
The Miller Effect amplifies the gate-to-drain capacitance (Cgd ) and the amplification
enhances the challenge of loop compensation. By contrast, the NMOS shown in Figure
2.1.1 serves as a Source Follower (SF) stage that acts as a buffer stage in an LDO
regulator. Thus, the compensation complexity of an NMOS based LDO is considerably
lower than that of a PMOS based LDO. Considering the dropout voltage of an NMOS,
a large voltage headroom equal to Vsd + Vgs is the crucial drawback, which is similar
to that in the BJT. While addressing a problem in commercial products, a charge pump
circuit can be used to decrease the dropout voltage, as shown in Figure 2.1.1. [2]
Figure 2.1: Charge Pump based NMOS LDO (left) and PMOS based LDO (right)
2.1.2 Error Amplifier

An Error Amplifier is used to compare the input signal with the feedback signal
from the output and generate an error signal to regulate the output voltage. [3] It has
two leading roles: first, it provides gain to maintain high voltage accuracy, and second,
it should be a high-speed amplifier to maintain transient response. [4]
2.1.3 Feedback Loop

A negative feedback system is used to regulate the output voltage, which consists
of two resistors. It is crucial to know that if the pass element is PMOS, we connect the
feedback signal to the positive terminal of the error amplifier and if the pass element is
NMOS, we connect the feedback signal to the negative terminal of the error amplifier
to achieve a negative feedback loop. [5]
11
2.1.4 Reference voltage

Reference voltage comes from Bandgap Reference (BGR) circuit, which is used to
maintain the output voltage constant. So any error or mismatch occurring in Vref is
directly depicted in output voltage. [1] Therefore, the design of a suitable BGR circuit
for LDO is essential. ✓ ◆
R1
VOU T = VREF ⇥ 1 + (2.1)
R2
2.1.5 Output Capacitor

In LDO, the output capacitor plays a very crucial role. It helps to maintain the
transient response as well as stability. The output and parasitic poles move whenever
load variation occurs. [6] So, it is not easy to maintain a stable system when the pole
moves with the load. It also helps to maintain PSRR high at high frequency.
2.2 Working Principle of LDO

The output voltage should always be stable concerning the load and supply varia-
tion. When the load is turned ON, the Pass Transistor’s gate voltage changes with the
help of a negative feedback loop, and the pass transistor should be able to supply load
current. [3], [2] Similarly, when the load is turned OFF, the pass transistor goes to the
cutoff (subthreshold) region and draws a very meager amount of current to maintain
regulated output voltage, as shown in Figure 2.3.
Initially, we biased the output voltage at position-1, as shown in Figure 2.3 (a) and
Figure 2.3 (b). Suddenly, the load current increases from IOU T1 to IOU T2 making the
output voltage change from position-1 to position-2 to provide load current (Vsd will
increase by decreasing Vd ) until the loop starts responding. Once the loop responds to
the output voltage, it reverts to position-3. There will be a slight decrease in the output
voltage due to the difference in bias current. This phenomenon is called load regulation.
[7]
Similarly, we maintain an initial output voltage at position-4, as shown in Figure
2.3 (a) and Figure 2.3 (c). When there is a sudden change in load current from IOU T2
to IOU T1 , the voltage will change from position-4 to position-5 to maintain the output
current change until the loop responds. [8] Once the loop responds, the output voltage
reverts to position-5 to position-6. Also, there is a little bit of difference in the output
voltage.
12
Figure 2.2: PMOS based LDO
Figure 2.3: Steps (a)(left), (b)(middle) and (c)(right) in LDO working
2.3 Parameters of LDO Regulator

There are some design specifications to evaluate the regulator performance in steady
state and transient state.
2.3.1 Dropout Voltage

It is the voltage drop across the Power Transistor. Vdrop is a crucial parameter to
maintain high efficiency and low power dissipation.
Vdrop = VIN VOU T (2.2)
If Vdrop is very less, then the Power Transistor operates as a switch which provides
very low loop gain and it is challenging to make regulated VOU T . Vdrop also depends on
maximum load current and on resistance of the Power Transistor.
Vdrop = Iload .RON (2.3)
13
Figure 2.4: Outpout Voltage vs. input voltage
2.3.2 Load Regulation

Load Regulation is the steady-state performance that defines the change in output
voltage to the change in output current.
VOU T
Load Regulation = (V /A) (2.4)
IOU T
2.3.2.1 Derivation of Load Regulation
Figure 2.5: Analysis of Load Regulation
By applying KCL at point X shown in Figure 2.5,
14
Vsd
IOU T + + gm Vsg = 0
rds ||(R1 + R2 )
(0 VOU T )
IOU T + + gm (0 AE VOU T ) = 0
rds ||(R1 + R2 )
VOU T
IOU T = + gm AE VOU T
rds ||(R1 + R2 )
VOU T
IOU T =
rds ||(R1 + R2 ) + gm AE
VOU T rds ||(R1 + R2 )
=
IOU T 1 + (rds ||(R1 + R2 ))gm AE
VOU T 1
) ⇡ (2.5)
IOU T g m AE
From Equation 2.5 we can observe that Load Regulation depends on Loop Gain
( AE ).
Figure 2.6: Load Regulation
2.3.3 Line Regulation

Line regulation is the ratio of the change in output voltage to the change in input
voltage.
VOU T
Line Regulation = (V /V ) (2.6)
VIN
15
2.3.3.1 Derivation of Line Regulation
Figure 2.7: Small Signal Analysis
VOU T
HIN =
VIN
VOU T
Href =
Vref
By applying Superposition Theorem,
VOU T = HIN VIN + HREF VREF
By applying KVL in loop 1 shown in Figure 2.7,
gm1 V1 rdsp VIN

VIN + gm1 V1 rdsp = Vo
rdsp
VIN
VIN + V1 (gm1 gm1 rdsp ) =Vo
rdsp
✓ ◆
1 rdsp
V1 (gm1 gm1 rdsp ) = Vo + VIN
rdsp
✓ ◆
Vo 1
V1 = + VIN
gm1 (1 rdsp ) gm1 rdsp
Vo VIN
V1 = +
gm1 (1 rdsp ) gm1 rdsp
By applying KVL in loop 2 shown in Figure 2.7,
16
( VOU T Vref )AE V1 VIN = 0
AE VOU T Vref AE V1 VIN = 0
Vref V1 VIN
VOU T = + +
AE AE
On substituting the value of V1 ,
✓ ◆
Vref 1 Vo VIN VIN
VOU T = + + +
AE gm1 (1 rdsp ) gm1 rdsp AE
VOU T Vref VIN (1 + gm1 rdsp )

VOU T + = +
AE gm1 rdsp AE gm1 rdsp
Assuming, AE gm1 rdsp >> 1 and (1 + gm1 rdsp ) ⇡ gm1 rdsp
Vref VIN
VOU T = +
AE
If offset is introduced in Error Amplifier,
Vref + VOS VIN

VOU T = +
AE
where VOS = Vof f set and = Feedback Factor
Vref VOS VIN

VOU T = + +
AE
Figure 2.8: Line Regulation
17
When offset and Reference Voltage Variation are neglected,
VOU T 1
) ⇡ (2.7)
VIN AE
From Equation 2.7 we can observe that if the Loop Gain ( AE ) is high, line Regu-
lation is good.
2.3.4 PSRR
PSRR refers to the power supply rejection ratio or ripple rejection ratio. The ratio
of input ripple to the output ripple is called PSRR (Equation 2.8). It is also frequency-
dependent. [8]
Figure 2.9: PMOS based LDO
✓ ◆
VINripple
P SRR = 20log (2.8)
VOU Tripple
2.3.4.1 Factors determining PSRR
While maintaining a constant difference in the voltages (VG and VS ), the output
voltage is free of ripple if the ripple on the gate voltage (VG ) of the Pass Transistor is
equal to the ripple on input side VIN (VINripple ). In this case, the Pass Transistor does
not pass any ripple current to the output due to the VINripple . [9]
The VINripple voltage is divided according to the ratio of the output impedance
(ZOU T ) of an LDO (i.e., low impedance with negative feedback and the output resis-
tance (rDS )) of the Pass Transistor. Hence, PSRR is calculated by this voltage division
18
ratio shown in Equation 2.9.

✓ ◆ ✓ ◆
(VIN )ripple ZOU T + rDS
P SRR = 20log = 20log (dB) (2.9)
(VOU T )ripple ZOU T
The LDO has a low output impedance (ZOU T ) because of the negative feedback
(ZOF B is described later). The gain of the Error Amplifier is a crucial factor in achieving
low output impedance. As the amplifier gain is dependent on the frequency, PSRR is
also dependent on frequency. The determination of PSRR of an LDO is discussed in
detail in the forthcoming sections. [10]
2.3.4.2 Reduction in ZOU T by negative feedback
The LDO uses voltage-voltage type of feedback (series-parallel feedback) to apply

the output voltage (VOU T ) to the input in order to maintain the output voltage regulated.
Additionally, the negative feedback also reduces the output impedance (ZOU T ). [3]
Figure 2.11: Negative Feedback of LDO
Figure 2.10: Typical LDO
The output resistance can be measured by giving a test signal (VT ) to the output, as
shown in Figure 2.12. The negative feedback decreases the output resistance (ROU T ) to
roughly A1 (where A is the gain of the Error Amplifier, and is the feedback factor).
[11], [2]
Figure 2.12: Calculating output impedance
19
When there is no feedback, output resistance of an LDO = ROU T With negative

feedback, output impedance of an LDO = ZOF B
On applying KCL in circuit given in Figure 2.12, we get,
VT ( AVT )
IT =
ROU T
VT (1 + A)
IT =
ROU T
VT ROU T
ZOF B = = (2.10)
IT 1+A
As the amplifier is in negative feedback, it has a large gain (A) of the order of 60dB
to 80dB, and the output impedance (ZOF B ) is negligibly small—less than a hundred-
thousandth of the inherent output resistance (ROU T ). Considering this, the measurement
of PSRR is given in Equation 2.11:
✓ ◆ ✓ ◆ ✓ ◆
(VIN )ripple ZOF B + rDS rDS
P SRR = 20log = 20log = 20log 1 + (dB)
(VOU T )ripple ZOF B ZOF B
(2.11)
From the Equation 2.11, it can be observed that an LDO provides high PSRR when
the output impedance (ZOF B ) is much smaller than the output resistance (rDS ) of the
Pass Transistor. Here the output impedance (ZOF B ) in the Equation 2.11 is a function
of the gain of the Error Amplifier of the LDO, which is dependent upon the frequency.
The gain reduces in the high-frequency region. Hence, the negative feedback has less
effect on reducing the output impedance (ZOF B ), causing PSRR to reduce accordingly.
The frequency dependence of PSRR is discussed in the forthcoming sections. [2], [3]
2.3.4.3 Frequency dependence of LDOs
It was already mentioned that the PSRR of the LDO is dependent on frequency.
Normally, the LDO provides a high PSRR in the low-frequency region, which gets
reduced in the high-frequency region, as shown in Figure 2.13. The PSRR of an LDO
can be broken down into three frequency regions: [2], [12], [13]
• Low-frequency region from DC to a few kHz (from now on, low-frequency re-
gion)
• High-frequency region from a few kHz to 100 kHz (from now on, high-frequency
region)
• Ultra-high-frequency region above 100 kHz (from now on, ultra-high-frequency

region)
20
Figure 2.13: PSRR in Low Frequency to Ultra-High Frequency Region
PSRR in low-frequency region (DC to Low frequency)
Figure 2.9 shows a simplified circuit diagram of an LDO, including an external

output capacitor (COU T ). As mentioned in Equation 2.9, the PSRR in the low-frequency
region is the VINripple divided by the ratio of the output impedance (ZOF B ) of an LDO
with negative feedback and the output resistance (rDS ) of the Pass Transistor (because
the gain of the Error Amplifier is constant at the low frequency):
✓ ◆ ✓ ◆
(VIN )ripple ZOU T + rDS
P SRR = 20log = 20log (dB) (2.12)
(VOU T )ripple ZOU T
Equation 2.12 consists of the following frequency-dependent parameters for which

low frequency is taken into account: Output impedance with negative feedback (ZOF B )
is given by Equation 2.13:
ZOU T
ZOF B = (2.13)
1+A
Output impedance without negative feedback (ZOU T ) is given by Equation 2.14:
✓ ◆
ZCO (R1 + R2 )
ZOU T = rDS ||ZCO ||(R1 + R2 ) = rDS || ⇡ rDS ||(R1 + R2 )
ZCO + (R1 + R2 )
(2.14)
The PSRR Equation 2.14 can be recalculated as shown below. The feedback resis-
tance (R1 + R2 ) can be neglected as it is very high than the output resistor for the Pass
Transistor (rDS ).
✓ ◆ ✓ ◆
(VIN )ripple ZOF B + rDS
P SRR = 20log = 20log (dB)
(VOU T )ripple ZOF B
ZOU T
! rDS ||(R1 +R2 )
!
1+A
+ rDS 1+A
+ rDS
P SRR = 20log ZOU T
= 20log rDS ||(R1 +R2 )
(dB)
1+A 1+A
21
rDS
!
1+A
+ rDS
P SRR ⇡ 20log rDS ⇡ 20logA (dB) (2.15)
1+A
Equation 2.15 indicates that the LDO exhibits very high PSRR in the low-frequency
region.
PSRR in high-frequency region (Low frequency to about 100 kHz)
The Error Amplifier gain that determines the output impedance (ZOF B ) of the LDO
is dependent on frequency in the high-frequency region. Therefore, ZOF B reduces with
the frequency. Hence, PSRR reduces as the gain reduces, as shown in Figure 2.13. The
high-frequency region PSRR is described as: [13]
Figure 2.15: Loop Gain

Figure 2.14: PSRR in High Frequency Range
Normally, the PSRR equation for the low-frequency region can be used at frequen-
cies near the boundary between the low- and high-frequency regions. At such frequen-
cies, the output capacitor (COU T ) has no significant effect on the PSRR. However, the
gain (A) of the Error Amplifier is now dependent on frequency. When this is taken into
account, the PSRR in the high-frequency region can be calculated as in Equation 2.16:
✓ ◆ ✓ ◆
(VIN )ripple ZOF B + rDS
(VOU T )ripple ZOF B
rDS
! 1
!
1+A
+ rDS A
+1
P SRR ⇡ 20log rDS ⇡ 20log 1 (dB)
1+A A
!
A
P SRR = 20log 1 + s (2.16)
1+ p
where, p is the cutoff frequency of the Error Amplifier, and s (=j!) is the Lapla-
cian operator. [2] As observed from this equation, PSRR decreases as frequency in-
22
creases. Subsequently, moving on to the measurement of PSRR at a frequency close to

the boundary with the ultra-high-frequency region shown in Figure 2.13.
Figure 2.15 shows the relationship between the open-loop and closed-loop gains of
an LDO.
According to the theory of the negative feedback, the cutoff frequency of the closed-
loop transfer function is A times that of the open-loop transfer function, that is, A !1 .
A !1 is assumed to be near the boundary with the ultra-high-frequency region. [13] The
PSRR can be calculated as in Equation 2.18 when the frequency of the input voltage
ripple is A !1 Hz
!
A
P SRR|s=A p = 20log 1 +
1 + Ap p
✓ ◆ ✓ ◆
A A
P SRR|s=A p = 20log 1 + ⇡ 20log +1
1+A A
P SRR|s=A p = 20log(1 + 1) = 6dB (2.17)
PSRR in ultra-high-frequency region (above about 100 kHz)
The impedance (ZCO ) of the output capacitor (COU T ) including the equivalent se-
ries resistance (ESR = RESR ) is dominant in the ultra-high-frequency region shown in
Figure 2.14. Therefore, PSRR can be calculated as in Equation 2.18:
✓ ◆ ✓ ◆
(VIN )ripple ZCO + rDS
(VOU T )ripple ZCO
1
!
sCOU T
+ RESR + rDS
P SRR = 20log 1 (dB) (2.18)
sCOU T
+ RESR
When the capacitive impedance of the output capacitor (COU T ) is larger than its
equivalent series resistance (RESR ), PSRR can be calculated as in Equation 2.19:
✓ ◆ ✓ ◆
(VOU T )ripple ZCO
1
!
sCOU T
+ rDS
P SRR = 20log 1 = 20log(1 + sCOU T rDS ) (dB) (2.19)
sCOU T
23
When the frequency exceeds to such a point at which the capacitive impedance of
the output capacitor (COU T ) becomes zero, PSRR is dominated by its equivalent series
resistance (RESR ). Hence, PSRR loses its dependency on frequency. [14]
✓ ◆ ✓ ◆
(VOU T )ripple ZCO
✓ ◆ ✓ ◆
RESR + rDS rDS
20log = 20log 1 + dB (2.20)
RESR RESR
Figure 2.19 shows the PSRR-vs-frequency curve over the frequency regions de-
scribed above.
Figure 2.17: Effect of RESR

Figure 2.16: Effect of COU T
2.3.5 Quiescent Current

It is the current when the load is turned off. It is a vital parameter to maintain power
efficiencies at higher values and reduce power transistor’s power dissipation. [13] There
is also a trade-off between quiescent current and transient response.
2.3.6 Efficiency
It is also a vital parameter for any circuit. In LDO, the efficiency depends on the
dropout voltage, current flow through feedback resistors (ground current) and the max-
imum load that can be driven. This can be calculated as in Equation 2.21
POU T
⌘=
PIN
VOU T ILoad
⌘=
VIN IIN
Since we know that,
IIN = ILoad + Iq
24
ILoad VOU T
⌘= (2.21)
VIN (ILoad + Iq )
2.3.7 Figure of Merit

This parameter can be used to measure the overall regulator performance, as shown
in Equation 2.22. This is also a vital parameter.
Tset Iq
F OM = (2.22)
Iout
2.4 Transient Response of LDO

Transient response means how the circuit behavior will change if we apply any
sudden change (load current or line voltage in our application). The transient response
can be used to test the dynamic performance of LDO regulators. This response can be
categorized into two types: [2]
• Load Transient
• Line Transient
2.4.1 Load Transient

It is defined as the variation of output voltage with respect to a sudden variation of
load current. If the output voltage variation is less and settle very fast, then it will be a
good transient response as shown in Figure 2.20. The performance of transient response
is determined by the bandwidth of the system and rise/fall time of the load. On achiev-
ing a larger system bandwidth and a faster transient response, one must compromise
with the stability of the system. So, in LDO, a trade-off occurs between stability and
transient response. For better transient response, we usually use a large output capacitor
with small RESR which is discussed in the subsequent section.
Figure 2.19: Equivalent Circuit of

Cout
Figure 2.18: LDO Block Diagram
25
Figure 2.20: Time domain analysis for load transient response
2.4.1.1 Calculation of VOU T Undershoot
When the load current increases all of a sudden in a very short time, the nega-
tive feedback loop cannot instantaneously track its change and thus does not affect the
reduction of the LDO’s output impedance (ZOU T ). Therefore, ZOU T is expressed in
Equation 2.23.
ZOU T = rds ||rF B ||ZLOAD (2.23)
The increase in load current is IOU T and the resulting change in the output voltage
is VOU T . When the load current increases by IOU T in such a short time that the
LDO’s negative feedback loop cannot instantaneously track its change. The resulting
output voltage sag ( (VOU T )M AX ) is basically expressed in Equation 2.24:
VOU T = (rDS ||rF B ||ZLOAD ). IOU T (2.24)
During this time, an Error Amplifier gives an error voltage directly proportional
to the output voltage sag. When the error voltage signal drives the Pass Transistor, it
accommodates the increased load current, causing the output voltage to stop reducing.
However, it takes some time for the Error Amplifier’s output voltage to change due to a
phase compensation internal capacitor and the Pass Transistor’s gate capacitance. This
slope of voltage is known as the slew rate of the Error Amplifier. [2], [3] An error
amplifier with a fast slew rate can cease the LDO’s output voltage from decreasing
before it sags by as much as ( VOU T )M AX . However, with a fast slew rate, if it takes a
long time for the Pass Transistor to accommodate the increased load current, the LDO’s
output voltage sags by ( VOU T )M AX . Hence, the ability of an LDO to respond to the
sudden load changes (load transient response) is crucial to maintain an output regulated
voltage.
2.4.1.2 Calculation of VOU T Overshoot
While the drain-source voltage (VDS ) of the PMOS pass device changes, the LDO’s
negative feedback loop begins tracking the load change. Hence, the gate-source volt-
26
age of the Pass Transistor decreases from VGS2 to VGS1 to accommodate the decreased
output current (IOU T1 ). Once the LDO’s output current equals IOU T1 , the output voltage
stops increasing, bringing VDS1 to VDS3 (that is slightly higher than VDS2 ) as shown in
in Figure 2.3 (c). In other words, the output voltage (VOU T ) returns almost to the initial
voltage position-6.
As is the case with a sudden load increase, an increase in an LDO’s output voltage
due to a sudden load decrease is determined by the output impedance (ZOU T ) and the
output current change ( IOU T ) during the inherent delay in which the negative feedback
loop cannot track IOU T . [10] Likewise, an LDO’s negative feedback loop causes a de-
lay dependent on an error amplifier’s slew rate, which lasts until the output current from
the PMOS pass device matches the decreased load current. When an LDO’s negative
feedback loop cannot track a fast load change, the resulting maximum output voltage
change is determined by a change in load current and the output impedance (ZOU T )
during the inherent delay the LDO’s negative feedback cannot track the load change.
Without an output capacitor (COU T ), an LDO generally has a large output impedance
(ZOU T ). Therefore, even a slight load change results in a considerable change in an
LDO’s output voltage, reaching even the GND or power supply voltage. Adding an
output capacitor (COU T ) is very useful in preventing this situation and thus improv-
ing the load transient response. [11] The next section describes the effect of an output
capacitor (COU T ) on improving load transient response.
2.4.1.3 Improvement of Load Transient
As described above, an LDO exhibits extremely poor load transient response with-
out an output capacitor (COU T ), causing its output voltage to vary considerably. This
is because the output voltage variation of an LDO is equal to a change in load current
multiplied by a large open-loop output impedance of the LDO. [2] Therefore, the out-
put voltage variation due to sudden load changes can be reduced by reducing its output
impedance. Adding an output capacitor (COU T ) to the output of an LDO is useful for
this purpose. This subsection describes the effect of an output capacitor (COU T ). Sup-
pose that the load current (IOU T ) increases suddenly, as shown in Figure 2.20. In the
previous section’s discussion, the increased load current is supplied only by the PMOS
pass device.
In contrast, when an output capacitor (COU T ) is connected to an LDO, the increased
load current is supplied from the output capacitor (COU T ) during the inherent delay
before the current through the PMOS pass device is adjusted through the LDO’s nega-
tive feedback loop. As a result, the output capacitor (COU T ) is discharged by the load
current. Therefore, the output voltage (VOU T ) sag is determined by the value of the out-
put capacitor (COU T ) and a change in load current. This is described in the following
27
paragraphs.
When an output capacitor (COU T ) is connected to an LDO, its output impedance
(ZOU T ) is expressed as:
ZOU T = rDS ||RF ||ZL ||ZCOU T (2.25)
where, ZCOU T is the impedance of the output capacitor, including its equivalent
series resistance (RESR ). Suppose that the load impedance and the feedback resistor
(RF) value in the LDO are higher than other impedances. The LDO’s output impedance
can then be expressed as follows by ignoring the load impedance and RF. (* s is the
Laplacian operator.)
⇣ ⌘ ⇣ ⌘
1 1
rDS sCOU T
+ RESR sCOU T
+ RESR
ZOU T = ⇣ ⌘= ⇣ ⌘ (2.26)
1 1
rDS + sCOU T
+ RESR 1+ sCOU T +RESR
/rDS
The output resistance (rDS ) of the PMOS pass device can also be ignored because
it is higher than the impedance of the output capacitor (COU T ) during the sudden load
change discussed here. When we neglect series resistance of the output capacitor is an
LDO, output impedance can be determined largely by the impedance (ZCOU T ) of the
output capacitor (COU T ):
1
ZOU T ⇡ = ZCOU T (2.27)
sCOU T
As described above, an LDO’s output voltage variation due to load changes is equal
to a change in load current multiplied by the LDO’s output impedance. Because CV =
IT (where, C is the capacitor value, V is the voltage across the capacitor, I is the current
flowing through the capacitor, and T is the period of time during which this current
flows), the LDO’s output voltage variation can be approximated as follows:
IOU T .T
VOU T = (2.28)
COU T
As described above, T is the sum of the time required for an error amplifier to
generate an error voltage signal according to its slew rate immediately after a change
in an LDO’s output voltage and the time required for the PMOS pass device to pass
an output current equal to the increased load current. In other words, T is the time
required for the negative feedback loop to begin tracking the output voltage change.
T is determined by the drive capability of the error amplifier, the capacitances on its
output (phase compensation capacitance and the gate capacitance of the PMOS pass
device), and the transconductance of the PMOS pass device. The above equation is
28
simplified to approximate the output voltage variation ( VOU T ) due to load changes. To
accurately calculate VOU T due to load changes, it is necessary to accurately determine
the transfer function of an LDO’s internal circuitry.
2.4.2 Line Transient

The Line transient response is also dynamic. When the input voltage rises from zero
to the maximum value, the output voltage should be stable after a particular time. Also,
when the line voltage suddenly jumps to another value such as 1.8V to 2V , then output
voltage must overshoot due to the sudden rise in output current. And whenever there is
a sudden decrease of line voltage, then output voltage should also dip suddenly due to
decreasing load current.
2.5 Frequency Response of LDO

Any circuit’s frequency response gives an idea of whether the circuit is stable or not
for the full operating range of frequencies. Frequency responses tell us the location of
pole and zero, phase margin, and gain margin. In the LDO, stability issue is the biggest
challenge; substantial research is going on for making LDO with excellent stability for
low and high load application.
The main issue of LDO is the output pole move with the load that creates difficulties
in stability. As shown in Figure 2.21, LDO circuit, it usually has two pole systems, one
is located at the output (P2 ), and the other is at the gate of the pass transistor (P1 ).
Figure 2.21: Frequency Response of LDO
29
⇣ ⌘
sCgd
A1 A2 1 gmp
Open Loop T ransf er F unction G(s) = ⇥ (2.29)
(1 + sro Cgp )(1 + sRo Co )
1 1
P1 = ⇡ (2.30)
(R1 ).(C1 + CGS + Apass CGD ) (R1 .(C1 + CGS ))
1 1
P2 = ⇣ ⌘⇡
(rDS ||(Rf 1 + Rf 2 )||RLOAD ) COU T +
Cgd (RDS ||(Rf 1 + Rf 2 ))Cout
gm rds
(2.31)
From this expression, we can conclude that P1 , as well as P2 , move concerning the
load variation. If the load is not connected, the pass transistor is in off state or generally
in the cut off region. At this time, the Rds of the pass transistor is about in k⌦, and
gain is less than 1. However, when the load is turned on, the pass transistor will go to
either saturation or linear region (if the load is light pass transistor go to saturation if
the load is heavy, it goes to the linear region of operation). P1 is dependent on pass
transistor gain, which usually varies in the range of 0 to 10 due to the load variation,
and it is further decreased if the load is heavy. However, P2 directly depends on Rds ,
which varies 1000 times (⌦tok⌦). So P2 varies drastically concerning the load. This
makes the system unstable.
To make the system stable, we keep our P1 in very high frequency and keep our
output pole (P2 ) below UGB. We put a large output capacitor to make the output pole
dominant, and this will be off-chip. To keep parasitic poles beyond UGB, we have used
some techniques. This is called compensation techniques, which we discussed in the
next section.
Pole Location without output capacitor
Let us briefly analyze the pole and zero location of the LDO circuit. Initially, ignore
the effect of Cgd . P1 and P2 are plotted in Figure 2.22. P1 is nearer to origin because the
pass transistor aspect ratio (W/L) is very high; hence it offers high Cgs , and also output
impedance of error amplifier is very high. These two parameters decided the location
of the P1 .
Now consider the effect of Cgd which further pushes the pole P1 towards origin and
pushes P2 towards high frequency. It also adds a right half plane zero ( gCmp gd
).
30
Figure 2.22: Pole Distribution of LDO without Cout
Pole Location with output capacitor
When we use a high value of the capacitor, the output pole moves towards the origin,
and it becomes dominant.
Figure 2.23: Pole Distribution of LDO with Cout
2.6 Compensation technique of LDO

Compensation mainly requires circuits where more than one pole is situated within
UGB. As we discussed LDO circuit having two movable poles, so we need a compen-
sation circuit.
2.6.1 Miller Compensation Technique

In this technique, we put a capacitor in between the pass transistor’s output and
gate, which can further push the one pole to high frequency and another pole to low
31
frequency. However, it adds RHS zero, which degrades our stability. We can add a
resistor and tune it to push the zero to the LHS plane.
2.6.2 Buffer Technique

In this technique, we add a buffer in between error amplifier and pass transistor. The
output impedance of the buffer is very low, and the input impedance is very high. By
putting a buffer, we can shift our parasitics pole(P1) to very high frequency. After that,
we put an output capacitor which makes the output pole to be dominant.
Figure 2.24: Pole Distribution of LDO with Buffer
2.7 Capless LDO

As we discussed, the LDO comprises a huge off-chip capacitor, which is the primary
headache for the SoC applications. So we can design LDO without an output capacitor
called “Capless LDO” which is very suitable for SoC application. We have to make our
parasitic pole(P1) become dominant and push the output pole to very high frequency.
In Capless LDO, we used miller compensation technique to make our parasitics pole to
be dominant. We can discuss details about Capless LDO in the next chapter.
32
2.7.1 Difference between Capacitor based and Capless LDO
Table 2.1: Difference between Capacitor based and Capless LDO

Characteristics Capacitor based LDO Capless LDO
Off chip capacitor On chip capacitor
Nature of Capacitor
(in µF range) (small value)
Dominant Pole Output Capacitor Gate Capacitor of Pass Transistor
Range of Load Restriction in Imax Restriction in Imin
Increase for good Slew Rate,
Increase only for good Slew provide better stability at very light loads
Iq
Rate and transient response and pushing output pole
to higher frequency
Variation of
Less More
Vout
Transient Response Excellent Poor
33
Chapter 3
Design of Low Power Biomedical LDO
The design of any analog circuit varies from one application to the other. Before de-
signing any circuit, the designer must know about the specifications thoroughly. Finding
out the detailed specification of an analog circuit is not an easy task, and it depends upon
many factors like applications and operating conditions, to name a few. This chapter
discusses the acquisition of the specifications and the implementation of an LDO for
low power implantable biomedical chips.
In the last 10+ years, it is experimentally found that in most of the implantable
biomedical devices, the average power consumption of the system is about 10 µW from
the battery. Even with this meager energy budget, bio-medical devices are observed to
be able to detect complex vital signals like EEG, ECG and EMG (shown in Figure 3.1),
with wide dynamic range (µV –mV ) covering a low-frequency band (< 10kHz).
Figure 3.1: Frequency and Signal Amplitude of Human Body
So batteries are not the right solution for the implantable biomedical chip. Such
small powers can be transmitted by RF link, and the implantable biomedical chips
nowadays receive this power and in-turn, regulate it. These chips are known as self-
powered implantable biomedical chips.
3.1 Specification
As already mentioned, finding out the proper specification for an application-specific
circuit is a difficult task. In the way mentioned in the forthcoming sections, the specifi-
34
Chapter 3. Design of Low Power Biomedical LDO
cations are found, and the LDO is designed for the implantable biomedical chips. It is
seen that within the power consumption of 10µW , vital signals such as ECG, EEG, and
EMG could be conveniently detected. So from this, the following metrics are set:
1. Maximum power consumption within 10µW initially, and
2. Frequency of operation to about 10Khz
As the implantable biomedical chips are self-powered, the power can be transmitted
using an inductive link, and the chip will receive this power. This power can be con-
verted into DC power by a rectifier and then can be fed to the LDO’s input. Here, the
total power transmission efficiency by the inductive link can be noted as in Figure 3.2.
From equation 3.1, it is observed that the total efficiency of the system depends on the
power of the conditioning block. So the LDO’s design must be highly efficient.
Figure 3.2: Power Transmission Efficiency in RF Link
⌘T otal = ⌘S ⇥ ⌘1 ⇥ ⌘T ⇥ ⌘2 ⇥ ⌘L (3.1)
⌘L mentioned in the Equation 3.1 is the LDO’s efficiency. So the efficiency is set to
be at least 90% to make the system reasonably efficient.
Finally, the main thing for implantable biomedical chips is that it is entirely a system
on chip. So it is established that the LDO must be Capless.
After gathering all these pieces of information, the design of the LDO is started.
3.2 Design Procedure

Now, LDO, which consumes low power at no load ( 10µW ), Capless (frequency
of operation = 10Khz), and highly power-efficient (⌘ 90%) is designed.
3.2.1 Selection of Components

Firstly, appropriate components like Error Amplifier, Pass Transistor, and On-chip
output capacitor are chosen.
35
Selection of Error Amplifier
As the design must consume low power, the Error Amplifier must be a Single-Stage
op-amp architecture like Telescopic or Folded-Cascode, but at the same time, a higher
swing is required when the pass transistor supplies current from no load to full load.
The choice of Error Amplifier is made through the Table 3.1:
Table 3.1: Various Architectures vs. Parameter Metrics

Output Power
Architecture Gain Speed Noise
Swing Dissipation
Telescopic $ $ * # #
Folded-Cascode $ $ " $ $
Two-Stage " * # $ #
Gain-Boosted " $ $ " $
*Highest, "High, $Medium and #Low
Initially, the Error Amplifier in Telescopic architecture is selected and designed. The
desired swing, which is able to drive the Pass Transistor from no load to full load, is
obtained. Then, the Single-Stage Differential Pair is picked, and the results are studied.
Later, the design with Two-Stage op-amp is chosen as the Error Amplifier. Every option
had its advantages and disadvantages. Comparison and tabulation are made later in the
chapter.
Selection of Pass transistor
There are two options for selecting a Pass Transistor i.e., either an NMOS or a
PMOS type. The NMOS Pass Transistors gave better PSRR but high dropout voltage.
The PMOS Pass Transistor had relatively low dropout voltage. However, the PMOS
Pass Transistor is chosen for the LDO as the primary concerns are lower power dis-
sipation and higher efficiency. Moreover, as the operating frequency is low for the
biomedical applications, so the Error Amplifier gain took care of PSRR.
Selection of On-chip Output Capacitor
Since the design is required to be Capless, a capacitor with capacitance as low as

the On-chip capacitor is selected because the chip area directly depends on the capacitor
value. However, at the same time, transient response and stability should not be ignored.
So initially, the On-chip capacitor value of 1pF is chosen.
3.2.2 Design
After obtaining the specifications and selecting the components, we proceeded to
the designing of LDO. We followed the steps shown in Figure 3.3.
36
Figure 3.3: LDO Design process
3.2.2.1 Design-1: Telescopic Error Amplifier based Capless LDO
A capless LDO in SCL 180nm for low power biomedical application having Vin =
1.8V , Power Consumption =  10µW , ⌘ 90%, on-chip capacitor= 1pF , PSRR
60dB at 10KHz is designed.
Vout Iout
P ower Ef f iciency = ⌘ = 100% (3.2)
Vin (Iout + Iq )
P ower Dissipated = PD = (Vin Vout )Iout (3.3)
From the Equations 3.2 and 3.3, the parameters are fixed as follows:
VDROP = 100mV
37
Iq = 10µA
IOU T = 100µA
As a designer, some design parameters like voltage accuracy, maximum voltage

change during transient (Vout undershoot and Vout overshoot) also needed to be picked.
Iout .T
Vout = (3.4)
Cout
where T is the complete time taken for the loop response.
V oltage Accuracy 99.9% (3.5)
Vout
LineRegulation =  0.1% (3.6)
Vin
From the line and load regulation, the required gain of the Error Amplifier is calculated
as in Equation 3.7:
Vout 1
= (3.7)
Vin AE
AE = 60dB
R1 and R2 decided the current through the Pass Transistor when the load is turned
off. Also they transfered Vref to Vout as shown in Equation 3.8.
✓ ◆
R1
VOU T = VREF ⇥ 1+ (3.8)
R2
Figure 3.4: Full transistor level diagram of telescopic based LDO
38
The Load Regulation is considered to be less than 0.1%. So,
Vout 1
⇡  0.1% (3.9)
Iout gm AEA
From Equation 3.9, the aspect ratio of the Pass Transistor is determined.
Simulation Results
Figure 3.5: Load transient response of LDO
Figure 3.6: Load Regulation Figure 3.7: Line Regulation at full load
Figure 3.8: Loop Gain at Full Load Figure 3.9: Loop Gain at No Load
39
Figure 3.10: PSRR at Full Load Figure 3.11: PSRR at No Load
Figure 3.12: Ripple Rejection at Full Load Figure 3.13: Ripple Rejection at No Load
Disadvantages
From the above observations, it is observed that the line regulation is not proper. A
change in the input voltage’s amplitude (Vin ) beyond 2V , introduced the chances of a
decrease in loop gain due to the Cascode architecture. Line regulation is directly pro-
portional to the loop gain, making the Telescopic architecture a tough choice. Moreover,
PSRR also depended on the loop gain.
3.2.2.2 Design-2: Buffer based LDO
A Single-Stage Error Amplifier (Cascode avoided) with a buffer for a better driving
of the pass transistor is chosen next.
Figure 3.14: Block diagram of Buffer based LDO
40
Figure 3.15: Full circuit diagram of Buffer based LDO
Simulation Results
Figure 3.16: Load transient response of Buffer based LDO
41
Figure 3.23: Ripple Rejection at Full Load Figure 3.24: Ripple Rejection at No Load
Disadvantages
The buffer is helping to drive the Pass Transistors. Additionally, the earlier difficulty
of line regulation is also avoided. However, for capless LDO, the dominant pole at the
Pass Transistor’s gate needed to be maintained. The usage of buffer in between the
Error Amplifier and the Pass Transistor pushed the dominant pole to the high frequency,
making the system less stable.
3.2.2.3 Design-3: Current Amplifier based LDO
In this design, a technique that helped to improve the transient response and stability
is introduced. An auxiliary loop that consisted of a Current Amplifier with a coupling
capacitor is brought in. The Current Amplifier’s output impedance is very high, and
input impedance is very low, which helped to improve the stability. Also, this auxiliary
loop helped in improving transient response.
42
Figure 3.25: Block diagram of Current Amplifier based LDO
Mathematical Analysis of Transient Response
Iload = IF + ID
As the output impedance of Current Amplifier is infinite, IF is neglected.
Iload = ID
Iload = gm Vg
Considering Current Bufferl,
Cg dVg
I CF =
dt
ICF dt
=
Cg
gm ICF dt
Iload =
CG
where ICF is the forward transient current.
gm CF dVout
Iload =
CG
gm CF Vout
Iload =
CG
43
gmp CG Iload
Vout = (3.10)
CF
In the Equation 3.10, we can conclude that if CF is high, then Vout undershoot is
low as shown in Figure ??. gm and CG are constant because (W/L) of Pass Transistor is
fixed.
Figure 3.26: Vout undershoot vs. Cout
Stability Analysis
Initially, Cout and CG are comparable at no load. At no load, Pass Transistor must
be in cutoff (subthreshold) region to provide very low ground current which reduces
power dissipation of the LDO.
P ower Dissipation = Vdrop ⇥ Iground
When Pass Transistor goes to cutoff region, then RDS of the Pass Transistor is com-
parable with the Error Amplifier’s resistance. Therefore, at light or no load, loop might
be suffering from stability issue.
Figure 3.27: Pole Location when Auxiliary Loop is absent
44
But by using this auxiliary loop of Current Amplifier whose output impedance is
very high, is able to push the pole (located at gate of the Pass Transistor) towards low
frequency. Also, input impedance of the Current Amplifier is very low which is able to
push output pole towards very high frequency as shown in Figure 3.28.
Figure 3.28: Pole Location when Auxiliary Loop is present
So, by splitting these two poles, system stability is achieved.
Figure 3.29: Full circuit diagram of Current Amplifier based LDO
45
Simulation Results
Figure 3.30: Load transient response of Current Amplifier based LDO
46
Figure 3.37: Ripple Rejection at Full Load Figure 3.38: Temperature Variation
Figure 3.39: Monte Carlo simulation of Load Transient
Figure 3.40: Process Corner Variation of Regulated Vout
47
3.3 Comparison of Techniques
Table 3.2: Comparison of all designs

Parameter Specification LDO with Telescopic EA Buffer Technique Current Amplifier Technique
T echnology CMOS 180nm CMOS 180nm CMOS 180nm CMOS 180nm
P ower Consumption(µW )
<10 13.5 19.8 19.8
(N o load)
Vdrop (mV ) <100 100 100 100
Vout (mV ) <100 188 110
Iq (µA) <10 7.5 11 11
Line Regulation <1(mV /V ) 32.3mV /V (upto2V ) 1.6mV /V 200µV /V
Load Regulation <1mV /mA 8.2mV /mA 34.6mV /mA 170µV /mA
Vin (V ) 1.8 1.8 1.8 1.8
Vout (V ) 1.7 1.7 1.7 1.7
Settling time(µs) 1.7µS 1.4µS
Cout (pF ) 500f F 1 1
P SRR(10KHz) 49.9dB 46dB 64dB
T emp Sensitivity(µV / C) 1.8 6.3 1.01
M aximum Load current(µA) 0 to 100 0 to 50 0 to 200
Ef f iciency >90% 89.5 82.8 90.01
3.4 Results and Discussion

In this research work, designing a low power capless LDO for low power im-
plantable biomedical chip is the central focus. Three different architectures of Capless
LDO are proposed.
Initially, the Error Amplifier is designed in the Telescopic architecture. However,
it had a limitation of line voltage variation. If the line voltage varied exceeding 2V (in
this work), we got an inferior line regulation due to drastic gain reduction. However,
it is the least power-consuming architecture, but performance parameters cannot be
compromised simultaneously. If the line voltage is fixed between 1.8V to 2V (for
this work), this architecture could have been suitable. However, power is transmitted
through the RF link in this self-powered application, so there is a chance to increase the
voltage level.
In the second design, the Telescopic architecture is avoided, and the power budget
is increased a little bit to satisfy the performance. Here, a Single-Stage Differential Pair
is used as the error amplifier with a buffer that increased the driving capacity. However,
the buffer had a very low output impedance and very high input impedance. So, upon
the usage of buffer between the Error Amplifier and the Pass Transistor, the pole at the
Pass Transistor’s Gate moved to the high frequency, and the output pole became dom-
inant. So, upon driving a heavy load (> 50µA) for this design, the output impedance
further reduced, and the output pole also moved to the high frequency comparable with
pole present in the Pass Transistor’s Gate. Therefore, it made our system unstable.
Finally, an architecture that consisted of an auxiliary loop is proposed. This loop
48
helped to improve both the transient response and stability without spending much
power. The auxiliary loop consisted a Current Amplifier (simple Common Gate struc-
ture) with a miller capacitor. The Current Amplifier’s output resistance is very high,
making the pole (at the Pass Transistor’s Gate) move toward the low frequency and
made it dominant. Simultaneously, the auxiliary loop responded to the sudden change
of load current and changed the gate voltage by charging the gate capacitor very fast.
When the steady-state occurred, the main loop took care of regulated output voltage.
This technique is the fittest among the three techniques and provided tremendous per-
formance. There is a little increase in power consumption as compared to the Telescopic
architecture; however, it is within the budget.
Also, we extracted all the three architectures’ results for a better understanding and
to provide a qualitative and quantitative comparison.
49
Chapter 4
Sources of Error in LDO
Every analog circuit faces some or the other error while designing for real-world
practical application. These errors prop up while doing the analog layout. Even though
the circuits are designed and laid out still, they may have shortcomings. These errors
may be minimized by designing the circuit carefully, but they can never be nullified.
Some of the errors are discussed in the forthcoming sections.
4.1 Error in Reference Voltage

While designing the LDO circuit, we used a reference voltage signal to compare it
with our output signal and generate the negative feedback error signal. This reference
signal is obtained from bandgap reference (BGR) circuits. BGR circuits provide con-
stant voltage even in varying temperatures. However, this circuit also is not ideal. It has
some error due to temperature variation, which is called curvature error.
Due to this error, output voltage gets affected directly as shown in Equation 4.1.
✓ ◆
R1
Vout = Vref ⇥ 1+ (4.1)
R2
So a good analog designer must design a good BGR before designing an LDO.
4.2 Loop Gain

The open-loop gain of an op-amp is not infinite, as it is not ideal. So, the inverting
terminal’s voltage is not exactly equal to the non-inverting terminal’s voltage. There-
fore, proper Vref at both the terminals of the error amplifier is not obtained, causing the
error.
50
Chapter 4. Sources of Error in LDO
4.3 Mismatch in feedback resistor

In an LDO, a feedback network is always used, which causes another source of
error due to the mismatch of the feedback resistor. For e.g., when R1 gets changed to
R1 ± R (shown in Figure 4.1), then Vout also gets changed as shown in Equation 4.2.
✓ ◆
R1 ± R
Vout = 1+ Vref (4.2)
R2
Figure 4.1: Mismatch in Feedback Resistor
To cancel this error, it is taken care that the resistor ratio remains constant and if it
is not achieved, then the resistor is trimmed.
4.4 Offset
Offset is a considerable problem for analog designers. If it is considerably high,
then it can change the whole circuit performance. If any offset is present in the error
amplifier in an LDO, then the regulated output is given by the Equation 4.3.
✓ ◆
R1
Vout = 1+ (Vref ± Vof f set ) (4.3)
R2
There are mainly three approaches to mitigate this error. They are discussed in the
forthcoming sections.
4.4.1 Offset cancellation

In order to cancel offset, we can use some techniques mentioned below:
51
• Trimming
• Chopping
• Auto zeroing
4.4.1.1 Trimming
In this technique, a resistor is added in the differential amplifier’s source terminal

to cancel the offset (shown in Figure 4.2). The polarity of the offset voltage decides the
location of the resistor. Then, the value of the resistance is calibrated to minimize the
offset. This technique is also called offset reduction by source degeneration.
Figure 4.2: Trimming
4.4.1.2 Chopping
In this technique, we swap the input and output polarity to cancel the offset main-
taining the feedback always at negative side (inverting terminal). For e.g., the op-amp
is connected in a unit gain negative feedback configuration in Figure 4.4.1.2 and ini-
tially let the offset be present in the positive side (non-inverting terminal). The output
obtained is Vref + V , and when we swap the Vref terminal, the output voltage then
obtained is Vref V . Upon taking the average of these two outputs, then the offset
gets canceled. In an LDO, a lesser offset ripple is always preferred. So it is required to
keep the chopping frequency higher than the LDO bandwidth.
52
Figure 4.3: Output Offset Voltage
4.4.1.3 Auto zeroing
In this technique, the offset sample is stored by the capacitor beforehand, and it
cancels the offset on the input side. For e.g., auto-zero technique for a comparator is
shown in Figure 4.4.1.3. During , the output is Vof f set and during bar the input is
compared with the Vof f set . In this way, Vof f set gets canceled subsequently.
Figure 4.4: Offset cancellation in Comparator
53
Chapter 5
Conclusion
This chapter concludes our work and provides a brief overview for future work.
5.1 Conclusion
In this research work, we learned about the PMICs and their components. Then
we focussed our work towards power management of bio implanted chips. We saw
that the LDO was an excellent and compatible solution for the purpose. Then, we
studied some critical parameters of LDO in detail for better understanding. We also
discussed the difference between capless LDO and capacitor-based LDO and how to
maintain stability without affecting the transient response. Then we proposed three
different architectures of LDO with the simulated result in SCL 180nm technology node
in Cadence Virtuoso HSpice model. In the first design, we took our error amplifier in
the telescopic architecture and then observed its drawbacks. To overcome those, we
developed a second design architecture, which was a simple differential pair with a
buffer. However, it also had some stability issues which restricted the value of the
maximum load. Finally, we designed an LDO architecture consisting of the current
amplifier, which solved the above two architecture’s drawbacks and gave us the desired
results. During the whole work, we came across many errors of LDO and learned how
to minimize it.
5.2 Future Scope

In this work, we designed the schematic of our low power biomedical application
based LDO. We can incorporate a BGR circuit for generating Vref . Also, by different
techniques, we can improve the LDO’s stability and the load transient. We can also
implement the layout of this LDO for the further fabrication process for practical use.
Moreover, the minimization of the discussed errors (errors in Vref , loop gain, feedback
resistor mismatch, offset) is possible at this stage by comparing with the post-layout
simulation result.
54
REFERENCES
[1] P. Crepaldi, T. Pimenta, R. Moreno, and E. Rodriguez, “A cmos linear power

supply for a wireless biomedical sensor,” in 2010 IEEE International Workshop
on Medical Measurements and Applications, 2010, pp. 97–101.
[2] K. Chen, Design of Low Dropout (LDO) Regulators, 2016, pp. 28–121.
[3] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-chip cmos

low-dropout voltage regulator,” IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 54, no. 9, pp. 1879–1890, 2007.
[4] S. Fan, Z. Xue, H. Lu, Y. Song, H. Li, and L. Geng, “Area-efficient on-chip dc–dc
converter with multiple-output for bio-medical applications,” IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 61, no. 11, pp. 3298–3308, 2014.
[5] P. Crepaldi, T. Pimenta, R. Moreno, and E. Rodriguez, “A cmos linear power

supply for a wireless biomedical sensor,” in 2010 IEEE International Workshop
on Medical Measurements and Applications, 2010, pp. 97–101.
[6] B. S. Rikan, H. Abbasizadeh, J.-H. Kang, and K.-Y. Lee, “A high current effi-
ciency cmos ldo regulator with low power consumption and small output voltage
variation,” , vol. 18, no. 1, pp. 37–44, 2014.
[7] S. K. Lau, P. K. Mok, and K. N. Leung, “A low-dropout regulator for soc with
q-reduction,” IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 658–664,
2007.
[8] M. Zargham and P. G. Gulak, “Fully-integrated, power-efficient regulator and

bandgap circuits for wireless-powered biomedical applications,” in 2012 IEEE
International Symposium on Circuits and Systems (ISCAS). IEEE, 2012, pp.
2873–2876.
[9] M. Ho and K. N. Leung, “Dynamic bias-current boosting technique for ultralow-

power low-dropout regulator in biomedical applications,” IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 58, no. 3, pp. 174–178, 2011.
[10] A. Bstract, “An output-capacitor-less low dropout (ldo) voltage regulator with su-
perior transient response,” 2016.
[11] G. Patounakis, Y. W. Li, and K. L. Shepard, “A fully integrated on-chip dc-dc

conversion and power management system,” IEEE Journal of Solid-State Circuits,
vol. 39, no. 3, pp. 443–451, 2004.
55
View publication stats

M techThesisReport1

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

M techThesisReport1

Uploaded by

Copyright:

Available Formats

See discussions, stats, and author profiles for this publication at: https://www.researchgate.

Design of LDO for Low Power Biomedical Applications

Thesis · October 2020

Rakesh Kumar Pothal

The user has requested enhancement of the downloaded file.

Rakesh Kumar Pothal

A dissertation submitted in partial fulfillment

Prof. Nihar Ranjan Mohapatra (Supervisor)

To my parents and those who inspired me

List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

1.1 Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Frequency and Signal Amplitude of Human Body . . . . . . . . . . . . . . 34

4.1 Mismatch in Feedback Resistor . . . . . . . . . . . . . . . . . . . . . . . 51

LDO Low Drop-out

PSRR Power Supply Rejection Ratio

SWRs Switching Regulators

PMICs Power Management Integrated Chips

SoC System on Chip

PCE Power Conversion Efficiency

SAR Specific Absorption Rate

BGR Band Gap Reference

ESR Effective Series Resistance

UGB Unit Gain Bandwidth

SCL Semiconductor Laboratory

PMOS P-Channel Metal Oxide Semiconductor

NMOS N-Channel Metal Oxide Semiconductor

• Stability of the system

• Transient Response Time (Tr )

• Variation of the Voltage ( V )

These are unwanted factors for any Analog ICs.

• Battery usage lifetime

• Power-conversion efficiency (PCE)

So, it is required to apprehend the comprehensive design of power management cir-

1.1 Power Management ICs (PMICs)

1. AC-DC / DC-AC converters (Rectifier and Inverter)

2. AC-AC converters (Transformer)

3. DC-DC converters (Voltage Regulator)

1.1.1 Role of PMICs

5. Monitoring and Reporting

1.1.1.1 Power Conversion

to destination. A power converter circuit (Linear/Switching) converts this unregulated

Figure 1.1: Power Conversion

Figure 1.2: Distribution

Figure 1.3: Regulation

Figure 1.4: Monitoring

1.1.2 Difference between PMICs and Power Electronics

1.1.3 Power Management of Smart Phone

Figure 1.6: Exploded View of Samsung Galaxy S4 [16]

1.2 Component of PMICs

(a) Buck Converter (Step-Down)

1.2.1 DC-DC Converter

Figure 1.7: Components of DC DC Switching Converter

1.2.2 Low Dropout Regulator(LDO)

Figure 1.8: Basic LDO Regulator

1.3 Power Management and Transmission of Implantable

Figure 1.9: ECG Monitoring System by Wireless Power Transmission [17]

1.3.1 Safety Considerations of Human Body

c = the specific heat capacity

1.3.2 Block Diagram of Bio Implanted Chip

Figure 1.10: ECG Sensor Implanted Device

1.4 Thesis Organization

2.1 LDO Structures

2.1.1 Pass Element