SERVICE MANUAL

8M29B CHASSIS

Design and specifications are subject to change without prior notice.

(Only Referrence)

Description:
SERVICE MANUAL 8M29B
MODEL. Brand Name: SKYWORTH
JOB NO.

Engineering Dept:

Artwork By: Date: 2011-5-23

SIZE:A5 Checked By:

Approved By:
Date:

Date:
Content-------------------------------------------------------------------------------2
Technical Specification-----------------------------------------------------------3-14
8M29 Block Diagram -------------------------------------------------------------15
List of key parts---------------------------------------------------------------------16
IC BLOCK Diagram----------------------------------------------------------------17-31
MAIN PCB-TOP--------------------------------------------------------------------32
MAIN PCB-BOT--------------------------------------------------------------------33
Circuit Diagrams--------------------------------------------------------------------34-42

-2-
LCD 8M29B chassis.

-3-
4.

105 For 32LED

140 For 42LED

Base on different order

5.

93 95 97
93 95 97
400 FOR 32LED
450 FOR 42LED

-4-
 For 42LED
For 42LED

9800 12500 12500(266, 276)

9800(280, 290)
6500(313, 329)

８
８

１０ １５

-5-
 24

40

40
3
2
1
4.2
50
0.5
80 12000
40
6

-6-
 1080 For 42LED
1920 For 42LED

40 uv
NO
YES
8
6
46 uv
46
NO

Standard
Standard
20

English Base on different order

No

Middle "Low" in some status

-7-
 4

-8-
 DTV-PRODUCTOINS SPECIFICATION
Model # 32"̚46"
Country( West Eu./East Eu./Russia/AP/US/S.A./Japan/
Brazil & Argentina
…)
Brand Skyworth/ODM
Category (Monitor/TV/Combo/Portable TV…) TV
Panel technology (LCD / PDP) LCD/LED
Market Position (High/Mid/Access,,,) Class
Cabinet Design (Example: 01,23 series ) K06/E60
Product Nb -
Chassis solution MSD309
Chassis name 8M29B

Chassis PCB Standard Skyworth RGB New Standard

Predecessor (replace) -
MP date requested (ETD) 2011.1
MP date confirmed by supplier (ETD/ETA) -
Status( Pre./Finish ) -
Regional requirement

Homologation (Gostandard/CE/MPTT/CB/…) CB

RoHS Yes
Power supply(100-240V AC +/-10%/...) 100-240V AC (-20%,+10%)
Power consumption working / Annual -
Power consumption standby <1W
Power plug(VDE/UL/BS/…) UCIEE/2pins
Picture display
Screen size : diagonale (inch) 32",42", 46"
Aspect ratio (16/9 // 4/3 // 15/9) 16:9
1st panel supplier : panel suppliers LG
1st panel supplier : panel reference
Panel Display Type(MVA/PVA/IPS/…) TFT LCD
1st panel supplier : resolution 32:1366x768ǃ42/46:1920x1080
Dynamic contrast ratio >10000˖1

Video signal process

Comb Filter (2D/3D) 3D
Noise Reduction (adaptative/3D/…) 3D
Picture improvement ( LTI/CTI,BLE,WLE,...) LTI/CTI
Color process (Gama correction/Skin correction /... ) Follow main IC

-9-
Colour preset (Cool/Normal/Warm/Personal) Medium, Cool, Warm and Personal in PC mode

Picture control ( Bright/Con./Sharpness/Color/Tint/…) Yes

Picture presets : Standard / Bright / Soft / User Standard / Mild / Film / Dynamic / Personal
Picture freeze Yes
Multi picture : PIP ( AV )/POP ˄AV˅ No
Dynamic Backlight Control No
LED Backlight Yes
Deinterlacer (No/linerar/motion adaptive/motion
3D motion adaptive
compensative)
Film mode / reverse 3:2/2:2 pull down Yes / Yes
Full HD support ( 1080P ) Yes
Single scan / Dual scan ( 120HZ ) 32:Single scan,42/46:Dual scan(only for LED)
Zoom type : 4/3 format Yes
Zoom type : 14/9 Zoom Yes
Zoom type : 16/9 Zoom 16/9 ZOOM 1
Zoom type : 16/9 Zoom up/down 16/9 ZOOM 2
Zoom type : Cinerama Yes
Zoom type : 16/9 Format Yes
Zoom type : Auto ( by SCART Pin8 and WSS ) Yes
Picture Auto adjustment (PC mode) Yes
3D Panel Type(PR / SG)
3D Mode
3D To 2D (Y/N)
2D To 3D (Y/N)
Left / Right Swap (For PR Panel)
Sound
Sound type ( Mono/AV stereo/Stereo ) stereo
Music Power (Watt)/RMS Power (Watt) 2 x 8W
Tone control ( Bass&Treble / Graphic Equalizer ) Bass&Treble
Special sound effect ( AVL / WIDE / Pseudo /… ) AVL
Suround system ( Dolby / VD / SRS / BBE / … ) Built-in Surround
Sound control ( Volume , Balance , Mute ) Volume, Balance, Mute
Sound presets (User/Speech/News/Standard) Standard / Music / Movie / Sport / Personal
Headphone volume control ( Separated / linked ) Yes(Linked)
Sound quality ( High / Mid / Low ) Mid
Reception and Decoding capability
RF range˄ATV˅ 54MHz̚864MHz
RF range˄DTV˅ VHF 177-213 MHZ, UHF 473-803 MHZ
Color System (PAL/SECAM/NTSC/PAL M,N ) PAL M,PAL N,NTSC M
Audio Standard ( B/G/H/D/K/K'/I/L/L' ) M,N
Stereo audio system ( Nicam,MTS,A2,….) BTSC,SAP
Video standard NTSC 3.58 / 4.43 (AV)/PAL 60 NTSC 3.58/4.43 , PAL

-10-
DTV SD support (DVB-T/S/C , ATSC , QAM , … ) ISDB-T
DTV HD Support MPEG2,MPEG4,H.264
MHEG5 No
HD capability with YPbPr Yes (720p; 1080i; 1080p@24/50/60Hz; 480i/p; 576i/p)
PC capability (up to maximum format) Up to 1280X1024 60Hz
HDMI capability ˄AV/PC Format) Up to 1080P 24/50/60HZ
Compatible video format if DVD/USB:
JPEG/MPEG2/MPEG4/H.264/DivX (depending on license)
DviX/VCD/SVCD/JPEG/AVI/MPEG2/WMV- HD/SD
Compatible audio format if DVD/USB:
MP3/WMA(depending on license)
MP3/WMA/AAC/MPEG1/…
Playable Discs (CD/CD-R(RW)/CD-ROM/DVD+R/+RW/-
No
R/-RW)
Card reader format compatibility No
Macrovision Yes
PVR Yes˄FOR USB˅
Network No
User convenience
OSD Language* English/Spanish/Portuguese/French
OSD Positioning No
OSD Transparency Adjust No
OSD Timeout Adjust No
Customer Brand name(LOGO) Yes
IB languages English
ATV Program Numbers (example: 99+3AV input ) 99+7AV
DTV Program Numbers 600
Program edit ( naming , sorting , skip , swap …. ) Naming / Skip / Swap
Auto Naming/Auto Sorting No
TV Guide(DTV EPG) EPG(next Seven-day)
Favorite program Yes
Number of buttons on cabinet (Power; Vol+/-; Pr+/-,
Vol+/-; Pr+/-, Menu ,Source,Power(optional)
Menu )
Main switch button (yes/No) Yes
CCD˄Closed Caption)/V-CHIP Yes/No
Text Standard: (Top, FLOF,,,) No
Teletext Level: 2.5 / 1.5 -
Pages for teletext -
Teletext character sets **** -
DVB-T teletext -
Real clock From DTV
Sleep timer 10-240 Min.
Timer Turn On / Off, Program Switch
Parent Control -Source and Channel lock (Input code for
Yes
certain channel)
Parent Control - Child lock (set the lock of the keyboard,
No
only the RCU can control the TV)

-11-
Parent Control - Kid pass (preset the ontime, channel for
No
each day of the week)
Parent Control - Channel lock (For digital transmission
Yes
and DVD program, to filter some programms)
Calendar / Games No
No program auto switch off 15 mins.
Hotel mode (Y/N) T.B.D
DVD player (No/slot/tray) No
Tuner FM (yes/No) No
software download(RS232/CI/USB/OAD) USB

Factory reset Yes˄in factory menu,reset the setting to shipment state )

Screen saver Yes

Blue Back No
LED indicator(Power on/Standby) Blue / Red
Connectors -Rear
RF Input (Antenna): Air/ Cable/ 2in1 Air+Cable
Scart : CVBS in&out / RGB / S-VIDEO No
CINCH video in / out˄AV1˅ No
CINCH audio in / out (No volumpe control on Audio
No
out/can be jack 3,5mm)
S-video in No
Component Video Input (YCrCb/YPrPb) No
Component Audio Input (YCrCb/YPrPb) No

VGA in / Audio L/R in / Jack audio in 3.5mm VGA + dia. 3.5mm for audio in

HDMI 2
DVI No
Audio input for DVI No
CINCH subwoofer out / Coaxial out (S/PDIF) No
Headphone output connector (mm) No
RS232 ( Y/N , VGA or DB9 port …) No
Card Readers No
1 (Software update, JPEG, MP3, WMA, RMVB, DivX) Multimedia
USB slot (No/1.1/2)
depends on license
DVB-CI (common interface) No
External power converter input No
Connectors -Side
HDMI 1

AV-IN 1

AV-OUT No

-12-
Component Video Input (YCrCb/YPrPb) 1
Component Audio Input (YCrCb/YPrPb) 1 with cable adapter
Headphone output connector (dia.mm) 1˄3.5mm)
CINCH subwoofer out / Coaxial out (S/PDIF) S/PDIF out ( optical ˅
1 (Software update, JPEG, MP3, WMA, RMVB, DivX) Multimedia
USB slot (No/1.1/2)
depends on license
DVB-CI (common interface) No
DLNA No
UI/RC
UI design (font/pixel, 2D/3D graphic engine..) SOD Standard
RC Model YK76B3 ( Toshiba )
RC system RGB Standard
RC # of keys
Accessories included
Carton (English/French/Spanish) English
IB English
Circuit diagram No
Batteries Yes
Product registration Card Yes˄English)
AC Cable Length 1.8m
Audio Cord (Jack 3.5mm) Yes(For component audio in)
VGA Cord No
Wallmount frame Optional
Antenna Cable No
6 in 1( YPbPr & CVBS) cable adapter No
3D Glasses No
General Data
Size (W x H x D, with stand) in mm -
Size (W x H x D, without stand) in mm -
Package Size (W x H x D, without stand) in mm -
Net Weight in kg -
Gross Weight in Kg -
Design / Mechanical
Wallmount VESA compatible (standard reference) Yes
Adaptor for VESA wallmount compatibility (accessory
Yes
ref)
Desktop Stand (included/optionnal + ref/No) included
Panel Tilt (Fowards/Backwards/Rotation) No
Swivel function desktop stand (yes/No) + motorized? No
Docking station (yes/No) No
Floor Stand (included/optionnal + ref/No) No
Glass shield (yes/No) No
Finish on Front -
Finish on side -
Finish on back -

-13-
Finish on stand -
number of colors on carton box 2
Brand logo Customer Inlet
Other logo No
External AC/DC Power with DC power cord (yes/No) No
Handle (yes/No) No
Detachable speaker (yes/No) No
Rating Label langages English

-14-
 SYSTEM
POWER SUPPLY

Uplayer1 KEY PAD, IR Receiver ,Ambient Sensor

Optional

PIXELWORKS 3D Processor FLASH

Motion Engine
PA131DG

HDMI1
DDRII
DVB-T&ATV MSD309PX-LF-SB
Demo d
PR DVB-T & IF Demo. Build in
MPEG1/2/4 /H.264 Decoder
PB JPEG MP3 Decoder R/L TPA3121
3D Comb filter Video Decoder
10W + 10W
Y
R
L DTV Toshiba TC90517

ATV
ISDB-T Demod
Video SAW P/S
IF (ATV) IF+/-

Rear Terminals

PC PC Audio S/PDIF
Uplayer2 HDMI2 HDMI3
Tuner

Side Terminals -15-

List of key parts

No. Name Position Type P/N

1 IR U29 HS0038B4 5300-140038-0010

Bass SL-R3018H-3E 5600-106154-0060

2 Speaker
Treble YDG3040-2 5600-708254-00

Y2 49U3H 4900-125453-R000
3 Crystal
Y1 HC-49U/S 4900-124053-R000

4 Tuner U10 VA1P1BF8405 5202-45733D-7H10

5 Saw U30 F4401 4900-744015-0X00
U3 MP1482DS 476A-M14820-0080
U5 MP1482DS 476A-M14820-0080

8 MP1482DS 476A-M14820-0080

8 MP1482DS 476A-M14820-0080

U9 W9751G6JB-25 4737-W97511-0840

U15 W9751G6JB-25 4737-W97511-0840

6
IC U24 EN25F32-100HIP 471R-N25321-0080
U55 TC90517FG 4701-T90510-0640
U37 AS1117L-3.3 47B6-A11170-03
U38 AS1117L-3.3 47B6-A11170-03
N1 AS1117L-3.3 47B6-A11170-03
N2 AS1117L-1.2 47B6-A11175-0300
U54 TPA3121D2PWPR 4722-T31210-0240
U2 MSD309PX-LF-Z1-SB 475C-M30900-5230

-16-
IC Block Diagram

Pin Configurations---AS1117L-3.3

L Package U Package
(SOT-223) (SOT-89)

3 INPUT INPUT
3
V OUT
2 OUTPUT V OUT
2 OUTPUT

1 ADJ/GND 1 ADJ/GND

T Package R Package
(TO-220) (TO-252)
3 INPUT

3 INPUT 2 OUTPUT
V OUT
V OUT 2 OUTPUT
1 ADJ/GND 1 ADJ/GND

S Package
(TO-263)

3 INPUT

V OUT 2 OUTPUT

1 ADJ/GND

-17-
IC Block Diagram

Pin Configurations---AS1117L-ADJ

L Package
(SOT-223)

3 INPUT

V OUT
2 OUTPUT

1 ADJ/GND

PIN ASSIGNMENT
The package of AX3113 is SOP-8L; the pin assignment is given by:
Name Description
FB Feedback pin
( Top View ) Power-off pin
HΚnormal operation(Step-down)
FB 1 8 Vss EN
LΚStep-down operation stopped
EN 2 7 Vss (All circuits deactivated)
AX3113
Ocset 3 6 SW Add an external resistor to set max
OCSET
Vcc 4 5 SW switch output current.
VCC IC power supply pin
SOP–8L
Switch pin. Connect external
SW
inductor & diode here.
VSS GND pin

-18-
IC Block Diagram

LM4558

MP1482DS

TOP VIEW

BS 1 8 SS
IN 2 7 EN

SW 3 6 COMP
GND 4 5 FB

-19-
IC Block Diagram

MST6M20S-LF

-20-
IC Block Diagram

.
W25X40BVSNIG
PWP (TSSOP) PACKAGE
(TOP VIEW)

PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR

PIN CONFIGURATION PAD CONFIGURATION

SOIC 150-MIL / 208-MIL WSON 6X5-MM

PIN CONFIGURATION
PDIP 300-MIL

-21-
IC Block Diagram

EN25F32
Figure.1 CONNECTION DIAGRAMS

8 - LEAD SOP / DIP 8 - CONTACT VDFN

16 - LEAD SOP

-22-
IC Block Diagram

EN25F32
Figure 2. BLOCK DIAGRAM

-23-
IC Block Diagram

EN25F32
SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle
is in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS#
must transition from high to low before a new instruction will be accepted.

Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.

Table 1. PIN Names

Symbol Pin Name

CLK Serial Clock Input

DI Serial Data Input

DO Serial Data Output

CS# Chip Enable

WP# Write Protect

HOLD# Hold Input

Vcc Supply Voltage (2.7-3.6V)

Vss Ground

-24-
 IC Block Diagram

CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]

2. Configuration

All functions required for ISDB-T demodulation and error correction are built into the TC90517.
The input signals to be supported are a low IF (intermediate frequency) signal and direct IF signal.
Baseband IQ signals can also be input.

The output signal is an MPEG-2 transport stream (TS) in serial format. Note that a TS in parallel format
can be output by setting registers.

IF input ADC Quadrature Interpolation ISIC (unguarded Frequency Pilot Adaptive

detection Filter phase interpolation
or IQ input AGC‡ ‡
preecho/postecho
suppression)
FFT CPE extraction
ADC AFC correction filter

AGC control output Tuner Synchroni FFT window CVI CSI Equalization
SW AGC Control (CW interference (reliability
zation control detection)
control detection)

External AGC input

AGC distortion signal
2 2
Tuner I C‡ ‡ IC Layer TMCC
2
Host I C control isolation demodulation

Frequency Demapping Viterbi Energy RS Error Synchroni-

Bit deinterleaving‡ ‡
Modulation division

Crystal Clock PLL CSI

Byte deinterleaving

deinterleaving decoding despreading decoding detection zation flag

(reference clock) processing
TS multiplex

Demapping Energy
Time CSI despreading Output
Memory processing control TS output
deinterleaving
Demapping Energy
CSI despreading
processing

Fig. 2.1 TC90517FG Block Diagram

-25-
IC Block Diagram

CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]

3. Pin Assignment (Top view)

-26-
IC Block Diagram

4. Pin Functions
This specification indicates pins and their signals in upper case letters and registers and their signals in lower case
letters.
(Note4) (Note5,7) (Note 3)
Pin Pin name Function Remarks(Note 2 and 6)
I/O PU/PD
1 TSMD0 I - Shut down 0: Normal operation 1: Shut down
2 XSEL1 I - Crystal frequency division ratio 1 Set according to crystal frequency.
3 XSEL0 I - Crystal frequency division ratio 0 Set according to crystal frequency.
4 VSS - - Digital GND Connects to DGND.
5 SLADRS1 I/O - Slave address 1 Set according to slave address.
6 SLADRS0 I/O - Slave address 0 Set according to slave address.
7 AGCI I - External AGC input Connects to DGND when not used.
8 S_INFO I - Pin for pre-shipment test Connects to DGND.
9 AGCCNTI I/O PD IF_AGC control output Connects to tuner IF_AGC control input pin.
Connects to tuner RF_AGC control input pin.
10 AGCCNTR I/O PD RF_AGC control output
Open, fixed to L when not used.
11 CKI I - Pin for pre-shipment test Connects to DGND.
Connects to tuner I2C clock pin.
12 TNSCL I/O OD I2C clock output
(Pull-up performed outside IC.)
13 VDDS - - I/O power supply Connects to digital +3.3 V typ.
Connects to tuner I2C data pin.
14 TNSDA I/O OD I2C data I/O
(Pull-up performed outside IC.)
15 VSS - - Digital GND Connects to DGND.
16 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
17 PLLVSS - - Clock PLL GND Connects to AGND.
Connects to crystal.
18 XO O - Crystal output ixosl="1" and open when an external reference clock
is input.
Connects to crystal.
19 XI I - Crystal or reference clock input The amplitude (p-p) is 0.5 V to PLLVDD when an
external reference clock is input.
20 PLLVDD - - Clock PLL power supply Connects to analog +2.5 V typ.
21 FIL O - PLL filter output Connects to AGND via 1500 pF.
22 AD_AVDD - - ADC analog power supply Connects to analog +2.5 V typ.
23 AD_AVSS - - ADC analog GND Connects to AGND.
24 AD_VREFP - - ADC reference voltage output +1.75 V typ. Connects to AGND via PC.
25 AD_VREFN - - ADC reference voltage output +0.75 V typ. Connects to AGND via PC.
26 AD_VREF - - ADC reference voltage output +1.25 V typ. Connects to AGND via PC.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Q signal (differential negative side)
27 ADQ_AIN I - Single-ended IQ: Connects to AGND via PC.
input
Differential IQ: Connects to tuner Q (-) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Q signal (differential positive side) Single-ended IQ: Connects to tuner Q output after
28 ADQ_AIP I -
input the DC component was cut.
Differential IQ: Connects to tuner Q (+) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to tuner IF (-) output after
IF signal (differential negative side)
the DC component was cut.
29 ADI_AIN I - input or I signal (differential
Single-ended IQ: Connects to AGND via PC.
negative side) input
Differential IQ: Connects to tuner I (-) output after the
DC component was cut.
Single-ended IF: Connects to tuner IF output after
the DC component was cut.
IF signal (differential positive side) Differential IF: Connects to tuner IF (+) output after
30 ADI_AIP I - input or I signal (differential the DC component was cut.
positive side) input Single-ended IQ: Connects to tuner I output after the
DC component was cut.
Differential IQ: Connects to tuner I (+) output after the
-27-
IC Block Diagram

CONFIDENTIAL TC90517FG Toshiba products specification [Tentative]

DC component was cut.

31 AD_DVSS - - ADC digital GND Connects to DGND.
32 AD_ DVDD - - ADC digital power supply Connects to digital +2.5 V typ.
33 VSS - - Digital GND Connects to DGND.
34 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
35 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
36 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
37 VSS - - Digital GND Connects to DGND.
38 STSFLG1 O PD Status flag 1 output Open, fixed to L when not used.
39 DTCLK I PD Pin for pre-shipment test Open or connects to DGND.
40 DTMB I PU Pin for pre-shipment test Open or connects to digital +3.3 V typ.
41 TSMD1 I - Pin for pre-shipment test Connects to DGND.
42 SYRSTN I/O OD System reset input Inputat specified timing at power ON.
43 DR2VDD - - Digital +2.5 V power supply Connects to digital +2.5 V typ.
44 VSS - - Digital GND Connects to DGND.
Connects to I2C clock bus.
45 SCL I/O OD I2C clock input for host CPU
(Pull-up performed outside IC.)
Connects to I2C data bus.
46 SDA I/O OD I2C data I/O for host CPU
(Pull-up performed outside IC.)
47 VSS - - Digital GND Connects to DGND.
48 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
49 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
50 VSS - - Digital GND Connects to DGND.
51 STSFLG0 I/O PD Status flag 0 output Open, fixed to L when not used.
Synchronization completion Open, fixed to L when not used.
52 SLOCK O
(sequence 8 or higher) flag
53 RERR O - RS decoding error flag output Open, fixed to L when not used.
54 RLOCK O - RS decoding error free flag output Open, fixed to L when not used.
55 RSEORF O - TS error flag output Open, fixed to L when not used.
56 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
57 VSS - - Digital GND Connects to DGND.
58 PBVAL O - TS valid flag output Open, fixed to L when not used.
59 SBYTE O - TS synchronization byte flag output Open, fixed to L when not used.
60 SRDT O - Serial TS data output -
61 SRCK O - TS serial clock output -
62 VSS - - Digital GND Connects to DGND.
63 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
64 VDDS - - I/O power supply Con nects to digital +3.3 V typ.

Note 2 AGND is the abbreviation for analog GND, and DGND is the abbreviation for digital GND.
Note 3 The test dedicated pin is used for the pre-shipment test only. Make sure that processing is performed as
indicated in the "Remarks" column. Any other method will lead to malfunction or failure.
Note 4 I/O indicates the type of the cell used. It may be different from the pin function because a test is conducted
concurrently.
Note 5 PU indicates an I/O with a pull-up resistor (50 k typ.) and PD indicates an I/O with a pull-down resistor (50
k typ.). Pulling down the PU pin or pulling up the PD pin outside the IC sometimes changes the electric
potential to the midpoint, resulting in instability. Caution is required.
Note 6 The unused output pins must be open and fixed to L by setting the output enable control register of each pin
for noise reduction or to set
the output OFF state.
Note 7 OD indicates an open drain I/O. To use the pin for output, pull up the resistance outside the IC.

* The following pins are added with the upgrade from TC90507 to TC90517 (except the changes of power
supply and GND pins):
Pin
Pin Name Description
Number
21 FIL Added to the PLL loop filter.
27 ADQ_AIN Added for IQ input (differential).
28 ADQ_AIP Added for IQ input.
7 AGCI Added to passthrough the AGC control signal of other ICs.
52 SLOCK Changed from conventional FLOCK.

-28-
IC Block Diagram

PRELIMINARY W9751G6JB

4. B A L L C O N FIG U R A TIO N

1 2 3 4 5 6 7 8 9

VD D NC VSS A VSSQ U D Q S VD D Q

D Q 14 V S S Q UDM B U D Q S VSSQ D Q 15

VD D Q DQ9 VD D Q C VD D Q DQ8 VD D Q

D Q 12 V S S Q D Q 11 D D Q 10 V S S Q D Q 13

VD D NC VSS E V S S Q LD Q S V D D Q

DQ6 VSSQ LD M F LD Q S V S S Q DQ7

VD D Q DQ1 VD D Q G VD D Q DQ0 VD D Q

DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5

VD D L VR EF VSS J VSSDL C LK VD D

C KE W E K RAS C LK ODT

NC BA0 BA1 L CAS CS

A 10/A P A1 M A2 A0 VD D

VSS A3 A5 N A6 A4

A7 A9 P A 11 A8 VSS

VD D A 12 NC R NC NC

-29-
IC Block Diagram

PRELIMINARY W9751G6JB

5. BALL DESCRIPTION
BALL NUMBER SYMBOL FUNCTION DESCRIPTION
Provide the row address for active commands, and the column
M8,M3,M7,N2,N8,N3 address and Auto-precharge bit for Read/Write commands to select
,N7,P2,P8,P3,M2,P7 A0−A12 Address one location out of the memory array in the respective bank.
,R2 Row address: A0−A12.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0−BA1 define to which bank an ACTIVE, READ, WRITE or
L2,L3 BA0−BA1 Bank Select
PRECHARGE command is being applied.
G8,G2,H7,H3,H1,H9 Data Input
,F1,F9,C8,C2,D7,D3, DQ0−DQ15 Bi-directional data bus.
D1,D9,B1,B9 / Output
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
K9 ODT
Control DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write
LDQS, data for source synchronous operation. Edge-aligned with read data,
F7,E8 LOW Data Strobe center-aligned with write data. LDQS corresponds to the data on
LDQS DQ0−DQ7. LDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write
UDQS, data for source synchronous operation. Edge-aligned with read data,
B7,A8 UP Data Strobe center-aligned with write data. UDQS corresponds to the data on
DQ8−DQ15. is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when is registered
L8 Chip Select HIGH. provides for external bank selection on systems with
multiple ranks. is considered part of the command code.

RAS , CAS RAS , CAS and (along with ) define the command being
K7,L7,K3 Command Inputs
entered.
DM is an input mask signal for write data. Input data is masked when
UDM DM is sampled high coincident with that input data during a Write
Input Data Mask
B3,F3 LDM access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
CLK, Differential Clock input signals are sampled on the crossing of the positive edge of CLK
J8,K8
CLK Inputs and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
K2 CKE Clock Enable
deactivates clocking circuitry on the DDR2 SDRAM.
J2 VREF Reference Voltage VREF is reference voltage for inputs.
A1,E1,J9,M9,R1 VDD Power Supply Power Supply: 1.8V ± 0.1V.
A3,E3,J3,N1,P9 VSS Ground Ground.
A9,C1,C3,C7,C9,E9,
VDDQ DQ Power Supply DQ Power Supply: 1.8V ± 0.1V.
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
VSSQ DQ Ground DQ Ground. Isolated on the device for improved noise immunity.
F2,F8,H2,H8
A2,E2,L1,R3,R7,R8 NC No Connection No connection.
J7 VSSDL DLL Ground DLL Ground.
J1 VDDL DLL Power Supply DLL Power Supply: 1.8V ± 0.1V.

-30-
IC Block Diagram

PRELIMINARY W9751G6JB

6. BLOCK DIAGRAM

CLK DLL
CLK CLOCK
BUFFER

CKE

CONTROL
CS
SIGNAL

GENERATOR
RAS COMMAND

CAS
DECODER
COLUMN DECODER COLUMN DECODER
WE

CELL ARRAY CELL ARRAY

A10 BANK #0 BANK #1

MODE
A0
REGISTER
SENSE AMPLIFIER SENSE AMPLIFIER
ADDRESS
A9
BUFFER
A11
A12
BA0
BA1 ODT

DQ0
PREFETCH REGISTER
DQ |
DQ15
DATA CONTROL BUFFER ODT
LDQS
CIRCUIT CONTROL LDQS

REFRESH COLUMN UDQS

UDQS
COUNTER COUNTER
LDM
UDM

COLUMN DECODER COLUMN DECODER

CELL ARRAY CELL ARRAY

BANK #2 BANK #3

SENSE AMPLIFIER SENSE AMPLIFIER

NOTE: The cell array configuration is 8192 * 1024 * 16

-31-
MAIN PCB-TOP

-32-
MAIN PCB-BOT

-33-
 5 4 3 2 1

Power Input 1.32V DC-DC DC-DC Module

1.32V

3.3VU U50
5VA MP1482 U3 5VA
2 3 1482OUT L37 22uH 12VA L2 MPS1482
VCC OUT FB
5VU 12VA 24VA R52 10k 1482EN L3 22uH

1k
C105 7 EN 2 IN SW 3
1482COMP 6 C122 R57 C3
1n CA54 + COMP 0.1u 2.2K C1 C2
C116 C14 1 + R41 4 10nF C386
100uF/16V 0.1u 1n BST GND 1nF R14
14 8 1

R319
SS 100K BS
13 1482FB + CA1 0.1uF 6 nc 43K_1%
R342 100R STB 0.1u CA17 C114 100uF COMP
12
D
2 PWR-ON/OFF C178 11 R29 470uF/16V 0.1u D
H:ON 0.1u 10 4.7k C123 R55 7 CA2 C6
L:OFF 4.7K Low ESR EN +
9 C4
8 4 5 C383 R18 2K_1%
CON6 GND FB 0.1uF
7 FB 5
10uF
6 8 SS
5 3.3nF C11 R12 470uF/16V
4 R40 10K_1%
3
For MCU 2010-3-14 5.6K
PB-ADJUST 2 47NF
PB-ON/OFF 1

CON25-J25-14 1.8V DC-DC

C118 5V DC-DC
0.1u 1.8VA

U51
5VA MP1482
2 3 1482OUT18 L38 22uH
VCC OUT
Note: C103,C104 close to CON6 for EMI R53 10k 1482EN18 7
1482COMP18 EN C127 R60
6 COMP 0.1u 10K_1%
+ C15 1
C396 1n BST
8 SS
10u 1482FB18 +

CA12
100uF/16V
0.1u CA18 C389
12VA 24VA 12-24 R30 470uF/16V 0.1u
4.7k C128 R58
10K_1% Low ESR
L108 FB 4 5
GND FB

L116 NC/FB

For DDR

C C

MST Power supply PANEL POWER

R10 NC
12VA R203
PL12V FB
NC/100K
3.3VU 1.32V 1.8VA 5VA VCC-PL U1 VCC-Panel

4
380mA 3.3VA 150mA 1100mA 110mA PL5V NC/FB VCC-PL 1 8
S D
2 S D 7
3 6 +
C377 C407 C410 C412 C399 C400 C401 R37 S D CA10
4 G D 5
0.1u C380 C394 NC/0.1u NC/0.1u 0.1u 0.1u 0.1u 0.1u 10K C13 100uF/16V

IN

ADJ
OUT
U37 0.1u NC/0.1u 0.1uF CEM9435A
AMS1117-3.3V

1
2
3
5VU 3.3VU
+
CA11
R44 C32 100uF/16V
10K NC/0.1uF
CA40 + C378 C385 C387 R22
+ 10K
3

100uF/16V 0.1u NC/0.1u 0.1u

1 Q411
3904
3
2

CA7 100uF/16V
2 ON_PANEL R27 1 Q409
1K 3904
10n

1.8VA
2

H:ON
L:OFF

4
C104

C439 C442 C473 C450 C438 C436 C452

0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u

IN

ADJ
OUT
B U38 Inverter Interface B

1
2
3
AMS1117-3.3V
5VA 5VA
3.3VA 2.5VA 1.8VA 3.3VA

D38 1N4001
230mA 300mA_DDR2 Max R20
C379 R19 10K
C391 C393 C432 C445 C441 C468 C443 C427 C429 C444 10K
0.1u C384 + + NC/0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u R21
100R PB-ON/OFF
3

CA8
CA6
0.1u

100uF/16V
100uF/16V
2 ON_PBACK R24 1K 1 Q407
3904
L:ON C334
2

H:OFF 1n

5VA
USB Power For Power Drop
R15
Power Test Point 10K
R339
U5 10K
12VA L8 MPS1482 5VU 1
L9 +5V_USB
FB TP3 R31 NC/0 R16 0 / 22k PB-ADJUST
3

5VU 2 DCR-OUT
2 3 C495 R74 1 5V_TUNER 1 C255
IN SW 11K HW-RST TP4 TP22 R25 0 R17 4.7K Q406 NC/0.1u
2 HW-RST 2 12VA 2 ADJ-PWM 1
1 VCC-Panel 1 3904
+ C25 R45 10nF 22uH C29 12VA DD31 TP5 TP12 R39 NC/0 Note: Left C255 NC if want to output PWM puls
4 3
2

GND 3.3VU
CA4 100K 1 C31 R49 D141 BAT54 1 1

3
BS 1.8VA
100uF/16V 10uF C481 6 1nF 47K_1% C34 9.1V R67 1 R69 TP6 TP8
3

COMP 3.3VA 2 DCR-IN

+ 4.7K 1 R76 10K 1 1.32V 1
nc R42 CA19 39K 1 2.5VA TP7 TP9
LEDR 2
3.3nF 7 2K_1% 470uF/16V 0.1uF C449 R68 Q413 D139 1
2
EN 10n 2.2K 3904 4.1V Q415 TP11
2

VCC-PL
C37 3904
R43 0.1uF 5
A 5.6K FB R46 A
8 SS 10K_1%
C475
0.1uF

+5V_USB Power trace width

8 ON_USB_MOS should be > 40mil
R178 NC/10K 5V DC-DC

Title
POWER

Size Document Number Rev

A2 1/10 0.1

Date: Friday, March 04, 2011 Sheet 1 of 10

5 4 3 2 1
 5 4 3 2 1

SYSTEM EEPROM
MSD309PX 3.3VA

C316
U2C MSD309PX U2B MSD309PX 2010-3-31
U21 0.1u

R239
R237
R248
NC/24C64
HDMI AUDIO PCMCIA TS1

10K
HD1-Lin

4.7K
4.7K
6 RXA0N G2 PAD_RX0N_A PAD_LINEIN_L0 R4 HD-Lin 7 W21 PAD_PCM_D[0] PAD_TS1_D[0] Y16 1 A0 VCC 8
6 RXA0P H3 R5 HD1-Rin HD-Rin 7 U21 AD14 2 7
PAD_RX0P_A PAD_LINEIN_R0 AV1-Lin PAD_PCM_D[1] PAD_TS1_D[1] A1 WP SCL
6 RXA1N H2 PAD_RX1N_A PAD_LINEIN_L1 T6 AV1-Lin U19 PAD_PCM_D[2] PAD_TS1_D[2] AD15 3 A2 SCL 6
6 RXA1P J3 U6 AV1-Rin AV1-Rin AD12 AC15 4 5 SDA
PAD_RX1P_A PAD_LINEIN_R1 VGA-Lin PAD_PCM_D[3] PAD_TS1_D[3] GND SDA
6 RXA2N J2 PAD_RX2N_A PAD_LINEIN_L2 V6 VGA-Lin 7 AC12 PAD_PCM_D[4] PAD_TS1_D[4] AC16
6 RXA2P J1 U5 VGA-Rin VGA-Rin 7 AD13 Y17 EPM_WP
PAD_RX2P_A PAD_LINEIN_R2 HD2-Lin PAD_PCM_D[5] PAD_TS1_D[5]
6 RXACLKN G3 PAD_RXCN_A PAD_LINEIN_L5 AD6 AV2-Lin 7 Y12 PAD_PCM_D[6] PAD_TS1_D[6] AB17 I2C address 3.3VA
6 RXACLKP G1 AC6 HD2-Rin AV2-Rin 7 AA11 AB19 at 0xA0
PAD_RXCP_A PAD_LINEIN_R5 PAD_PCM_D[7] PAD_TS1_D[7]
6 DDCASCL M4 DDCDA_CK PAD_TS1_CLK Y18
6 DDCASDA M5 DDCDA_DA PAD_LINEOUT_L0 V1 AUOUTL0 9 Y24 PAD_PCM_A[0] PAD_TS1_VLD AE16
6 HOTPLUGA K6 V2 AUOUTR0 9 Y22 AB16 C507 C508
PAD_HOTPLUGA PAD_LINEOUT_R0 PAD_PCM_A[1] PAD_TS1_SYNC SCL NC/100pF NC/100pF
PAD_LINEOUT_L3 AA6 AUOUTL1 AB22 PAD_PCM_A[2] SCL 10
6 RXB0N D2 Y5 AUOUTR1 AA22 SDA SDA C-L10W05-2
10 C-L10W05-2
D PAD_RX0N_B PAD_LINEOUT_R3 PAD_PCM_A[3] D
6 RXB0P E3 PAD_RX0P_B AA20 PAD_PCM_A[4]
6 RXB1N E2 AD5 䴴䖥MSD309ᬒ㕂 Y21 SCL I2C-SCL
PAD_RX1N_B PAD_EARPHONE_OUTL AUOUTL2 9 PAD_PCM_A[5] TS0 R344 100
6 RXB1P F3 PAD_RX1P_B PAD_EARPHONE_OUTR AE5 AUOUTR2 9 AA18 PAD_PCM_A[6]
F2 AA19 U20 TS_D0 SDA I2C-SDA 2010-5-6
6 RXB2N PAD_RX2N_B PAD_PCM_A[7] PAD_TS0_D[0] TS_D0 10
6 RXB2P F1 AB4 AUVRP AA16 V20 TS_D1 TS_D1 10 U2F MSD309PX R364 100
PAD_RX2P_B PAD_VRP AUVAG PAD_PCM_A[8] PAD_TS0_D[1] TS_D2
6 RXBCLKN D3 PAD_RXCN_B PAD_VAG AB5 AA14 PAD_PCM_A[9] PAD_TS0_D[2] R19 TS_D2 10
D1 AC3 AUVRM AA12 AE13 TS_D3 1.32V
6 RXBCLKP PAD_RXCP_B AVSS_VRM_ADC_DAC PAD_PCM_A[10] PAD_TS0_D[3] TS_D3 10
6 DDCBSCL J6 C30 C36 Y15 AC13 TS_D4 TS_D4 10
DDCDB_CK PAD_PCM_A[11] PAD_TS0_D[4] TS_D5
6 DDCBSDA L6 DDCDB_DA I2S 2.2u 2.2u AA17 PAD_PCM_A[12] PAD_TS0_D[5] Y11 TS_D5 10 E22 VDDC1.2V
6 HOTPLUGB J4 AA15 AB11 TS_D6 TS_D6 10 F22
HOTPLUGB I2S_OUT_MCK PAD_PCM_A[13] PAD_TS0_D[6] TS_D7 VDDC1.2V
PAD_I2S_OUT_MCK A6 AE14 PAD_PCM_A[14] PAD_TS0_D[7] AB13 TS_D7 10 E21 VDDC1.2V
6 RXC0N AC8 B5 I2S_OUT_SD L34 Y20 Y19 TS_CLK TS_CLK 10 F21 AC2 LVDS CONNECTOR
PAD_RX0N_C PAD_I2S_OUT_SD PAD_PCM_RESET PAD_TS0_CLK TSVALID VDDC1.2V GND
6 RXC0P AD9 PAD_RX0P_C PAD_I2S_OUT_WS B6 PAD_TS0_VLD Y23 TSVALID 10 G21 VDDC1.2V GND AE1
6 RXC1N AC9 C6 I2S_OUT_BCK AD16 W20 TSSTART TSSTART 10 H21 Y10
PAD_RX1N_C PAD_I2S_OUT_BCK PAD_PCM_IRQA_N PAD_TS0_SYNC VDDC1.2V GND
6 RXC1P AD10 PAD_RX1P_C Y13 PAD_PCM_OE_N E20 VDDC1.2V
6 RXC2N AE10 C1 FB Y14 F20 V7
PAD_RX2N_C PAD_I2S_IN_BCK(USB_OCD) PAD_PCM_IORD_N VDDC1.2V GND CON3
6 RXC2P AC10 PAD_RX2P_C PAD_I2S_IN_SD(LED_ON) H6 AA13 PAD_PCM_CE_N G20 VDDC1.2V GND W7
6 RXCCLKN AE8 PAD_RXCN_C PAD_I2S_IN_WS(WARM_LED_ON) G6 AC14 PAD_PCM_WE_N G22 VDDC1.2V 46 GND GND 45
6 RXCCLKP AD8 AB23 I2C-SCL 44 43 I2C-SDA
PAD_RXCP_C PAD_PCM_CD_N FRONT END C171 0.1u R381 2.2K I2C-SCL SCL SDA I2C-SDA
6 DDCCSCL AE7 DDCDC_CK AB20 PAD_PCM_WAIT_N 42 GND GND 41
6 DDCCSDA AD7 AB14 AA3 C174 0.1u R382 2.2K V8 RXO0- 40 39 RXO0+
DDCDC_DA PAD_PCM_IOWR_ N PAD_IP GND RXO1- A0- A0+ RXO1+
6 HOTPLUGC AC7 PAD_HOTPLUGC SPDIF AA21 PAD-PCM_REG_N PAD_IM AA2 H20 DVDD_MIUA GND W8 38 A1- A1+ 37
䴴䖥MSD306ᬒ㕂 J20 V9 RXO2- 36 35 RXO2+
DVDD_MIUB GND RXOC- A2- A2+ RXOC+
6 HDMI-CEC K5 PAD_CEC PAD_SPDIF_OUT P5 SPDIFO 7 PAD_QP Y3 GND W9 34 AC- AC- 33
Y25 Y2 J21 J10 RXO3- 32 31 RXO3+
PAD_PCM2_CE_N PAD_QM AVDD1P2 GND RXO4- A3- A3+ RXO4+
GND K10 30 A4- A4+ 29
PAD_VIFP AB1 VIFP 4 GND M10 28 GND GND 27
U2E MSD309PX AA1 2.5VA N10 DCR-OUT 26 25 DCR-IN
PAD_VIFM VIFM 4 GND 1 DCR-OUT DCR-IDCR-O DCR-IN 1
P10 MODE 24 23 I/O
GND MODE I/O
RGB CVBS PAD_SIFP AB2 TV-SIFP M8 AVDD2P5_ADC GND R10 22 GND GND 21
AB3 TV-SIFM M9 T10 RXE0- 20 19 RXE0+
NAND FLASH PAD_SIFM AVDD2P5_ADC GND RXE1- B0- B0+ RXE1+
7 RGB0_RIN- M2 PADA_RIN0M PADA_CVBS0 AC5 AV1-Vin+ GND U10 18 B1- B1+ 17
M3 W4 SV2-Yin 7 T21 AD3 N8 V10 RXE2- 16 15 RXE2+
7 RGB0_RIN+ PADA_RIN0P PADA_CVBS1 PAD_PF_ALE PAD_IFAGC AVDD25_REF GND B2- B2+
L2 W5 SV2-Cin 7 T19 AE3 L35 N9 W10 RXEC- 14 13 RXEC+
7 RGB0_GIN- PADA_GIN0M PADA_CVBS2 PAD_PF_AD[15] PAD_RFAGC_TAGC AVDD25_REF GND BC- BC+
L3 AA5 P21 D11 RXE3- 12 11 RXE3+
7 RGB0_GIN+ PADA_GIN0P PADA_CVBS3 PAD_PF_CE0Z GND B3- B3+
K1 W2 AV4-Vin+ 7 P20 AC4 RF_AGC_SEL 4 R9 G11 RXE4- 10 9 RXE4+
7 RGB0_BIN- PADA_BIN0M PADA_CVBS4 PAD_PF_CE1Z PAD_TGPIO0(RF_AGC_CTRL) AVDD_AU25 GND B4- B4+
7 RGB0_BIN+ K3 PADA_BIN0P PADA_CVBS5 W3 R20 PAD_PF_OEZ PAD_TGPIO1(DEMOD_RESET) AD2 SIF_CTL GND H11 8 GND GND 7
K2 T20 AD4 5V_Tuner P8 J11 VCC-Panel 6 5
7 RGB0-SOG PADA_SOGIN0 PAD_PF_WEZ PAD_TGPIO2(TUNER_SCL) AVDD25_MOD GND GND GND
N4 V3 CVBS_OUT P19 AE4 FB P9 K11 4 3
7 VGA_HSYNC PAD_HSYNC0 PADA_CVBS_OUT1 CVBS_OUT 7 PAD_F_RBZ PAD_TGPIO3(TUNER_SDA) AVDD25_MOD GND VCC VCC
7 VGA_VSYNC N5 PAD_VSYNC0 PADA_CVBS_OUT2 AA4 GND L11 2 VCC VCC 1
R176 C44 T8 M11
C82 68R R504 R180 AVDD25_PGA GND
7 RGB1_R- R3 PADA_RIN1M PADA_VCOM W1 47n 10K GND N11
P2 10k 0.1u U8 P11 C75 CON46
7 RGB1_R+ PADA_RIN1P AVSS_PGA GND
P3 R11 0.1u
7 RGB1_G- PADA_GIN1M RF_AGC 4 GND
N2 L41 T11
7 RGB1_G+ PADA_GIN1P 3.3VU GND
N3 C166 U11
7 RGB1_B- PADA_BIN1M GND C75 close to CON30
M1 47n V11
7 RGB1_B+ PADA_BIN1P GND
7 RGB1_SOG N1 PADA_SOGIN1 E9 AVDD_DVI GND W11
W6 FB E10 D12
PAD_HSYNC1 R215 4.7K AVDD_DVI GND
Y6 PAD_VSYNC1 5V_Tuner F9 AVDD_DVI GND E12
C R188 4.7K F10 F12 FLASH C
AVDD_DVI GND
7 COMP_R- U2 PADA_RIN2M G9 AVDD_DVI GND G12
U3 R216 100 T_SDA T_SDA 4 H12
7 COMP_R+ PADA_RIN2P GND
T2 R217 100 T_SCL T_SCL 4 G10 J12
7 COMP_Y- PADA_GIN2M AVDD_DMPLL GND
T1 K12 3.3VU
7 COMP_Y+ PADA_GIN2P GND
7 COMP_B- R1 PADA_BIN2M H9 AVDD3P3_ADC GND L12
R2 2010-9-10 For IIC selection H10 M12
7 COMP_B+ PADA_BIN2P AVDD3P3_ADC GND
7 COMP_SOG+ T3 PADA_SOGIN2 GND N12
V4 PAD_HSYNC2 K9 AVDD_AU33 GND P12
R12 U24
24
23
22
21

U2A MSD309PX GND MX25L6445E

J9 AVDD_EAR33 GND T12
GND U12
3.3VA V12
GND SPI-SCK
䴴䖥MSD306ᬒ㕂 MIUA MIUB GND W12 1 HOLD CLK 16
U2D MSD309PX MIUA_A[0:13] MIUB_A[0:13]
SOP8-DI

3 MIUA_A[0:13] MIUB_A[0:13] 3 GND D13

SOP8-CLK

MIUA_A0 MIUB_A0 SPI-SDI

SOP8-VCC

C10 PAD_IO[8](A_A0) PAD_IO[55](B_A0) E23 E19 VDDP GND E13 2 VCC DI 15

SOP8-HOLD

MIUA_A1 A22 U24 MIUB_A1 F19 F13

PWM LVDS MIUA_A2 PAD_IO[41](A_A1) PAD_IO[88](B_A1) MIUB_A2 VDDP GND C170
A9 PAD_IO[5](A_A2) PAD_IO[52](B_A2) D24 3 NC1 NC8 14
PWM0 AB25 AC24 LVB0P LVB0N 0RX4 RP52 RXO0- MIUA_A3 B23 V25 MIUB_A3 G18 H13 0.1u
PWM1 PAD_PWM0 PADA_OUTP_CH[6](PAD_R_ODD[7]) LVB0N LVB0P RXO0+ MIUA_A4 PAD_IO[44](A_A3) PAD_IO[91](B_A3) MIUB_A4 AVDD_LPLL_MEMPLL GND
AB24 PAD_PWM1 PADA_OUTN_CH[6](PAD_R_ODD[6]) AC25 B9 PAD_IO[3](A_A4) PAD_IO[50](B_A4) D25 GND J13 4 NC2 SOIC8 NC7 13
E6 AD24 LVB1P LVB1N RXO1- MIUA_A5 A23 V24 MIUB_A5 K13
1 ADJ-PWM PAD_PWM2 PADA_OUTP_CH[7](PAD_R_ODD[5]) LVB1N LVB1P RXO1+ MIUA_A6 PAD_IO[43](A_A5) PAD_IO[90](B_A5) MIUB_A6 GND 208mil
D6 PAD_PWM3 PADA_OUTN_CH[7](PAD_R_ODD[4]) AD25 C9 PAD_IO[6](A_A6) PAD_IO[53](B_A6) D23 GND L13 5 NC3 NC6 12
AE24 LVB2P LVB2N 0RX4 RP53 RXO2- MIUA_A7 C23 W25 MIUB_A7 1.8VA M13
PADA_OUTP_CH[8](PAD_R_ODD[3]) LVB2N LVB2P RXO2+ MIUA_A8 PAD_IO[45](A_A7) PAD_IO[92](B_A7) MIUB_A8 GND
PADA_OUTN_CH[8](PAD_R_ODD[2]) AC23 B8 PAD_IO[4](A_A8) PAD_IO[51](B_A8) C25 GND N13 6 NC4 NC5 11
AE23 LVBCP LVBCN RXOC- MIUA_A9 A24 W24 MIUB_A9 E17 P13
SAR PADA_OUTP_CH[9](PAD_R_ODD[1]) LVBCN LVBCP RXOC+ MIUA_A10 PAD_IO[46](A_A9) PAD_IO[93](B_A9) MIUB_A10 AVDD_DDRA GND SPI-CSN
PADA_OUTN_CH[9](PAD_R_ODD[0]) AD23 B22 PAD_IO[42](A_A10) PAD_IO[89](B_A10) V23 E18 AVDD_DDRA GND R13 7 SO16-CS VSS 10
KEY0 J5 AE22 LVB3P LVB3N 0RX4 RP54 RXO3- MIUA_A11 C8 C24 MIUB_A11 F17 T13
KEY1 PAD_SAR0 PADA_OUTP_CH[10](PAD_G_ODD[7]) LVB3N LVB3P RXO3+ MIUA_A12 PAD_IO[2](A_A11) PAD_IO[49](B_A11) MIUB_A12 AVDD_DDRA GND SPI-SDO FLASH_WP
G4 PAD_SAR1 PADA_OUTN_CH[10](PAD_G_ODD[6]) AC22 B24 PAD_IO[35](A_A12) PAD_IO[82](B_A12) W23 F18 AVDD_DDRA GND U13 8 DO WP/Vpp 9
B4 AC21 LVB4P LVB4N RXO4- MIUA_A13 B7 B25 MIUB_A13 G17 100K R224
PAD_SAR2(POWER_DET) PADA_OUTP_CH[11](PAD_G_ODD[5]) PAD_IO[0](A_A13) PAD_IO[47](B_A13) AVDD_DDRA

7 5 3 1 7 5 3 1 7 5 3 1
8 6 4 2 8 6 4 2 8 6 4 2
AA7 AD22 LVB4N LVB4P RXO4+ MIUA_DQ[0:15] MIUB_DQ[0:15]
SOP8-CS
SOP8-DO
SOP8-WP/Vpp
VSS

PAD_SAR3 PADA_OUTN_CH[11](PAD_G_ODD[4]) 3 MIUA_DQ[0:15] MIUA_DQ0 MIUB_DQ0 MIUB_DQ[0:15] 3 C336

C13 PAD_IO[14](A_DQ0) PAD_IO[61](B_DQ0) H23 G16 AVDD_DDRB GND D14
AC20 LVA0P LVA0N 0RX4 RP58 RXE0- MIUA_DQ1 A19 P24 MIUB_DQ1 H16 E14 0.1u
SPI PADA_OUTP_CH[12](PAD_G_ODD[3]) PAD_IO[32(A_DQ1) PAD_IO[79](B_DQ1) AVDD_DDRB GND
17
18
19
20

AD21 LVA0N LVA0P RXE0+ MIUA_DQ2 A12 G24 MIUB_DQ2 H17 F14
PADA_OUTN_CH[12](PAD_G_ODD[2]) LVA1P LVA1N RXE1- MIUA_DQ3 PAD_IO[15](A_DQ2) PAD_IO[62](B_DQ2) MIUB_DQ3 AVDD_DDRB GND
C4 PAD_GPIO_PM6(BOOT_FLASH_CS) PADA_OUTP_CH[13](PAD_G_ODD[1]) AE20 B19 PAD_IO[33](A_DQ3) PAD_IO[80](B_DQ3) R23 J16 AVDD_DDRB GND G14
SPI-CSN22R SPI-CSNI
R505 A4 AD20 LVA1N LVA1P RXE1+ MIUA_DQ4 C20 R24 MIUB_DQ4 J17 H14
SPI-SCK22R SPI-SCKI
R506 PAD_SPI_CZ(BACKUP_FLASH_CS) PADA_OUTN_CH[13](PAD_G_ODD[0]) LVA2P LVA2N 0RX4 RP55 RXE2- MIUA_DQ5 PAD_IO[34](A_DQ4) PAD_IO[81](B_DQ4) MIUB_DQ5 AVDD_DDRB GND
A2 PAD_SPI_CK PADA_OUTP_CH[14](PAD_B_ODD[7]) AE19 B12 PAD_IO[13](A_DQ5) PAD_IO[60](B_DQ5) G25 GND J14
SPI-SDI22R SPI-SDII
R507 B3 AC19 LVA2N LVA2P RXE2+ MIUA_DQ6 C19 P23 MIUB_DQ6 K14 #F_WP
SPI-SDO22R SPI-SDOI
R508 PAD_SPI_DI PADA_OUTN_CH[14](PAD_B_ODD[6]) LVACP LVACN RXEC- MIUA_DQ7 PAD_IO[31](A_DQ6] PAD_IO[78](B_DQ6) MIUB_DQ7 GND
A3 PAD_SPI_DO PADA_OUTP_CH[15](PAD_B_ODD[5]) AC18 A13 PAD_IO[17](A_DQ7) PAD_IO[64](B_DQ7) H24 GND L14
FLASH_WP B2 AD19 LVACN LVACP RXEC+ MIUA_DQ8 B14 J25 MIUB_DQ8 M14
PAD_GPIO_PM8(FLASH_WP) PADA_OUTN_CH[15](PAD_B_ODD[4]) LVA3P LVA3N 0RX4 RP56 RXE3- MIUA_DQ9 PAD_IO[18](A_DQ8) PAD_IO[65](B_DQ8) MIUB_DQ9 GND
PADA_OUTP_CH[16](PAD_B_ODD[3]) AC17 C18 PAD_IO[29](A_DQ9) PAD_IO[76](B_DQ9) N23 DVDD_NODIEL10
DVDD_NODIE GND N14
AD18 LVA3N LVA3P RXE3+ MIUA_DQ10 C14 J24 MIUB_DQ10 P14
PADA_OUTN_CH[16](PAD_B_ODD[2]) LVA4P LVA4N RXE4- MIUA_DQ11 PAD_IO[19](A_DQ10) PAD_IO[66](B_DQ10) MIUB_DQ11 GND
UART/I2CS PADA_OUTP_CH[17](PAD_B_ODD[1]) AE17 A18 PAD_IO[30](A_DQ11) PAD_IO[77](B_DQ11) N24 GND R14

7 5 3 1 7 5 3 1 7 5 3 1
8 6 4 2 8 6 4 2 8 6 4 2
AD17 LVA4N LVA4P RXE4+ MIUA_DQ12 B18 N25 MIUB_DQ12 C52 T14
UART-RX PADA_OUTN_CH[17](PAD_B_ODD[0]) MIUA_DQ13 PAD_IO[28](A_DQ12) PAD_IO[75](B_DQ12) MIUB_DQ13 GND
P6 DDCA_CK B13 PAD_IO[16](A_DQ13) PAD_IO[63](B_DQ13) J23 GND U14
UART-TX N6 MIUA_DQ14 B17 M25 MIUB_DQ14 2.2u KEYBOARD
DDCA_DA MIUA_DQ15 PAD_IO[27](A_DQ14) PAD_IO[74](B_DQ14) MIUB_DQ15
GPIO_TCON C15 PAD_IO[20](A_DQ15) PAD_IO[67](B_DQ15) K23
GND D15
AA10 EPM_WP MIUA_DQS0 A16 L24 MIUB_DQS0 E15
I2CM PAD_TCON0 3 MIUA_DQS0 MIUA_DQS0B PAD_IO[23](A_DQS0) PAD_IO[70](B_DQS0) MIUB_DQS0B MIUB_DQS0 3 GND CON10 5VU
PAD_TCON1(SC1_RE1) T5 3 MIUA_DQS0B C16 PAD_IO[24](A_DQS0B) PAD_IO[71](B_DQS0B) L23 MIUB_DQS0B 3 GND F15
SCL AA23 AB10 L_R_INDICATOR MIUA_DQS1 A15 K24 MIUB_DQS1 G15
B 10 SCL SDA PAD_DDCR_CK PAD_TCON2(FE_ANT5V_MONITOR) 3 MIUA_DQS1 MIUA_DQS1B PAD_IO[21](A_DQS1) PAD_IO[68](B_DQS1) MIUB_DQS1B MIUB_DQS1 3 GND B
10 SDA AA24 PAD_DDCR_DA PAD_TCON3(TUNER_RESET) AB7 Demod_RST 10 3 MIUA_DQS1B B15 PAD_IO[22](A_DQS1B) PAD_IO[69](B_DQS1B) K25 MIUB_DQS1B 3 GND H15 1
AA9 LOCAL_DIM J15 2 KEY0-in
PAD_TCON4 3D_ENABLE MIUA_DQM0 MIUB_DQM0 GND KEY1-in
PAD_TCON5(SC1_MUTE) V5 3 MIUA_DQM0 B16 PAD_IO[26](A_DQM0) PAD_IO[73](B_DQM0) M23 MIUB_DQM0 3 GND K15 3
AC11 MIUA_DQM1 C17 M24 MIUB_DQM1 L15 4
IR PAD_TCON6(PCM_5V_CTL) 3 MIUA_DQM1 PAD_IO[25](A_DQM1) PAD_IO[72](B_DQM1) MIUB_DQM1 3 GND
PAD_TCON7(SIDE_AV_DET) AA8 HEADPHONE_DET 9 GND M15 5
IR_SYNC G5 MIUA_MCLK C12 G23 MIUB_MCLK N15 6
C173 PAD_IRIN 3D-RST 3 MIUA_MCLK MIUA_MCLKZ PAD_IO[12](A_MCLK) PAD_IO[59](B_MCLK) MIUB_MCLKZ MIUB_MCLK 3 GND IR-in
R6 B11 F25 N19 P15 7

2
39p PAD_TCON9(COMP_DET) 3 MIUA_MCLKZ MIUA_MCKE PAD_IO[10](A_MCLKZ) PAD_IO[57](B_MCLKZ) MIUB_MCKE MIUB_MCLKZ 3 GND GND
PAD_TCON10(HP_DET) Y8 ON_USB 8 3 MIUA_MCKE C21 PAD_IO[37](A_CKE) PAD_IO[84](B_CKE) T23 MIUB_MCKE 3 M19 GND GND R15 8
3 Y1 R212 Y9 L19 T15 9 LED R496 100 LED_R
24MHZ XTAL PAD_TCON11(HP_MUTE) MUTE_HP MIUA_WEZ MIUB_WEZ GND GND 3.3VA 3.3VU
3 MIUA_WEZ B20 PAD_IO[36](A_WEZ) PAD_IO[83](B_WEZ) R25 MIUB_WEZ 3 K19 GND GND U15 10
C172 1M XTALI AD1 MIUA_RASZ B10 F23 MIUB_RASZ N20 11

1
R476 0R XTALOAE2 PAD_XTAL_IN 3 MIUA_RASZ MIUA_CASZ PAD_IO[9](A_RASZ) PAD_IO[56](B_RASZ) MIUB_CASZ MIUB_RASZ 3 GND R499 NC/0
PAD_XTAL_OUT 3 MIUA_CASZ A10 PAD_IO[7](A_CASZ) PAD_IO[54](B_CASZ) E24 MIUB_CASZ 3 M20 GND 12
39p T4 MIUA_BA0 A21 T24 MIUB_BA0 L20 D131D133D132 D138
2
2
2
2

PAD_TCON15(SC1_DET) 3 MIUA_BA0 MIUA_BA1 PAD_IO[39](A_BA0) PAD_IO[86](B_BA0) MIUB_BA1 MIUB_BA0 3 GND R500 0

3 MIUA_BA1 B21 PAD_IO[38](A_BA1) PAD_IO[85](B_BA1) T25 MIUB_BA1 3 K20 GND
MIUA_BA2 C22 U23 MIUB_BA2 N21 U16 CON20W-J20-12
RESET 3 MIUA_BA2 MIUA_ODT PAD_IO[40](A_BA2) PAD_IO[87](B_BA2) MIUB_ODT MIUB_BA2 3 GND GND
GPIO 3 MIUA_ODT C11 PAD_IO[11](A_ODT) PAD_IO[58](B_ODT) F24 MIUB_ODT 3 M21 GND GND T16
HW-RST E5 3.3VA L21 R16 INPAQ_VPORT R497
1
1
1
1

PAD_RESET MUTE_AMP 9 GND GND INPAQ_VPORT

INPAQ_VPORT
INPAQ_VPORT NC/4.7K 2010-4-14
PAD_GPIO0(NTP_MUTE) A7 K21 GND GND P16
C7 D22 MVERF N22 N16
PAD_GPIO1(AMP_RST) MVREF GND GND
USB PAD_GPIO2(INV_CTL) F4 ON_PBACK 1 M22 GND GND M16
PAD_GPIO3(PANEL_CTL) E4 ON_PANEL 1 L22 GND GND L16
8 USB_DP C2 C3 R371 R372 R373 K22 K16
PAD_DP_P0 PAD_GPIO4(USB_CTL) GND GND
8 USB_DM B1 PAD_DM_P0 PAD_GPIO5(ERROR_OUT) D4 4.7K 4.7K 4.7K J22 GND GND F16
8 USB1_DP AD11 PAD_DP_P1 PAD_GPIO12(AMD_SCL) F6 IPOD_RX H22 GND GND E16
8 USB1_DM AE11 F5 IPOD_TX D16 3.3VU
PAD_DM_P1 PAD_GPIO13(AMP_SDA) GND
GND K17
1.8VA L17
R8 GND R495 R489
GPIO_PM U18 GND GND M17
MUTE_AMP 10k T18 N17
GND GND
PAD_GPIO_PM0(5V_HDMI_3) AB8 R18 GND GND P17
H5 LEDR IPOD_RX R145 100 I/O MVERF P18 R17
PAD_GPIO_PM1(5V_HDMI_1) GND GND 8.2K 8.2K
PAD_GPIO_PM4(POWER_ON_OFF) C5 PWR-ON/OFF 1 N18 GND GND T17
K4 IPOD_TX R154 100 MODE M18 U17 KEY0-in R493 100 KEY0 KEY0
PAD_GPIO_PM5(5V_HDMI_2) R9 C39 GND GND
F11 PAD_GND_EFUSE PAD_GPIO_PM11(DSUB_DET) L5 L18 GND
E11 M6 10k 0.1u K18
PAD_TESTPIN PAD_GPIO_PM12(EDID_WP) GND KEY1-in R492 100 KEY1 KEY1
20100122
C330 C331
0.1uF
0.1uF

5VU

R490
RESET LED 3D Mode Selection
DEBUG PORT
A 3.3VU 10K A
IR-in R494 1K IR_SYNC IR_SYNC
3.3VA 3.3VU

3
DD30 3.3VU C337
39P

R253 BAV99 R33 10K I2S_OUT_SD NC/10K R350

C208

100K R221 39pF

2.2K
R35 NC/10K I2S_OUT_MCK 10k R349 4.7K
R222
C309 0.1u R70 10K I2S_OUT_BCK NC/10K R351 CON31 4.7K

1
2
HW-RST Close to MSD309

R411

2
1 HW-RST R26 10K PWM1 NC/10K R352 1 R126
R259 10K 1 2 ISP-RXD 22R UART-RX
3906 LEDR R47 10K PWM0 NC/10K R356 3 ISP-TXD 22R UART-TX
Q41 R249 100R HW-RST LEDR R347 100R LED_R 1 LEDR 4 R124

3
ISP-TXD 7
NC/CON4-2.0mm ISP-RXD 7
R252 Debug Port
C308 100K C307
2.2u 1n
Title
MSD309

Size Document Number Rev

Custom2/10 0.1

Date: Friday, December 10, 2010 Sheet 2 of 10

5 4 3 2 1
 5 4 3 2 1

RP39
RP50 22RX4 22RX4
MIUA_DQS0 MA_DQS0
2 MIUA_DQS0
MIUA_DQS0B MA_DQSB0 MA_MCLK
2 MIUA_DQS0B 2 MIUA_MCLK 1.8VA
MA_MCLKZ
2 MIUA_MCLKZ

1 3 5 7
2 4 6 8
22RX4

1 3 5 7
2 4 6 8
RP57
MIUA_DQS1 MA_DQS1
2 MIUA_DQS1
MIUA_DQS1B MA_DQSB1 U9 W9751G6IB-25

A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
2 MIUA_DQS1B

1 3 5 7
2 4 6 8
MA_DQM1 B3
MA_DQM0 UDM

Vdd
Vdd
Vdd
Vdd
Vdd
F3 LDM

VddL
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
Close to DRAM MA_DQS0 F7 1 2 3 7 8 9 J2 A_MVERF
MIUA_ODT R13 75R MA_ODT MA_DQSB0 LDQS A Vref MA_CKE
2 MIUA_ODT E8 LDQS# CKE K2
MA_DQS1 B7 Vdd NC Vss VssQ UDQS# VddQ J8 MA_MCLK
75RX4 MA_DQSB1 UDQS B CLK MA_MCLKZ
D
A8 UDQS# CLK# K8 D
RP12 22RX4 MIUA_WEZ RP15 MA_WEZ DQ14 VssQ UDM UDQS VssQ DQ15
2 MIUA_WEZ C
MIUA_DQM1 MA_DQM1 MIUA_MCKE MA_CKE MA_DQ11 D3 B9 MA_DQ15 R23 R71
2 MIUA_DQM1 2 MIUA_MCKE DQ11 VddQ DQ9 VddQ VddQ DQ8 VddQ DQ15
MIUA_DQM0 MA_DQM0 MIUA_BA1 MA_BA1 MA_DQ12 D1 C8 MA_DQ8
2 MIUA_DQM0 2 MIUA_BA1 DQ12 DQ8

7 5 3 1
8 6 4 2
MIUA_BA0 MA_BA0 MA_DQ9 C2 D D7 MA_DQ10
2 MIUA_BA0 DQ9 DQ10

1 3 5 7
DQ12 VssQ DQ11 DQ10 VssQ DQ13

2 4 6 8
MA_DQ14 B1 D9 MA_DQ13
DQ14 E DQ13 100R 100R
Close to MSD306
MA_DQ6 F1 Vdd NC Vss VssQ LDQS# VddQ F9 MA_DQ7
MA_DQ1 DQ6 F DQ7 MA_DQ0
Close to MSD306 G2 DQ1 DQ0 G8
MIUA_A[0:13] MA_DQ3 H3 DQ6 VssQ LDM LDQS VssQ DQ7 H7 MA_DQ2
2 MIUA_A[0:13] DQ3 G DQ2
MA_DQ4 H1 H9 MA_DQ5 C430
MIUA_A4 RP5 75RX4 MA_A4 DQ4 VddQ DQ1 VddQ VddQ DQ0 VddQ DQ5 47n
MIUA_DQ[0:15] MIUA_A6 MA_A6 H K9 MA_ODT
2 MIUA_DQ[0:15] DQ4 VssQ DQ3 DQ2 VssQ DQ5 ODT
MIUA_DQ11 RP1 22RX4 MA_DQ11 MIUA_A8 MA_A8 K7 MA_RASZ Close to DRAM
MIUA_DQ12 MA_DQ12 MIUA_A11 MA_A11 MA_BA1 J RAS#
L3 BA1 CS# L8

1 3 5 7
VddL Vref Vss VssDL CK Vdd

2 4 6 8
MIUA_DQ9 MA_DQ9 MA_BA0 L2 L7 MA_CASZ
MIUA_DQ14 MA_DQ14 BA0 K CAS#

1 3 5 7
CKE WE# RAS# CK# ODT

2 4 6 8
MA_A1 M3 M8 MA_A0
MIUA_DQ6 RP2 22RX4 MA_DQ6 MIUA_A5 RP6 75RX4 MA_A5 MA_A10 A1 L A0 MA_A2
M2 A10 A2 M7
MIUA_DQ1 MA_DQ1 MIUA_A10 MA_A10 MA_A5 N3 RFU BA0 BA1 CAS# CS# N8 MA_A4
MIUA_DQ3 MA_DQ3 MIUA_A1 MA_A1 A5 M A4 MA_A6
A6 N7
MIUA_DQ4 MA_DQ4 MIUA_BA2 MA_BA2 A10 A1 A2 A0 Vdd
2 MIUA_BA2

7 5 3 1

8 6 4 2
1 3 5 7
N

2 4 6 8
MA_A9 P3 P8 MA_A8
MIUA_DQ15 RP3 22RX4 MA_DQ15 MIUA_A12 RP7 75RX4 MA_A12 MA_A12 A9 Vss A3 A5 A6 A4 A8 MA_A11
R2 A12 A11 P7
MIUA_DQ8 MA_DQ8 MIUA_A7 MA_A7 MA_A7 P2 P K3 MA_WEZ
MIUA_DQ10 MA_DQ10 MIUA_A9 MA_A9 MA_A3 A7 A7 A9 A11 A8 Vss WE#
N2 A3
MIUA_DQ13 MA_DQ13 MIUA_A3 MA_A3 R

1 3 5 7
Vdd A12 RFU RFU NC

2 4 6 8
R7 RFU
MIUA_DQ7 RP4 22RX4 MA_DQ7 MIUA_A2 RP18 75RX4 MA_A2 MA_BA2 L1
MIUA_DQ0 MA_DQ0 MIUA_A0 MA_A0 RFU
R3

NC
NC
NC
Vss
Vss
Vss
Vss
Vss
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssDL
MIUA_DQ2 MA_DQ2 MIUA_CASZ MA_CASZ RFU
2 MIUA_CASZ

7 5 3 1 1 3 5 7
8 6 4 2 2 4 6 8
MIUA_DQ5 MA_DQ5 MIUA_RASZ MA_RASZ
2 MIUA_RASZ

J3
J7

F2
F8

1 3 5 7
A2
E2
A3
E3
P9
A7
B2
B8
E7

R8
N1
D2
D8
H2
H8

2 4 6 8
MIUA_A13 R383 75R MA_A13 MA_A13
Close to DRAM
Close to MSD309

C 1.8VA C

R107
10k

A_MVERF

R116 C428
10k 47n

RP40
RP59 22RX4 22RX4
MIUB_DQS0 MB_DQS0
2 MIUB_DQS0
MIUB_DQS0B MB_DQSB0 MB_MCLK
2 MIUB_DQS0B 2 MIUB_MCLK 1.8VA
MB_MCLKZ
2 MIUB_MCLKZ

1 3 5 7
2 4 6 8
1 3 5 7
22RX4

2 4 6 8
RP60
MIUB_DQS1 MB_DQS1
2 MIUB_DQS1
MIUB_DQS1B MB_DQSB1 U15 W9751G6IB-25

A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
2 MIUB_DQS1B

1 3 5 7
2 4 6 8
MB_DQM1 B3
MB_DQM0 UDM

Vdd
Vdd
Vdd
Vdd
Vdd
F3 LDM

VddL
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
VddQ
Close to DRAM MB_DQS0 F7 1 2 3 7 8 9 J2 B_MVERF
MIUB_ODT R380 75R MB_ODT MB_DQSB0 LDQS A Vref MB_CKE
2 MIUB_ODT E8 LDQS# CKE K2
MB_DQS1 B7 Vdd NC Vss VssQ UDQS# VddQ J8 MB_MCLK
75RX4 MB_DQSB1 UDQS B CLK MB_MCLKZ
A8 UDQS# CLK# K8
RP13 22RX4 MIUB_WEZ RP17 MB_WEZ DQ14 VssQ UDM UDQS VssQ DQ15
B 2 MIUB_WEZ C B
MIUB_DQM1 MB_DQM1 MIUB_MCKE MB_CKE MB_DQ11 D3 B9 MB_DQ15 R378 R379
2 MIUB_DQM1 2 MIUB_MCKE DQ11 VddQ DQ9 VddQ VddQ DQ8 VddQ DQ15
MIUB_DQM0 MB_DQM0 MIUB_BA1 MB_BA1 MB_DQ12 D1 C8 MB_DQ8
2 MIUB_DQM0 2 MIUB_BA1 DQ12 DQ8

7 5 3 1
8 6 4 2
MIUB_BA0 MB_BA0 MB_DQ9 C2 D D7 MB_DQ10
2 MIUB_BA0 DQ9 DQ10

1 3 5 7
DQ12 VssQ DQ11 DQ10 VssQ DQ13

2 4 6 8
MB_DQ14 B1 D9 MB_DQ13
DQ14 E DQ13 100R 100R
Close to MSD306 Close to MSD306
MB_DQ6 F1 Vdd NC Vss VssQ LDQS# VddQ F9 MB_DQ7
MB_DQ1 DQ6 F DQ7 MB_DQ0
G2 DQ1 DQ0 G8
MIUB_A[0:13] MB_DQ3 H3 DQ6 VssQ LDM LDQS VssQ DQ7 H7 MB_DQ2
2 MIUB_A[0:13] DQ3 G DQ2
MB_DQ4 H1 H9 MB_DQ5 C433
MIUB_A4 RP8 75RX4 MB_A4 DQ4 VddQ DQ1 VddQ VddQ DQ0 VddQ DQ5 47n
MIUB_DQ[0:15] MIUB_A6 MB_A6 H K9 MB_ODT
2 MIUB_DQ[0:15] DQ4 VssQ DQ3 DQ2 VssQ DQ5 ODT
MIUB_DQ11 RP11 22RX4 MB_DQ11 MIUB_A8 MB_A8 K7 MB_RASZ Close to DRAM
MIUB_DQ12 MB_DQ12 MIUB_A11 MB_A11 MB_BA1 J RAS#
L3 BA1 CS# L8

1 3 5 7
VddL Vref Vss VssDL CK Vdd

2 4 6 8
MIUB_DQ9 MB_DQ9 MB_BA0 L2 L7 MB_CASZ
MIUB_DQ14 MB_DQ14 BA0 K CAS#

1 3 5 7
CKE WE# RAS# CK# ODT

2 4 6 8
MB_A1 M3 M8 MB_A0
MIUB_DQ6 RP14 22RX4 MB_DQ6 MIUB_A5 RP9 75RX4 MB_A5 MB_A10 A1 L A0 MB_A2
M2 A10 A2 M7
MIUB_DQ1 MB_DQ1 MIUB_A10 MB_A10 MB_A5 N3 RFU BA0 BA1 CAS# CS# N8 MB_A4
MIUB_DQ3 MB_DQ3 MIUB_A1 MB_A1 A5 M A4 MB_A6
A6 N7
MIUB_DQ4 MB_DQ4 MIUB_BA2 MB_BA2 A10 A1 A2 A0 Vdd
2 MIUB_BA2

7 5 3 1

8 6 4 2
1 3 5 7
N

2 4 6 8
MB_A9 P3 P8 MB_A8
MIUB_DQ15 RP21 22RX4 MB_DQ15 MIUB_A12 RP10 75RX4 MB_A12 MB_A12 A9 Vss A3 A5 A6 A4 A8 MB_A11
R2 A12 A11 P7
MIUB_DQ8 MB_DQ8 MIUB_A7 MB_A7 MB_A7 P2 P K3 MB_WEZ
MIUB_DQ10 MB_DQ10 MIUB_A9 MB_A9 MB_A3 A7 A7 A9 A11 A8 Vss WE#
N2 A3
MIUB_DQ13 MB_DQ13 MIUB_A3 MB_A3 R

1 3 5 7
Vdd A12 RFU RFU NC

2 4 6 8
R7 RFU
MIUB_DQ7 RP20 22RX4 MB_DQ7 MIUB_A2 RP19 75RX4 MB_A2 MB_BA2 L1
MIUB_DQ0 MB_DQ0 MIUB_A0 MB_A0 RFU
R3
NC
NC
NC
Vss
Vss
Vss
Vss
Vss
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssQ
VssDL

MIUB_DQ2 MB_DQ2 MIUB_CASZ MB_CASZ RFU

2 MIUB_CASZ

7 5 3 1 1 3 5 7
8 6 4 2 2 4 6 8
MIUB_DQ5 MB_DQ5 MIUB_RASZ MB_RASZ
2 MIUB_RASZ
J3
J7

F2
F8

1 3 5 7
A2
E2
A3
E3
P9
A7
B2
B8
E7

R8
N1
D2
D8
H2
H8

2 4 6 8
MIUB_A13 R396 75R MB_A13 MB_A13
Close to DRAM
Close to MSD309
1.8VA
A A

R310
10k

B_MVERF

R377 C431
10k 47n Title
MEMORY

Size Document Number Rev

C 3/10 0.1

Date: Friday, December 10, 2010 Sheet 3 of 10

5 4 3 2 1
 5 4 3 2 1

DVB-T TUNER
TUNER POWER RF AGC Switch

U10 U11

Q604䴴䖥tuner RFAGC㛮ᬒ㕂

4
VA1P1BF8401 VA1P1BF8402 U23
T_RF_AGC 3 2 RF_AGC RF_AGC 2
D D
LM7805 Q604

IN
12VA 3906

GND
OUT
5V_TUNER R422

1
2
3

Body
Body
IFD_OUT2
IFD_OUT1
IF_AGC
IFA_OUT
VCC_5V
SDA
SCL
AS
NC
NC
RFAGC_M
Body
Body
Body
Body
IFD_OUT2
IFD_OUT1
IF_AGC
IFA_OUT
VCC_5V
SDA
SCL
AS
NC
NC
RFAGC_M
Body
Body
5V_B 100K
L40 3.3VA

9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1

15
12
11
10
14
13
15
12
11
10
14
13
C509 FB R409
47pF 0.1u 5V_TUNER 10K
C510
5V_B 47pF 5V_B C446 R415

100uF/16V
470uF/16V
T_RF_AGC T_RF_AGC + 0.1u + 10K
3

T_SCL 2 T_SCL 2
T_SDA 2 T_SDA 2 C474 R400

CA5
IF_TV IF_TV 䴴䖥tunerᬒ㕂 Q403 1 10K

CA57
RF_AGC_SEL 2
3904
T_IFAGC 10 T_IFAGC 10
2

IF_OUT 10 IF_OUT 10
#IF_OUT 10 #IF_OUT 10

C 10 IF_AGC_DVB T_IFAGC C

SAW Drive

5V_TUNER

B B

U30
C465
IF_TV R456 47n 1 5 C87 0.1u VIFP VIFP 2
22R IN SAWOUT2
R429 L42 2.2uH
NC/390R
2 4 C89 0.1u VIFM VIFM 2
GND

ING OUT1
A A
3

F4401 close together

Close to MSD309

Title
TUNER

Size Document Number Rev

Custom4/10 0.1

Date: Friday, December 10, 2010 Sheet 4 of 10

5 4 3 2 1
 5 4 3 2 1

HDMI Input
P1 P1A HDMI CEC
21 1 DB2+ R133 10R RXB2P 21 1 DB2+
21 DATA2+ R135 10R RXB2N 21 DATA2+
DATA2 SHIELD 2 DATA2 SHIELD 2
3 DB2- R137 10R RXB1P 3 DB2-
DATA2- DB1+ R136 10R RXB1N DATA2- DB1+
DATA1+ 4 DATA1+ 4
5 R139 10R RXB0P 5 3.3VU
DATA1 SHIELD DB1- R140 10R RXB0N DATA1 SHIELD DB1-
DAT1A- 6 DAT1A- 6
7 DB0+ R141 10R RXBCLKP 7 DB0+ 2 RXB0N RXB0N
DATA0+ R142 10R RXBCLKN DATA0+ RXB0P R324
DATA0 SHIELD 8 DATA0 SHIELD 8 2 RXB0P
9 DB0- R143 10R DDCBSDA 9 DB0- 2 RXB1N RXB1N NC/33K
DATA0- CLKB+ R146 10R DDCBSCL DATA0- CLKB+ RXB1P R389
CLK+ 10 CLK+ 10 2 RXB1P
11 11 2 RXB2N RXB2N 100R
CLK SHIELD CLKB- CLK SHIELD CLKB- RXB2P cec
CLK- 12 CLK- 12 2 RXB2P HDMI-CEC 2
D 22 13 cec 22 13 cec 2 RXBCLKN RXBCLKN D
22 CEC 22 CEC RXBCLKP cec_SD R390 100R
23 23 NC 14 23 23 NC 14 2 RXBCLKP
15 DDCBSCL1 15 DDCBSCL1 2 DDCBSCL DDCBSCL
SCL DDCBSDA1 SCL DDCBSDA1 HDMIB_5V DDCBSDA
SDA 16 SDA 16 2 DDCBSDA
17 HDMIB_5V 17
DDC/CEC GND DDC/CEC GND
+5V POWER 18 +5V POWER 18
20 19 20 19 HOTPLUGB1
20 HOT PLUG 20 HOT PLUG
HDMI_H R157 HDMI_V
R152 10K

ESD-0402
ESD-0402
R153 10K
1K

HOTPLUGB1
<20pF

ESD-0402
DD50
DD55

HDMIB_HP
DB0-
DB1-
DB2-

DB0+
DB1+
DB2+

CLKB-
CLKB+

NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
HDMIB_5V 5VA
<=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF

DD54
R353 must pull up
to HDMI_5V

DD73
DD72
DD78
DD79
DD80
DD81
DD82
DD83

10K

3
R353
R354 NC/10K
Q412 1 HOTPLUGB HOTPLUGB 2
3904 1K R161

2
C C
P2
21 1 DA2+ R134 10R RXA2P P2A
21 DATA2+ R172 10R RXA2N DA2+
DATA2 SHIELD 2 21 21 DATA2+ 1
3 DA2- R151 10R RXA1P 2
DATA2- DA1+ R163 10R RXA1N DATA2 SHIELD DA2-
DATA1+ 4 DATA2- 3
5 R144 10R RXA0P 4 DA1+
DATA1 SHIELD DA1- R149 10R RXA0N DATA1+
DAT1A- 6 DATA1 SHIELD 5
7 DA0+ R148 10R RXACLKP 6 DA1- 2 RXA0N
DATA0+ R173 10R RXACLKN DAT1A- DA0+
DATA0 SHIELD 8 DATA0+ 7 2 RXA0P
9 DA0- R150 10R DDCASDA 8 2 RXA1N
DATA0- CLKA+ R147 10R DDCASCL DATA0 SHIELD DA0-
CLK+ 10 DATA0- 9 2 RXA1P
11 10 CLKA+ 2 RXA2N
CLK SHIELD CLKA- CLK+
CLK- 12 CLK SHIELD 11 2 RXA2P
22 13 cec 12 CLKA- 2 RXACLKN
22 CEC CLK- cec
23 23 NC 14 22 22 CEC 13 2 RXACLKP
15 DDCASCL1 23 14 2 DDCASCL
SCL DDCASDA1 23 NC DDCASCL1
SDA 16 SCL 15 2 DDCASDA
17 HDMIA_5V 16 DDCASDA1 HDMIA_5V
DDC/CEC GND SDA
+5V POWER 18 DDC/CEC GND 17
20 20 HOT PLUG 19 +5V POWER 18
20 19 HOTPLUGA1
HDMI_H R162 20 HOT PLUG
R158 10K HDMI_V

ESD-0402
ESD-0402
R183 10K
1K

HOTPLUGA1
<20pF

ESD-0402
DD51
DD66
DA0-
DA1-
DA2-

DA0+
DA1+
DA2+

HDMIA_HP
CLKA-
CLKA+

NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
5VA
B HDMIA_5V <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF B

DD67
R353 must pull up

DD85
DD84
DD86
DD87
DD88
DD89
DD90
DD91
to HDMI_5V

10K

3
R355
R357 NC/10K
Q416 1 HOTPLUGA HOTPLUGA 2
3904 1K R186

2
P3
21 1 DC2+ R174 10R RXC2P RXC2P 2
21 DATA2+ R182 10R RXC2N
DATA2 SHIELD 2 RXC2N 2
3 DC2- R171 10R RXC1P RXC1P 2
DATA2- DC1+ R181 10R RXC1N
DATA1+ 4 RXC1N 2
5 R160 10R RXC0P RXC0P 2
DATA1 SHIELD DC1- R169 10R RXC0N
DAT1A- 6 RXC0N 2
7 DC0+ R165 10R RXCCLKP RXCCLKP 2
DATA0+ R185 10R RXCCLKN
DATA0 SHIELD 8 RXCCLKN 2
9 DC0- R170 10R DDCCSDA DDCCSCL 2
DATA0- CLKC+ R166 10R DDCCSCL
CLK+ 10 DDCCSDA 2
CLK SHIELD 11
12 CLKC-
CLK- cec_SD
22 22 CEC 13
23 23 NC 14
15 DDCCSCL1
SCL DDCCSDA1
SDA 16
17 HDMIC_5V
DDC/CEC GND
+5V POWER 18
20 20 HOT PLUG 19
R193 10K

DC0-
DC1-
DC2-

DC0+
DC1+
DC2+

CLKC-
CLKC+
HDMI_H R190
R197 10K

ESD-0402
ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402
NC/ESD-0402

1K
A A

HOTPLUGC1
<=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF <=0.6pF
<20pF

DD93
DD92
DD94
DD95
DD96
DD97
DD98
DD99

ESD-0402
HDMIC_5V 5VA

DD52
DD69
10K

3HDMIC_HP

DD68
Title

R358
R359 NC/10K
Q417 1 HOTPLUGC HOTPLUGC 2 HDMI
3904 1K R191
Size Document Number Rev

2
R358 must pull up A2 6/10 0.1
to HDMI_5V
Date: Friday, December 10, 2010 Sheet 6 of 10
5 4 3 2 1
 5 4 3 2 1

VGA INPUT Analog Video & Audio in

HD1-Y
P4
VGA_5V 7 6 HD1-Y
R97 0R C62 1n ESD-0402 76

16
RGB0-SOG 2
DD14 VGA-HS HD1-Pb
11 1 VGA-R 5 4 HD1-Pb
VGA-G R90 33R C56 47n ESD-0402 54
6 RGB0_GIN+ 2
12 2 VGA-G DD16 VGA-VS 1
1 HD1-Pr HD1-Pr
7 3 3
13 3 VGA-B ESD-0402 2
VGA-B R91 33R C57 47n DD17 DDC-SCLIN 2 DD74 DD65 DD75
8 RGB0_BIN+ 2
14 4 VGA_RX R156 0R

R241
R254
R242
ISP-RXD 2
9 ESD-0402 P16A RCA2-R R331 10K C125 2.2u HD-Rin HD-Rin 2
15 5 R168 0R DD18 DDC-SDAIN
10 VGA-R R92 33R C58 47n RGB0_RIN+ 2 PHONEJACK STEREO SW 180d

75R
75R
75R
ESD-0402 1 R332 C69
VGA DD21 VGA_TX 2 RCA2-R 12K 200p
DD76

17
NC/ESD-0402

R110
R129
R128
DD23 DD24 DD25 ESD-0402 3 RCA2-L
D VGA_TX R119 0R R117 68R C90 47n DD22 VGA_RX NC/ESD-0402 NC/ESD-0402 D
ISP-TXD 2 RGB0_BIN- 2
R167 0R NC/ESD-0402
P6

75R
75R
75R
VGA-HS ESD-0402 ESD-0402 ESD-0402 R114 68R C91 47n RGB0_GIN- 2 RCA2-L R330 10K C126 2.2u HD-Lin HD-Lin 2
VGA-VS R111 68R C92 47n RGB0_RIN- 2
R329 C67
DDC-SDAIN R113 100R DDC-SDA 12K 200p
YPbPr IN DD77
NC/ESD-0402
DDC-SCLIN R118 100R DDC-SCL
5VA

C43

1
2
D48 R79 0R 1n COMP_SOG+ 2
BAT54C
VGA-Rin1 R112 10K C66 2.2u VGA-Rin 2 HD1-Y R84 33R C49 47n COMP_Y+ 2
VGA-5V RCA-R R327 10K C121 2.2u AV2-Rin HD1-Pb
AV2-Rin 2
HD1-Pr R81 33R C45 47n COMP_B+ 2
P4A DD19 R115 C68
VGA-5V 12K 200p R328 C55 R83 33R C48 47n

3
R121
R122
COMP_R+ 2
R120 12K 200p

16
DD100
U6 NC/24C02 NC ESD-0402 NC/ESD-0402
C73 1 11 1 VGA-R PHONEJACK STEREO SW 180d R104 68R C76 47n COMP_Y- 2
NC VCC 8

10K
10K
0.1u 2 6 1
NC VCLK 7 DDC-SCL VGA-G R102 68R C81 47n
3 NC SCL 6 12 2 2 COMP_B- 2
4 DDC-SDA 7
GND SDA 5 VGA-B VGA-Lin1 R101 10K C63 2.2u RCA-L R214 10K C124 2.2u AV2-Lin R100 68R C88 47n
13 3 3 VGA-Lin 2 AV2-Lin 2 COMP_R- 2
8 7 6 Videoin
VGA_RX 76
14 4
R125 VGA_5V P5 DD20 R106 C65 R326 C50
9
If U6=24C01/24C02,solder R125 10k 15 5 12K 200p 5 4 RCA-L 12K 200p
and left R120 float 54 DD101
10 NC/ESD-0402
ESD-0402 1
VGA P5A 1 RCA-R
3 3

17
PHONEJACK 2
2
3
VGA_TX 2 Videoin R94 33R C101 47n AV4-Vin+ 2
VGA-HS R103 100R 6 P15A
VGA_HSYNC 2
VGA-HS 5
VGA-VS R105 100R VGA_VSYNC 2 4 C71 R95
VGA-VS 1 200p 75R
7

R109
R108
AV-IN & Audio-out DD102
DDC-SDAIN NC/ESD-0402

DDC-SCLIN

10K
10K
C C

FOR UN-USED PORTS

VIDEO_OUT
5VA
2010-4-22

C41 0.1u
R56
R66 220R

2
10K
1 Q632

3
3906
C94 2.2u 1 Q414

3
2 CVBS_OUT

1
3904 H17
R59 100R R62 75R AVOUT-V TPAD

2
C271
R54 R63
4.7k 75R 2010-4-22
10uF
2010-4-22

Y R138 0R C97 1n RGB1_SOG 2

Pb R131 33R C46 47n RGB1_G+ 2

Pr R130 33R C96 47n RGB1_B+ 2

R86
R87
R88
R132 33R C51 47n RGB1_R+ 2

75R
75R
75R
R99 68R C59 47n RGB1_B- 2
R98 68R C60 47n RGB1_G- 2
B B
R96 68R C61 47n RGB1_R- 2

R48 33R C42 47n SV2-Yin 2

R51 33R C77 47n SV2-Cin 2

SPDIF_Optical Out
L44 FB 3.3VA

CA53 +
C120
100uF/16V 0.1u

P12 RCA1

1 2
3
SPDIFO 2
R78
R346 330R
NC/100R
A DD15 C27 A
NC

ESD-0402
CLOSED TO MSD309

Title
AV IN & OUT

Size Document Number Rev

A1 7/10 0.1

Date: Friday, March 04, 2011 Sheet 7 of 10

5 4 3 2 1
 5 4 3 2 1

+5V_USB

+ CA110
D D
100uF/16V
3.3VA

R189
4.7K close to USB connector

ON_USB_MOS 1

3
2 ON_USB ON_USB R61 4.7K 1 Q434
3904
+5V_USB

2
C P8 USB_A C
1 1 5 5
USB1_DMO 2
USB1_DPO 2
3 3
4 4 6 6

+5V_USB
2 USB_DP R297 0R USB_DPO
2 USB_DM USB_DMO P9 USB_A
R282 0R 1
USB_DMO 1 5 5
2 2
USB_DPO 3
DD44 DD58 3
4 4 6 6

<=2pF <=2pF
B B
NC/ESD-0402 NC/ESD-0402

+5V_USB

P9A USB_A
1 1 5 5
2 USB1_DP R298 0R USB1_DPO USB_DPO 2
USB1_DMO USB_DMO 2
2 USB1_DM 3 3
R287 0R 4 6
4 6

DD46 DD64

2010-3-3
<=2pF <=2pF
A NC/ESD-0402 NC/ESD-0402 A

Title
USB

Size Document Number Rev

A 8/10 0.1

Date: Friday, December 10, 2010 Sheet 8 of 10

5 4 3 2 1
 5 4 3 2 1

Power Down MUTE

AMPLIFIER AUDIO pre-ap HeadPhone Out 12VA 12-24

12-24 R283
5VA 10K
R294
24K R296 SHUTDOWN

3
NC/24K R306

2
mute R308 100K 1 1 Q447
Q35 10k/NC 3904/NC
A03401 R437 NC/1N4148

2
NC / 100 C270 1uF/35V 12-24

3
1N4148 Place close to OP
D P10 D40 D37 mute D

1
4
R438 12-24 R286
470 20110510 For Earphone "POP" AMP-PLout 2 2 3 PWD_MT R374 NC/10K
3906 D39 47K
AMP-PRout 3 Q622 R288 4.7K 1N4148
6VBuf1
1 R280 MUTE_TDA3121

1uF C248
+ CA55 10K 0 R295
100uF/16V CA84 PHONEJACK STEREO SW_3

+
220uF/35V

R418 33K R416 33K OP_VCC1 3.3VA MUTE_TDA3121 : HIGH = MUTE

C341 + CA83 R333
0.1uF 470uF/16V 10k

3
20110510 100uF to 470uF For Earphone "POP" R334 2.2K
HEADPHONE_DET 2 R293 10K Q424
1

3
2 MUTE_AMP
R335 3904
U45A 10K 1 Q16 CA81 +

8
47uF/16V
NPN_3904

2
3 + MUTE_AMP : LOW = MUTE
R442 1K 1 CA464 R397 330R AMP-PLout C392

1
2 AUOUTL2 AUOUTL2 C340 2.2uF R439 10K 2 - 100uF/16V 2N2
D126
C344 C342 AMP_LIN AMP-PLout

4
ESD

3
3

TL062 R404

2
mute R299 100K 1 Q433 mute R300 NC/100K 1 Q435
NC/200P 1nF 3904 NC/ 3904

2
2

R460 33K 47K 20110510 For Earphone Mute

C497 100pF

AMP_RIN AMP-PRout

3
3

OP_VCC1
mute R303 100K 1 Q445 mute R307 NC/100K 1 Q446
U45B 3904 NC/3904

8
2
2

5 + 20110510 For Earphone Mute

C R443 1K 7 CA465 R398 330R AMP-PRout C

1
2 AUOUTR2 AUOUTR2 C343 2.2uF R441 10K 6 - 100uF/16V
D127
C345 C179 R407

4
ESD
TL062

2
NC/200P 1nF
R461 33K 47K

C496 100pF
TDA3121
2010-5-8
Close to MSD309PX

CA98
220uF
+

12-24 CA96 CON4

R365
L5 1.5K 220uF
+

2
3

2 10uH/Inductor
1
CA80 + CA82 + C266 C265 C268
CA86 + CA85 + 220uF/35V 1
C253 10uF/35V
220uF/35V 220uF/35V 220uF/35V 0.1uF
4
5

0.68uF
C252 CA99 CON2
2 AUOUTL0 4.7u R278 100R 220uF
+

L6

10n
U54 1uF
3

C269

12K
2 10uH/Inductor
1 0.68uF
+

1 PVCCL PGNDL 24 2
SHUTDOWN 2 23

C236
SD PGNDL R370
C250 3 22 CA97

R317
4
5

PVCCL LOUT 1.5K

AMP_LIN R395 330R 1u MUTE_TDA3121
4 21 220uF 1
MUTE BSL C258 0.22uF
5 LIN AVCC 20
C251 6 19 CON5
CON5
C254 AMP_RIN R401 330R 1u RIN AVCC GAIN0
7 BYPASS GAIN0 18
2 AUOUTR0 4.7u R316 100R C243 C244 8 17 GAIN1
R360 AGND GAIN1 C262 0.22uF
9 16

10n
AGND BSR

12K
R369 10 15
10K 1nF 1nF PVCCR ROUT
11 VCLAMP PGNDR 14
10K 12 13
PVCCR PGNDR

C237
R320
THERMAL

B B
12-24 12-24 C257 C263C267 TPA312X
25

C264
1uF 1uF 1uF 1uF
R361 R367
10K 10K

GAIN0 GAIN1 TPA3121 MUTE PIN

R366 R368
NC/10K NC/10K LOW:OPERATING
Near MST.IC
Ground in the middle of the L/R
HIGH:MUTE

HOLE
H7 H5 H3 H1
1

1
1
1

L1
5 9 5 9 5 9 5 9

4 8 4 8 4 8 4 8 4 5
3 6
3 7 3 7 3 7 3 7 2
1
2 6
10

2 6 2 6 2 6
NC NC NC NC CON2_1

EMI Cover
H6 H4 H8
A A
1
1
1

5 9 5 9 5 9

4 8 4 8 4 8
1
1
1
1
1

3 7 3 7 3 7 H14 H13 H12 H11 H10

TPAD TPAD TPAD TPAD TPAD
2 6 2 6 2 6
NC NC NC
1
1

H15 H16
TPAD TPAD
Title
AUDIO

Size Document Number Rev

A2 9/10 0.1

Date: Tuesday, May 10, 2011 Sheet 9 of 10

5 4 3 2 1
 5 4 3 2 1

60mA
2.5V_Demod
3.3V_Demod L406 B3_3.3V L407 DR2VDD
FB0603 FB0603

3.3V_Demod
D C859 C860 C861 C862 C863 C867 C868 D
1u
0.1u 0.1u 0.1u 0.1u 1u 0.1u
R509

4.7k
closed to Demod 2 Demod_RST R510 100R

2 SCL
2 SDA

SCL
100R SDA
100R
10K
10K
10K
B4_1.2V
B3_3.3V
B4_1.2V

DR2VDD
B4_1.2V
1.2V_Demod L410 B4_1.2V 120mA 2.5V_Demod L408 AD_AVDD

R511
FB220/300mA FB0603

R513
R512
R514
R515
C874 C875 C876 C877 C878 C879 C880 C869 C871
1u 0.1u

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 1u B3_3.3V U55
49 VDDS
R516 33R C866 R517 0R #IF_OUT

SCL

VSS
VSS
VSS
VSS

SDA
2 TS_D5 #IF_OUT 4
C0402

VDDS

DTMB
VDDC
50 32 AD_DVDD

DTCLK
VSS AD_DVDD

TSMD1
closed to Demod 31 L409

SYRSTN

DR1VDD
DR2VDD
DR1VDD

STSFLG1
AD_DVSS C864 1u
51 STSFLG0 ADI_AIP 30 NC
29 C865 1u L0603 NC
ADI_AIN R518 0R IF_OUT
ADQ_AIP 28 IF_OUT 4
2 TS_D4 52 27
2 TS_D3 SLOCK ADQ_AIN C870 0.1u
53 RERR AD_VREF 26
2 TS_D2 54 25 C872 0.1u

7 5 3 1
RLOCK AD_VREFN

8 6 4 2
2 TS_D1 55 24 C873 0.1u
PLLVDD RP61 33RX4 RSEORF AD_VREFP
B4_1.2V 56 VDDC
2.5V_Demod L411 AD_DVDD 2.5V_Demod L412 57 23
FB0603 FB0603 VSS AD_AVSS
58 PBVAL AD_AVDD 22 AD_AVDD
2 TSVALID 59 21 C881 1500pF
C886 C888 2 TSSTART SBYTE FIL
60 SRDT
1u C885 C887 2 TS_D0 61 20 PLLVDD

7 5 3 1
SRCK PLLVDD

8 6 4 2
0.1u 1u 0.1u 2 TS_CLK 19 C882 18p
C883 X1 Y2
C 62 C
1

RP62 33RX4 NC/10p VSS R519 25.4MHz

X0 18
B4_1.2V 63 VDDC R520 3
closed to Demod 64 17 1M
B3_3.3V VDDS PLLVSS C884 18p
2

TSMDO
XSEL1
XSEL0
VSS
SLADRS1
SLADRS0
AGC I
S_INFO
AGCCNTI
AGCCNTR
CKI
TNSCL
VDD33
TNSDA
VSS
VDDC

1K2
TC90517FG

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

3.3V_Demod
L10
2.5VA FB 2.5V_Demod

10K
10K
10K
10K
10K
+ C897 C896 R530 R531 15K
100uF/16V 100nF 1K 1K
C0402
R529 10K

R523
R524
R525
R526
R527
R528
B3_3.3V
B4_1.2V

R521 NC/33R
2 TS_D7
R522 NC/33R
2 TS_D6

IF_AGC

C893
100nF
C0402

4
N1

IN

ADJ
OUT
AMS1117-3.3V

1
2
3
3.3V_Demod
B B

5VA
C858
C856 + C857 0.1u
+ C894 C855 0.1u 100uF/16V
100uF/16V 1u

5VA 3.3V_Demod

R532 R533 Close to tuner

NC/1K NC/1K
R535

4
1K

IF_AGC T_IFAGC T_IFAGC 4

C895
N2 100nF

IN

ADJ
OUT
AMS1117-1.2V

1
2
3
AGC CIRCUIT
1.2V_Demod

3.3V_Demod
C892
C890 + C891 0.1u
C889 0.1u 100uF/16V
1u

A A

Title
ISDB-TC90517FG
Size Document Number Rev
A2 Demodulator 1.0

Date: Tuesday, December 14, 2010 Sheet 10 of 15

5 4 3 2 1