NAME : SUDHAN RAJ M

ID NO : 19MV36
DEGREE : M.E
BRANCH : VLSI Design
COLLEGE : PSG College of Technology, Coimbatore

Father’s name Manickarajan S Permanent Address

Gender Male 23, Ponnammal
Date of Birth 21st June 1998 Nagar,Nesapakkam,
Languages English, Tamil Chennai- 600078,
known Email sudhanraj.m@gmail.com Tamil Nadu.
Mobile +91-9500495472

ACADEMIC RECORD

Completion Marks
Course Institution Board
By (%)
Sri Krishnaswamy
Matric Higher
X State 2013 91.4
Secondary School,
Chennai
Chinmaya
Vidyalaya Higher
XII Secondary School., State 2015 85.8
Chennai
B.E(EIE) Meenakshi College of Anna 2019 7.4
Engineering., University
Chennai

Semester I II III IV
CGPA / 10 8.42 8.9 - -

AREAS OF INTEREST
 VLSI Physical Design
 RTL Design Using Verilog HDL
 Low Power VLSI Design
SKILL SET

Languages C Programming
Platforms Linux, Windows
FPGA Boards Zedboard, Basys3
Tools Cadence - RTL Compiler, SOC
Encounter,Virtuoso, NC-Launch
Mentor Graphics – QuestaSim 10.0b, Tessent.
Xilinx – ISE 14.3, Xilinx System Generator,
Vivado Design Suite-2017.1
MATLAB- Simulink,
UG PROJECTS

 TITLE:INTEGRATED HOME SECURITY AND AUTOMATED SYSTEMS using

ESP32( WiFi Ready Embedded System).

PG ACADEMIC PROJECTS

RTL Design and FPGA implementation

 Design and implementation of 8 bit RISC Processor using Basys3 board

 Design and implementation of control path and data path for Sequential
Multiplier in Basys3 board

Physical Design

 Design and implementation of 8 bit RISC Processor from RTL to GDSII

using Cadence tool suite(180nm technology)
 Performed functional verification using Cadence NC Launch
 Synthesized using RTL complier and analyzed area, power and timing reports
 Physical design is done using Cadence Encounter
 Performed pre-layout and post-layout simulation with IO PADS.

Hardware verification

 Design and simulation of Verification Environment for Dual-port

RAM using Questasim.
 Performed Code coverage and Functional coverage.

Low power VLSI design

 Design and power estimation of Double Edge Triggered Flip Flop using Cadence
Virtuoso.
 Design and power estimation of 4 bit comparator with precomputation logic
using Cadence Virtuoso.

Digital IC Design

 Design of MUX-OR BASED CARRY LOOKAHEAD ADDER

using Cadence Virtuoso(180nm technology).
ACADEMIC ACHIEVEMENTS AND EXTRA-CURRICULAR ACTIVITIES

 3rd Department Topper of B.E. Electronics and Instrumentation Engineering in

Meenakshi College of Engineering of all 8 semesters.
 Undergone Internship in VP PETRO6 Engineers and consultants, Chennai (DEC 2017).
 Undergone Internship in YOKOGAWA INDIA LIMITED, Bangalore (MAY to JUNE
2018).
 Organized an Industrial Visit to Ennore Thermal Power Plant for Instrumentation
Engineers in Meenakshi College of Engineering.
 CLASS REPRESENTATIVE for 4 semesters in UG .
 Completed Proficiency Course in British Council, Chennai.
 Completed NPTEL course on VLSI PHYSICAL DESIGN during ME VLSI course.

DECLARATION
I, Sudhan Raj M, do hereby confirm that the information given above is true to
the best of my knowledge.

Place: Coimbatore
Date: ( Sudhan Raj M )