A 75.5-to-120.

5-GHz, High-gain CMOS Low-Noise Amplifier

De-Ren Lu, Yu-Chung Hsu, Jui-Chih Kao, Jhe-Jia Kuo, Dow-Chih Niu*, and Kun-You Lin
Department of Electrical Engineering and Graduate Institute of Communication Engineering, National
Taiwan University, Taipei 10617, Taiwan
*Chung-Shan Institute of Science and Technology (CSIST), Taoyuan 325, Taiwan

Abstract — In this paper, a high-gain and wideband low-noise

amplifier using 65-nm CMOS process is proposed. A four-stage 30
Gmax (4 fingers) NFmin (4 fingers)
8
cascode configuration is adopted to achieve the high gain and
wideband performance. With 24-mA dc current and 2-V supply Gmax (8 fingers) NFmin (8 fingers)
25 7
voltage, the LNA not only provides gain higher than 20 dB from Gmax (12 fingers) NFmin (12 fingers)
75.5 GHz to 120.5 GHz, but also has a measured noise figure
between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB 20 6

MSG/MAG (dB)
compression power (OP1dB) is -3 dBm at 110 GHz, and the chip

NFmin (dB)
size is 0.55 × 0.45 mm2. 15 5
Index Terms — W-band, low noise amplifier, MMIC, CMOS.
10 4

I. INTRODUCTION
5 3
There are several applications including astronomy
telescope, imaging, and radar systems in the W-band regime. 0 2
In the past, most of the W-band amplifiers are realized by III- 70 80 90 100 110 120 130 140 150
V technologies such as GaAs and InP pHEMT processes. Frequency (GHz)
Recently, thanks to the great progress of the CMOS Fig. 1. Simulated MSG/MAG and NFmin of the cascode configuration
technologies, more and more W-band LNAs are implemented with unit gate width of 2 μm.
by advanced CMOS processes [1]-[7]. By using 90-nm CMOS
technologies, a 104-GHz three-stage common-source (CS)
LNA is proposed with 9.34 dB gain in a narrow bandwidth [1],
and a three-stage cascode LNA achieves a wideband
performance from 86 to 108 GHz with a peak gain of 17.4 dB
[2]. Several LNAs implemented in 65-nm CMOS are
presented with gain lower than 15 dB [3]-[6]. A high-gain
LNA with a peak gain of 27 dB is demonstrated by five-stage
cascode configuration [7].
In this paper, a W-band LNA adopting four-stage cascode
configuration in 65-nm CMOS process is presented. This
design achieves a measured small-signal gain which is higher
than 20 dB from 75.5 to 120.5 GHz. The noise figure from 87
GHz to 100 GHz is 6-8.3 dB. With the wideband, high-gain
and low-noise characteristics, the LNA is suitable for the
wideband applications in W-band.
Fig. 2. Circuit schematic of the proposed W-band LNA.
II. CIRCUIT DESIGN Simulated maximum stable gain (MSG)/maximum available
This circuit is fabricated in TSMC 65-nm CMOS process. gain (MAG) and NFmin of cascode configuration under various
The process provides one poly layer for the gates of CMOS finger numbers with 2-μm unit finger width are shown in Fig.
transistors, nine metal layers with ultra-thick top metal (metal 1. It shows that using smaller device results in lower NFmin.
9) of 3.4 μm for interconnections, and metal-insulator-metal However, the transition frequency of MSG and MAG
(MIM) capacitors between metal 8 and metal 7. Based on the increases when a 4-finger transistor is selected for the cascode
model provided by foundry, the NMOS device in common- configuration. This means the cascode device is more unstable
source configuration has a maximum oscillation frequency in the desired band. Finally, the device with 8 fingers and total
(fmax) of about 220 GHz under 1-V drain-to-source voltage. gate width of 16 μm is selected in this design due to the trade-
In order to achieve high gain performance and minimize the off between gain and noise performance. The cascode device
chip size, cascode configuration is selected for this design. has 12-dB simulated MSG at 130 GHz and demonstrates 3.4-

978-1-4673-1088-8/12/$31.00 ©2012 IEEE

 50

25 100

T
TLp=0 μm

TLp=200 μm
10 80 GHz 250
80
0 GHz
Γ*out@TLP=0 μm
Γ*out@TLP=50 μm
10 25 50 100 250
Γ*out@TLP=100 μm
Γ*out@TLP=150 μm
-10
Γ*out@TLP=200 μm -250 Fig. 5. Chip photograph of the widebannd LNA with the area of 0.55
x 0.45 mm2.
ΓL 30
25
-25 -100
20
-50 15
Fig. 3. Simulated Γ*out at different TLp and ΓL.

S parameters (dB)
10 Sim. |S
S11| Meas. |S11|
24 Sim. |S
S21| Meas. |S21|
TL
Lp=0 μm 5
22 Sim. |S
S22| Meas. |S22|
TL
Lp=50 μm 0
20
TL
Lp=100 μm -5
18 TL
Lp=150 μm -10
16 TL
Lp=200 μm
MSG/MAG (dB)

14
12
10
8
6
4
2
0
40 50 60 70 80 90 100 110 120 130 140 150
Frequency (GHz)
Fig. 4. Simulated MSG/MAG of the cascode devicee with different
lengths of TLp.
5.4 dB NFmin from 80 GHz to 120 GHz whhile 2 V/6 mA is
consumed.
To implement a LNA with a gain better thaan 20 dB from 80
to 120 GHz, the four-stage design is adopted.. Fig. 2 shows the
complete schematic of the proposed widebband LNA. The
matching networks are realized by thin-film m microstrip lines
(TFMS). The ultra-thick top metal is used as signal line of the
TFMS, and the ground plane is implemented by metal 1 and 2
to meet the requirement of density rules. In thhe first stage, the
source feedback is adopted, and the input mattching network is
consisted of series transmission lines, an openn stub and a short
stub to achieve wideband noise matching. The inter-stage
matching networks are realized by series trransmission lines
and short stubs.
Although the cascode configuration proviides a high gain
characteristic, the output impedance is too hhigh to achieve a
wideband impedance matching at the outpuut port. To solve
this problem, an extra transmission line (TLp), as shown in Fig.
2, is placed between the CS and common-gatee (CG) transistors
of the cascode device at the final stage. F Fig. 3 shows the
simulated conjugate output reflection coefficiient (Γ*out) of the
-15
-20
-25
65 70 75 80 85 90 95 100 105 110 115 120 125
Frequency (GHz)
Fig. 6. Simulated and measured S param
meters of the wideband LNA.
four-stage amplifier with the new final stage device. When the
length of TLp increases from 0 μm to 200 μm, Γ*out decreases
correspondingly and makes the wideband impedance matching
easier. However, the transition freq quency of MSG and MAG
decreases with increasing length of o TLp, as shown in Fig. 4.
This shows a trade-off between the gain and the bandwidth of
output return loss. Finally, a 190 0-μm TLp is selected. The
output matching network is simillar to the input matching
network and is consisted of series lines, a short stub and an
open stub. The reflection coefficieent of the output matching
network (ΓL) is shown in Fig. 3. It is close to the Γ*out of the
four-stage amplifier with the final cascode device which has
190 μm TLp. The die microphotograph is shown in Fig. 5. The
2
chip size which includes all the totaal pads is 0.55 x 0.45 mm .
III. MEASUREMENT
T RESULTS
The proposed LNA is measured d by on-wafer probing. To
implement wideband S parameterss measurement, the vector
network analyzer (VNA), Anritsu 37397D, is used for the
measurement from 65 to 110 GH Hz, and the VNA, Agilent
E8361C, is used for the measurem
ment from 110 to 125 GHz.
This LNA consumes 48-mW dc power from 2-V supply
voltage. Fig. 6 shows the sim mulated and measured S
parameters of the proposed wideb band LNA. The measured
peak gain is 25.3 dB at 117.5 GHzz, and the measured gain is
higher than 20 dB from 75.5 GHzz to 120.5 GHz. The input

978-1-4673-1088-8/12/$31.00 ©2012 IEEE

 TABLE I
COMPARISON WITH PREVIOUSLY REPORTED W-BAND CMOS LNAS.
Ref. CMOS DC Power Chip Size
Topology Peak Gain (dB) Gain (dB) NF (dB)
Process (mW) (mm2)
[1] 90 nm 3-stage CS 9.34 @103.8 GHz - - 22@1 V 0.36
[2] 90 nm 3-stage cascode 17.4 @ 91 GHz > 14.4 (86-108 GHz) - 54@2.5 V 0.42
[3] 65 nm 6-stage CS 12 > 9 (75-81 GHz) 9-10.5 (75-81 GHz) 32.4@1.2 V 0.24
[4] 65 nm 4-stage CS 14.8 @ 90 GHz > 11.8 (82-103 GHz) 7.5-9 (82-100 GHz) 86.4@1.2 V 0.33
[5] 65 nm 5-stage CS 15 @ 86 GHz > 12 (81-92 GHz) 7-9 (85-95 GHz) 42@1.2 V -
[6] 65 nm 3-stage cascode 13.5 @ 81 GHz > 10.5 (72-92 GHz) 6.4-8.4 (75-88.5 GHz) 36.3@1.5 V -
[7] 65 nm 5-stage cascode 27 @ 88 GHz > 24 (83-93 GHz) 6.8-10 (75-89 GHz) 36@1.2 V -
This Work 65 nm 4-stage cascode 25.3 @ 117.5 GHz > 20 (75.5-120.5 GHz) 6-8.3 (87-100 GHz) 48@2 V 0.25
10
Simulated NF from 87 to 100 GHz. The OP1dB of -3 dBm is obtained at 110
Measured NF GHz. This circuit accomplishes wide bandwidth
8 characteristics with high-gain and low-noise performance by
using 65-nm CMOS technology.
6
NF (dB)

4
2
0 2219-E-002-005, Excellent Research Projects of National
85 90 95
Frequency (GHz)
Fig. 7. Simulated and measured noise figure of the wideband LNA.
and output return losses are both better than 5 dB from 75.5 to
120.5 GHz. The measured results agree to the simulated
results reasonably. Fig. 7 shows the simulated and measured
noise figure, and the measured noise figure is 6-8.3 dB from
87 to 100 GHz. Output power versus input power is also
measured. The OP1dB are -5, -6 and -3 dBm, while the
saturated output power (Psat) are -2.5, -3 and 0.5 dBm at 78, 94
and 110 GHz, respectively.
TABLE I summarizes the comparison with the previously
reported W-band CMOS LNAs. The proposed LNA
demonstrates high gain, low noise figure and wideband
performance in a miniature size.
VII. CONCLUSION
A W-band LNA using TSMC 65-nm CMOS technology has
been designed, fabricated and measured. The circuit achieves
high gain and wideband performance. The four-stage cascode
circuit topology is used to obtain a high gain performance, and
a transmission line between the CS and CG transistors of the
cascode device for the final stage is added to achieve
wideband output matching. This design demonstrates a
measured small signal gain which is better than 20 dB from
75.5 to 120.5 GHz. The measured noise figure is 6-8.3 dB
ACKNOWLEDGEMENT
The authors would like to thank Prof. Huei Wang and Dr.
Zuo-Min Tsai of National Taiwan University for their
valuable suggestions. This work is supported in part by the
National Science Council of Taiwan, under Grant NSC 100-
100
Taiwan University, under 10R80919-3, 10R80300 and the
University Shuttle Program of Taiwan Semiconductor
Manufacturing Company (TSMC), Hsin-chu, Taiwan.
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978-1-4673-1088-8/12/$31.00 ©2012 IEEE