MAXIM 12 Bit A/D Converter With _ General Description The 1OLTID9 fs a monoithie 12 Bit A/D converter @ designed for eaby infortaco with microprocessors nd LARS. The *2Btoinary plus polarity and over™ fange outputs can be dractyintelacedtsario. —g processor bus. ninismogethe ICL? 001s controled Eyrime microprocessor trough the chp sel! and ‘lo bye enable inputs, For remote data logging Dentetiong tre 101108 outputsareeasiycomeetod {52 Unt parvmake mode, werng with inoutty $Sandard UABTTs to prowds sonal Cala varsmisson ‘Tis device otters ign accuracy by oneringrollover Grrorto ess man T count ange reading enh fess tian pV. In many data acgusiion systems the 1617100 iam atracive, fom cost one-per= channel afernative 19 analog ruliploxing due to is low power consumption and input bias Current. Maxim has acded a zero‘ntegrator phase to the 1s toe elimnating overrange fengover ross and nystoressellacts Maxim hes aso increase ie Gurrertsoureng eapabities of te ICL? 109. enaoling IRtorapely dre the large eapactances ofion found ‘paimieroprocessor busses. Applications “This devi is used in awide range} data acquisition and contl applioatione. Most appications mich the measurement of analog data Pressure ‘Speed Voltage Resistance Flow” Weight Temperature Power Current i Typical Operating Circult 3-State Binary Outputs ___ Features Improved 2nd Source! (See Ord page for “Maxim Advantage™). Zero integrator Phase for Fast Overload Recovery Hysteresis and “Crossalk” Eliminated Enhanced Bus Driving Capability ‘Byte Organized Three-state Outputs LUART Handshake Mode for Sera interfacing “Tue Differential Input and Reterence Up to 30 Conversions per Second Significantly Improved ESD Protection Monolithic, Low Power CMOS Design Ordering Information O'S to POC a Load Pat (GarvACGH—O°S tn 7M Lene Plane On Carr ANGCD 9S wee De | a _ Pin Configuration Top View teed OP Seq tnt ap tor tod Cn Cur en MAXIM ee Call toll free 1-800-998-8800 for free samples or literature. 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs ABSOLUTE MAXIMUM RATINGS Positive Supply Valage (GND tov") -62y ‘Negative Supa vattags (GND to V) ay “S805 Tas +1250 PeaiogInptt Voltage Lo ory (Note 3)... VE to Coralp Package (GIL) DOG ts aoe Reterance input Vottage (bo or i) (Note tj) Vo Pasle Package (CPL) OG Tas 0S Bigtal npu Gage Paste Grip Carrior (os 2.24) Not Sy... GND-OSY. | ee Rots Err (erence | a Sea tons to 42360 ‘ington po an wn seas scaamuwsooty || | we | a | com _nag. inputs near full scale) bis Yornper Common Mode Rejection ano | onmn | YTV, * ww inp Caran Mode Rane | VER inpu pit ow, Common ras ra owe (6 a 1 Yn 00 : a exceeded 95% of time) Full Scale = 409.6 7 a Tiseatenerse 5) Be) eS Leakage current at Input u {uric Tew - | ~ tame he | fetrone ‘ae £4 aso fm | i | pe L | tetraacetate P| |e Zea Reig a v=o [ee are Seal Fatt Tenpeare “= > 74 eng tte | pom sence | Binet oon e Sin Cuvee Ww GWOT] Va 8, rant Ose ao_[ woe | a caren — Sour Cross supply Guetv" 0 touop_| RES 3.29 open ro wo | a retered V7 24 ze | az |v at Ou Yotge wer | Somesteananerour | 2 Fat oa Tp, Coma 25k btwn rd REP OUT = aan Inout Common Mode Range | Yow | INHLINLO, COMMON vis] Ye] veal ov vivo] 8) se yo apne pl i AS TSA Nee seats tito tanta Snag cause Soexcte See ep fo tharessontiafceomardes Sarno ue SSRIS SR Se serie tommer sus secmone cet iSpeesissatel os ee nates te sens Tarlnt Settee aint tt ce ror pion 1 incr te eae teed et eo ees aracanstes Yeo" tang men cassie excess rom the orginal manvactrers data sect have Doth nuded sn ths dita set MAXIM- MAXIM 12 Bit A/D Converter With 3-State Binary Outputs and Hysteresis Eliminated ¢ Significantly Improved ESD Protection (Note 4) ABSOLUTE MAXIMUM RATINGS ths covicecontormsto he Absolie Manu Ratings on he sotesnt page ELECTRICAL CHARACTERISTICS (= 65K, = 8V, GND = O¥. Ty = 25°C: Test Gut Figure 1: unless noted) ‘ANALOG SECTION - PARAMETER svwoo0 ‘CONDITIONS ‘outhos Sts MAXIM — a 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs ELECTRICAL CHARACTERISTICS (Allparameters wih > = 180. Y"=-6V,GNO =OV, Ta = 28, ules ted) PARAMETER sywsot ‘CONDITIONS in| te [wae ns ‘ure igh vage vou | Bae ai on as fa | | utp tow Vion Wor [lowe = 168 o [ey ‘up eacane Curene — [ins 3-16 nam moosanss of |] onto v0 Putup Coren Fon 8,32 = Vr a 5 J“ MODE ut GND. ” Cone oss BEN Fin 9 BEN Pn ote Inout righ vnige | vw _—| Pea 8.7 2s v to rtorea 3 GN | ve | retorts 6 _ Pins 26 27 voyr =a up Curent Ping V7. 24our= VP Input Pudown Curt int Wout = GND TV isto Output Cure [Hh _Son_| Nour = 25 oe {lw 00.) Vour= 250 uted Oseiaor ——(Hgh Bon | Vour= 25 ‘he satel arctic above rg a open of» porton of ners ght 99:14) dts book Thi intron does 108 vata ay voter by ism at ines proaues wil pein aceooanca mth hare shentone fe ccna horace Tae” song wih deserve occres Wah he egal manatees eae se! hav 5 Meaod ns daa eet 18 oe compare ures bm —, Ba. Semoan or a Sap —__3. Esa —agr mr moe BoMAXIM 12 Bit A/D Converter With 3-State Binary Outputs ELECTRICAL CHARACTERISTICS specitstons betow say or sxnad al “tesa paranatert on astcont 2850 (Wr -54,¥"~“8V.GND ~O¥, Ta 25, unions noe) DiarraL section ” PanaweTen | SYMBOL ‘ouput High Votiage You sienna eae ion Wotage a ‘uput Leakage Curent Bins 58 igh npc 18,20 You) VW inputs cu v1 BEN Fin 18 contol V0 Patlup Curent Conver Lonang Pin 18:2, 26, 37 Input Lom Vane ve | Feros te Gnd er oe [ses oe ‘owe Note 6) vp Enable wth ‘een_| Woe from Cup Enable fosc_| (Mote 6) ‘rom Cop Enble i MAnm 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs Table 1. PIN FUNCTIONS: [pin] FUNCTION | TYPE] DESCRIPTION in] FUNCTION | TYPE DESCRIPTION. loge. Ov ‘Sulput made. Makes CBEN. sa oa comer ateacamial icant cuca Beet, ree ngnae ce Sa ee RE, Sore Seats Eccuperien arene az [ose | wet [oom ser — famy-w-Fosmetoa| [a fosseut [usu Oxrasroroe ne Sinton] | aes oa arg Seas as ro oo ESSN SEE our Hee = ee | Cea TN ae | sprereca eases | aH viel Sohne jer] fae] frmorecs Sere cece em ler os ae nes = ee sole | _ beer 7 Yam Tain i oe Rae alee | mode. Connect 3v Connect to <5V if not used. a eee ~ 7 CBEN ‘wpa | Low Byte Enable ale Napatie suppl. Nominaiy eee ! ‘Pion Ser ce Rann marae ‘outputs 81-88. gn ___} Cutput| Butter “ mwa SEE aver | [SPORES | ee TE iscad Faron | Ho Rear — i ag as] So —— High Bie Enabdie low | "95 INPUT HI High side ef sitferent ‘outputs A9-B12, POL & OR. +36] Fer Positive input of ferential coo) Bas roe een eh ae Pot | Gapeeree Teas oar oo Bees ay ——[ ter sb Ra GEN an CHEW orton Bina GR. Outpt) In andanake mse aon as Hobe ens pn becomes Note: Adiga ovals are poate tu MAXIML 12 Bit A/D Converter With 3-State Binary Outputs _______ Detailed Description Analog Section “The equivalent circuit of the Analog Section ofthe (CL7109 8 anown in Figure 2 The circuit will perform Conversions ata fate determined by the clock fre~ Queney (8192 clock periods per eycle) when the RUN'HOLD input is left open oF connected to V Each measurement cyele is divided into four phases fs shown in Figure 8 They are. 41. Auto-Zero (AZ) 2 Signa Intagrato (INT) 3. Desirtegrate (DE) 4. Zero Integrator (21) ‘Auto-Zoro Phase ‘Thrge events occur during Auto-zera. Tne inputs, nM and In-Lo, are disconnected trom the pins ans informally snorted toanalog common. The reer~ ‘noe capacitor Is charged to the reference voliage. tasty, feedback loops closed around the system {Geharge ieauto-zero capacitor Cazt0 compensate ‘or affet voltages in the comparator. bufferampiier fang inlegrator The inherent nove of the system ‘etermines he A-Z accuracy. ivany avent, the otfect Folerad to the input ie lass than 10 Signal Integrate Phase The internal input high (In-Hi) and input ow (In-Lo} fre connected fo the external pins, tne internal short is\removed and the auto-zero loop ts opened. The Converter then integrates. the differential voltage Betwaen Ie-Hi and In-Lo fora fixed time of 2048 Clock periods. Note that this cifferential voltage must ‘be'wiin the common mode range of the inputs. The MAXIM _ polarity of tne integrated signa is determined at the fend of this phase, De-integrate Phase ‘The third phase is De-integrate, also known as refer- ence Integrate. input high Is internally ‘connected fcross the previously charged reference capacitor nd Input low ss internally connected to analog Commer. The polarity detection citcuttconnects ime Feforence capacitor with the polarity such that the Integrator output returns with a thxed slope to the zero level established in the Aulo-Zoro phase, The time required for the output 10 return to zero (represented by tenure a lock periods counted} |S proportional to the input signal Zoro Integrator Phase Input low is shorted to analog, Corwmon and the releronce capacitor is charged to the reference Voltage. A feedback loop is closed around the system te ineut high, causing tho integrator output to return rapidly to zero (See Figure 3) This phase normally lasts detwoon 16 and 32 clock pulses buts extended 10-7552 clock pulses after a7 Overrange conversion, ‘This phase will remove any residual charge left on the integrator ospactor after an overioad reading ‘This Zero Integrator phase virtually eliminates tye problem of isractan or “crosstalk Betwean tne var us channais of a Maxim ICLT108 based multiple Channel data aequistion system, Without the zero Integrator phase, an overload on one channel would Jeave charge on the integrator capacitor. which ‘would then be fransterred to the autozaro capacitor uring the autozera cycle. resulting in an erroneous reading for ie next channel that's measured after fhe channel with the overloes, 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs — Frage Comoran Ting UN OTD Pn Hh) Ditlerentiat Input Differential input voltages anywhere within. the common-mode range of the input amplifier can be accepted (Specifically from 15V below the postive Supply to 1.5V above the negative supply). The System has & OMAR of 86d8 typical in this range. For optimum performance the input voltage at In-Lo fand th-tii should not come within 2 vote ot ether the positive or negative supply. Care must be exer. ised to ensure that the integrator output does not Salurate, since the integrator also swings withthe Gommon-mode voltage. A large positive common= ‘mods voltage with a near full-scale negative ifferen- tia input voltage ‘s'@ worst-case condition. When most! the swing has boen used up oy the positive Sommoremode voltage, the negative input signal Srives the Integrator positive, Tre integrator output Swng can be reduced to less han the recommended 4V foll-seale swing witn tte loss of accuracy 19 these ‘crical applications. The integrator output an swing within 0.3V of either supply without loss of inesny. ‘The ICL7109 has been optimized for operation with Analog common near cigitalground Thisallowstora AV full Seale integrator swing posite or nogative ‘which maximizes performance of the analog section with =8V power supplies, Differential Reference ‘The reference voltage can be generated anywhere within the power supply voltage ofthe converter. The main souree of common-mode error fa rall ovar Voltage. This is caused by the reference capacitor losing or gaining charge to stay capactance on ts noses. The reterence capacitor can gain charge aoe | A a a ae {increase voltage) it there is large common-mose voltage. This is the result of a positive signal de Integration, In contrast, the reference eapacttor wil los charge (Soerease tage) uron deantegraing 4 negative input signal. Roll over error defines the Sifference in ratorance for positive or negative input ‘Voltages. This error can be nel to less than one Rall ‘Count for worst-case condition by using an optimum erence capacitor (See component value seston ) By having the reference common rode voltage neat Gratanalog COMMON, thevolvovererrorlam these Sources is minimized. Component Value Selection Care must be exercised in the selection of values forthe. integrator capacitor and resistor, "auto: Zero capacitor relerence voltage, and conversion Fate for optimum performance of the analog sec tion, “The ‘optimum values must be selected for ‘each application Integrating Resistor oth the integrator and butfer amplifier havea class output stage with a quiescent current of 100 nA tihieh can supply 20,.A with negigibienon-ineahty ‘Tho infograting reatstor shouls small enough ?at Undue leakage requirements are not placed @n the BC" oard. but large enough to keep the. output Current tess than % yA“ For 3.46 vot fal sale SOOktt is optimum and similarly 20K11 fs optimum fora 409.6RV scale For one Ulscale voltages, Rat should be selected by the relation {ull sale voltage (m¥) Fecr= full scale voltage (MV) yy 2 uk _MAXImMIntegrating Capacitor CCivr (tne integrating capacitor) should be selected for maximum integrator output voliage swing with- fut saturation of the integrator (at. Svolt from either Supply). A #35 to ta volt integrator output swing is ineal for the ICL7109 with a5 volt supplies and fnalog common connected to GND. Nominal values for Car and Cazare0.16 uF and0.$3 uF, respectively, for Tis conversions per. second. (61 4akHz. clock frequency), These values should be changed to ‘aintain'the integrator output voltage sing, it Biferent clock requencies are used. The value of Ghats generally given By Con ~ —(2088.x clock period) (20 WA) yp Integrator output voltage swing W ‘To prevent rollover and linearity erors alow dielec- thc absorption eapaettor fs required. Polypropylene Capacitors give undelgctable errors al reasonable Gost upto 88°. Tetlon "capacitors arerecommended for the miltary temperature range. Polypropylene {and Teflon” capacitors should give lee than 08 Gount ‘of error cue fo dielectric absorption even though their absorption characteristics vary some” what tram unit unl ‘Auto-Zero Capacitor ‘The Maxim ICL7109 has a zero integrator phase nich ensures that any charge left on the integrator liter an overrange Teasing Is removed before the Autozero phase i starteg. This zero integrator phase dlows the use of larger values otautozero capacitors than allowed with olhor manufacturer ICLT 108s Normally: the optimum value of the autezara sapact {aris between 2 and dimes the valusof the integrator teapacitor The typical value ofthe autozerocapacttor 150.38 4h Lower values of Cyzincresse nenovsein the ‘lutozero loop, very large value wil taka longer time fo charge tothe proper value ater power-up. The outer fol of Caz should be connected to the in, Gir Sureming junction and the inner foil to pin $1 for optimal rejection of stray pickup. Similarly, fre inner fol of Civr should be cotmacted to he RC Summing junction, ana the outer follet Gir should bbe connected to pin 82. Above 85°C, Tellon™ or fequivalent eapacitors are recommended for weir low leakage characteristics Roterence Capacitor Good results can be achieved in mast applications with 21 uF capacitor. A larger value is required to prevent roll-over orror whore a 409.6mv sealoisused End a large common mode voltage exists (Le, The Felerence fow is not at analog common). The rol ‘ver error can generally Bo held to one half count by. ‘durin thiscase. Above 85°C, Tevlon'* or equivalent Capacitors are again recommended for thelr low feakage characterises. MAXIM 12 Bit A/D Converter With 3-State Binary Outputs Aeterence Voltage ‘An analog input of Vv = 2 x Vaer generates a ful Scale output 64006 counts, ora normalizes sae reference of 204 8m sold be used for 2408 rd {ul sea (100. per USB}. and 1 028V reference shouldbe used for a 2.048 full sale (500 por 33) There wil exist a scale factor other than unity benweon the absolute output voliage tobe measured anda desired cigital output many applications ‘tere the A/O Is sonsing the output of atansucer in'a waxghing system, for exarplo, the sesgner ould possibly want full seale feacing wher te ‘ollage from tho transducer Is O882V, The Input Voltage sould be measured ciecy and areterance Vollage of © 90 should be used Inteadof ducing the inpat down to 408.6. Skit and O19 uF are Suitable vaiues for the Integrating reslstor and apacttor”A divider on the input 1s thus avoided When @ 2or0 reading i dosited for non-20ro put srother advantage oft systom realizes Examples imigh include temperature and weight measurements wifan offset or fare Te oveet may be ttoduced By connecting the voltage output ofthe vanscucer Began common snd avai hgh and hw ot Yoltage between common andanaig iow observing polariescorelulyltmay bemoreetfcent however {o perform tis tyoe of sealing or tare subtraction italy using soltware in processor based systoms cing the e708 Reference Sources [A major factor in the overall absolute accuracy of ‘he converter the stability of the reference votage, The resolution of the ICL7109 at 12 bits Ts 244 ppm Gr one part in 4098. Therefore, temperature difer- Shoe of 3°0 will ntroduee a one-bit error the reer fenoe hasa temperature coefficient ofB0 ppm’. (ke the onboard reteronce). Where the ambient tempera ture isnot controled or whare high-accuracy absolute measurements are being made, an external high Gualty vlerence should be used To generate asultable reference voltage, the ICL7109, provides a AeFerence OUTaut (pin 29) which may be tised with a resietive divider "Tle output wil snk up {o'apdut aima wiinout asigaeant output vara on RR pullup bias evice which sources about 10.uA 1S aiso provided. The output voltage is nominally 2 8v below V' and has a temperature coefficient of #80, om"C iypleal REF" should be connected to the Uiper of @ precision potentiometer between AEF GOT ana Wand AEF OUT (Pin 29) should be con- ected to REF. (pin 38) when using the onboard Felerence. Shown in the test circu isthe circus for 1 204.8mV reletence, The fixed resistor should be Femoved for’a WV reierence, and a 25411 precision 601ZTOIICL7109 12 Bit A/D Converter With 3-State Binary Outputs potentiometer between REF OUT and V- should be uses. Noto that if pins 29 and 38 are tied together and pins 3B ang 40 accidentally shortes (eq. during testing), ihe teterence supply’ wil sink Suficent eurrent 10 destroy the device. By lacing a Tkttresistor nseries ‘with pn'38, this can be avoided __ Detaifed Description Digital Section ‘The digital section (Figure 4) incluges: 1) the clock ossilator and ‘divider circut, 2) a 12on onary Counter with output latches. ang TrL-compatible ‘hree-state ‘output. rivers. 3) control iogle. and 4) UART nandshake Toate Note: The term "clock cycles” as used inthe follow ing discussion relates ta the internal clock, which i> the oscillator ouiput 58 when O80 SEL Is low. Three-State Outputs ‘The ICL7109has 14 three-state outputs: 12 data bits, {polarity bi) and. 1 oyertange bit, These ais are Cnabled either by the CELOAD, UBEN and HEN onto! signals. (2 Table 2), or by entering the Handshake mode, CETCOAD, (BER, and HBER ‘These three control pins can function aseither inputs ‘or outputs. In tho Dirac interlace mode (see “Inter facing, beiow), these tree pins are Chip Enable and Byte Enable inputs. n the Handshake mode these thee pins become outputs that 1oad data into the LUART. These pins wil be outputs while handshake transfer isin progross or at any time that the Mode Input is high un/FOF@ input Wihea the Ruri input i tee nign, the 16-7109 Continuously performs A/D conversions with fined fengtn of 8192 clock oyeles par conversion. When unr. 1s taken low, the {CL7109 wll Complete thaconserson im progroan tna wat the autocro hase. Ait the Minimum autozoro tne hag been, Eompleted, a high-going pulse on Hun/HOld of at Teast 200 nanosecones ls required to star. anew Conversion: Out any pulses during a conversion oF tp to 208 clock cycles after Status goes fom wi 8 tanored, i the (C1108 fs holding atthe enc at the autozero phase, @ new conversion wil iar anc Status mil go.high Wihin 7 clock cycles. after Runiald goes nigh In adaition to starting and stopping conversions, tha Fun Hold pin ean sis be veed to minimize con Yetsion time. Fun/#010 Is high, each conversion takes a ful 6192 lok cycles whine Decetegate hare taking #098 clock eycles Independent of put Woltage. Onthe other tend, Finca ow at any lime aioe Status goes low, the ICL7109 immaciately lumps to re Auto Zero phase rather than faking & {at 45g6ctoceeyeles for Dermtograto.A smote way {o ensure minimom conversion time eto dre ne Bun'moid input withthe Buffered Oscilafor Outpt. Wien tian done, he conversion be fs cependont bn the input voltage, £098 clock cycles fora Zero Notage input rising 10 8192 slock cycles for fll Sealer overrango inputs pe SAELSLE ES SY PPR RR Poe piRehey12 Bit A/D Converter With 3-State Binary Outputs ae Figure RUNOTE Operation ‘Mode Input ‘Tha Mode input is used to control the converter Sutput mode, The converter ig ns Direct output f, where the output data is directly accessible Under the control of the chip and byte enable puts vanon the Mace pin is low or let open. (To ensure @ Tow Tovel when the pin s let open, this input is pro- \ided mith an interna pulldown resistor} When the Mode input is puleed nigh, the converter enters the UART nandshake mode an gutputs the data in two bytes, then returns to “Direct mode. The converter ‘ail output Gata in the handshake mode atthe end Of every conversion ‘cyclo when the Mode input remaig rin (See Harsnaxe Mode” section for more details, ‘Send Input The Send Input is @ handshake control input used uring handshake transfers. The use of Send to Contrel a handshake interface is discussed in te inlerfacing® section, below. ‘The Maxim ICL7109 contains an improved power-up reset eveut that ensures ina he ICL? 109 dowersup inthe Direct mode i the Made mputis low, but other manufacturers IGL7108s may power up inthe Han Shake mode ever ‘f the Mode Input ig held Tow. Although the Send input of the Maxim {L103 ean be tied elthor high or low if only the Direct mode 1 tiseo, other manufacturer's [GL74098 require tmatthe Send input be teghigh so thatthe ICL 7109 mil return tothe Direct mode in7 clack cycles the Handshake made is inadvertently entered on power-up MAXIM Osellator ‘The ICL7109 has a versatile three terminal oscillator that may be operated as 2 crystal or RC oscillator It also thay be overdriven by an external clock source, Tovoptimize it for crystal 0” AG operation, the Osc lator Select input changes tne internal configuration bf the oscilator The osellators configures for RC ‘peration when the Oscillator Select inputs high OF fete open tine nput is provides with an internal pallup resistor), and the intemal clock will be of the same pphase and frequency a9 the signal at the Buffered Sseillator Output. (See Figure B for the resistor and ‘capacitor connections } Osctlation will occurin the Sireuttata requeney given ay -0.48RC, Tho osc fator resistor should Ge “00Kt2, The capacitor value Should be chosen such that 2048 elock periads are ‘lose to an integral multiple of the 6OHE period for ‘optimum 60He ine rection, Sut the capacttor value Should not be Tess than SOpF | feedback device and input ang output capacitors fare added to the oscillator when the Oscilatar Select input is iow. With ao external components, the asel infor willfunation with most crystals nthe 7 to SM range, (See Figure 7) A fied ~ 58 circu 6 nserted Setween the Butlered. Oscillator Output and the internal clack by taking the Osellator Select input Tow. This division ratio provides 83.18ms integration time, By using a'3.S8MHe TY crystal ‘T= (2048 clock periods) x = 33.188 8 Tsar 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs This time is quite close to 83.83ms oF two 6OH2 periods. The ettor Is lower shan one percent, which full yield better than 40d of 2M rejection, at any lime the oseatoris to be overdriven. the overcriving ‘Signal should be apaed at the Oscllator Input. and the Oscilvor Output shouldbe left open. When Oseilator Select Islet open. tne internal clock will be of te same duty cycle, requency ana phase as the input signal The clock willoe tre nput frequency divided by $8 when Oselator Select Is at Ground ‘The divide by’58 ciccull wil operate reliably Uo to bout SMe [Ovellator Salect iow), while the Gon ‘erter ise wil operate at clock raies Up to’? Mz Gseitator Select high). This implies a conversion fate of 224 conversions/ee, To operate the converter af these rates the auto-zero ang integrating eapac = tors must be, scaled using the guidelines in the ‘Component Selection section. AB the conversion rate increases, the accuracy of the converter is compram'sed, primarily due to noise ang the delay of the comparator If the elock perod Is lass tha the comparator delay (typically 1-3 usec) the low ‘order bits become meaningless. At 2 Miz. typical Feadings with tne inputs shorted may be-10 counts, rendering tne 4 LSBe meaningless Note: At 18 conversions per second, the integration ime of 2048 clock pulses equals one complete period "60 He. This is tharelore the maximum conversion ‘ate that will provide 60 Hz noise rejection, Status Output ‘Atneend ota conversion cyee the Status output 9003 fouone-half clock period after new data fro he rvaraan hae bah stor nthe Quo atc ats goos high athe begining ot Sighal integrate Phase’) Figure 9 shows te ming Seals eh Signal may be utlized:as_a flag indiesting "data ‘alig" for montoning the status ofthe Converter oF 19 drveintrapts sco dala never cares whe its low Test input ‘The counter output latches are enabled when the ert input is taker toa level halfway between V" and Groung. allowing the counter contents to Be exam= ined. When the Test itput Is grounded, the internal Glock is disabled and the counter oulputs areal forced into the nigh state. The counter Outputs will be clocked to the low state when the Input returns. to the 1/2 (V" ~Ground) voltage (or to V") and one. Table 2. DIRECT MODE TRUTH TABLE Baia CEROAD | IBEN | HBEN | e183 POLOR + cra at Fez ° 1] 4 2 5 ofa Bea ° § | 0 [Oe 2 | nets out leo 0 | 6 | peta Gut | data Out Clock is appied. This tacuitates testing of the counter and the Output crvers. Although the Test pinhas aninterna pulp, it should be tied high trot used. This ensures that high speed transitions on adiacent pins (particularily LBEN) So not inaavertontly activate the test mode. Interfacing Direct Mode ‘The ICL7109sinthe Dicectmode when the Mode in iow. In hie modo ihe guipat nero faatmpla parallel ntrtace witha Ship Enable (CET oad) and Grobytegnabes (BEN ang LEER) Asshowninthe {rot fable of Table 2. the leat signficant bits ot Gata are anabied vine botn CELaad ang LEEN are erage iow: fre upper dois of data pola are enabled whenever Goi 2a and HBEN are low ‘he Maxim version of the (CLT109 has signtcany ‘enbancad current sourcing capabity, which enables itto rapidly dre the large capacitances often found ‘on microcomputer busses, In Figure 12, an aporgacn to intrtacing several [Grids tga ‘bus ts shown. This fs achieved by Using the CE/Load inputs (decoded from an ade ‘dress possibly) 19 select the desired ‘converter Ane tying the HBEN and CHEN signals to several Convertors together The GL7109 can also be controlled through VO peripheral ports, as shown in Figures 14.19 and 16, Figures 19 through 16 are sorse practical circuts utilizing the parallel three-stste output capabiities ol the ICLT108° Shown in gure 18 isa swaigntorward Interface tothe Inte! MCS"48,-80and-B8 systems v9 4n.8255 PPI. where the ICL7109 date outputs are Setive at all tes, The 8158" ports may be utlized in the same way. Although a read performed walle the data fatehes are undergoing updates will lead 19 seramaled data, ins interlace canbe used in readanytime mode. One way of solving this problem isto fead the Status output as wel itis high, read the data a'second time after @ delay of more than 1/2 converter clock period, if Status fs til high, te first feauing is correet if Status is now low the second feadings correct. On the other hand, the problom of timing Is completely avoised by using a fead-ater late sequence. (See Figure.) Data can be ‘accessed by the high to low tansition ‘of the Status output driving an interrupt to the micro- processor Figure 14 also demonstrates the Fun Flaeinput being used to initiate conversions under software conta Figure 15 shows a similar interface to 850X or 680X systems, The transition of the Stalus output from high fo low generates an interrupt va tae Contr! Register @ CBI line. Nate that CBZ controls the RunvHold pin through Control Regisie 6. This application” permit ‘software-contalled.iniiation Of conversions Direct intertacing to most microprocessor busses is allowed by the three-state output capability of the icL7t09"fSee Figure 13 ano the typical operating circuit on the frst page.) It is Important that the 12 Bit A/D Converter With 3-State Binary Outputs requirements for setup andhokd times, and minimum pulse widihs are met. There are algo drive limitations 5 fong Busses that should be noted. In general, his type ot interface Is Tavored only it the memory Penpheral address. density is iow so that simple Bddress decoding can be used. Interrupt hanging an mandato several extra componenis. The use of interfacing evices will simply the system in many cases. Handshake Mode Handshake Mode permits the_ interface with a umber of external devices” For example. vyt Enables may be used as load enables oF as byte Identification flags, and. exterpal latches may be lacked by the rising edge of CE/Loaa. ‘The handshake mode is specifically designed to Gireetly interlace the 1CL7209 to industry standard GAATS within externallogic required. The IGL7 109 Isinthenandshake mode whenever the Mode nautis high. Inthe handshake made the CE/Load, CHEN. and BEN pins are outputs and Send is an Input A {ypical UART to ICL7109 interface is shown in Figure WB. win tne Interface timing shown in Figures 9 through 11 “ee —ITLI-} If wR mJ LI = vt Tr femme 17 MAXIM 6012791ICL7109 12 Bit A/D Converter With 3-State Binary Outputs _ MaximWhen Mode is continuously held high, @:new UART transiiasion willbe started when Status goes low. provided Send is high at that time. Asshown in Figure {0 the hign pyre of data wil be written into the UART by the fist puse of GE/Load. The TBRE signal of ne ART will momentarily go low upon receiving the sta. Atfer the UART transfers the data to the ‘yansmitter register, the UART's TBRE output drives, the ICL7109'¢ Send ingut high. The IGL7109 sensas {ne high level on the Sard input and loads the low byte of data into the UAAT with a second pulso of CEitoat the T6L7I00 continues is conversion ycles while this hangshake lakes place, anc i the UaRT's TBRE has driven the 1CL7108 Send input high by the end of the next conversion, the gata fransfer sequence will repeat. if the UARTS TERE {and theretare the ICL7109's Seng input) is low wnen the ICL7108 completes tne nex: conversion, the internal laien pulse is inhibited and the data trom that conversion is lost [A handshake transfer can be initiated by a high- going pulse on the Mode pin. Upon receiving a Nigh Sing pulse, the IGL7109 sets an internal Mode atch land wil stata handshake transmission when Status ‘Goes iow at the en of tre next conversion. An alter Bala method of controling the ICL7109 Is to leave Mode high and initiate conversions viatne fun Fold input. With this method the ICL7109 wil fist make.a Conversion then transmit the dats. Another method ff initiating a transmission is shown in Figure 11 Hore Mode Is pulsed ign while Send is tow, A UART transmission is started when Send ie teken tia (at least 2 negative clock edges later). 12 Bit A/D Converter With 3-State Binary Outputs ‘The UART mode is also useful in intertacing the ICLTi08 te 7O ports such as the 8255 and 6520. Figure {7 is an example of such an interface. The handshake operation with the 8258 is cornrolles by inverting ts Input Butfer Full (IBF) flag to srive tho Send inputto the ICL7109, and using the CE/Load to ‘rive the 8255 strobe. The internal control register of the PPI should be set in MODE 1. The next Cconversion’s result willbe strobed othe son ifthe. £8055 IBF flag is loW and the IGL7108 in nandshake mode. The strobe will cause IBF to go high (Send foes low) which will prevent the TCL7103 from loading the second byte of data. The PPI will {generate an interrupt. When executes, the result is {hat the data is r2ad. The IBF willbe reset low when the byte is tead which causes the ICLT109 to Sequence into te nextbyte, Figure 17 shows the PCT line of the PPI connected to the Mode input of the ICL7103.11 this inputs ties high a tetthign, the data from every conversion will be sequenced into the system [provided the data access takes less time than @ conversion). The output sequence can be ‘obtained on demand by using the PCT outputtodrive the Mode input. Note that the 8255 can service another peripheral device since only one port is fed. The 8155 can utilize the same arrangement. The IGL7109 1s not limited to tro applications de- scribed here, These examples show some of the any interfaces and uses ofthe (CLTI08 and merely provide a paint of departure for users t0 develop Sppropriate systems, Many of te suggestions made hhore may be combined. More specifically, the uses of tne Mode, Status, and un/Hold signals may be mixed, Figure 12 Tseng sve) 71098 10 @ Bue MAXIM 601ZTOIICL7109 12 Bit A/D Converter With 3-State Binary Outputs , 8 ‘gure 18 Palin Para race MSAK or MOSEBDK Meraprocessors MAXIM12 Bit A/D Converter With 3-State Binary Outputs Fue Ta Tynes! Connection Baran UART ieee MAXIM 601ZT91'CL7109 12 Bit A/D Converter With 3-State Binary Outputs Pin Configuration “Lees ate Chip cai (Qn Pak) Chip Topography Maxim12 Bit A/D Converter With 3-State Binary Outputs Package Information oo = uit Se ei) it = Toe lL. oo z a { oir * CERDIP lon aS mi ETERS| \\ DUAL-N-LINE —[o” ‘ae farm )) wae Hoos oeeeeeeee 7, « . ” “s aaa ares gt fe it on i 7 He a “tom I. 2 mice . 3 = at | Plastic DIP se \\ PLASTIC — fxaloya|pns] CHES [nucimerens| P \\ | puauan-uive POSES } | package. [rps ser tes, ns (o600in) [eto t area rau tsisn sn MAXIM 6 60KZT91ICL7109 12 Bit A/D Converter With 3-State Binary Outputs Package Information (continued) ee are Te. use| nice plastic LEADED CHIP CARRIER ae joes pase ona Lona ater aes 2 nm mieten toscana OA HoH 0 80 (© 1998 Mon byegiied Products ‘Printed USA AMAL i a registra aderark ota nigra Product