Outline

l Memories today
l Fault Model
l MARCH algorithms

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Memory Testing
• Memory is the most dense physical structure
- Embedded memories begin to dominate physical die area vs. logic
- Memory arrays can be doubly embedded (ex: microprocessor with
cache within a larger chip design
• Considering the increase density, memory arrays are more sensitive to
defects

LOGIC EMBEDDED
MEMORY

SoC
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 Memory Organization
l Address Decoder
l Data Decoder
l Control Circuitry Data Bus
Address Bus

Data in Data out

Address in
Read/write MEMORY
Output enable

Control
Signals
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Memory Design Concerns

l Aspect ratio: square, rectange, in pieces, number of memory
modules. It affects routing, chip area, power dissipation etc
l Recent trend is to have many distributed memory arrays close
to the logic they serve
Chip floorplan

Memory 2
Memory 1

Processor

Logic
M em ory 4
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 Embedded Memory Testing Methods
♦ Scheme A: Embedded Microprocessor Access
♦ Scheme B: Direct Memory Access
♦ Scheme C: Memory Build-in Self-Test

Data
Processor Address
EMBEDDED
SCHEME A MEMORY
Control
Data
Address EMBEDDED
SCHEME B MEMORY
Control

Invoke BIST
EMBEDDED Done
SCHEME C Fail
Hold/Reset MEMORY

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Embedded Memory Testing Methods

l SCHEME A: uses embedded microprocessor to test memory.
These vectors consume “test vector memory”

l SCHEME B: accesses memory directly via I/O package pins.

Signal pins needs to be reserved/borrowed and it requires a
route-intensive bus structure to different memories

l SCHEME C: includes tester function right into the silicon.

Little chip interface but once BIST is build it cannot be
changed. BIST mechanism can be shared between different
memory modules. BIST can operate memory at-speed.
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 Memory Layout
column 0 1 2 3

row
0 0 0 1 0

1 0 1 0 1

2 0 0 1 1

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Failure Modes and Fault Model

l Failure modes: l Fault models:
s Data Storage
s Data Delivery
l Stuck at faults
s Data Recovery l Bridges
s Address Recovery

s Data Retention

s Data Decode

s Address Delivery

s Address Decode

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 Stuck-at Fault Model
l We can have a single cell or a group of cells stuck to some
constant value “0” or “1”
♦ Fault exercise and detection: Write both 0 and 1 and read 0
and 1, respectively

cell
Stuck-at 1 1
word stuck-at 1101
1 1 0 1

00

cell stuck-at 0
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Bridging Fault Model

l Bridges can be 0 Ohm or resistive or diodic. They can cause
change in one or multiple cells
♦ Fault exercise and detection: write and read alternating
or complementing patterns such as 0-F, 5-A etc. Diodic
bridges may be sensitive to address writing order
horizontal cell bridge
bi-directional
1 0 0 1
word bridging
vertical cell 1 1 0 1 bi-directional
bridge
one-way 1 0 0 1

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 Decode Fault Model
l Stuck-at and bridge faults can cause to always choose wrong
address, select multiple address etc
C
O 4
1, 2: stuck at faults 1 L
result choosing R
2 0
1 11 0 0
always a wrong O
address W
1 0 0 0
3,4: bridges result 3
always choosing 1 0 0 0
multiple columns
and rows 1 1 0 0

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Data Retention Fault

l Leakage or bridging may cause the stored data value
to degrade over time
♦ Fault exercise and detection: put data in target memory
cell and surround with complementary values

01 11 0 0

1 0 0 0 target cell

1 0 1 0

1 0 0 0

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 Algorithmic Test Generation
l Observation: memory testing needs certain pattern
sequences to exercise and detect the different fault
failure modes

l Algorithmic Test Generation: research area that tries

to identify such pattern sequences for memory testing

♦ Usually called MARCH tests

♦ We will examine MARCH tests for a bit-slice memory (sake
of simplicity)

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5N MARCH TEST
Consider following sequence of operations:
Address(0) à Address(MAX): WRITE(0)
Address(0) à Address(MAX): READ(0) WRITE(1)
Address(MAX) à Address(0): READ(1) WRITE(0)

time

bit
0
numbers
0
…

… …
…

#operations 0

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 Algorithmic Test Generation
l 5N MARCH detects:
s Single stuck-at faults
s 1-step neighbor bridge faults

s Address decode faults

l Consider 14N MARCH:

Address(0) à Address(MAX): WRITE(5)
Address(0) à Address(MAX): READ(5) WRITE(A) READ(A)
Address(0) à Address(MAX): READ(A) WRITE(5) READ(5)
Address(MAX) à Address(0): READ(5) WRITE(A) READ(A)
Address(MAX) à Address(0): READ(A) WRITE(5) READ(5)
Address(MAX) à Address(0): READ(5)
♦ Homework: detects stuck-at, bridges, address decode, data
decode and access time faults (why?)
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