CSE413 Microprocessor-Based Systems

CPU + Memory + IO
 Topics
➢ CPU
– Architecture: CISC / RISC
– ARM Cortex M0+ Programming Model

➢ Memory
– Memory Types: ROM / RAM
– Memory Organization and Addressing

➢ Input and Output (IO)

– IO Types: Digital / Analog … Serial
– IO Addressing: Isolated IO / Memory-Mapped IO
 CPU
The CPU performs basic arithmetic, logic, controlling,
and input/output (I/O) operations specified by the instructions.
It fetches, decodes, and executes program instructions.

A CPU includes:
1. The ALU
Performs arithmetic and logic operations.

2. Registers
– General purpose registers:
Hold operands to operate on.
– Special purpose registers:
Each of these register has a function such as the
Program Counter & the Stack Pointer

3. The control unit

‒ Fetches instructions from memory, decodes, and
"executes" them.
‒ Handles Exceptions and interrupts.
Internal buses
 CPU
➢ CPUs typically are 4, 8, 16, 32, or 64-bits
The size of the CPU registers, and accordingly the size of the internal data buses:
Buses A, B, and C in the previous slide

➢ CPU clock rate is decisive in determining its speed.

However, the clock frequency is useful for providing comparisons between CPUs in the
same family, as it is only one of several factors that can influence performance:
▪ Processor architecture
▪ Width of the CPU data bus
▪ The latency of the memory
▪ The cache architecture affect the whole system performance

ARM Cortex-M processors adopt Harvard architecture. It has separate data and instruction buses.
• Instructions are fetched from flash ROM using the ICode bus
• Data are exchanged with RAM and I/O via the system bus.

Some internal peripherals, like the NVIC, communicate directly with the processor via the private peripheral
bus (PPB) to provide fast interrupt handling.
 CPU Architecture Types
RISC
Memory is referenced only through LOAD & STORE
instructions (Load-Store architecture)
To do an operation with an operand in memory
Three separate instructions:
1. A LOAD instruction from memory to a named CPU
register
2. An instruction to perform the operation
3. Optionally a STORE instruction to store the result back
in memory
➢ Simple instructions → Simple CPU circuitry.
➢ Simple circuit → less power.
➢ More memory references means slower performance
(overcome by improved pipelining)
➢ Most RISC designs use uniform instruction length for
“almost” all instructions.
―ARM, MIPS
―Atmel AVR, PowerPC
―intel i860 and i960
CISC
Can do arithmetic & logical operations with operands in
memory (Definitely through some inaccessible CPU registers)
A single instruction does the following:
1. Load the operand from memory to an invisible CPU
register
2. Perform the operation
3. Optionally store the result back in memory
➢ Complex instruction → Complex CPU circuitry
➢ Complex circuit → more power.
―Motorola 6800, 6809, 68000
―Freescale HC11, and HC12
―intel x86 family, i5 i7, and 8051-family
 ARM Cortex-M0 Programming Model
RISC example
ARM Core Registers The programming (programmer) model is
the user-visible registers and the function of
each of them.

7
 HC12 Programming Model
CISC Example
HC12 Core Registers

CISC CPUs usually have fewer registers compared to RISC ones

 Memory Types
• Volatile: Random access memory RAM (Read & write). Holds variables.
• Nonvolatile (NVM): Retains its contents without power supply. Holds instructions & constants.

Types of NVM:
―ROM: Read only memory. This term is usually used to refer to devices programmed by the manufacturer.

―PROM: Programmable read only memory. Programmed once by the user with special hardware.

―EPROM: Erasable programmable read only memory. Erased as a whole with ultra violet light, and
reprogrammed with special hardware.
―EEPROM: Like EPROM but it is erasable and reprogrammable by electrical signal, (no UV).
It can be reprogrammed on board one word at a time. Holds constants.
―FLASH: A type of EEPROM that can be erased and programmed in sectors (blocks). Used to hold the code
(program and constants)
➢ New technologies for NVM are still emerging; suitable for big data applications.
 Memory Organization
➢ Memory is usually byte-organized (byte-addressable)
↪ Each byte in memory has a distinct address.
The maximum addressable memory size is 2𝑁𝐴 bytes
The memory is interfaced to the CPU through:
• The first location address is 0
• Address bus (𝑁𝐴 bits)
• The last location address is 2𝑁𝐴 − 1
• Data bus (𝑁𝐷 bits)
10-bit address bits can address 2𝑁𝐴 = 1024 i.e.,1k
• Control signals (Read/Write, Wait …) of memory.
A 64k memory needs 16-bit address.
The CPU can read/write multiple bytes, two-byte or four-byte words,
in a single read/write in accordance with the data bus size 𝑁𝐷 .

Example:
A 4-byte read from address 0x1000 through a 4-byte data bus
retrieves four bytes from locations
0x1000
0x1001
0x1002
0x1003
 Input/Output Addressing
Memory-Mapped IO Isolated (Port-Mapped) IO

➢ The CPU uses the memory reference instructions, ➢ The CPU instruction set has distinct IN and OUT
LOAD and STORE, to do input and output instructions to do input and output operations, as in
operations. the intel processors

➢ IO port addresses do not overlap with memory ➢ IO port addresses can overlap with memory locations
locations addresses. addresses.
➢ IO ports have separate addresses.
➢ Used in ARM processors. ➢ Used in intel x86, i5 and i7 line of processors.

➢ The same MemRead and MemWrite signals on ➢ The control bus has a signal that
the control bus used in memory reference cycles differentiate I/O cycles from memory cycles.
are also used to reference IO ports as well. = 0 when executing a memory ref. instruction
= 1 when executing an IN or OUT instruction
 Memory-Mapped I/O
R/𝐖 Operation Instruction
Memory Write ST reg, mem
0 or Output
Memory Read LD reg, mem
1 or Input

Memory
ഥ
R/W

I/O

Memory

IO ports have distinct addresses

within the memory map.
 Isolated IO (Port-Mapped IO)
M/𝐈𝐎 R/𝐖 Operation Instruction
0 0 Output OUT reg, port
0 1 Input IN reg, port
1 0 Memory Write ST reg, mem
1 1 Memory Read LD reg, mem
M/IO
ഥ
R/W Memory

I/O

IO ports addresses can overlap with

memory locations in the memory map.
 Types of Input & Output
Digital interfaces: Read or write a single bit, or multiple bits, at a time
Simple binary inputs through switches and push buttons
Simple binary outputs to LEDs or seven-segment digits
Touch sensor interface (TSI)
LCDs and hex keypads
Binary waveforms (Pulse-Width Modulators PWM)
Analog interfaces
Analog-to-Digital Converters (ADC – ATD – A/D)
Digital-to-Analog Converters (DAC – DTA – D/A)
Analog comparators
Communication interfaces: Transmit or receive bits serially one after another
Wired:
USB (Universal Serial Bus), Serial Peripheral Interface (SPI), Synchronous, Serial Communication
Interface (SCI), Asynchronous, Universal Asynchronous Receiver-Transmitter (UART), Controller Area
Network (CAN) / Inter-Integrated Circuit (I2C)
Wireless:
Bluetooth, Zigbee
 Microcontroller Families

Microcontrollers are grouped in families based on the CPU used.

↪ Microcontrollers within the same family differ by:

– The amount of memory (ROM and RAM)
– The types of I/O modules (peripherals)
– Packaging

ARM Cortex-M microcontrollers have similar memory maps:

– Flash ROM begins at address 0x00000000
– RAM begins at 0x20000000
– Peripheral I/O space starts from 0xE0000000 to 0xE00FFFFF
 Members of Kinetis KL25 Sub-Family
Manufactured by NXP (previously Freescale)
All have ARM® Cortex®-M0+ core

Part Number Memory Pin Count Maximum Number of Package

FLASH (KB) RAM (KB) IOs
Quad-Flat No-leads
MKL25Z32VFM4 32 4 32 23 QFN
MKL25Z64VFM4 64 8 32 23 QFN
MKL25Z128VFM4 128 16 32 23 QFN
MKL25Z32VFT4 32 4 48 36 QFN
MKL25Z64VFT4 64 8 48 36 QFN
MKL25Z128VFT4 128 16 48 36 QFN
MKL25Z32VLH4 32 4 64 50 LQFN Low profile Quad-
MKL25Z64VLH4 64 8 64 50 LQFN Flat No-leads

MKL25Z128VLH4 128 16 64 50 LQFN

MKL25Z32VLK4 32 4 80 66 LQFN
MKL25Z64VLK4 64 8 80 66 LQFN
MKL25Z128VLK4 128 16 80 66 LQFN
 Our Choice for Study
Freescale (NXP) Kinetis KL25 Subfamily
CPU Human-machine interface
48 MHz ARM® Cortex®-M0+ 32-bit core Low-power hardware touch sensor interface (TSI)
24 MHz bus clock Up to 66 general-purpose input/output (GPIO)
Memory Communication interfaces
Up to 128 KB flash memory USB
Up to 16 KB SRAM Two 8-bit SPI modules
System peripherals One low power UART module
Nine low-power modes to provide power Two UART modules
optimization based on application requirements Two I2C module
COP Software watchdog Analog Modules
4-channel DMA controller 16-bit SAR ADC
Low-leakage wakeup unit 12-bit DAC
SWD debug interface and Micro Trace Buffer Analog comparator (CMP)
Bit Manipulation Engine Timers
Clocks Six channel Timer/PWM (TPM)
32 kHz to 40 kHz or 3 MHz to 32 MHz crystal Two 2-channel Timer/PWM modules
oscillator Periodic interrupt timers
Multi-purpose clock source 16-bit low-power timer (LPTMR)
1 kHz LPO clock Real time clock
Operating Characteristics
Voltage range: 1.71 to 3.6V