ASYNCHRONOUS DUAL PORT FIFO DESIGN

1 INTRODUCTION
1.1 ABOUT MEMORY

The major task in any system is managing the data/signal flow in system during its processing
time which is basically depended on the storage element and storage control unit of any system i.e.
memory and memory controller. Memory is a main function component of every system for saving a
data received and for use of data stored for further use. Main functionality of memory is to store the
data upon request and to enable the stored to use upon request. Capacities of memory, type of memory
are major parameters defining the functionality of any system.

Memory is an array of cells. Each cell is a storage device having unique address and fixed
number of storage elements. Unique address allows distinguish cells and to access the particular cell
and to perform read and write operation for a distinguishing cell.

The above is representation of a memory system and how bits are stored in it. Each word has
its own address in which are refer for write or read operations. For example Word 1 consists of data
0110 and stored in location 0000, word 2 consists of data 1001 and stored in location 0001 and so on.

A semiconductor memory chip is an electronic device for data storage which is implemented
on a semiconductor integrated circuit. Data is accessed by the semiconductor chip through a binary
memory address. If the address of the memory consists of M number of bits, then the address area
consists of 2^M addresses per chip. Semiconductor memory chips are designed with a certain word
length (which is the number of 1-bit cells that share the same memory address). The amount of data
which can be stored in a memory chip defines the number of bits. Through the combination of several
integrated circuits, memory may be arranged for a larger word length and/or a larger address space
than what is initially offered by the chip.

1.2 CATAGORIES OF MEMORY

Basically memories divided in to two categories,

Volatile memory: The data stored in the memory will be erased once the supply voltage
removed.
Non volatile memory: The data stored in the memory will not be erased if the supply
voltage removed.

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1.3 TYPES OF MEMORIES

Various types of memory based on accessing and storing data are:

RAM (Read Access Memory): R/W Operation can be performed at any selected address at
any sequence. It is used in place that has a fix operation such as start-up of the PC, game
players etc. Most of RAM is volatile.

ROM (Read Only Memory): They are programmed at the factory at the time of
manufacture. Once data has been written onto a ROM chip, it cannot be erased and can only
be read. ROM is a Non-volatile memory.

PROM (Programmable Read Only Memory): It’s programmable ROM. Its contents are
decided by the user. The user can store permanent programs, data etc in a PROM. The data is
fed into it using a PROM programs. PROMs are Non-volatile.

EPROM(Erasable Programmable Read Only Memory): An EPROM is an erasable

PROM. The stored data in EPROM’s can be erased by exposing it to UV light for about 20
min. It’s not easy to erase it because the EPROM IC has to be removed from the computer
and exposed to UV light. The entire data is erased and not selected portions by the user.
EPROM’s are cheap and reliable.

EEPROM (Electrically Erasable Programmable Read Only Memory): It is a special type

of PROM that can be erased by exposing it to an electrical charge. The chip can be erased &
reprogrammed on the board easily byte by byte. It can be erased within a few milliseconds.
There is a limit on the number of times the EEPROM’s can be reprogrammed, i.e.; usually
around 10,000 times.

Flash Memory: It is type of EEPROM memory except that EEPROM Read and Write
operations are performed in bytes. However, Flash memory Read and Write operations are
performed in blocks, this feature makes it faster for data update because It uses one transistor
memory all resulting in high packing density, low power consumption, lower cost & higher
reliability. It’s used in all power, digital cameras, MP3 players etc.

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2. RANDOM ACCESS MEMORY

2.1 ABOUT RAM

Random Access Memory (RAM) is a type of storage unit historically defined as memory
array with individual bit access. RAM refers to memory with both Read and Write capabilities. RAM
allows accessing the stored data directly and randomly through the address and to store the data
randomly through the addresses i.e. RAM provides memory read and write accessibility.

RAM basically consists of chip select signal, read/write signal, address bus, 2 data bus
namely input data bus and output data bus.
1. Chip select: It’s a control signal which on active ,RAM is accessible for the performing
read/write/read-write operation
2. Read/write signal: It’s a control signal which controls operation of RAM i.e. whether to read
/ write operation. This signal can be synchronous / asynchronous signal.
3. Address bus: It’s a unidirectional signal where in it points to memory cell where exactly
read/write operation as to be performed. Size of address bus specifies the depth of RAM.
4. Input data bus: It’s a data bus which carries data to be recorded/written in RAM in address
pointed by Address bus during write operation.
5. Output data bus: It’s a data bus through which data present in memory location pointed by
address bus is read out from the memory during read operation.

Any number of times data can be read from or written to an addressed memory array of RAM.

Depending on number of ports, RAM are of two types:

1. Single port RAM.
2. Dual port RAM.

Single port RAM: It can perform read / write operation on a specified addressed memory cell
.Thus single port RAM allows only one memory cell to be read/write at a time.

Dual port RAM: It can perform read and write operation simultaneously at different /same
memory cell. Thus Dual port RAM allows 2 memory cells to read/write at a time.

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2.1 DIFFERENT TYPES OF RAM :

Depending on number of ports accessing the RAM memory array and the synchronization of
read-write operation with clock signal RAM there are following kinds of RAM
a) Single port RAM with asynchronous read-write.
b) Single port RAM with asynchronous read, synchronous write
c) Single port RAM with synchronous read, asynchronous write
d) Single port RAM with synchronous read-write.
e) Dual port RAM with asynchronous read-write.
f) Dual port RAM with asynchronous read, synchronous write
g) Dual port RAM with synchronous read, asynchronous write
h) Dual port RAM with synchronous read-write.

2.2.1 SINGLE PORT RAM WITH ASYNCHRONOUS READ-WRITE:

Figure1 Single port asynchronous read-write

In this type of RAM, there won’t be clock signal. Depending on R/Wb signal read /write
operation of RAM is performed. Only a memory cell addressed by address bus can be either read or
written depending on R/Wb signal at a time.

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SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS INPUT It’s a control signal on assertion of this signal to 1 enables
Chip Select the RAM accessibility.

R/Wb INPUT It’s a control signal which defines the operation of RAM
Read/write .On assertion of this signal to 1 read operation is activated
while assertion of this signal to 0 write operation is
activated
ADDRESS BUS INPUT It contains the address of memory cell to be accessed to
perform specified operation .Size of address bus specifies
the depth of the RAM.

DATA_IN [N-1:0] INPUT It contains N-bit data to be recorded/written on the

memory cell addressed by ADDRESS BUS during write
(R/Wb=0) operation.
DATA_OUT [N- OUTPUT It contains N-bit data to be read from the memory cell
1:0] addressed by ADDRESS BUS during read (R/Wb=1)
operation.
Table 1 Single port asynchronous read-write

Operating Modes:

READ operation
Read operation is performed when R/Wb is 1.During read operation, N-bit data present in
memory location addressed by ADDRESS BUS is read out from RAM to DATA_OUT [N-1:0] data
bus.

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Waveform 1 Read operation in Single port RAM with asynchronous read-write

WRITE operation
Write operation is performed when R/Wb is 0. During write operation, N-bit data present in
DATA_IN [N-1:0] data bus is recorded/written in to RAM memory cell specified by ADDRESS
BUS.

Waveform 2 Write operation in single port ram with asynchronous read-write

2.2.2 SINGLE PORT RAM WITH ASYNCHRONOUS READ, SYNCHRONOUS WRITE :

In this type of RAM, write operation is performed during active edge of clock signal CLK
with R/Wb=0 and read operation is performed immediately whenever R/Wb=1irrespective of clock
signal .Only a memory cell addressed by ADDRESS BUS can be either read or written depending on
R/Wb signal at a time.

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Figure 2 Single port ram with asynchronous read, synchronous write

SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS INPUT It’s a control signal on assertion of this signal to 1 enables
Chip Select the RAM accessibility.

CLK INPUT It’s a synchronizing clock signal for write operation.

Clock

R/Wb INPUT It’s a control signal which defines the operation of RAM .
Read/write When R/Wb=1 – read operation.
When R/Wb=0 during active edge of CLK – write
operation.
ADDRESS BUS INPUT It contains the address of memory cell to be accessed to
perform specified operation .Size of address bus specifies
the depth of the RAM.

DATA_IN [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS during write operation.

DATA_OUT [N-1:0] OUTPUT It contains N-bit data read from the memory cell addressed
by ADDRESS BUS during read operation.

Table 2 Single port ram with asynchronous read, synchronous write

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Operating Modes:

READ operation
Read operation is performed whenever R/Wb is arrested to 1 irrespective of CLK signal.
During read operation, N-bit data present in memory location addressed by ADDRESS BUS is read
out from RAM to DATA_OUT [N-1:0] data bus.

Waveform 3 Read operation in Single port RAM with asynchronous read synchronous write
Write operation
Write operation is performed when R/Wb is 0 during active edge of CLK. During write
operation, N-bit data present in DATA_IN [N-1:0] data bus is recorded/written in to RAM memory
cell specified by ADDRESS BUS.

Waveform 3 Write operation in Single port RAM with asynchronous read synchronous write

2.2.3 SINGLE PORT RAM WITH SYNCHRONOUS READ, ASYNCHRONOUS WRITE :

In this type of RAM,read operation is performed during active edge of clock signal CLK with
R/Wb=1 and write operation is performed immediately whenever R/Wb=0 irrespective of clock signal
.Only an memory cell addressed by address bus can be either read or written depending on R/Wb
signal.

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Figure 3 Single port ram with synchronous read, asynchronous write

SIGNAL DIRECTION DESCRIPTION
ATTRIBUTES
CS INPUT It’s a control signal on assertion of this signal to 1 enables the
Chip Select RAM accessibility.

CLK INPUT It’s a synchronizing clock signal for read operation.

Clock

R/Wb INPUT It’s a control signal which defines the operation of RAM .
Read/write When R/Wb=1 during active edge of clock – read operation.
When R/Wb=0 – write operation.

ADDRESS BUS INPUT It contains the address of memory cell to be accessed to

perform specified operation .Size of address bus specifies the
depth of the RAM.

DATA_IN [N-1:0] INPUT It contains N-bit data to be recorded/written on the memory

cell addressed by ADDRESS BUS during write operation.

DATA_OUT [N-1:0] OUTPUT It contains N-bit data, read from the memory cell addressed
by ADDRESS BUS during read operation.

Table 3 Single port ram with synchronous read, asynchronous write

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Operating Modes:

READ operation
Read operation is performed when R/Wb is 1 during active edge of CLK. During read
operation, N-bit data present in memory location addressed by ADDRESS BUS is read out from
RAM to DATA_OUT [N-1:0] data bus.

Waveform 5 Read operation in Single port RAM with synchronous read asynchronous writ
Write operation
Write operation is performed whenever R/Wb is arrested to 0 irrespective of CLK signal.
During write operation, N-bit data present in DATA_IN [N-1:0] data bus is recorded/written in to
RAM memory cell addressed by ADDRESS BUS.

Waveform 6 write operation in Single port RAM with synchronous read asynchronous write

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2.2.4 SINGLE PORT RAM WITH SYNCHRONOUS READ-WRITE :

It’s a type of RAM ,read and write operation are synchronous with CLK signal. Whenever
R/Wb=0 during active edge of CLK signal write operation is activated .Whenever R/Wb=1 during
active edge of CLK signal read operation is active. Only a memory cell addressed by ADDRESS
BUS can be either read or written depending on R/Wb signal.

Figure 4 Single port ram with synchronous read-write

SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS INPUT It’s a control signal on assertion of this signal to 1
Chip Select enables the RAM accessibility.

CLK INPUT It’s a synchronizing clock signal for read/write

Clock operation.
R/Wb INPUT It’s a control signal which defines the operation of
Read/write RAM .
During active edge of CLK ,whenever
R/Wb=1 – read operation or whenever
R/Wb=0 – write operation.
ADDRESS BUS INPUT It contains the address of memory cell to be accessed to
perform specified operation .Size of address bus
specifies the depth of the RAM.
DATA_IN [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS during write operation.

DATA_OUT [N-1:0] OUTPUT It contains N-bit data read from the memory cell
addressed by ADDRESS BUS during read operation.

Table 4 Single port ram with synchronous read-write

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Operating Modes:

READ operation
Read operation is performed when R/Wb is 1 during active edge of CLK. During read
operation, N-bit data present in memory location addressed by ADDRESS BUS is read out from
RAM to DATA_OUT [N-1:0] data bus.

Waveform 7 read operation in single port ram with synchronous read-write

Write operation
Write operation is performed whenever R/Wb is 0 during active edge of CLK signal. During
write operation, N-bit data present in DATA_IN [N-1:0] data bus is recorded/written in to RAM
memory cell specified by ADDRESS BUS.

Waveform 8 write operation in single port ram with synchronous read-write

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2.2.5 DUAL PORT RAM WITH ASYNCHRONOUS READ-WRITE :

In this type of RAM, there will be two ports which can access a memory cell of RAM (or
common memory) simultaneously or one after the other depending on their control signals. Thus
memory cell/s of common memory can be accessed at a specified time i.e. Two different or same
operations can be performed on two different memory cells or same memory cell at a specified time
.There won’t be any synchronizing clock signal in this type of RAM. Whenever, R/Wb of respective
port is triggered respective read/write operation takes place depending on triggered value at the R/Wb
at the respective port. Ambiguity occurs whenever both the ports tries to perform write for same
memory cell at same time or whenever a port tries to read and another port at same time tries to write
to same memory cell. Address bus of both ports must be either same or the address bus of the port
whose size is more defines the size of RAM.

Figure 5 dual port ram with asynchronous read-write

SIGNAL DIRECTION DESCRIPTION
ATTRIBUTES
CS1 INPUT It’s a control signal on assertion of this signal to 1
Chip Select enables the RAM accessibility at port1

CS2 INPUT It’s a control signal on assertion of this signal to 1

Chip Select enables the RAM accessibility at port2

R/Wb1 INPUT It’s a control signal which defines the operation of RAM
Read/write at port1.On assertion of this signal to 1, read operation is
activated at port1 while on assertion of this signal to 0,

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write operation is activated at port1.

R/Wb2 INPUT It’s a control signal which defines the operation of RAM
Read/write at port2.On assertion of this signal to 1, read operation is
activated at port2 while on assertion of this signal to 0,
write operation is activated at port2.
ADDRESS BUS1 INPUT It contains the address of memory cell to be accessed
from port1 to perform specified operation .

ADDRESS BUS2 INPUT It contains the address of memory cell to be accessed

from port2 to perform specified operation .

DATA_IN1 [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS1 during write (R/Wb=0)
operation from port1.
DATA_IN2 [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS2 during write (R/Wb=0)
operation from port2.
DATA_OUT1 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS1 during read (R/Wb=1)
operation at port1.
DATA_OUT2 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS2 during read (R/Wb=1)
operation at port2.
Table 5 dual port ram with asynchronous read-write

Operating Modes:

READ operation
Read operation is performed at respective ports whenever R/Wb is 1 at respective ports.
During read operation ,N-bit data present in memory location addressed by respective port ADDRESS
BUS is read out from RAM to respective port DATA_OUT[N-1:0] data bus.

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WRITE operation
Write operation is performed at respective port whenever R/Wb is 0. During write operation,
N-bit data present in DATA_IN [N-1:0] at respective port data bus is recorded/written in to RAM
memory cell specified by respective port ADDRESS BUS.

Waveform 9 read-write operation in dual port ram with asynchronous read-write

2.2.6 DUAL PORT RAM WITH ASYNCHRONOUS READ, SYNCHRONOUS WRITE :

In this type of RAM, there will be two ports which can access a memory cell of RAM(or common
memory) simultaneously or one after the other. Thus, memory cell/s of common memory can be
accessed at a specified time i.e. Two different or same operations can be performed on two different
memory cells or same memory cell at a specified time .Whenever, R/Wb of respective port is
triggered respective read/write operation takes place depending on triggered value at the R/Wb at the
respective port. In this of RAM, there exists a synchronizing clock .Write operation is synchronous
with clock signal i.e. write operation is activated only when R/Wb is arrested to 0 during active edge
of clock at respective port to perform write operation at respective port. Ambiguity occurs whenever
both the ports tries to perform write for same memory cell at same time or whenever a port tries to
read and another port at same time tries to write to same memory cell. Address bus of both ports must
either be same or the address bus of the port whose size is more defines the size of RAM.

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Figure 6 dual port ram with asynchronous read, synchronous write

SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS1 INPUT It’s a control signal on assertion of this signal to 1
Chip Select enables the RAM accessibility at port1

CS2 INPUT It’s a control signal on assertion of this signal to 1

Chip Select enables the RAM accessibility at port2

CLK1 INPUT It’s a synchronizing clock signal at port1 used for

Clock synchronous write operation at port1.

CLK2 INPUT It’s a synchronizing clock signal at port2 used for

Clock synchronous write operation at port2.

R/Wb1 INPUT It’s a control signal which defines the operation of

Read/write RAM at port1.On assertion of this signal to 1, read
operation is activated at port1, while on assertion of this
signal to 0 during active edge of CLK1, write operation
is activated at port1.
R/Wb2 INPUT It’s a control signal which defines the operation of
Read/write RAM at port2.On assertion of this signal to 1, read
operation is activated at port2 while on assertion of this
signal to 0 during active edge of CLK2, write operation
is activated in port2.
ADDRESS BUS1 INPUT It contains the address of memory cell to be accessed
from port1 to perform specified operation.

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ADDRESS BUS2 INPUT It contains the address of memory cell to be accessed

from port2 to perform specified operation.
DATA_IN1 [N-1:0] INPUT It contains N-bit data to be written on to the memory
cell addressed by ADDRESS BUS1 during write
operation at port1.
DATA_IN2 [N-1:0] INPUT It contains N-bit data to be written on to the memory
cell addressed by ADDRESS BUS2 during write
operation at port2.
DATA_OUT1 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS1 during read operation
at port1.
DATA_OUT2 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS2 during read operation
at port2.
Table 6 dual port ram with asynchronous read, synchronous write

Operating Modes:

READ operation
Read operation is performed at respective ports whenever R/Wb is 1 at respective ports.
During read operation ,N-bit data present in memory location addressed by respective port ADDRESS
BUS is read out from RAM to respective port DATA_OUT[N-1:0] data bus.

WRITE operation
Write operation is performed whenever R/Wb is 0 during active edge of clock at respective
ports. During write operation, N-bit data present in DATA_IN [N-1:0] at respective port data bus is
recored/written in to RAM memory cell specified by respective port ADDRESS BUS .

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Waveform 10 Read-write operation in Dual port RAM with asynchronous read synchronous write

2.2.7 DUAL PORT RAM WITH SYNCHRONOUS READ, ASYNCHRONOUS WRITE :

In this type of RAM, there will be two ports which can access a memory cell of RAM (or
common memory) simultaneously or one after the other. Thus, memory cell/s of common memory
can be accessed at a specified time i.e. Two different or same operations can be performed on two
different memory cells or same memory cell at a specified time .Whenever, R/Wb of respective port is
triggered respective read/write operation takes place depending on triggered value of the R/Wb at the
respective port. In this of RAM, there exists a synchronizing clock .Read operation is synchronous
with clock signal i.e. read operation is activated only when R/Wb is or arrested to 1 during active edge
of clock at respective port to perform read operation at respective port. Ambiguity occurs whenever
both the ports tries to perform write for same memory cell at same time or whenever a port tries to
read and another port at same time tries to write to same memory cell. Address bus of both ports must
be same or the address bus of the port whose size is more defines the size of RAM.

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Figure 7 dual port ram with synchronous read, asynchronous write

SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS1 INPUT It’s a control signal on assertion of this signal to 1
Chip Select enables the RAM accessibility at port1

CS2 INPUT It’s a control signal on assertion of this signal to 1

Chip Select enables the RAM accessibility at port2

CLK1 INPUT It’s a synchronizing clock signal at port1 used for

Clock synchronous read operation at port1.

CLK2 INPUT It’s a synchronizing clock signal at port2 used for

Clock synchronous read operation at port2.

R/Wb1 INPUT It’s a control signal which defines the operation of

Read/write RAM at port1.On assertion of this signal to 0 write
operation is activated at port1 while on assertion of this
signal to 1 during active edge of CLK1 write operation
is activated at port1.
R/Wb2 INPUT It’s a control signal which defines the operation of
Read/write RAM at port2.On assertion of this signal to 0 write
operation is activated at port2 while on assertion of
this signal to 1 during active edge of CLK2 write
operation is activated at port2.

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ADDRESS BUS1 INPUT It contains the address of memory cell to be accessed

from port1 to perform specified operation.

ADDRESS BUS2 INPUT It contains the address of memory cell to be accessed

from port2 to perform specified operation.

DATA_IN1 [N-1:0] INPUT It contains N-bit data to be written on memory cell

addressed by ADDRESS BUS1 during write operation
from port1.
DATA_IN2 [N-1:0] INPUT It contains N-bit data to be written on memory cell
addressed by ADDRESS BUS2 during write operation
from port2.
DATA_OUT1 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS1 during read operation
at port1.
DATA_OUT2 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS2 during read operation
at port2.
Figure 7 dual port ram with synchronous read, asynchronous write

Operating Modes:

READ operation
Read operation is performed whenever R/Wb is 1 during active edge of clock at respective
ports. During read operation ,N-bit data present in memory location addressed by respective port
ADDRESS BUS is read out from RAM to respective port DATA_OUT[N-1:0] data bus.

WRITE operation
Write operation is performed at respective ports whenever R/Wb is 1 at respective ports.
During write operation, N-bit data present in DATA_IN [N-1:0] at respective port data bus is
recorded/written in to RAM memory cell specified by respective port ADDRESS BUS.

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Waveform 11 Read-write operation in Dual port RAM with synchronous read asynchronous write

2.2.8 DUAL PORT RAM WITH SYNCHRONOUS READ-WRITE :

In this type of RAM, there will be two ports which can access a memory cell of RAM(or
common memory) simultaneously or one after the other. Thus, memory cell/s of common memory
can be accessed at a specified time i.e. Two different or same operations can be performed on two
different memory cells or same memory cell at a specified time .Whenever, R/Wb of respective port is
triggered respective read/write operation takes place during active edge of clock signal at respective
port depending on triggered value at the R/Wb at the respective port. In this of RAM, there exists a
synchronizing clock. Both Read and write operation are synchronous with clock signal i.e. read
operation is activated only when R/Wb is or arrested to 1 during active edge of clock at respective
port ,while write operation is activated only when R/Wb is or arrested to 0 during active edge of clock
at respective port . Ambiguity occurs whenever both the ports tries to perform write for same memory
cell at same time or whenever a port tries to read and another port at same time tries to write to same
memory cell. Address bus of both ports must be same or the address bus of the port whose size is
more defines the size of RAM.

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Figure 8 Dual port ram with synchronous read-write

SIGNAL DIRECTION DESCRIPTION

ATTRIBUTES
CS1 INPUT It’s a control signal on assertion of this signal to 1
Chip Select enables the RAM accessibility at port1

CS2 INPUT It’s a control signal on assertion of this signal to 1

Chip Select enables the RAM accessibility at port2

CLK1 INPUT It’s a synchronizing clock signal at port1 used for

Clock synchronous read/write operation at port1.

CLK2 INPUT It’s a synchronizing clock signal at port2 used for

Clock synchronous read/write operation at port2.

R/Wb1 INPUT It’s a control signal which defines the operation of

Read/write RAM at port1.On assertion of this signal to 1 /
R/Wb1=1 during active edge of CLK1,read operation is
activated at port1 while on assertion of this signal to 0 /
R/Wb1=0 during active edge of CLK1, write operation
is activated at port1.

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R/Wb2 INPUT It’s a control signal which defines the operation of

Read/write RAM at port2.On assertion of this signal to 1 /
R/Wb2=1 during active edge of CLK2,read operation is
activated at port2 while on assertion of this signal to 0 /
R/Wb2=0 during active edge of CLK2, write operation
is activated at port2.
ADDRESS BUS1 INPUT It contains the address of memory cell to be accessed
from port1 to perform specified operation.

ADDRESS BUS2 INPUT It contains the address of memory cell to be accessed

from port2 to perform specified operation.

DATA_IN1 [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS1 during write operation
at port1.
DATA_IN2 [N-1:0] INPUT It contains N-bit data to be written on the memory cell
addressed by ADDRESS BUS2 during write operation
at port2.
DATA_OUT1 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS1 during read operation
at port1.
DATA_OUT2 [N-1:0] OUTPUT It contains N-bit data to be read from the memory cell
addressed by ADDRESS BUS2 during read operation
at port2.
Table 8 dual port ram with synchronous read-write

Operating Modes:

READ operation
Read operation is performed whenever R/Wb is 1 during active edge of clock at respective
ports. During read operation ,N-bit data present in memory location addressed by respective port
ADDRESS BUS is read out from RAM to respective port DATA_OUT[N-1:0] data bus.

WRITE operation
Write operation is performed whenever R/Wb is 0 during active edge of clock at respective
ports. During write operation, N-bit data present in DATA_IN [N-1:0] of respective port data bus is
recorded/written in to RAM memory cell specified by respective port ADDRESS BUS.

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Waveform 12 Read-write operation in Dual port RAM with synchronous read-write

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3. FIRST IN FIRST OUT(FIFO)

3.1 ABOUT FIFO

FIFO is acronym for First In First Out is a sequential memory, where in data written first is
read out first hence the name FIFO.

The very first FIFOs were actually asynchronous shift registers, but today almost all FIFOs
are based on dual-ported RAMs. Very small FIFOs can be implemented with flip-flops or register
arrays, sometimes even with shift registers. Basically, FIFO behaves like a shift register, but with
independent control of write and read operation. Most of the practical implementated FIFO use a
dual-ported memory (RAM), writing into one port, addressed by the internal write counter, and
reading through the other port, addressed by the internal read counter. Most FIFO designs require
free-running clocks, where the write or read operation is controlled by the respective clock enable.

A typical FIFO has a DATA IN bus, a DATA OUT bus, a free-running write clock with its
Enable control, and a free-running read clock with its Enable control.

Actual depth of the FIFO will be unknown by user since write and read pointers are implicit
in nature.

There are Flags in FIFO indicating the FULL and EMPTY status of FIFO. Whenever, data is
available at DATA IN bus to write into memory, the data present in the DATA IN bus will b stored in
memory cell pointed by write pointer and then write pointer is incremented implicitly. Once the data’s
stored in FIFO is equal to memory size, FULL flag is asserted indicating memory is full, further data
writing into memory is not possible till read operation happens. Data present is memory cell pointed
by implicit read pointer will be read out into DATA OUT bus during read pointer later read pointer
implicitly gets incremented. Data that has been written will be readied out first in sequential manner.
When all the data present in memory is readied out, EMPTY flag is arrested indicating there are no
more data in memory to read, till read operation occurs. With EMPTY flag arrested 1, if data read
operation is tried Underflow condition occurs. If write operation is tried to perform, with FULL flag
arrested 1, Overflow condition occurs. EMPTY flag will be asserted to 1 till an data is written into
FIFO, as soon as an data is written to FIFO with EMPTY flag 1, immediately after writing data into
FIFO EMPTY will b arrested 0 indicating the presence of data in FIFO for read operation. Likewise,
FULL flag will be asserted till an read operation is occurred once read operation starts, FULL will be
asserted to 0 indicating availability of memory for writing data into FIFO.

Assertion of these flags to 1 or 0 requies an internal comparion of write and read pointers. In
oreder to avoid uncontrolled asynchronous decoding spikes, the counters usually count in a Gray

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

sequence, where only one bit changes on any increment Even more complex is in the decoding of
Almost Empty and Almost Full conditions, especially when their offset values are programmable. The
“Almost” flags are useful as a “friendly early warning”, before the harsh FULL or EMPTY flags
become active, which must be obeyed instantly. The user is isolated from all these complexities, but
must accept certain timing ambiguities. The FULL and EMPTY flags will always go active exactly
on-time, to stop further reading or writing, but these flags must of necessity be allowed to take a few
clock periods to go inactive again. The “Almost” flags have a slight uncertainty caused by the
unknown phase relationship between the two clocks.

FIFOs are widely used in logic design for buffering, queuing and management of rate,
priorities and flow control in data applications. Disk controllers use FIFO as a disk scheduling
algorithm in order to be able to determine the order to service disk input and output requests. In
communications and networking, bridges, routers and switches use FIFO memory to hold data packets
that are in route to a given destination. Some devices can have several FIFOs in order to
independently and simultaneously queue several types of information. FIFO is also often used in
electronic circuits for flow control and buffering. In hardware, it generally consists of a set of read and
write pointers, control logic and storage. Storage can be flip-flops, latches, SRAM or other storage
types.

3.2 TYPES OF FIFO

Depending on free running clock, there are two kinds of FIFO namely
Synchronous FIFO.
Asynchronous FIFO.

In case of Asynchronous FIFO there will be use of two totally independent clocks for write
and read operation, but writing and reading operations are synchronous operation with respect to their
respective clock domain. Where as in case of Synchronous FIFO there will be only one clock for read
and write operation, where in read and write operation occurs with respective read and write enables
enable.

3.2.1 SYNCHRONOUS FIFO:

Synchronous FIFO consist of DATA IN bus, a DATA OUT bus, write clock with its
Enable control, and a read clock with its Enable control, FULL and EMPTY flag. Write clock and
read clock are synchronous .Internally synchronous FIFO consist of RAM as data storage element
with a signal clock source for write clock as well as read clock for write and read operation
respective. Pointers of RAM are initially initiate to 0 and are mechanised to increment upon

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

respective operation. Initial EMPTY flag will b 1 indicating no data presence in memory and FIFO is
ready for write operation. Up on receiving the write enable signal with write clock, EMPTY flag goes
low .Write pointer increments upon writing DATA IN into memory with write enable during every
write cycle. Once write pointer reaches to memory size i.e. when there is no free space availability for
further data store FULL flag is asserted to 1.If write operation is tried to perform with FULL flag 1,
data in DATA IN will not be stored or that data will b discarded/lost this condition is stated as
overflow condition .FULL flag goes to 0 immediately when read operation occurs. During read
operation data present in memory addressed by read pointer is readied out to DATA OUT port, data
will be readied out in order in which it has been written into memory. Immediately after reading data
from memory to DATA OUT, read pointer will be incremented once all the data stored in memory is
readied out or when pointer reach to write pointer EMPTY full read is asserted to 1 till an write
operation occurs. When an read operation is tried to perform with EMPTY flag 1 , error is posted
stating no data available for read operation, read operation possible is not possible till an write
operation occurs in condition is started as underflow condition. Write and read pointers will be
initialled to initial positions upon reset condition.Read and write operation can take place
simultaneously by incorporation of dual port RAM.

Figure 9 Synchronous FIFO

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

SIGNAL ATTRIBUTES DIRECTION DESCRIPTION

RESET_n INPUT Active low reset signal,upon activation
reset (RESET_n=0) FIFO will be reseted .
CS INPUT On assertion of CS ,write/read operation
Chip select is possible during respective modes.
CLK INPUT Synchronous clock for read/write
clock operation
R_EN INPUT Enable signal for read operation
Read enable
W_EN INPUT Enable signal for write operation
Write enable
DATA IN [N-1:0] INPUT N bit input data for writing data in to
Input data FIFO during write operation
DATA OUT [N-1:0] OUTPUT N bit output data read from FIFO during
Output data read operation
FULL OUTPUT A flag for indication of full memory
EMPTY OUTPUT A flag for indication of empty memory
Table 9 Synchronous FIFO

Waveform 13 Synchronous FIFO operation

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

3.2.2 ASYNCHRONOUS FIFO:

Asynchronous FIFO consist of DATA IN bus, a DATA OUT bus, write clock with its Enable
control, and a read clock with its Enable control, FULL and EMPTY flag. Write clock and read clock
are asynchronous i.e clock signals are from different clock source.Internally asynchronous FIFO
consist of RAM as data storage element with a signal clock source for write clock as well as read
clock for write and read operation respective. Pointers of RAM are initially initiate to 0 and are
mechanised to increment upon respective operation. Initial EMPTY flag will b 1 indicating no data
presence in memory and FIFO is ready for write operation. Up on receiving the write enable signal
with write clock, EMPTY flag goes low .Write pointer increments upon writing DATA IN into
memory with write enable during every write cycle. Once write pointer reaches to memory size i.e.
when there is no free space availability for further data store FULL flag is asserted to 1.If write
operation is tried to perform with FULL flag 1, data in DATA IN will not be stored or that data will b
discarded/lost this condition is stated as overflow condition .FULL flag goes to 0 immediately when
read operation occurs. During read operation data present in memory addressed by read pointer is
readied out to DATA OUT port, data will be readied out in order in which it has been written into
memory. Immediately after reading data from memory to DATA OUT, read pointer will be
incremented once all the data stored in memory is readied out or when pointer reach to write pointer
EMPTY full read is asserted to 1 till an write operation occurs. When an read operation is tried to
perform with EMPTY flag 1 , error is posted stating no data available for read operation, read
operation possible is not possible till an write operation occurs in condition is started as underflow
condition. Write and read pointers will be initialled to initial positions upon reset condition. Read and
write operation can take place simultaneously by incorporation of dual port RAM.

Figure 10 Asynchronous FIFO

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

SIGNAL ATTRIBUTES DIRECTION DESCRIPTION

RESET_n INPUT Active low reset signal,upon activation
reset (RESET_n=0) FIFO will be reseted .
CS INPUT On assertion of CS ,write/read operation
Chip select is possible during respective modes.
R_CLK INPUT clock for synchronous read operation
Read clock
R_EN INPUT Enable signal for read operation
Read enable
W_CLK INPUT clock for synchronous write operation
Write clock
W_EN INPUT Enable signal for write operation
Write enable
DATA IN [N-1:0] INPUT N bit input data for writing data in to
Input data FIFO during write operation
DATA OUT [N-1:0] OUTPUT N bit output data read from FIFO during
Output data read operation
FULL OUTPUT A flag for indication of full memory
EMPTY OUTPUT A flag for indication of empty memory
Table 10 Asynchronous FIFO

Waveform 14 Asynchronous FIFO operation

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

4. ASYNCHRONOUS DUAL PORT FIFO AN INTERFACE

BLOCK FOR OCX TRANSMITTER

OCX transmitter outputs (ERROR, VALID, SOP, EOP, 8-bit data) are given as input to a
memory interface block. Memory interface block internally consist of 3 blocks namely

a) Write mode controller block.

b) Read block.
c) Asynchronous dual port FIFO.

Figure 11 block diagram of asynchronous dual port FIFO an interface block for OCX
transmitter
4.1 WRITE MODE CONTROLLER BLOCK:

Outputs from OCX transmitter (ERROR, VALID, SOP, EOP, 8-bit data) are given as input to
write mode controller block of memory controller to generate signals (CS, W_ENABLE) for the write
mode operation of asynchronous dual port FIFO. Write mode operation of asynchronous dual port
FIFO is synchronous write operation with respect to write clock.

Figure 12 Write mode controller block.

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

Operation:

Write mode operation of ASYNCHRONOUS DUAL PORT FIFO is enabled by generating

the W_ENABLE=1 and CS=1 whenever valid data packets are received from OCX transmitter block.
Write mode of operation is enabled during following cases and all the following cases are with respect
positive edge of write clock W_CLK

Case1: When SOP=1, VALID=1 i.e. when a valid start of data packet is received ,signals
W_ENABLE and CS are asserted to 1 to enable ASYNCHRONOUS DUAL PORT FIFO
to store the data received from OCX transmitter for further use.

Case 2: When EOP=1, VALID=1 i.e. when a valid end of data packet is received ,signals
W_ENABLE and CS are asserted to 1 but in immediate positive edge of W_CLK is de-
asserted to 0 till and another valid start of data packet is been transmitted by the OCX
transmitter .

Case 3: When VALID=1 i.e. whenever a valid data packet is received ,signals W_ENABLE
and CS are asserted to 1.

Thus write mode of operation of ASYNCHRONOUS DUAL PORT FIFO is enabled as long
an valid data is begin received by OCX transmitted by making CS and W_ENABLE asserted to 1.

INPUT OUTPUT
ERROR VALID SOP EOP CS W_ENABLE
1 X X X 0 0
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 INVALID STATE
0 1 0 0 1 1
0 1 0 1 0 0
0 1 1 0 1 1
0 1 1 1 INVALID STATE
Table12 : write controller truth table

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

Waveform 15 Write controller operation

4.2 READ BLOCK:

Read block controls the read mode operation of ASYNCHRONOUS DUAL PORT FIFO.
Read operation is synchronous read operation with respect read clock R_CLK. Whenever an positive
edge of R_CLK occurs the read signal from the read block is passed to read port of
ASYNCHRONOUS DUAL PORT FIFO with CS high. Depending on signal to read port ,read
operation is enabled / disabled . Read operation is enable if READ port is asserted to 1 else read
operation is disabled.

Figure 13 Read Block

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

Waveform 16 : read controller operation

4.3 ASYNCHRONOUS DUAL PORT FIFO:

Figure 14 Asynchronous dual port FIFO

ASYNCHRONOUS DUAL PORT FIFO has a DATA IN bus, a DATA OUT bus, two totally
independent clocks for write and read operation, but writing and reading operations are synchronous
operation with respect to their respective clock domain .Clocks are free running clock with enable
control. Write enable and Write clock are generated through the write block, while read enable and
read clock are generated through the read block. Whenever write enable and chip select active signals
are generated from write controller 8-bit data present at OCX transmitter output end will be stored in
FIFO, then write pointer is incremented by 1 i.e. from valid start of data packet to till invalid data/end
of data packet is reached data from OCX transmitter output end will be stored in designed

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 ASYNCHRONOUS DUAL PORT FIFO DESIGN

ASYNCHORNOUS DUAL PORT.As soon as read signal is obtained from read module ,8 bit data
written will be read out to DATA_OUT in order in which 8-bit data was been written . Designed
FIFO as write clock frequency twice that of read clock frequency i.e. two 8 bit data from OCX
transmitter will be recorded/ written with write enable signal from write controller unit by the time an
8-bit data is read out from FIFO with read enable signal from read mode. Capacity of FIFO is 1Mb
i.e. FULL flag is asserted to 1 when 1Mb of data’s transmitted by OCX transmitter is recorded. FULL
flag will asserted to 1 till an read signal is generated from read mode, FULL flag is asserted to 0 on
the immediate read clock when read signal is enabled, indicating availability of space in FIFO for
data storage. EMPTY flag is asserted to 1 till no data entry has been done to FIFO or when all the data
in FIFO has been read. The moment, the data entry starts into FIFO, EMPTY flag will be asserted to 0
indicating data available for reading from FIFO. Data cannot be written in FIFO with FULL flag is 1
indicating no free space available for data storage, Data recording to FIFO is possible only with FULL
flag is 0 similarly Data cannot be read out from FIFO with EMPTY flag is 1 indicating no data in
FIFO, Data reading is possible only when EMPTY flag is 0. Pointers of FIFO will be reseted to initial
position upto reset signal activation i.e when an 0 signal is applied to an active low reset (reset_n)pin.

SIGNALS MODE OF
CS RESET_n W_ENABLE R_ENABLE OPERATION
0 X X X NOP
1 0 X X RESET
1 1 0 0 IDLE
1 1 0 1 READ
1 1 1 0 WRITE
1 1 1 1 READ-WRITE
Table14 : asyncronous dual port fifo funtional table

Waveform 17 : Asynchronous dual port FIFO operation

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