United States Patent to 4,004,283

Bennett et al. 45 Jan. 18, 1977

54 MULTIPLE INTERRUPT Primary Examiner-Gareth D. Shaw
MICROPROCESSOR SYSTEM Assistant Examiner-James D. Thomas
75) Inventors: Thomas H. Bennett; Earl F. Carlow, Attorney, Agent, or Firm-Charles R. Hoffman
both of Scottsdale, Ariz., Charles
Peddle, Norristown, Pa.; Michael F. 57) ABSTRACT
Wiles, Phoenix, Ariz.
(73) Assignee: Motorola, Inc., Chicago, Ill. A digital system comprises a plurality of metal-oxide
semiconductors (MOS) chip random access memory
22 Filed: Oct. 30, 1974 (RAM) and read only mcmory (ROM) and peripheral
(21) Appl. No.: 519,139 interface adaptor circuits used as part of the computer
(52) U.S. C. ............................................ 340/172.5 coupled to a common bidirectional data bus which is
(5ll Int. Cl.’........................................... G06F 9/18 coupled to and controlled by a microprocessor unit
58 Field of Search ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . 340/172.5
(MPU) chip. The digital system uses a multi-level inter
rupt circuit arrangement including a masked interrupt
(56) References Cited request input responsive to a multi-plexed interrupt
UNITED STATES PATENTS request from peripheral circuits of the system and a
non-masked interrupt request input which activates
3,286,239 1/966 Thompson ...................... 340,172.5 circuitry internal to the microprocessor chip for by
3,290,658 12/1966 Callahan .... ... 340/172.5 passing program control in initiating an interrupt sc
3,386,082 5/1968 Stafford ..... ... 340,172.5 quence.
3419,852 12/1968 Marx ...... ... 340, 72.5
3,742,457 6/1973 Calle ...... ... 340ft 72.5
3,825,902 71.974 Brown .... ... 3401 172.5
3,828,325 8/1974 Stafford .......................... 340/172.5 5 Claims, 19 Drawing Figures

O 2D SYSTEM 3D
POWER
instruction -5D SUPPLY

60
REgSTER 7d
EG
INTERRUPT
-??-----a
- NTIALIZATION
9p, Power
FA
4.
defector
LOGC RESET

INTERRUPT Od NONMASKABLE
INTERRUPT
OD
MASK - - -2 circuitry

8D 2OO
9D PERIPHERA
7d UNIT
COMMON INTERFACE a"A
INTERRUPT ADAPTER
REGUEST ar PERPHERAL
Conductor UNIT
2O f B
2D 23D

27D
26D 28O 3D
24d
NTERFACE - PERIPHERAL
25D ADAPTER
a2
UNIT
12
29D
3OD

42D
PROGRAM 4D 35d
TMER 34D 360 39D
MODULE INTERFACE CO PERPHERAL
AOAPTER UN
33D N N
37
 U.S. Patent Jan. 18, 1977 Sheet 1 of 14 4,004,283

ps - - as a -le as on - - war -J - - - - - - - - - - - - ??A - - - -

CONTROLLER SYSTEM
DATA SouRCES AND
DATA DESTINATIONS
3A 2OA

2A

22A
PERPHERAL
UNIT
--- - - -- -- - - A - --- - - - - -- -- - - - - - - --

FGO

B 2B
- as a car - a - - - - - - - - - - - -? - -- - --
e DATA Sources AND -
MP U SYSTEM DATA DESTINATIONS
3B 3B -A9B 24B 29B
MPU C. 8B 4B
P. PA 35 KEYBOARD
4B 2OB 25B 3OB
g Odd K X gC CRT :
9B 5B AYSYNCHRONoUS DATA
5B 2B 26B CHANNEL
C X K X ACA is LOWSPEED
MODEM
ray
4B
OB 6B 3B SYNCHRONOUS DATA
SB 22B 27B CHANNEL
PTM C, X. K. 8 as HIGH SPEED arians
B 7B 325ft MODEM B
7B 23B 28B 33B
MPU C X K C ACA is TEETYPE
WRITER
2B BB
-- - - - - - -- - - - - - - - - - - - -- - - - - - - - - - -
U.S. Patent Jan. 18, 1977 Sheet 2 of 14 4,004,283
U.S. Patent Jan. 18, 1977 Sheet 3 of 14 4,004,283

2D SYSTEM 3D
D POWER
see n w was aw ship SUPPLY
- s
NSTRUCTION -5D
6Dr.
REGISTER 7D POWER 4D
- --- - - - FAL
INTERRUPT ki. INITIALIZATION DETECTOR
LOGIC (RESET
NTERRUPT OD NONMASKABLE - OD
MASK INTERRUPT
"Y - - M. 2D CIRCUITRY

8D, 2OD
7D 9D PERPHERAL
UNIT
5D INTERFACE aA
COMMON
INTERRUPT
16D, ADAPTER
r - PERIPHERAL
REQUEST UNIT
CONDUCTOR 2D 5 a B
2D 23D

27 D
26D 3D
24 D 28D
INTERFACE is a PERIPHERAL
25D, ADAPTER UNIT
a2 42
29D
3OD

42D
4D 35 D
PROGRAM 34D 39D
36D
ER
ME (iro)
(iro) 3 2D INTERFACE PERPHERAL
4 OD "ADATER
YN
O
33D 37D

FIG 3
U.S. Patent Jan. 18, 1977 Sheet 4 of 14 4,004,283

NORMAL
SYSTEM
OPERATION

"RESET" CHANGES E
TO T'S
ACTIVE STATE

"RESET" FORCES
ALL SYSTEM
CIRCUITS TO
A "BENIGN' STATE

NITALIZATION CIRCUIT SETS THE

INTERRUPT MASK SO INTERRUPTS
WILL BE IGNORED DURING EXCECUTION
OF INTIALIZATION PROGRAM

NITIALIZATION CIRCUIT FORCES THE

CONTENTS OF MEMORY LOCATION N
AND N- AS THE NEXT ADDRESS TO
BE READ. THIS ADDRESS CONTAINS
THE FIRST INSTRUCTION OF THE
INTIALIZATION PROGRAM WHCH
WILL RESTORE MPU TO NORMAL OPERATION

O FG. 4O
RESUME
NORMAL
SYSTEM
OPERATION
U.S. Patent Jan. 18, 1977 Sheet 5 of 14 4,004,283

NORMAL RESET HAS FORCED ALL NORMAL SYSTEM

SYSTEM SYSTEM CIRCUITS TO OPERATIONS
OPERATION "BENIGN' STATE BY RESUMED
THIS TIME. F = -
NACTIVE LEVEL e o o Ho o o
.
RESET
N 4F
ACTIVE LEVEL
..) NITIALIZATION PROGRAM
NITALIZATION CCUT FORCES S EXCECUTED
ADDRESS OF FIRST INITIALIZATION
NSTRUCTION AT THIS TIME.

MEMORY MEMORY MEMORY MEMORY

ADDRESS CONTENTS ADDRESS CONTENTS

N-1
NSTRUCTION OF
Y NITIALZATION
X- PROGRAM
X NORMAL PROGRAM
NSTRUCTION s

Z
N21 kg)
NORMAL PROGRAM
fill-
Su -o-, -

NSTRUCTION - - - -- {

N PART OF Y
 U.S. Patent Jan. 18, 1977 sheet 7 of 14 4,004,283

2 INTERNAL STATUS CA
3. CONTROL CONTROL. A CA2
DO REGISTER A
4.
D
DATA DIRECTION
D2 REGISTER A
D3 DATA BUS
BUFFERS OUTPUT BUS
D4 (DBB)
D5 4 PAO
D6 OUTPUT
REGISTER A PA
D7 (ORA) PA2
PERPHERAL PA 3
INTERFACE
A PA4
BUS INPUT
REGISTER PA5
(BR) PA6
INPUT BUS PA7

CSO PBO
CS OUTPUT PB
REGISTER B O
CS2 CHIP (ORB) PB2
RSO SELECT PERIPHERAL PB3
AND INTERFACE
RS RAW PB4
RAW CONTRO PB5
ENABLE PB6
RESET PB7

cause
CONTROL
H DATA DIRECTION
REGISTER B 9
REGISTER B (DDRB)
(CRB)
8
7
INTERNAL STATUS CB
CONTROL B CB2

F.G. 6
U.S. Patent Jan. 18, 1977 Sheet 8 of 14 4,004,283

J <3) 6
AO DO
A D
A2 D2
A3 ADDRESS 3-STATE D3
MATRIX
A4 DECODE (28 x 8) BUFFER D4
A5 D5
A6 D6
---- D7
CS5 4J

9J 8 7
CS 2

CSO
D IOU
i 9J
MEMORY
CONTROL

READ/WRITE
FG.7
AO 6L
Al (2. DO
A2 D
A3
D2
A4 ')
ADDRESS MEMORY 3-STATE D3
A5 DECODE MATRIX
(O24x8) BUFFER D4
A6
D5
A7
D6
A8
D7
A9

CSO 8L 7L

CS
CS2 D
CS3
ACTIVE LEVEL DEFINED AT TIME OF MANUFACTURE.

FG. 8
 U.S. Patent Jan. 18, 1977 Sheet 9 of 14 4,004,283

GROUND - VssO CTS-CLEAR TO SEND

RECEIVE DATA - RXD DCD-DATA CARRIER DETECT
RECEIVE CLOCK - CRX
TRANSMIT CLOCK - CTX
REQUEST TO SEND - RSC
TRANSMT DATA - TXD
DATA LINES
NTERRUPT - RQ D4
CSO D5
CHP SELECTS < CS2 D6
CS D7
REGISTER SELECT - RS E-ENABLE
POWER (5.O.V) - VOD

2N
STATUS TRANSMIT DATA
REGISTER REGISTER
(O) (O)

TRANSMIT CLOCK-(TXC)
RECEIVE CLOCK-RXC) (RQ-INTERRUPT REQUEST
READ/WRITE-(RAW)
ENABLE-(E) CONTROL CTS)-CLEAR TO SEND
AND
DATA BUS-(DO-D7) KO SELECT
(CSO) LOGIC (RTS)-REQUEST TO SEND
CHP SELECTS K(CSI)
(CS2) (DCD-DATA CARRIER DETECT
REGISTER SELECT-(RS)

CONTROL RECEIVE DATA RECEIVE

REGISTER REGISTER
(OO) () DATA
'INDICATES--(RS RAW)
FG 9 b
U.S. Patent Jan. 18, 1977 Sheet 10 of 14 4,004,283

LNSI3COJN!O

Og| Og?
a
|
} } } }{
6

O4. O4. O4.

U.S. Patent Jan. 18, 1977 Sheet 11 of 14 4,004,283

10-O0
U.S. Patent Jan. 18, 1977 sheet 12 of 14 4,004,283

FG. 2

3C
RESTART
40

ADDRESS DATA +5
AB BUS BUS
AI3 RES 3.
RSO RE
RSI PACd A DATA
CSO
CSI
 U.S. Patent Jan. 18, 1977 Sheet 13 of 14 4,004,283

START OF CYCLE

O 50% — R
O2 50%
/
RAW
N
ADDRESS
FROM
MPU

VMA
DATA
FROM
MPU

DBE = O2

FG. 3O

FG. 3b
O

O2

RAW

ADDRESS

WMA

DATA

Eat WMA O2
U.S. Patent Jan. 18, 1977 Sheet 14 of 14 4,004,283

RESTART SEQUENCE FETCH BEGIN

RESTART INSTRUCTION
ADDRESS EXCECUTION
g CLOCK

WMA CYCLE

NOTE: FOR RESTART, 9 CLOCK MUST BE ON FOR 8

CYCLES PRIOR TO BRING ING RESTART HIGH

NONMASKABLE INTERRUPT SEQUENCE FOR POWER DOWN.

COMPLETON OF BEGIN POWER

NONMASKABLE CURRENT INST. DOWN SEQUENCE
INTERRUPT

2 CYCLES (MIN)
FG 3C
HALT CYCLE IS COMPLETED

COMPLETION OF
CURRENT INST,
(alt FETCH
EXCECUTION
OF TYPICAL
2-CYCLE INST.
CLOCK 2.
HALT IS
NITIATED
HALT/GO
WMA

BUS
AVAILABLE
ADDRESS
BUS

DATA BUS

RAW
 1.
4,004,283
2
printers, readers, plotters, terminals, etc. Other appli
MULTIPLE INTERRUPT MCROPROCESSOR cations for such microcomputer systems include com
SYSTEM puter systems and countless other applications within
RELATED APPLICATIONS the fields of transportation, automotive uses, medical
electronics, test systems, and many others.
This invention is related to the following patent appli The recent development of "Microprocessor Unit"
cations filed simultaneously herewith and assigned to (MPU) which is fabricated in the form of a MOS mono
the assignee of this application: Ser. No. 519, 150, by lithic integrated circuit, has made feasible a broad new
Bennett et al, entitled MICROPROCESSOR ARCH range of digital control applications and has, concur
TECTURE; Ser, No. 519,138 by Bennett et al entitled O rently, introduced a number of additional constraints
INTERFACE ADAPTOR ARCHITECTURE; Ser. No. which must be met for optimum system design of the
519,149 by Bennett etal entitled MICROPROCESSOR stored program digital control systems which are based
SYSTEM; Ser. No. 519,131 by Bennett et al entitled on the MPU. First, the cost and complexity of the hard
INTERFACE ADAPTOR HAVING CONTROLREG ware and programs required to work with associated
ISTER; Ser. No. 519,132, by Bennett et al entitled 15 peripheral units must be minimized. In conventional
MCROPROCESSOR CHP BUS CONTROL SYS systems based on stored program digital computers, the
TEM; Ser. No. 519,133 by Bennett et al entitled MI cost and complexity of the hardware required for the
CROPROCESSOR CHP REGISTER-BUS STRUC system to interface with a given peripheral unit was
TURE; Ser. No. 519,134, by Bennett, et al entitled usually a minor consideration when compared with the
MICROPROCESSOR CHP CIRCUITRY; Ser. No. 20 cost of the main system. Systems based on use of inte
519,135, by Bennett et al entitled MICROPROCES grated circuit microprocessors, however, are much
SOR SYSTEM DATABUS; Ser. No. 519,136 by Ben lower in cost because of the economies of integrated
nett et all entitled SPLT LOW ORDER INTERNAL circuit fabrication. In systems where an MPU is used to
ADDRESS BUS FOR MICROPROCESSOR: Ser. No. control a large number of peripherals, cost of the hard
519,137 by Bennett et all entitled INTERRUPT CR 25 ware, complexity of the interconnecting wiring and the
CUTRY FOR MICROPROCESSOR CHIP, Ser. No. quantity of memory required for program storage are
519,140 by Bennett et al entitled INTERRUPT CR often the dominant constraint. Second, systems utiliz
CUTTRY FOR MICROPROCESSOR CHIP; Ser. No. ing an MPU must be designed to operate successfully
519,141, by Mathys et all entitled CONTROL REGIS without operator intervention. In conventional systems
TER FOR INTERFACE ADAPTOR ADDRESS EX 30 based on stored program digital computers, the avail
PANSION; Ser. No. 519,142 by Carlow et al entitled ability of operator actions at key points in the overall
DATA DIRECTION REGISTER FOR INTERFACE operation of the system is generally assumed. When
ADAPTORCHIP; Ser. No. 519,143 by Carlow et al system operation is interrupted due to malfunction,
entitled INTERRUPT STATUS REGISTER FOR IN such as failure of the system power, the general pur
TERFACE ADAPTOR CHIP; Ser. No. 519,144 by 35 pose digital computer system requires than an operator
Wiles entitled NON-MASKABLE INTERRUPT M manually control the system via a control panel to
CROPROCESSOR SYSTEM; Ser. No. 519,145 by perform the required functions of rewinding tapes,
Hepworth et al entitled MASTERSLAVE CONTROL resetting discs, and reloading basic "bootstrap" pro
REGISTER FORINTERFACE ADAPTORCHIP; Ser. grams via a computer control panel. In the case of
No. 519,146 by Bennett et al entitled MICRO 40 MPU based systems, however the typical application
PROCESSOR SYSTEM INCLUDING PLURALTY assumes operation in a remote location without an
OF CONTROLLERCHPS. BACKGROUND OF THE operator present and an optimum system design must
INVENTON make provisions for the system to reinitialize itself
Since their inception, digital applications have without the assistance of an operator and accomplish
evolved fromm calculations to data processing in the this reinitialization with a minimum of extra hardware
area of control. In recent years, with the development and/or dedicated blocks of memory for special initial
of the so-called "minicomputers', applications, partic izing programs. Third, MPU based systems must be
ularly in the control area have greatly increased. Mini organized to use a minimum number of wires in inter
computers today are at the heart of many systems since connecting to peripheral devices and must provide for
they are more flexible, can be easily personalized to a SO expansion of the system in a modular fashion which
particular application, can be more readily changed or satisfies the minimum wire constraint. In a system
updated in such logic design systems, and most signifi based on conventional stored program digital comput
cantly, the cost of such computers is less than the cost ers, the requirement for additional wires to provide the
of the large purpose digital computer. Unfortunately, electrical signals required for address selection, control
the size and cost of even the smallest minicomputers 55 and interrupts for an additional peripheral device was
has limited their use to relatively large and costly sys not a major concern because it was relatively inexpen
tems. Because of this, many smaller systems are fabri sive to modify the printed circuit board structures used
cated with complex hardwire logic circuits. Recently to fabricate the system in order to make available the
developed microprocessor chips implemented using required signals and to interconnect them via special
MOS technology and associated families using periph wire. In MPU based systems however, the total range of
eral circuits now promise to bring a computing power control signals available must be predetermined at the
of minicomputers, at much lower cost, to the many new time of chip design and further, because of integrated
areas and applications, including control functions circuit package costs, and the lower production yields
such as numeric control, elevator control, and rail traf associated with the larger packages required to accom
fic control and process control. Such computers fabri 65 modated larger numbers of integrate circuit pins, it is
cated using MOS microprocessor chips may be referred important that the total number of wires dedicated to
to as microcomputers, and can be used as computer communication with peripheral devices be kept at a
peripheral equipment control displays, keyboards, minimum.
 4,004,283 4
3
SUMMARY OF THE INVENTION
FIG. 4A is a flow chart showing steps in a reset/reini
tialize sequence for a microprocessor.
An object of the invention is to provide a digital FG. 4B is a timing diagram for a reset/reinitialize
controller system allows simple and economical sharing sequence for a microprocessor.
of controller tasks to meet a given system application 5 FIG. 4C is a memory map for the reset/reinitialize
requirement. sequence for a microprocessor.
A further object of the invention is to provide on an FIG. 5 is a logic diagram of a microprocessor chip
integrated circuit chip a digital controller system which unit.
incorporates a multilevel interrupt arrangement such FIG. 6 is a block diagram of a peripheral interface
that routine interrupts from the peripheral units of a 0. adaptor.
given system arrangement are requested over a com FIG. 7 is a functional block diagram of a random
mon "interrupt request" conductor. A further object of access memory for use in a microcomputer system in
the invention is to provide a digital controller system F.G. 13.
which eliminates the need for a memory controller FIG. 8 is a functional block diagram of the 1024 x 8
circuit and an associated memory synchronization sig 15 read only memory which may be used in the system of
nal conductor. Interrupts held in abeyance or FG. B.
"masked' by program control thus allowing the pro FIG. 9A is a block diagram showing an asynchronous
grammer to establish a "polling' arrangement which communications interface adaptor's signal line designa
allows interrupts to be serviced in the order of their 20 tions.
importance. A second "non-maskable" interrupt input FIG.9B is a functional block diagram of an asynchro
is provided for more catastrophic system malfunctions nous communications interface adaptor which may be
such as power failure which must be assigned higher used in the system of FIG. B.
priority in the system data processing scheme if correct FIG. 10 is a programming model of a microprocess
system operation is to be maintaind. ing unit according to the invention.
A further object of the invention is to provide a digi F.G. 11 is a minimum configuration for a micro
tal controller system which provides maximum flexibil processor system.
ity in the application and control of peripheral units sor system.is a typical configuration for a microproces
FIG. 12
while minimizing the required peripheral interconnec F.G. 13A -13D are timing diagrams for write data,
tion through use of control register structures in inter 30 read data, restart and and non-maskable interrupt, and
face circuits associated with the system.
A further object of the invention is to provide a digi halt/go sequences for a microprocessor system.
tal controller system which uses a master system reset DETALED DESCRIPTION OF THE INVENTION
reinitialize arrangement which minimizes the amount TABLE OF CONTENTS
of time, complexity of program and quantity of pro 35
gram storage needed to resume normal system opera ENRY COLUMNS
tion. Microprocessor System
A further object of the invention is to provide a low MPU
PA
cost integrated circuit microcomputer system. RAM
Briefly described, the invention is a multi-level inter ROM
rupt system in a digital system. The digital system in ACA
Programming Model of MPU
cludes a data bus, a peripheral unit and a microproces Minimum System Configuration
System interrupts
sor chip having a masked interrupt request input and a MPU Operation
non-masked interrupt input. The microprocessor chip PIA Operation
coupled to a data bus which in turn couples to a periph 45 RAM Operation
eral adaptor chip which couples to a peripheral bus ROM Operation
ACIA Operation
which couples to a peripheral unit, the peripheral adap
tor chip also being coupled to the masked interrupt
request input of the microprocessor chip. MICROPROCESSOR SYSTEM
MOS technology is utilized to implement the above SO
mentioned chips in the presently preferred embodi The MPU system of this application is a particular
ment of the invention. means and read only memory case of a more general class of stored program data
means are coupled to the common data bus and are processing systems which may be referred to as data
also coupled to address bus means coupled to the mi controller systems. FIG. 1A shows one possible em
croprocessor chip. MOS technology is utilized to im 55 bodiment of such a data controller system. The control
plement the above mentioned chips in the presently ler system 1A consists of a group of data controllers
preferred embodiment of the invention. 3A, 4A, 5A, 13A, 14A and 15A each of which is cou
BRIEF DESCRIPTION OF THE DRAWINGS pled to a common bus 4A via, respectively, bidirec
tional bus coupler 6A, 7A, 8A, 10A, 11A, and 12A. in
FIG. 1A is a block diagram of a generalized common a controller system of this type, the system design is
bus-controller system according to the invention. optimized by specifying functions of each controller
FIG. 1B is a block diagram of an MPU system ac and interconnecting the controllers to each other via
cording to the invention. the common bus such that the total range of data pro
FIG. 2 is a partial block diagram of an MPU system cessing that has to be performed by the overall control
illustrating control register organization according to 65 ler system is efficiently subdivided into groups of tasks
the invention. to be performed by each of the controller circuits that
FIG. 3 is a partial block diagram of an MPU system make up the system. In a typical controller system,
showing an interrupt and reset/reinitialize organization. some of the controller circuits will be adapted to be
 S 4,004,283
6
operationally coupled to a group of data sources and adapt a wide variety of peripheral units to the common
data destinations 2A. Thus, in addition to the previ bus of the MPU system, as will be discussed in greater
ously recited bidirectional coupling to the common detail below.
bus, controller 13A is coupled to a bidirectional bus A similar adaptive function may be performed by the
16A, which is coupled to a peripheral unit 20a. Con asynchronous communications interface adaptor
troller 14A is coupled to a bidirectional but 17a, which (ACIA) chip shown in FIG. 1B. The ACLA chip was
is coupled to a peripheral unit 21A, and controller 15A specifically designed to handle the special data process
is coupled to a bidirectional bus 18A which is coupled ing requirements of low speed asynchronous data chan
to a peripheral unit 22A. nels. The specific embodiment of FIG. 1B shows two
FIG. 1B shows a MPU system 1B which is a specific O examples where ACIA chip 21B is coupled to the com
embodiment of a stored program digital system which mon bus 13B via bidirectional coupler 16B and also is
falls within the general category of data controller sys coupled to a low speed modulator-demodulator chip
tems. As in the previous discussion for FIG, 1A, the 31B via bidirectional peripheral unit bus 26b. The low
system is organized around a common bus, in this case, speed modem 31B is connected to a asynchronous data
the common address and data bus 13B. The MPU chip 15 channel 34B. Similarly, ACIA data chip 32B is coupled
3B is coupled to a bidirectional coupler 8B which is to the common data bus 13B via bidirectional coupler
coupled to the common bus 13B. The MPU chip per 18B and to peripheral bus 28B. Peripheral bus 28B is
forms a "master controller function' in this system coupled to a particular asynchronous data source and
since it executes stored program instructions and trans data direction, teletypewriter 33B.
mits and receives data and control signals required to 20 FIG. 2 shows another specific embodiment of an
perform over-all functions of the MPU system. The MPU system with particular emphasis on the control of
random access memory chip 4B is coupled to common the control register in adapting a wide variety of pe
bus 13B via bidirectional coupler 9B to provide tempo ripheral units to the electrical requirements of the com
rary data storage for the system. Similarly, read only mon system bus. The MPU chip 1C is coupled to the
memory chip 5B is coupled to the common bus 13B via 25 common system bus 2C which provides the means for
bidirectional coupler 10B to provide permanent data bidirectional data transmission between all the other
storage for the system. The program timer module chip chips in the system. Thus, random access memory 3C is
6B is coupled to the common bus 13B via bidirectional coupled to the common bus 2C via data coupler 4.C.
coupler 11B. This module responds to requests from The Read Only memory 5C is coupled to common bus
the MPU chip 3B to generate timing signals of long 30 2C via coupler 6C and the programmed timing module
duration and provides signals back to the MPU chip 3B 7C is coupled to common bus 2C via data coupler 8C.
when the extended time period is complete. This dele Further, common bus 2C is coupled to a group of inter
gation of data processing requirements for generation face adaptor chips. Common bus 2C is coupled to a
of timing signals to an extended duration frees the first interface adaptor chip 10C via bidirectional cou
microprocessing unit chip to perform other tasks while 35 pler 9c, a second interface adaptor chip 23C via bidi
the timing generation takes place. rectional data coupler 22C, and interface adaptor chip
For certain complex or high speed data processing 27C via bidirectional coupler 26C.
requirements, the data processing capability of the Internally to the first interface adaptor chip 10C is
MPU system may be extended by coupling one or more coupled via bidirectional data bus 2C to input logic
additional microprocessor chips to the common bus. 40 circuit 11C, which in turn is coupled to a control logic
Thus MPU chip 7B is coupled to common bus 13B via circuit 13c via bus 12C. Control logic circuit 13C is
bidirectional coupler 12B. This interconnection pro coupled to bus 14C which is coupled to the output logic
vides a further example of the manner in which control 15C and to bus 16C which is coupled to the control
ler chips of differing data processing capability may be register 17C. The output logic 15C is adapted to con
coupled to a common bus to form a data processing 45 nect to different combinations of peripheral units, in
system which meets overall data processing require this case to peripheral unit 1-1, 19C via peripheral bus
ments. 18c and to peripheral unit 1-2, 20O via peripheral bus
In a typical MPU system, the major data processing 21C. The function of the control register 17C is to
task involves the correct sequencing of data and con modify the sequential and combinatorial logic func
trol signals between data source and data destinations 50 tions of the control logic circuit 13C as dictated by
2B. Typically, communication with these data sources control words transmitted for the MPU chip 1C during
and data destinations requires the data to be processed appropriate times in the data processing sequence. This
and signal levels to be translated to put the data in function of control register 17C allows varying require
forms which are compatible with the interconnection ments of the peripheral units such as peripheral unit
and signal levels suitable for transmission on common 55 19C and peripheral unit 200 to be adapted to require
bus 13B. A special category of chips which can be ments of common bus 2c of the system.
called in general, interface adaptor chips, are used to The same type of control register organization re
perform this function. Thus the MPU system 1B has a sides in the other interface adaptor chips of the system
peripheral interface adaptor (PIA) chip 19B which is such as second interface adaptor chip 23C which is
coupled to the common bus 13B via bidirectional cou 60 coupled to the common bus 2C via bidirectional data
pler 14B and also is coupled to bidirectional peripheral coupler 22C and to peripheral unit number 2, 25C via
bus 24B. This bidirectional peripheral bus then is con bidirectional peripheral bus 24C, and interface adaptor
nected to a particular data source and data destination, chip 27C which is coupled to the common bus 2C via
in this case, a keyboard 29B. In a similar manner, PIA bidirectional coupler 26C and to three peripheral units
chip 20B is coupled to the common bus 13B via bidi 65 31C, 32C, and 33C via bidirectional peripheral buses
rectional coupler 15B and also is coupled to peripheral 28c, 29c, and 30C, respectively.
bus 25B which is coupled to the cathode ray tube FIG. 3 shows a partial view of a microprocessing
(CRT) 30b. The PIA chip is specifically designed to system arranged to highlight the structure associated
 4,004,283 8
7
with the maskable interrupt, non-maskable interrupt peripheral unit 23D and to an input control conductor
and master reset/reinitialize features of the MPU sys 22" which is connected to the same peripheral unit. The
tem. In FIG. 3, data buses and address buses have been second interface adaptor 26D has a different arrange
ment of control connections to the peripheral unit it
omitted for clarity. MPU chip 1D has as an input a serves, wherein it is coupled to three output control
common interrupt request conductor 14D which is conductors 27D, 28D, and 30D, all of which are con
connected to the other chips shown. Thus, conductor nected to peripheral unit 31 D. Second interface adap
14D is coupled to 15D, 24D, 33D, and 41D which are,
respectively, reset inputs of first interface adaptor chip tor chip 26D also is connected to an input control
17D, sound interface adaptor chip 26d, Nth (where N conductor 29D which is connected to peripheral unit
is an integer) interface adaptor chip 34D and program 10 31d. The Nth interface adaptor chip 34A shows still
timer module 42D. MPU chip 1D also has as an input to another arrangement of control conductor connections
conductor 10D which is connected to non-maskable the peripheral unit it serves wherein it connects to
interrupt circuitry 10D'. The MPU system power sup three output control conductors 35B, 36B and 38B and
ply 3D provides power to the MPU chip via conductor to one input control conductor 37B all of which are
coupled to the Nth peripheral unit 39D. The different
15
2D, which also is connected to power failure detector arrangements
circuit 4D. Power failure detector circuit 4D also is of control inputs and outputs shown for
connected to conductor 13D, which is a reset input the fact that the usechips
the interface adaptor of FIG. 3 are illustrative of
conductor to the MPU chip 1D, first interface adaptor interface adaptor allowofcontrol control registers within the
lines to the peripherals
chip 17D via conductor 16D, a second interface adap to be defined as inputs or outputs under program con
tor chip 26D via conductor 25D, the Nth interface trol.
adaptor chip 34D via conductor 33D and the program FIG. 4A shows a flow chart of the basic MPU system
timer module 42D via conductor 41D.
Internal to the MPU chip 1D, the common interrupt conductoractions that occur when the "master reset/reinitialize'
request conductor 14D is connected to interrupt mask changes to its active state. Starting from
circuit 12D. This interrupt mask circuit functions 25 normal system operation, the sequence is initiated
under program control to block out an interrupt re when the reset conductor is changed to its active state
as shown in block 1E. As previously shown in FIG. 3,
quest from any of the peripheral equipment devices of the "master reset/reinitialize' conductor is connected
the system when the MPU is performing higher priority
tasks. The interrupt mask circuit is coupled to the inter 30 to all systems circuits so that the active level on the
reset conductor input forces all system circuits to a
rupt logic circuit via internal bus 11D. Thus when the "benign"
interrupt mask is set, the common interrupt request state, the state MPU
as shown by block 2E. In this “benign"
system can safely wait until the reset
conductor 14D cannot cause the required signals on conductor goes back to its inactive level as shown by
bus 11D to initiate an interrupt sequence within the block 3E, block 5E and the interconnecting arrows 4E
interrupt logic 7D. Interrupt logic 7D also is coupled to and 6E in the flow chart. When the reset conductor
non-maskable interrupt conductor 10D. This conduc 35 changes back to the inactive state the MPU system is
tor functions to provide for a higher priority class of ready to move into a reinitialization sequence as shown
interrupts which the MPU chip must respond to imme
diately, regardless of the data processing sequence it is by arrow 7E. In this sequence the initialization circuit
performing. Thus this class of interrupts must not be 40 forces the contents of the last two locations in memory,
masked, i.e., must be "non-maskable". Interrupt logic N and N-1, as the next address memory to be read by
7D also is coupled to internal bus 8D which is con the MPU. This address contains the first instruction of
nected to initialization logic 9D. Initialization logic 9D the initialization program which restores the MPU sys
is connected to reset conductor 13D. The function of tem to normal operation when executed. This step is
13D is to signal the MPU signal that a system power shown by block 9E of the flow chart. Prior to executing
malfunction has been detected by the power failure 45 the initialization sequence, the initialization circuit sets
detector 4D and that all major system elements must be the interrupt mask 12D previously described for FIG. 3
put in a "benign" state where there will be no cata so that all interrupts will be ignored during the execu
strophic false manipulation of data within the chips of tion
of
of the initialization program. When the execution
the initialization program is complete, the MPU
the system or false data transmission to the peripheral 50 system resumes normal system operation.
units controlled by the system. When the reset conduc FIG. 4B shows the timing diagram of the reset con
tor changes to its active level in response to the detec ductor for the sequence of system operations described
tion of a power failure, the coupling of reset conductor in FIG. 4A.
13D to initialization logic 9D causes a sequence of FIG. 4C shows a partial memory map of the MPU
initialization signals to be generated which are then 55 program
coupled to the interrupt logic 7D via internal bus 8D. locations illustrating the various groups of memory
The interrupt logic 7D then causes the MPU chip to quence shown by the the
involved in
flow
reset and reinitialization se
chart of FIG. 4A.
perform the required instructions for establishing the
“benign" state via internal bus 6D which is coupled to theFIG. 5 is a block diagram of an MPU chip showing
major functional elements which allow it to execute
instruction register 5D of the MPU chip. stored program instructions and transmit and receive
The interface adaptor chips of this system also have 60 data
control conductors which are connected to peripheral MPUand control information from another chip in the
system. Central to the structure of the MPU chip
units which each of them serve. Thus the first interface
adaptor chip 17D is connected to a control conductor ismajor bidirectional internal bus 2H which is coupled to the
registers and buffers which must communicate in
18D which is an input to peripheral unit 1A, 20D and 65 order to process instructions and data. Bus 2H is cou
to an input control conductor 19D which is coupled to
the same peripheral unit 20D. Similarly, the first inter pled to program counters 4-H and 7H, stack pointer
face adaptor chip 17D is connected to an output con registers SH, 8H, index registers 6H, 9H, A accumula
tor 10H, B accumulator 11H, condition code register
trol conductor 21D which is connected to another
 4,004,283
10
12H, arithmetic logic unit (ALU) 13H, and instruction of output bus 8 allow data received from the periph
register 16H. Bus 2H also is coupled to address output eral units to be transferred from the peripheral inter
buffers 1 and 3, and to data buffers 17. Data buf face circuits to the various registers of the PIA chip and
fer 17 is coupled to eight data bus conductors D0 - ultimately, via the data bus buffer circuitry 3 to the
D7 of the bidirectional data bus which has the function 5 MPU chip of the MPU system.
of transmitting and receiving data to and from other The PIA chip also contains internal status control
chips of the MPU system. Address output buffers 3H, circuits which function to transmit and receive control
1 are coupled to sixteen address bus conductors AO signals from the MPU chip to the peripheral device and
-A15, which allow the MPU chip to select the address to relay interrupt request signals from the peripheral
location assigned to the memory and other chips of the 10 device to the MPU chip. The A internal status control
MPU system. The register arrangement shown in FIG. circuit 1 is coupled to the peripheral unit via control
5 illustrates the structure of the MPU chip as a "byte" conductors CA1 and CA2 and also is coupled to the
organized processor, so that the sixteen bit program MPU chip via the interrupt request conductor IRQA.
counter is shown as program counter 7H which con Similarly, the B internal status control circuit 20I is
tains the low order eight bits and program counter 4H 15 coupled to the peripheral unit via control conductors
which shows the high order eight bits. Stack pointer CB1 and CB2 and also is coupled to the MPU chip via
registers 8H and SH and index registers 9H and 6H the interrupt request conductor IROB.
show the same structural division. The PIA chip also contains chip select and read/write
in addition to executing stored program instructions, control circuit 12 which is coupled to conductors CS0,
the MPU chip alters the data processing sequence of 20 CS1, CS2, RSO, RS1, R/W, Enable, and Reset, which
the system in response to various control inputs and transmit control signals from the MPU chip. The chip
accordingly generates other control outputs. Those select and read/write control circuit generates internal
functions are performed by the control portion of the register selection and circuit timing signals which act as
instruction decode and control circuit 14H. The in control signals for the other registers of the PIA chip.
struction decode and control circuit 14H is coupled to 25 For clarity, the various conductors for these signals
the clock conductors 91 and O2, the reset input con have been omitted from FG. 6.
ductor, the non-maskable interrupt (NMI) conductor, FIG. 7 shows a functional block diagram of a typical
the halt conductor, the interrupt request (IRO) con random access memory (RAM). The particular RAM
ductor, the prestate control (TSC) conductor, the data in this figure is organized as 128 words of eight bits per
bus enable (DBE) input conductor, the bus available 30 word. The selection of a particular word is accom
(BA) output conductor, the valid memory address plished by a unique combination of address signals on
(VMA) output conductor and the read/write (R/WO the seven address conductors A0 - A6 which are cou
output conductor. Instruction decode and control cir pled to the address decode circuit 1.J. The output of
cuit 14 also is coupled to the instruction register 16H address decode circuit 1.J are the 128 word select con
via bus 15. It is this interconnection which allows the 35 ductors 3J - 4J which are coupled to memory matrix
stored program instructions to be transmitted to in 2J. When selected, the eight memory cells form the
struction register 16H from the bidirectional data bus selected word are either read on to or written from the
via internal data bus2H. These instruction are decoded eight bit conductors SJ which are connected to three
by the instruction decode and control circuit 14H to state buffer 6J. Three-state buffer 6J is coupled to the
generate the appropriate sequence of internal signals data bus of the MPU system via the eight data bus
and register operations. conductors D0 - D7 and also are coupled to the mem
F.G. 6 is a block diagram of a of a peripheral inter ory control circuit H8 via conductor 7. The function
face adaptor circuit showing the major functional ele of the three-state buffer is to present a very high imped
ments involved in adapting and controlling peripheral ance to the eight data bus conductors D0 - D7 during
units the MPU system. The eight conductors D0 - D7 those times when the RAM is not being accessed so
of the MPU data bus are connected to the data bus that the data bus connections to the RAM do not load
buffer circuit 3, which in turn is connected to bus the MPU system data bus.
input register 6 via the internal bus 6' and to the The additional address selection required to define
output bus AI. Data and control words from the MPU when aparticular RAM is to be active is provided by chip
data bus are transmitted via data bus buffer circuit 3 SO select conductors CSO, CS1, CS2, CS3, CS4, and CS5.
and are stored in bus input register 6 pending transfer These six conductors are coupled to the six input NAND
to the other registers of the PIA chip. This transfer is gates 9J with conductor CS3 being coupled via inverter
accomplished via input bus 7 which is coupled to the 11J and conductor CSObeing coupled via inverter 10.J.
bus input register 6 and is coupled to the A control When selected, the output of NAND gate 9J transmits a
register 2, the A output register 14, the B output 55 logical "1" to a memory control circuit AJ via conductor
register 10, the A direction register 4, the D data 9J'. The memory control circuit AJ also is coupled to the
direction register 19, and the B control register 17. read/write conductor from the MPU chip with the result
The output portion of the PIA chip is divided into two that the required control signal levels are transmitted to
sections - The 'A' side and the 'B' side. Thus, the the three-state buffer 6J via conductor 7.
eight conductors PAO - PA7 of the bidirectional pe 60 via conductor 7.
ripheral bus "A" are coupled to peripheral interface FIG. 8 shows a functional block diagram of a typical
circuit A 9 and the eight conductors PB0 - PB7 of the read only memory (ROM) used in the MPU system.
bidirectional peripheral bus "B" are coupled to the The particular ROM shown in FIG. 8 contains 8,192
peripheral interface circuit B, 11. The peripheral in bits of information organized as 1,024 words of eight
terface circuits both are coupled to output bus 8 which bits per word. The functional organization of the ROM
is coupled to A control register 2, A data direction is very similar to that of the RAM previously described
register 4, data bus buffers circuit 3, B control register in FIG. 7. Ten address conductors (AO - A9) of the
17, and B data direction register 19. The connections MPU system address bus are coupled to an address
 4,004,283 12
11
decode circuit 1. The word selection outputs 2L-3L sixteen bit program counter designated TC, the sixteen
of the address decode circuit 1L are coupled to the bit stack pointer designated SP and the eight bit condi
memory matrix 4L. The selected word of the memory tion code register which records the system state at the
in the memory matrix 4L then produces data signals on various stages of an MPU data processing operation. A
the eight bit line conductors 5L which are coupled more detailed description of these elements of the pro
from the memory matrix 4L to the three-state buffer gramming model and the way in which they interact in
circuit 6L. The control input for the three-state buffer performing a MPU program instruction is given in
6L is provided by conductor 7L which is coupled to the greater detain below.
four input NAND gate 8L. The four chip select con MNIMUM SYSTEM CONFIGURATION
ductors CSO - CS3 provide the additional selection 10
information required to select a given ROM chip and FIG. 11 shows a minimum configuration for an MPU
also determine the correct signal for the three-state system including the detailed interconnection of the
buffer circuit 6L via the coupling of conductors 7 L. various chips and circuits in the system. MPU chip 6P
The output of three-state buffers 6L is coupled to the is connected to conductor TSC for three-state control
eight data conductors. D0 - D7 of the MPU system data 5 and to conductor RES for reset. Both of these conduc
bus so that the selection of a particular word in the tors are coupled to restart circuit 4P, which is used to
ROM chip results in the appropriate signals on the generate the reset and three-state control signals in this
eight data conductors D0 - D7. Three-state buffer particular case. The MPU chip 6P is coupled to the two
circuit 6L also responds to control signals on conductor phase clock generator circuit via clock conductors ol
7L to present a high impedence to the eight data bus 20 and 2 and provides a "valid memory address' signal to
conductors. D0 - D7 when the ROM is in its unselected the two phase clock circuit 1P via conductor VMA.
state. Conductor 2 also is connected to the data bus enable
FIG. 9A and FIG. 9B relate to the asynchronous (DBE) input of the MPU in this particular case.
communications circuit adaptor (ACLA), another type For this particular configuration the MPU chip
of adaptor circuit used to interconnect a particular 25 makes use of the ten address conductors AO-A9 and
class of peripheral units to the MPU system. FIG. 9A address conductors A13 and A14. The ten address
shows a block diagram summarizing the input and out conductors AO-A9 are connected to the ROM2P and
put conductors which are connected to the ACIA. The the seven conductors A0 - A6 are connected to the
basic function of the ACIA chip is to receive and trans RAM 5P. In addition, address conductor A13 is con
mit serial asynchronous data via conductors RXD and 30 nected to one enable input of ROM. 2P and one enable
TXD and to perform the appropriate control functions, input of RAMSP. Similarly, address conductor A14 is
parallel to serial or serial to parallel conversion re connected to another enable input of ROM. 2P and
quired for compatibility with the eight data conductors another enable input of RAM 5P. Address conductors
D0 - D7 of the MPU system data bus which must oper A13 and A14 further are connected, respectively, to
ate synchronously. Address selection is accomplished 35 the CS1 and CS2 inputs to the PIA chip 3P. Address
by conductors CS0, CS2, CS1, and RS which are con conductors A0, A1, and A2 from the ten conductor
nected to the address bus of the MPU system. The group A0 - A9 are connected, respectively, to inputs
ACIA chip also has conductor CRX and CTX to trans RSO, RS1, and CSO of the PIA chip 3P. Address con
mit and receive clock and conductors DCD, CTS, and ductors A13 and A14 also are connected to the chip
RTS, which are coupled to the associated modem or 40 select decoder circuit 7P which is coupled to an input
peripheral device. The ACIA chip also has an interrupt to the two phase clock circuit 1P. A function of the
request conductor IRO for transmitting interrupt re chip select decoder circuit is the recognition of particu
quests to the microprocessor chip as previously dis lar address combinations for which the system opera
cussed in FIG.3 and the control conductors E and R/W tion requires an "expansion" of a 92 clock pulse
which are coupled to the MPU chip. 45 length. When these combinations are decoded the out
FIG. 9B shows a functional block diagram of the put of the chip select decoder 7P is coupled to the
ACIA showing the basic logic and register elements "programmable' input of the two phase clock circuit
used and repeating the conductor connections previ 1P, indicating that the length of a 92 clock pulse should
ously discussed for FIG.9A. The basic registers of the be expanded.
system are the status register 1M, the transmit data 50 MPU chip 6P also produces a "valid memory ad
register 2N, the control register 4N and the receive dress' signal on conductor VMA which is coupled to
data register 5N. In addition the ACIA chip contains a two phase clock circuit 1. This signal indicates that a
control and select logic circuit which produces the given clock cycle is valid for addressing information
appropriate internal control signals in response to the from memory. The two phase clock circuit 1 contains
control conductors previously discussed in FIG. 8. A 55 logic which combines the valid memory address signal
more detailed description of the function of each of the with the phase two clock signal to produce the logical
conductors which are coupled to the ACA chip and AND of these two signals, which is coupled to conduc
tor VMA2 which is coupled to an enable input of the
the ACIA chip overall operation are given below.
RAM chip 5P and the enable input of the PIA chip 3P
PROGRAMMING MODEL OF MPU SYSTEM 60 to provide the basic clock timing for these two chips.
FIG. 10 shows a programming model of the micro The MPU chip is coupled to the eight data conduc
processor unit (MPU) in terms of the major registers tors D0 - D7 of the bidirectional data bus which in turn
and counters involved in the execution of program is coupled to RAM chip SP, ROM chip 2P, and the PIA
instructions. The basic elements of this model are the chip 3P, providing the basic bidirectional data trans
two eight bit accumulators A and B designated ACCA 65 mission path for the system. The MPU chip also has a
and ACCB, the sixteen bit index register designated IX, go?halt (HALT) input, which for this minimum system
the sixteen bit program counter designated DC, and configuration is coupled directly to a five volt power
ACCB, the sixteen bit index register designated IX, the supply to provide a steady state "go' condition.
 13
4,004,283
PIA chip 3P of this minimum system configuration is
arranged to connect to two peripheral devices "A' and
"B". Control inputs and outputs to peripheral "A" are
coupled to PIA chip 3P via conductors CA1 and CA2.
Similarly, control conductors from peripheral "B" are
coupled to PLA chip 3P via conductors CB1 and CB2.
Data transfer to and from the two peripheral units are
provided by the eight conductor peripheral bus PAO –
PA7 and the eight conductor peripheral bus PB0 -
PB7, each of which are coupled between the associated
peripheral unit and the PIA chip 3P. Interrupt request
signals are derived from control signals on CA1, CA2,
CB1, and CB2 and are transmitted to the MPU chip via
conductors IRQA and IRQB which multiplex to the
common interrupt request conductor IRQ which is
coupled to the MPU chip.
F.G. 12 shows the block diagram of an expanded
MPU system. The mode of interconnection and the
functions of the various elements of the system are the
same as previously recited for FIG. 11 except that the
system has been expanded for this case. MPU chip 20
now is connected to four RAM chips, 5Q, 6Q, 7Q and
80, four ROM chips 90, 100, 11O and 12O and three
PIA chips 130, 14Q and 15Q.
SYSTEM INTERRUPTS
Regarding differences from the system shown in FIG.
11, the system power supply and the power failure
detector have been omitted for simplicity, and non
maskable interrupt circuit 4Q and the halt?go logic 10
have been added. Nonmaskable interrupt circuit 4Q
interrupts the MPU chip's normal operating sequence
via the NMI input during catastrophic system malfunc
tions which require immediate MPU chip action, The
halt?go logic circuit 10 allows the MPU system to be
operated in a manual or "step-by-step" mode via sig
nals on the run/step conductor and the step conductor,
which is coupled to the halt/go logic circuit 10. The
system block diagram of FIG. 12 also omits the chip
select decoder which was used for expansion of the 2
clock in FIG. 11. Also, in FIG. 12, the common inter
rupt request conductor IRO is coupled to a pullup
resistor which is coupled to the -5 volt power supply
and is coupled to the IRQA and IROB inputs of the
three PIA chips 130, 14Q, 15Q.
If the elements of FIG. 1B are implemented as a
family of monolythic integrated circuits fabricated in
the N-Channel Silicon Gate technology, many features
result which offer technical advantages and system
economies to the user. The invention associated with
these features is recited in specific detail later in this
application. At this initial stage of the system descrip
tion, it is useful to list some, but not really all, of these
features including:
Eight-bit parallel processing,
Bi-directional data bus,
Sixteen-bit address bus-65 K bytes of addressing,
72 instructions-Variable length,
Seven addressing modes-Direct, Relative,
Immediate, Indexed, Extended, Implied
and Accumulator,
Variable length stack,
Power-on restart,
Maskable interrupt vectoring,
Separate Non-maskable Interrupt-Internal,
registers saved in stack,
Six Internal Registers, Two Accumulators,
Index Register, Program Counter, Stack
14
Pointer and Condition Code Register,
Direct Memory Addressing (DMA) and multiple
processor capability,
Clock rates as high as 1 MHz,
Simple interface with TTL,
Halt/Go and single instruction execution
capability
MPU OPERATION
10 The following discussion provides further orientation
on the basic elements of the MPU system and how they
functionally interrelate.
The Microprocessor Unit (MPU) performs the basic
control functions for the MPUSystem by executing the
15 internal or external data manipulations required by the
programs stored in the MPU system memory. FIG. 2
shows a basic block diagram of the internal logic ele
ments of the MPU which accomplish this. FIG. 2 also
shows the various electrical signal lines required for the
20 MPU to operate and communicate with the other inte
grated circuits (IC's) of the system. Referring to FIG. 5,
a basic description of the MPU's internal logic ele
ments is as follows.
The output buffer registers 1H and 3H hold the ad
25 dress of the memory location whose contents are re
quired for a given MPU operation and transmit it to
that location via the system address bus.
The data buffer 17H holds the data required for or
resulting from, a given MPU operation. Data from
30 external data sources or received from external data
destinations enters this register via the system data bus.
The instruction register 16H holds the program in
struction received from the MPU system memory,
pending interpretation by the Instruction Decode and
35 Control Circuit.
The instruction decode and control circuit 14H inter
prets (i.e., decodes) the program instruction entering
the MPU from a system memory and generates control
signals needed to manipulate data contents of the vari
40 ous MPU registers.
The program counter 4H, 7H which is a counter/reg
ister, holds the address of the next memory location
required by the stored program for a given MPU opera
tion as indicated by the results of decoding a given
45 instruction.
The stack pointer 5H, 8H register contains the ad
dress of a special location in system memory which
must be retained while the MPU performs other se
quences of operations.
50 The index register 6H, 9H contains data used to mod
ify the system memory address specified in the Program
Counter for certain classes of MPU operations.
The accumulator registers 6H and 9H provide a tem
porary storage location for data as it is manipulated
55 during a given MPU operation.
The condition code register 12H maintains a record
of special conditions required or generated by certain
classes of MPU system operations that imply a change
in the way data is to be manipulated.
60 The arithmetic logic unit (ALU) 13H contains logic
required to perform arithmatic data manipulations
such as addition when they are required by a given
MPU operation.
A basic description of the MUP's electrical signal
65 lines follows.
The Vpr and Vss lines provide the DC power re
quired by the MPU circuit. Typically, VD = +5 volts
and VSS = 0 volts.
 4,004,283 16
15
The phase one clock (91) and phase two clock (2) The interrupt request (IRQ) input requests that an
are non-overlapping clocks that run at the V voltage interrupt sequence be generated within the machine.
level. Sixteen pins are used for the address bus The microprocessor (or processor) will wait until it
(A0-A15). The outputs are three-state bus drivers completes the current instruction that is being exe
capable of driving one standard TTL load and 30 pfor 5 cuted before it recognizes the request. At that time, if
one low power TTL load and 130 pf. When the output the n-6 mask bit in the Condition Code Register is not
is turned off, it is essentially an open circuit. This per set (i.e., interrupt masked), the machine will begin an
mits the MPU to be used in DMA applications. For interrupt sequence. The Index Register, Program
further discussion of TTL circuits, see "Analysis and Counter, Accumulators, and Condition Code Register
Design of Integrated Circuits', edited by Lynn, et al, 10 are then stored away on the stack during the interrupt
McGraw Hill Book Co., 1967. sequence. Next the MPU will respond to the interrupt
Eight pins are used for the data bus (D0-D7). It is request interruptsby setting the interrupt mask bit high so that no
bidirectional, transferring data to and from the memory further16-bit address will
may occur. At the end of the cycle, a
be loaded that points to a vectoring
and peripheral devices. It also has three-state output
buffers capable of driving one standard TTL load and S address which is located in memory locations N-6 and
n-7. An address located at these locations causes the
30 pf or one low power TTL load and 130 pf. MPU to branch to an interrupt routine in memory.
When the halt/go, or halt input is in the high state,
the machine will fetch the instruction addressed by the to interruptin logic
As seen FIG. 3, instruction register SD is coupled
7D; as seen in FIG. 5, instruction
program counter and start execution. When low, all register 16H is coupled to instruction decode circuitry
activity in the machine will be halted. This input is level 20
sensitive. In the halt mode, the machine will stop at the 14H. (Instruction register 16H of FIG. 5 which is the
end of an instruction, the Bus Available line will be at same instruction register as SD in FIG. 3.) The instruc
a logical one level, Valid Memory Address will be at a tion register includes input gating circuitry (not shown)
enabled by a signal from interrupt logic 7D via coupling
logical zero, and all other three-state lines will be in the means 6D for conditionally allowing loading of an in
high impedence or three-state, mode. 25
The halt line must go low with the leading edge of struction from data input/output circuitry (i.e., data
phase one to insure single instruction operation. If the buffer 17H in FIG. 5) into the instruction register (5D
Halt line does not go low with the leading edge of phase in FIG. 3 or 16H in FIG. 5). This means that loading of
one, one or two instruction operations may result, de the next instruction is conditioned upon the informa
pending on when the halt line goes low relative to the 30 tion previously stored in the interrupt mask bit of the
condition code register. This is another way of saying
phasing of the clock.
The three-state control (TSC) input causes all of the that the loading of the subsequent instruction into the
instruction register is inhibited by a particular stored
address lines and the Read/Write line to go into the off
or high impedance state, The Valid Memory address state, in this case a logical 1, in the interrupt mask bit
and Bus Available signals will be forced low. The data 35 of condition code register 12H of FIG. S. When the
bus is not affected by TSC and has its own enable (Data interrupt
set,
mask bit in the condition code register 12H is
instruction decoder 14H operates on inputs from
Bus Enable). In DMA applications, the Three-State instruction register 16H so as to generate the above
Control line should be brought high on the leading edge mentioned interrupt sequence when the above-men
of the Phase One Clock. The 91 clock must be held in 40 tioned input gating circuitry is inhibited by the above
the high state for this function to operate properly. The mentioned interrupt signal from the interrupt logic
address bus will then be available for other devices to
directly address memory. Since the MPU is a dynamic circuitry 7D (FIG. 3). For a more detailed description
device, it must be refreshed periodically or destruction of the condition code register, see copending patent
of data will occur in the MPU. application Ser. No. 519,136 filed on even date here
The read/write (R/W) output signals the peripherals 45 with, page 18, lines 5-8. The structure of the condition
and memory devices whether the MPU is in a Read code register 12H is shown in the logic diagram (which
is the logic diagram of the entire microprocessor 10)
(high) or Write (low) state. The normal standby state obtained by piecing FIGS. 3AA-3TT of Ser. No.
of this signal is Read (high). Three-State Control 519,136 together.
(TSC) going high will cause Read/Write to go into the 50 cuitry is shown in More detail on the interrupt cir
copending patent application Ser.
off (high impedance) state. Also, when the machine is No. 519,137, filed on even date herewith, in FIGS. 2
halted, it will be in the off state.
The valid memory address (VMA) output indicates and 3 detail, thereof, and also on pages 18 and 19 thereof.
to memory and peripheral devices that there is a valid More interface
including a complete logic diagram, of the
adaptor described in the instant application
address on the address bus. In normal operation, this
signal should be ANDed with 92 for enabling memory 55 may be found in copending patent application Ser. No.
and peripheral interface devices such as the PIA and 519,138 filed on even date herewith.
The Go/Halt line must be in the Go (high) state for
ACLA. This signal is not a three-state signal, one stan interrupts to be recognized. If it is in the Halt (low)
dard TTL load may be directly driven by this active state, the MPU will be halted and interrupts will have
high signal. 60 no effect.
The data bus enable (DBE) input is a three-state
control signal for the MPU (external) data bus and will lowThestate;bus available (BA) signal will normally be in the
when activated, it will go to the high state
enable the bus drivers when in the high state. This input indicating that
is TTL compatible; however in normal operation, it the address bustheis available. microprocessor has stopped and that
This will occur if the Gof
should be driven by 92. During an MPU read cycle, the
data bus drivers will be disabled internally. When it is sor is in the WAIT state as a state
65 Halt line is in the Halt (low) or the microproces
result of the execution of
desired that another device control the data bus such as
in Direct Memory Access (DMA) applications, DBE drivers a WAIT instruction. At such time, all three-state output
should be held low. will go to their off state and other outputs to
 17
4,004,283
18
their normally inactive level. The microprocessor is cal, shift, rotate, load, store conditional or uncondi
removed from the WAIT state by the occurrence of a tional branch, interrupt and stack manipulation in
maskable or non-maskable interrupt. structions. A listing of these instructions is given in
The reset input is used to start the MPU from a power tables 7.
down condition, resulting from a power failure or an 5 The MPU is an eight-bit processor that has seven
initial start-up of the microprocessor. If a positive edge address modes that can be used by a programmer, with
is detected on the input, this will signal the MPU to the addressing mode a function of both the type in
begin the restart sequence. This will restart the MPU struction and the coding within the instruction. A sum
and start execution of a routine to initialize the micro mary of the addressing modes for a particular instruc
processor. All the higher order address lines will be O tion can be found in Table 9 along with the associated
forced high. For the restart, the last two (n-1, n) loca instruction execution time that is given in machine
tions in this area will be used to load the program that cycles. With a clock frequency of 1 MHz, these times
is addressed by the program counter. would be microseconds.
The non-maskable interrupt (NMI) input requests In accumulator only (ACCK) addressing, either ac
that a non-masked-interrupt sequence be generated S cumulator A or accumulator B is specified. These are
within the microprocessor. As with the Interrupt Re one-byte instructions.
quest signal, the microprocessor will complete the cur In immediate addressing, the operand is contained in
rent instruction that is being executed before it recog the second and third byte of the instruction. No further
nizes the NMI signal, The interrupt mask bit in the addressing of memory is required. The MPU addresses
Condition Code Register has no effect on NMI. this location when it fetches the immediate instruction
The Index Register, Program Counter, Accumulators for execution. These are two/three-byte instruction.
and Condition Code Register are stored away on the In direct addressing, the address of the operand is
stack. At the end of the cycle, a 16-bit address will be contained
loaded that points to a vectoring address which is lo addressinginallows the second byte of the instruction. Direct
the user to directly address the lowest
cated in memory locations n-2 and n-3. An address 25 256 bytes in the machine, i.e., locations zero through
loaded at these locations causes the MPU to branch to 255. That part of the memory should be used for tem
a non-maskable interrupt routine in memory. porary data storage and intermediate results. In most
To complete the discussion of the MPU as a func configurations, it should be a random access memory,
tional element of the system, it is useful to re-examine These are two-byte instructions,
its characteristics from the more specific viewpoint of 30 In extended addressing, the address contained in the
programming. To the programmer, the MPU consists
of a series of registers available for his use and a set of second byte of the instruction is used as the higher
eight-bits of the address of the operand. The third byte
instruction codes which will manipulate data within
these registers in a defined manner, dependant on the of the instruction is used as the lower eight-bits of the
sequence of instruction codes the programmer 35 address for the operand. This is an absolute address in
memory. These are three-byte instructions.
chooses.
The MPU has three sixteen bit registers and three second In indexed addressing, the address contained in the
eight-bit registers available for use by the programmer. register's byte of the instruction is added to the index
These registers are shown in FIG. 10 and function as then addedlowest eight-bits in the MPU. The carry is
to the higher order eight-bits of the index
follows: 40
The program counter is a two byte (16 bits) register register. This result is then used to address memory,
that points to the current program address. Its contents The modified address is held in a temporary address
are incremented after execution of an instruction. register so there is no change to the index register.
The stack pointer is a two byte register that contains These are two-byte instructions.
the address of the next available location in an external 45 In the implied addressing mode the instruction gives
push-down/pop-up stack. This stack is normally a ran the address (i.e., stack pointer, index register, etc).
dom access ReadWrite memory that may have any These are one-byte instructions.
location (address) that is convenient. In those applica In relative addressing, the address contained in the
tions that require storage of information in the stack second byte of the instruction is added to the program
when power is lost, the stack must be non-volatile. 50 counters lowest eight-bits plus two. The carry or bor
The index register is a two byte register that is used to row is then added to the high eight-bits. This allows the
store a sixteen bit memory address for the Indexed user to address data within a range of 125 to +129
mode of memory addressing. bytes of the present instruction. These are two-byte
The MPU contains two 8-bit accumulators that are instructions.
used to hold operands and results from an arithmetic 55 PA OPERATION
logic unit (ALU).
The condition code register indicates the results of an The Peripheral Interface Adapter provides a rela
Arithmetic Logic Unit operation: Negative (N), Zero tively universal means of interfacing peripheral equip
(Z), Overflow (V), Carry from bit 8 (C), Half carry ment to the Microprocessing Unit (MPU). This device
from bit 3 (H), and the Interrupt mask bit (I). These 60 is capable of interfacing an MPU to peripherals
bits of the Condition Code Register are used as testable through two 8-bit bidirectional peripheral data buses
conditions for the conditional branch instructions. The and four control lines. No external logic is required for
unused bits of the Condition Code Register (B6 and interfacing to most peripheral devices.
B7) are ones. The functional configuration of the PIA is pro
The MPU has a set of 72 different instructions that 65 grammed by the MPU during system initialization.
have been designed for uses such as in point-of-sale Each of the peripheral data lines can be programmed to
terminals, data communications, and peripheral con act as an input or output, and each of the four control
trol. Included are binary and decimal arithmetic, logi finterrupt lines may be programmed for one of several
 4,004,283 20
19
control modes. This allows a high degree of flexibility the output mode, the low state of CA2 (CB2) is estab
in the over-all operation of the interface. lished by an MPU Read or Write operation, while the
FIG. 3 shows a basic block diagram of the logical high state may be determined by an active transition of
elements of the PIA which accomplish the required CA1 (CB1), an E pulse transition, or by an MPUWrite
interface functions in accordance with the functional 5 operation.
configuration programmed by the MPU. The definition FIG. 3 also shows the various electrical signal lines
of allowable configurations and the internal control required. These signal lines fall into either the PLA to
established by the functional elements for the configu MPU category or the PLA to peripheral unit category
rations is as follows. and operate as follows:
There are six locations within the PIA accessible to 10 The PIA interfaces to the MPU with an eight-bit
the MPU data bus, two Peripheral Interfaces, two Data bidirectional data bus, three chip select lines, two regis
Direction Registers, and two Control Registers. Selec ter select lines, two interrupt request lines, read/write
tion of these locations is controlled by the RSO and RS1 line, enable line and reset line. These signals permit the
inputs together with bit 2 in the Control Register, as MPU to have complete control over the PIA.
shown in Table 1. 5 The bidirectional data lines (D0-D7) allow the trans
A reset pulse has the effect of loading logical zeros in fer of data between the MPU and the PIA. The data bus
all PIA registers. This will set PAO-PA7, PB0-PB7, CA2 output drivers are three-state devices that remain in the
and CB2 as inputs, and all interrupts will be disabled. high-impedance (off) state except when the MPU per
The PIA must be configured during the restart program forms a PIA read operation. The Read/Write line is in
which follows the reset pulse. 20 the Read (high) state when the PLA is selected for a
Details of possible configurations of the Data Direc Read operation.
tion and Control Register are as follows. The enable pulse, E, is the only timing signal that is
The two Data Direction Registers DDRA and DDRB, supplied to the PLA. Timing of all other signals is refer
reference numerals 4 and 19, respectively in FIG. 6, enced to the leading and trailing edges of the E pulse.
allow the MPU to control the direction of data through 25 In normal operation with the MPU this input is a MPU
each corresponding peripheral data line. A data Direc "Valid Memory Address' signal (designated VMA)
tion Register bit set at 0 configures the corresponding
peripheral data line as an input; a 1 results in an output. ANDed with the phase two clock (VMA-92).
The PIA Read/Write (R/W) signal is generated by
The two Control Registers CRA and CRB, reference the MPU to control the direction of data transfers on
numerals 2 and 17, respectively, in F.G. 6, allow the 30 the Data bus. A low state on the PIA Read/Write line
MPU to control the operation of the four peripheral enables the input buffers and data is transferred from
control lines CA1, CA2, CB1 and CB2. In addition they the MPU to the PLA on the E signal if the device has
allow the MPU to enable the interrupt flags. Bits 0
through 5 of the two registers may be written or read by been selected. A high (i.e., a "high' logic level) on the
the MPU when the proper chip select and register se the bus. Theline
35 Read/Write sets up the PIA for a transfer of data to
lect signals are applied. Bits 6 and 7 of the two registers proper address andoutput
PIA
the
buffers are enabled when the
enable pulse E are present.
are read only and are modified by external interrupts The active low Reset line is used to reset all register
occurring on control lines CA1, CA2, CB1 or CB2. The bits in the PIA to a logical zero (low). This line can be
format of the control words is shown in Table 2.
Bit 2 in each control register CRA and CRB (CRA2 40 used as a power-on reset and as a master reset during
and CRB2) allows selection of either a Peripheral In system operation. -
terface Register or the Data Direction Register when toThese three input signals CS, CS1 and CS2 are used
select the PIA. CS0 and CS1 must be high and CS2
the proper register select signals are applied to RSO and must be low for selection of the device. Data transfers
RS1.
are
The four interrupt flag bits CRA-6, CRA-7, CRB-6, 45 Read/Write then performed under the control of the Enable and
and CRB-7 are set by active transitions of signals on the signals. The chip select lines must be stable
four Interrupt and Peripheral Status lines when those forThe the duration of the E pulse.
lines are programmed to be interrupt inputs. These bits varioustwo register select lines are used to select the
registers inside the PIA. These two lines are
cannot be set directly from the MPU Data Bus and are used
reset indirectly by a Read Peripheral Data Operation 50 selectina conjunction with internal Control Registers to
particular register that is to be written or read.
on the appropriate section. The Register select lines should be stable for the
The two lowest order bits of the control registers
CRA and CRB are used to control the interrupt input duration of the E pulse while in the read or write cycle.
The active low Interrupt Request lines (IRQA and
lines CA1 and CB1. Bits CRA-0 and CRB-0 are used to
enable the MPU interrupt signals IRQA and IRQB, 55 IROB) through
act to interrupt the MPU either directly or
interrupt priority circuitry. These lines are
respectively. Bits CRA-1 and CRB-1 determine the
active transition of the interrupt input signals CA1 and "open source" (no load device on the chip) and are
CB1 (see Table 3). capable of sinking a current of 1.6 mA from an external
Bits 3, 4 and 5 of the two control registers CRA and source. This permits all interrupt request lines to be
CRB are used to control the CA2 and CB2 Peripheral 60 tied together in a wire-OR configuration.
Control lines. These bits determine if the control lines Each Interrupt Request Line has two internal inter
will be an interrupt input or an output control signal. If rupt flag bits that will cause the Interrupt Request line
bit AC-5 (BC-5) is low, CA2 (CB2) is an interrupt to go low. Each flag bit is associated with a particular
input line similar to CA1 (CB1) (Table 4). When AC-5 peripheral interrupt line. Also four interrupt enable bits
are provided in the PLA which may be used to inhibit a
(CRB-5) is high, CA2 (CB2) becomes an output signal 65 particular interrupt from a peripheral device. Servicing
that may be used to control peripheral data transfers.
When in the output mode, CA2 and CB2 have slightly an interrupt by the MPU is accomplished by a software
different characteristics see Tables 5 and 6. When in routine that, on a prioritized basis, sequentially reads
 21
4,004,283
22
and tests the two control registers in each PIA for inter RAM OPERATION
rupt flag bits that are set.
The Interrupt Flag is cleared (zeroed) as a result of The MPU system is readily adaptable to use with
an MPU Read Peripheral Data Operation. many different kinds of RAMs. One specific type, a
The PA provides two 8-bit bi-directional data buses 1024 bit static RAM, as shown in FIG. 7, is discussed
and four interrupt?control lines for interfacing to pe herein. This memory is byte organized as 128 words of
ripheral devices. 8-bits per word and is specifically designed for use in
Each of the peripheral data lines can be programmed bus-organized systems.
to act as an input or output. This is accomplished by It is fabricated with N-channel silicon-gate technol
O ogy. For ease of use, the device operates from a single
setting a 1 in the corresponding Data Direction Regis
ter bit for those lines which are to be outputs. A 0 in a power DTL,
supply, has direct compatibility with TTL and
and needs no clocks or refreshing because of
bit of the Data Direction Register causes the corre static operation.
sponding peripheral Data Operation wherein, the data This memory is compatible with the MPU system,
on peripheral lines programmed to act as inputs ap s providing
pears directly on the corresponding MPU Data Bus expansion random storage in byte increments. Memory
is provided through multiple Chip Select
lines. In the input mode these lines represent a maxi inputs.
mum of one standard TTL load. FIG. 7 shows a functional block diagram of the 128
The data in Output Register A, reference numeral 9 word x 8-bit RAM and FIG. 3B shows the RAM pin
in FIG. 6, will appear on the data lines that are pro 20 designations. Referring to these figures, the operation
grammed to be outputs. A logical 1 written into the of the memory is as follows:.
register will cause a "high" on the corresponding data Chip selection is accomplished by applying a low state
line while a 0 results in a "low". Data in Peripheral to the four negative enable inputs CS1, CS2, CS4, CS5,
Interface Register A may be read by an MPU. "Read and a high state to the two positive enable inputs CS0
Peripheral Data A" operation when the corresponding 25 and CS3. The memory is inhibited by inverting the state
lines are programmed as outputs. This data will be read of any enable input from the above conditions (e.g.,
properly if the voltage on the peripheral data lines is and E = low state). The chip select circuitry interfaces
allowed to be greater than 2.0 volts for a logic 1 output directly with the three-state output buffers; therefore,
and less than 0.8 volt for a logic 0 output. Loading the 30 for inhibiting the memory forces the open circuit condition
output lines such that the voltage on these lines does the three-state buffers.
not reach full voltage causes the data transferred into plying Each of the 128 eight-bit words is addressed by ap
the MPU on a Read Operation to differ from that con imputs.the proper binary code to the seven address
tained in the respective bit of Output Register A.
The peripheral data lines in the B Section of the PIA 35 when Because the RAM has a bidirectional output bus,
can be programmed to act as either inputs or outputs in must bea placed write cycle is to be preformed, the R/W line
a similar manner to PA0-PA7. However, the output chip is selected.inIfthe write mode (low state) before the
buffers 11 driving these lines differ from those driving try to drive the I/O busis atnotthedone,
this
same
then the RAM will
time an external
lines PA0-PA7. They have three-state capability, allow device is driving this same bus.
ing them to enter a high impedance state when the 40 Therefore, writing is accomplished by applying a low
peripheral data line is used as an input. In addition, state of the R/W control line before the chip is selected.
data on the peripheral data lines PB0-PB7 will be read Under this condition, the data on the input/output lines
properly from those lines programmed as outputs even is stored in the location designated by the address in
if the voltages are below 2.0 volts for a "high'. As puts.
outputs, these lines are compatible with standard TTL 45 Reading is accomplished by applying a high state to
and may also be used as a source of up to 1 milliampere the read/write control line when the chip is enabled.
at 1.5 volts to directly drive the base of a transistor This causes the data stored in the location designated
switch. by the address inputs to be placed on the input/output
Peripheral Input lines CA1 and CB1 are input only lines.
lines that set the interrupt flags of the control registers. 50 Most MPU system applications require some amount
The active transition for these signals is also pro of permanent data storage to provide a program nu
grammed by the two control registers. cleus for start-up, re-initialization after power failure,
The peripheral control line CA2 can be programmed etc. and this data storage is usually provided with
to act as an interrupt input or as a peripheral control 55 ROM's. As with RAM's, the MPU system of this appli
output. As an output, this line is compatible with stan cation is adaptable to a variety of ROM types. This
dard TTL, as as input it represents one standard TTL discussion is directed to a 8192 bit mask-programma
load. The function of this signal line is programmed use in bus organizedmemory
ble, byte organized specifically designated for
systems. This memory is organized
with Control Register A.
Peripheral Control line CB2 may also be pro as 1024 words of 8-bits and is fabricated with N-chan
nel silicon-gate technology. For ease of use, the device
grammed to act as an interrupt input or peripheral 60 operates
control output. As an input, this line has greater than 1 patibility from a single power supply, has direct com
megohm input impedance and is compatible with stan refreshing because ofand with TTL DTL, and needs no clock or
static operation.
dard TTL. As an output it is compatible with standard The memory is compatible with the MPU system,
TTL and may also be used as a source of up to 1 milli 65 providing read only storage in byte increments. Mem
ampere at 1.5 volts to directly drive the base of the ory expansion is provided through multiple chip Select
transistor switch. This line is programmed by control inputs. The active level of the Chip Select inputs and
Register B. the memory content are defined by the customer.
 4,004,283 24
23
logical AND of VMA and 92). VMA is the Valid
ROM OPERATION Memory Address and 2 is the phase two clock signal for
FIG. 8 shows a functional block diagram of the ROM theThe MPU.
Read/Write line is a high impedance input that is
including pin designations. The electrical operation of
the ROM is straight-forward. Power is applied to the data flow throughandtheis used
5 TTL compatible to control the direction of
ACIA's input/output data bus
ROM via the ground pin (1) and the Vcc pin (12). The interface. When Read/Write is high (for an MPU Read
memory matrix (26) is an array of 8192 MOS devices cycle), an ACIA output driver is turned on and a se
each of which will or will not have a gate connection in lected register is read. When it is low, the ACIA output
accord with permanently stored data required. The driver is turned off and the MPU writes into a selected
application of a binary coded address to the 10 address O register. Thus, the Read/Write signal is used to select
input pins (15)-(24) at the input to the address de the registers within the ACIA that are Read Only or
coder (25) will produce a selection signal at its output.
This selection signal will cause an 8-bit word of stored Write Only.
The three high impedence TTL compatible input
data to pass out of the matrix and through the three s lines CSO, CS, CS2 are used to address an ACIA. A
state buffer circuit (27) to the 8 data output pins particular ACIA chip is selected when CS0 and CS1 ar
(2)-(9). The passage of stored data through the three high and CS2
state buffer will only occur if the chip select input pins then performedis low. Transfers of data to an ACIA are
(11)-(14) are the state required to produce an "en and Read/Write.under the control of the Enable signal
able" signal from the enable gate to the 3 state buffer. 20 The Register Select line is high impedance input that
When the ROM is "disabled", the 3 state buffer circuit is TTL compatible and is used to select the Transmith
holds the data output pins (2)-(9) in a high impedance
state so that they do not interact with the MPU system The Receive Data or Control/Status registers in the ACIA.
data bus. The ROM also allows for mask programming Read/Write signal line is used in conjunction with
of the "active" state of the 4 chip select inputs 25 Register Select to select the Read Only or Write Only
(11)-(14). This provides more addressing flexibility for register in each register pair.
Interrupt request IRQ is a TTL compatible, open
large system applications. drain active low output that is used to interrupt the
ACIA OPERATION MPU. The Interrupt Requestreamins low as long as the
The ACIA is a monolythic integrated circuit specifi cause of the interrupt is present and the appropriate
cally designed to provide data formatting and control 30 interrupt enable within the ACLA is set.
Separate high impedance TTL compatible inputs are
for serial asynchronous (start-stop) data communica provided for clocking of transmitted and received data.
tions for the MPU system.
Four distinct functions are performed by the ACIA, Clock frequencies of 1, 16 or 64 times the data rate
including MPU Interfacing which is performed by se may be selected.
lect, enable, read/write, interrupt and bus interface 35 ingThe Transmit Clock input CTX is used for the clock
logic for compatibility with the Microprocessing Unit. on the transmitted
of data. The transmitter initiates data
negative transition of the clock.
A second function is Asynchronous Data Transmis The Receive Clock input RTX is used for synchroni
sion, which includes paralled-to-serial conversion of zation of received data. (In the as 1 mode, the clock
data, insertion of start and stop bits, parity bit insertion, 40 and data must be synchronized externally.) The re
and serial transmission of data words having commonly ceiver strobes the data on the positive transition of the
used numbers of bits.
A third function is Asynchronous Data Reception, clock. The Received Data line RXD is a high impedance
which includes serial asynchronous reception of stan TTL compatible input through which data is received
dard length data words, start and stop bit deletion, in a serial NRZ (Non Return to Zero) format. Synchro
parity and error checking, and serial-to-parallel con nization with a clock for detection of data is accom
version of data. plished internally when clock rates of 16 or 64 times
A fourth function is Modem Control, which includes
limited modem control functions Clear-to-send, Re the bit rate are used. Data rates are in the range of 0 to
500 Kbps when external synchronization is utilized.
quest-to-Send, and Data Carrier Detect. SO The Transmit Data output line TXD transfers serial
The ACIA signal interconnections fall into the NRZ (no return to zero) data to a modem or other
catagories of interconnections for communications to
the MPU and interconnections for communication and peripheral at the same range of rates as the received
control of the associated peripheral device. FIG. 9A data. The ACIA includes several functions that permit
shows these interconnections which are defined and
55 limited control of a data modem. The functions in
operate as follows. cluded are Clear-to-Send, Request-to-Send and Data
The ACIA interfaces to the MPU with an 8-bit bidi
rectional data bus, three chip select lines, a register Carrier Detect.
The high impedance TTL compatible input clear-to
select line, a read/write line, an enable line, and an send (CTS) provides automatic control of the transmit
interrupt request line.
The bidirectional data lines (D0-D7) allow for data 60 ting end of a communications link via the modem's
transfer between the ACIA and the MPU. The data bus "clear-to-send' active low output.
output drivers are three-state devices that remain in the toThe Request-to-Send output RTS enables the MPU
control a modem via the data bus. The active state is
high-impedance (off) state except when the MPU per low.
forms an ACIA read operation.
The enable signal, E, is a high impedance TTL com 65 Thedetected high impedance TTL compatible input data car
patible input that enables the input/output data buffers rier receiving end
DCD provides automatic control of the
of a communications link by means of the
and clocks data to and from the ACIA. In normal oper modem "Data-Carrier-Detect" or "Received-Line-Sig
ation with the MPU, this signal will be VMA2 (the
 4,004,283
nal Detect' output. The DCD input inhibits and initial
izes the receiver section of the ACIA when high. A low
to high transition of the Data Carrier Detect initiates an
interrupt to the MPU to indicate the occurrence of a
loss of carrier.
The ACIA makes use of internal registers on the chip
for the status, control, receiving and transmitting of
data. FIG. 9B shows these registers in a functional
block diagram of the ACIA. The ACIA control Regis
ter 4N consists of eight bits of write only buffer that are
selected when RS and R/W are low. This register con
trols the function of the receiver, transmitter, interrupt
enables, and the Request-to-Send modem control out
put.
The Counter Divide Select bits (CRA and CR1)
determine the divide ratios utilized in both the trans
mitter and receiver sections of the ACIA. Additionally,
these bits are used to provide a Master Reset for the
ACIA which clears the Status Register 1N and initial
izes both the receiver and transmitter. Note that when
the system is initialized, these bits must be set High to
reset the ACIA. After reseting, the clock divide ratio
may be selected. These counter select bits provide for
the following clock divide ratios:
CR1 CRO Function
O
O
O
6
1 O 64
1 Master Reset
The Word Select bits CR2, CR3, and CR4 are used to
select word length, parity, and the number of stop bits.
The encoding format is as follows:
CR4 CR3 CR2 FUNCTON
7 Bits - Even Parity-2 Stop bits
7 Bits - Odd Parity-2 Stop Bits
7 Bits + Even Parity-- Stop Bit
7 Bits - Odd Parity-1 Stop Bit
8 Bits + 2 Stop Bits
8 Bits - 1 Stop Bit
8 Bits - Even Parity-- Stop Bit
8 Bits - Odd Parity+l Stop Bit
Parity selection changes (Odd to Even or Even to
Odd) immediately affect the receiver operating state
but are delayed until after the next transmitter transfer
signal before becoming effective for the transmitter.
Word length, Parity Select, and Stop Bit changes are
not double-buffered and therefore become effective
immediately.
Transmitter Control Bits (CR5 and CR6) - Two
Transmitter Control bits provide for the control of the
Transmitter Buffer Empty interrupt output, the Re
quest-to-Send output and the transmission of a BREAK
level (space). The following encoding format is used:
CR6 CRS FUNCTION
O O RTS-low, Transmitting interrupt Disabled (TIE)
O RTS-low, Transmitting Interrupt Enabled (TE)
0 RTS-high, Transmitting interrupt Disabled (TE)
RTS-low, Transmitting interrupt Disabled (TE)
and Transmits a BREAK level on the
Transmit Data Output.
26
Receiver Interrupt Enable Bit (CR7) - Interrupts will
be enabled by a high level in bit position 7 of the Con
trol Register (CR7). Interrupts will be caused by the
Receiver Data Register Full going high or by a low to
high transistion on the Data Carrier Detect signal line.
The interrupt will be cleared by selecting the Receiver
Data Register or disabled by resetting the Receiver
Interrupt Enable Bit.
Data is written in the Transmit Data Register 2N
O during the peripheral enable time (EO) when the ACIA
has been addressed and RS.R/W is selected. Writing
data into the register causes the Transmit Data Register
Empty bit in the status register to go low. Data can then
be transmitted. If the transmitter is idling and no char
acter is being transmitted, then the transfer will take
place within one bit time of the trailing edge of the
Write command. If a character is being transmitted, the
new data character will commence as soon as the previ
ous character is complete. The transfer of data causes
the Transmit Data Register Empty (TDRE) bits to
indicate empty.
Data is automatically transferred to the empty Re
ceive Data Register (RDR), reference numberal SN,
from the receiver deserializer (a shift register) upon
25
receiving a complete character. This event causes the
Receiver Data Register Full bit (RDRF) (in the status
buffer) to go high (full). Data may then be read
through the bus by addressing the ACIA and selecting
30 the Receiver Data Register with RS and R/W high
when the ACIA is enabled. The non-destructive read
cycle causes the RDRF bit to be cleared to empty al
though the data is retained in the RDR. The status is
maintained by RDRF as to whether or not the data is
35 current. When the Receiver Data Register is full, the
automatic transfer of data from the Receiver Shift Reg
ister to the Data Register is inhibited and the RDR
contents remain valid with its current status stored in
the Status Register.
The MPU system and its functional building blocks
40
have now been discussed. A broad range of functioning
digital control sytems which capitalize on the MPU
systems special capabilities may be implemented there
with. In describing complete systems of this type, it is
45 useful to recite a specific example of a system configu
ration which summarizes and integrates the informa
tion thus far presented.
To demonstrate the versatility of the functional
building block concept, a typical system configuration
SO will be discussed. This configuration will demonstrate
how easily a basic system may be upgraded and ex
panded for an unlimited number of different applica
tions.
The Microprocessor Unit (MPU) may be configured
55 with a Read Only Memory (ROM), Random Access
Memory (RAM), a Peripheral interface Adapter
(PIA), restart circuitry and clock circuitry to form a
minimum functional system, as shown in FIG. 11).
Such a system can easily be adapted for a number of
60 small scale applications by simply changing the con
tents of the ROM.
The MPU requires a two-phase non-overlapping
clock which as a frequency range as high as 1 MHz. In
addition to the two phase, this circuit should alsogen
65 erate an enable Signal E, and its complement E, to
enable ROMs, RAMs, PIAs and ACIAs. This Enable
signal and its complement is obtained by ANDing 92 and
VMA (Valid Memory Address).
 4,004,283 28
27
The minimum system configuration permits direct tween the RAMs and ROMs and are not contiguous
selection of the ROM, RAM, ACIA and PA without because of the 1 of 4 line method of selection. This
the use of special TTL selection logic. This is accom method of selection could be expanded to eleven lines
plished by simply wiring the address lines A13 and A14 since A6 through A12 are not used.
to the Enable or chip select lines on the memories and Two-Phase Clock Circuitry and Restart circuitry for
PIA. This permits the devices to be addressed as foll this expanded system are the same as for the basic
lows: system.
Logic has been added to the basic system to handle
Go/Halt and single instruction execution or stepping.
DEWICE At 4 A3 HEX ADDRESSES O Single instruction execution is accomplished by allow
RAM O O 0000-007f ing the Go-Halt line to go high during one clock time
PA O 2004-2007 (Registers) when a momentary contact console switch is pressed.
ROM 6000-63FF The Interrupt lines for the three PAs are wired to
gether to form a common Interrupt Request (IRO) for
the MPU. A software interrupt polling scheme is used
Other addressing schemes can be utilized which use 5 to determine which PIA caused the interrupt.
any combination of two of the lines A10 through A14 Typical system timing sequences are shown in FIGS.
for chip selection. 13A - 13D.
All control and timing for the peripherals that are While the invention has been described with refer
connected to the PA is accomplished by software rou 20 ence to presently preferred embodiments thereof,
times under the control of the MPU. those skilled in the art will recognize that variations in
Since this basic system does not have a nonvolatile arrangement and placement of parts may be made to
RAM, special circuitry to handle loss of power using suit varying requirements within the scope of the inven
NMI is not required. Circuitry is, however, required to to.
insure proper initialization of the MPU when power is 25 TABLE 1.
turned on. This circuit should insure that the Restart
signal is held low for eight 91 clock cycles after the Vod INTERNAL ADDRESSING
power supply reaches a voltage of approximately 4.75 R
Control
volts DC. Also in order to insure that a PIA or ACIA is RS1 RSO AC-2 BC -2 Location Selected
not inadvertantly selected during the power-on se 30 O Peripheral Interface A
quence, Three-State Control (TSC) should be held O fo Control Register A
high until the positive transition of Restart, O Control Register A
Peripheral Interface B
The Go/Halt line is tied to Vcc and will automatically /O Control Register B
place the MPU in the GO state when power is turned Control Register B
on. This signal may be used to halt the MPU if a switch 35
is used to tie the line to ground for HALT and to Vcc
for RUN. TABLE 2
The minimum system may be easily expanded with
out the addition of TTL integrated circuits. One possi 7
CONTROL WORD FORMAT
6 s 4 3 2 O
ble expanded configuration which has 512 bytes of 40 AC ROA RCA2 CA2 Control DDRA CA1 Control
RAM, 4096 bytes of ROM and three PIAs is shown in Access
FIG. 12. Table 8 provides information on the device
select addresses that are used by this expanded system. 7 6 5 4 3 2 O
This method places the RAMs at the low order ad BC ROB ROB2. CB2. Contro DDRB
Access
CB Control
dresses and the ROMs at the higher order addresses. 45
Addresses for the PAs (or ACAs) are located be
TABLE 3
CONTROL OF INTERRUPT INPUTs CA AND CB
MPU interrupt
AC- AC-0 Interrupt Input Interrupt Flag Request
(BC-1) (BC-0) CA1 (CB) AC-7 (BC-7) RQA (ROB)

O O Active Set high on

CA1 (CB) Vof Masked-RQ remains
high
Goes low when the
0. Active Set high on Wof
CA1 (CBI)
interrupt flag bit
AC-7 (BC-7) goes
high

O h Active Set high on of Masked-IRQ remains

CA (CB) high
Goes low when the
interrupt flag bit
Active Set high on of AC-7 (BC-7) goes
CA 1 (CBE) high
Notes: 1. Indicates positive transition (low to high)
 4,004,283
29 30
TABLE 3-continued
CONTROL OF INTERRUPT INPUTs CA AND CE
MPU interrupt
AC- AC-0 Interrupt input Interrupt Flag Request
(BC- ) (BC-0) CA (CB1) AC-7 (BC-7) ROA (IRQB)
2. lindicates negative transition (high to low)
3. The Interrupt flag bit AC-7 is cleared by an MPU Read of the A
Data Register and BC-7 is cleared by an MPU Read of the B Data Register
4. If AC-0 (BC-0) is low when an interrupt occurs (interrupt masked)
and is later brought high, IRQA (IRQB) occurs on the positive transition
of CAC-0 (CBC-0).

TABLE 4
CONTROL OF CA2 AND C32AS INTERRUPT INPUTS
AC-5 (BC-5) is low
MPU Interrupt
AC-5 AC-4 AC-3 Interrupt input Interrupt Flag Request
(BC-5) (BC-4) (BC-3) CA2 (CB2) AC-6 (CRB-6) IROA (IROB)

O O O e Set high on Masked-RO remains

CA2 (CB2) high
Goes low when
the interrupt
e Set high on
CA2 (CB2)
f flag bit AC-6
(BC-6) goes high

O 1 O Active Set high on ?h f Masked-IRO re

CA2 (CB2) mains high
Goes low when
the interrupt
Active Set high on of flag bit AC-6
CA2 (CB2) (BC-6) goes
high

Notes: 1. ?m indicates positive transition (low to high)

2. M indicates negative transition (high to low)

3. The interrupt flag bit AC-6 is cleared by an MPU Read of the A Data Register
and BC-6 is cleared by an MPU Read of the B Data Register
4. If AC-3 (BC-3) is low when an interrupt occurs (interrupt masked) and is
later brought high, IRQA (RQB) occurs on the positive transition of AC-3
(BC-3).

TABLE 5
CONTROL OF CB2AS AS OUTPUT
-Chih
-C2
BC-5 BC-4 BC-3 Cleared Set
O 0 Low on the positive transition of High when the interrupt
the first E pulse following an BC-7 is set by an active
MPU Write "B" Data Register transition of the CB1
operation. signal
O 1 Low on the positive transistion of High on the positive
the first E pulse following an transition of the next
MPU Write "B" Data Register "E" pulse
operation.
O Low when BC-3 goes low as a Always low as long as BC-3
result of an MPU Write in Control is low. Will go high on an
Register "B". MPU Write in Control Regis
ter "B" that changes
to "one'
1 Always high as long as BC-3 in High when BC-3 goes high
high. Will be cleared when an as a result of an MPU
MPU Write Control Register "B" Write into control regis
results in clearing BC-3 to ter 'B'
"zero.'
 4,004,283 32
31
TABLE 6
CONTROL OF CA2AS AN OUTPUT
\C-S is his
AC-5 AC-4 AC-3
-CA
Cleared Set
0 O low on negative transition of High on an active trans
E after an MPU Read "A" Data ition of the CA1 signal.
operation.
O Low immediately after an MPU high on the negative edge
Read "A" Data operation. of the next "E" pulse.
O Low when AC-3 goes low as a Always low as long as
result of an MPU Write in AC-3 is low.
Control Register "A".
Always high as long as AC-3 High when AC-3 goes high
is high. as a result of a Write in
Control Register "A".

TABLE 7
MCROPROCESSORNSTRUCTIONS SET
- ALPHARETC SEQUENCE -
ABA Add. Accumulators CMP Compare ROL Rotate Left
ADC Add with Carry COMP Complement ROR Rotate Right
ADD. Add CPX Compare Index Register RT Return from Interrupt
AND Logical And RTS Return from Subroutine
ASL Arithmetic Shift Right DAA Decimal Adjust
DEC Decrernent SBA Subtract. Accumulators
BCC Branch if Carry Clear DES Decrement Stack Pointer SBC Subtract with Carry
BCS Branch if Carry Set DEX Decrement Index Register SEC Set Carry
BEO Branch if Equal to Zero SE Set interrupt Mask
BGE Branch if Greater or EOR Exchusive OR SEW Set Overflow
Equal Zero STA Store Accumulator
BGT Branch if Greater than NC increment STs Store Stack Register
Zero NS increment Stack Pointer STX Store Index Register
BH Branch if Higher NX increment Index Register SUB Subtract
BT BitText SW Software linterrupt
BLE Branch if Less or Equal JMP Jump
BLS Branch if Lower or Same SR Jump to Subroutine TAB Transfer Accumulators
BLT Branch if Less than Zero TAP Transfer Accumulators to
BM Branch if Minus LDA Load Accumulator Condition Code Reg.
BNE Branch if Not Equal to Zero LDS Load Stack Pointer TBA Transfer Accumulator
BPL Branch if Plus LDX Load Index Register TPA Transfer Condition Code
BRA Branch Always LSR Logical Shift Right Reg. to Accumulator
BSR Branch to Subroutine TST Test
BWC Branch if Overflow Clear NEG Negate TSX Transfer Stack Pointer
NOP No Operation to index Register
CBA Compare Accumulators Txs Transfer index Register
CLC Clear Carry ORA inclusive OR Accumulator to Stack Pointer
CLR Clear
CLV Clear Overflow PSH Push Data WAl Wait for Interrupt
PUL Pull Data

TABLE 8
DEW
ADDRESSING
DEVICE 15 4. 3 2 11 O 9 8 7 6 5 4 3 2 1 0.
RAM d O O d d d 0 0 X X X X X X X
RAM 2 d O O d d d 0 1 X X X X X X X
RAM 3 d O O d d d d 1 0 X X X X X X X
RAM 4 d O O d d d d 1 X X X X X X X
ROM d d d O O X X X X X X X X X X
ROM 2 d d d O l X X X X X X X X X X
ROM 3 d d d O X X X X X X X X X X
ROM 4 d d d 1 X X X X X X X X X X
PA d O d d d d d d d d 0 0 1 X X
PA 2 d O d d d d d 0 O X X
PA 3 d O d d d d d d 0 0 X. X
d don't care
0 is logical ero
x wariable addrea
1 Logical one

TABLE 9
NSTRUCTION ADDRESSING MODES AND ASSOCATED
(Dual Operand) ACCX immediate Direct Extended indexed implied Relative
ABA 2
ADC X 2 3 4. 5
ADD 2 3 4. 5
AND K 2 3. 4. s
ASL 2 6 7
 4,004,283 34
33
TABLE 9-continued
INSTRUCTION ADDRESSENG. MODES AND ASSOCATED
(Dual Operand) ACCX immediate Direct Extended Indexed Implied Relative
ASR 2 6 7
BCC 4
BCS 4. 4.
BEA o o 4.
BOE o 4.
4
BH 4
BT x 2 3 4 5 a
BLE o 4.
BLS 4.
BLT 4.
BM 4
BNE P 4.
BP 4.
BRA 4.
BSR 8
4.
RWS 4.
CBA 2
CLC 2
CL 2
CLR 2
CLV 2
CMP x 2 3
COM 2
CPx 3. 4
DAA 2
DEC 2
DES 4
DEX 4
EOR . 2 3. 5 -
NC 2 " . 7
NS 4.

l
NX 4
JMP 4 o
8
LDA s s
LDS
LDX
LSR 2
: 6
6
7
7
-

NEC 2
NOP 4.
ORA x 2 3 s
PSH s 4.
PUL 4.
ROL
ROR
RT
RTS
SBA
2
2 o

w
: 7
7
10
5
2
SBC X 2 3 4. s •
SEB o 2
SE 2
SEW 2
STA X 6
STS 7
STX 7
SUB x 2 5
SW y 12
TAB 2
TAP 2
TBA 2
TPA 2
TST 2 6 7
TSX 4
TSX 4.
WA 9

55 peripheral units, respectively, an interrupt system com

What is claimed is:
1. In a digital system including a memory for storing
instructions, a microprocessor for executing said stored
instructions, a bidirectional data bus connected to said
microprocessor, first and second peripheral units, a 60 a non-maskable interrupt conductor connected to
bidirectional peripheral data bus connected to said first
and second peripheral units, and first and second inter
face adaptors connected between said bidirectional
data bus and said bidirectional peripheral data bus for
controlling transfer of data flow between said bidirec
tional data bus and said first and second peripheral
units and generating interrupt request signals in re
sponse to interrupt requests from said first and second
prising:
an interrupt conductor for conducting said interrupt
request signals connected to said microprocessor
and said first and second interface adaptors;
said microprocessor;
interrupt signal generating means coupled to said
non-maskable interrupt conductor for generating a
priority interrupt signal on said non-maskable in
65 terrupt conductor;
interrupt logic means in said microprocessor coupled
to said non-maskable interrupt conductor for caus
ing said microprocessor to address a fixed location
 4,004,283 36
35
in said memory in response to a priority interrupt processor to address a fixed location in said mem
signal produced on said non-maskable interrupt ory in response to one of said interrupt signals on
conductor by one of said first and second interface said interrupt conductor, said fixed location con
adaptors, said fixed location containing an address taining an address of an interrupt routine; and
of an interrupt routine; and 5 interrupt mask means in said microprocessor con
interrupt mask means in said microprocessor con nected between said interrupt conductor and said
nected between said interrupt conductor and said interrupt logic means and coupled to said bidirec
interrupt logic means and coupled to said bidirec tional data bus for storing digital information from
tional data bus for storing digital information from O said rupt
bidirectional data bus and enabling said inter
logic means to cause said addressing of said
said bidirectional data bus and enabling said inter fixed location conditionally upon said digital infor
rupt logic means to cause said addressing of said mation in response to said one of said interrupt
fixed location conditionally upon said digital infor signals.
mation in response to one of said interrupt request 4. In a digital system including a memory, a micro
signals.
2. In a digital system including a memory for storing memory, aforbidirectional
15 processor executing instructions stored in said
instructions, a microprocessor for executing said stored microprocessor, first anddata bus connected to said
second peripheral units, a
instructions, a bidirectional data bus connected to said
microprocessor, said microprocessor including an in bidirectional peripheral data bus connected to said first
and second peripheral units, and first and second inter
struction register coupled to said bidirectional data bus face adaptors connected between said bidirectional
for storing instructions, first and second peripheral 20 data bus and said bidirectional peripheral data bus for
units, a bidirectional data bus connected to said first controlling transfer of data flow between said bidirec
and second peripheral units, and first and second inter tional data bus and said first and second peripheral
face adaptors connected between said bidirectional units and generating interrupt request signals in re
data bus and said bidirectional peripheral data bus for sponse to interrupt requests from said first and second
controlling transfer of data flow between said bidirec 25 peripheral units, respectively, an interrupt system com
tional data bus and said first and second peripheral prising:
units and generating interrupt request signals in re an interrupt conductor for conducting said interrupt
sponse to interrupt requests from said first and second request signal connected to said microprocessor
peripheral units, respectively, an interrupt system com 30 and said first and second interface adaptors; and
prising: interrupt logic means in said microprocessor coupled
an interrupt conductor for conducting said interrupt to said interrupt conductor for causing said micro
request signals connected to said microprocessor processor to address a fixed location in said men
and said first and second interface adaptors; ory in response to one of said interrupt request
interrupt logic means in said microprocessor coupled 35 signals on said interrupt conductor;
to said interrupt conductor and said instruction interrupt mask means in said microprocessor con
register for causing said microprocessor to address nected between said interrupt conductor and said
a fixed location in said memory and inhibiting load interrupt logic means and coupled to said bidirec
ing of a subsequent instruction into said instruction tional data bus for storing digital information from
register in response to one of said interrupt request said bidirectional data bus and enabling said inter
signals produced on said interrupt conductor, and 40 rupt logic means to cause said addressing of said
interrupt mask means in said microprocessor con fixed location by said microprocessor conditionally
nected between said interrupt conductor and said upon said digital information in response to said
interrupt logic means and coupled to said bidirec interrupt signal.
tional data bus for storing digital information from 45 5. A method of operating a digital system including a
said bidirectional data bus and enabling said inter memory, a microprocessor for executing instructions
rupt logic means to cause said addressing of said stored in said memory, a bidirectional data bus con
fixed location conditionally upon said digital infor nected to said microprocessor, a plurality of peripheral
mation in response to said one of said interrupt units coupled to said bidirectional data bus, and an
request signals. interrupt conductor coupled to said microprocessor
3. In a digital system including a memory for storing 50 and said plurality of peripheral units, said method com
instructions, a microprocessor for executing said stored prising the steps of:
instructions, a bidirectional data bus connected to said generating an interrupt request by one of said periph
microprocessor, first and second peripheral units cou eral units;
pled to said bidirectional data bus, an interrupt system 55 producing an interrupt request signal on said inter
rupt conductor representative of said interrupt
comprising: request in response to said interrupt request; and
an interrupt conductor for conducting interrupt sig
nals initiated by said first and second peripheral addressing a fixed location in said memory by said
units connected to said microprocessor and to said microprocessor in response to said interrupt re
first and second interface adaptors; 60
quest signal, wherein said fixed location contains
interrupt logic means in said microprocessor coupled an address of anst interrupt
sk k
routine.
k k
to said interrupt conductor for causing said micro

65