KATHMANDU UNIVERSITY

SCHOOL OF ENGINEERING
DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

ASSIGNMENT 5

SUBMITTED BY SUBMITTED TO
NAME: SAURAV BISTA DR. SAMUNDRA GURUNG
ROLL: 31005
GROUP: EE(COMMUNICATION)
LEVEL: III YEAR I SEMESTER
1. Explain the operation of either ramp-type ADC or dual-ramp-type ADC.
Ans:
Digital type Ramp ADC
The digital ramp ADC is also called counter-type ADC since it uses the binary
counter for conversion. Apart from the binary counter, it consists of a comparator,

Figure 1: Digital Ramp ADC

a Digital Analog Converter (DAC), the control circuit, a AND gate, and latches.

Here the output of the counter is given to the DAC. As the counter increments its
count, the output of the DAC increases in a ramp fashion. This is why the ADC is
called the ramp ADC.

Working
In the above figure, the input voltage is given to the non-inverting terminal of the
comparator while the output of the DAC is given to the inverting terminal of the
comparator. Then through the AND gate, the output of the comparator is applied to
the counter. Further, the output from the counter is passed to the DAC.

So, here initially when the conversions begin, the counter is RESET and the output
of the DAC is 0. Therefore, the input voltage is greater than the output of the DAC
at first and the comparator gives high output. In the figure above, the clock pulses
are applied to the counter using the AND gate. When the output of the comparator
is high, these clock pulses will be applied to the counter and the counter will then
start counting. As the counter increases its count, the output of the DAC will also
increase in a staircase fashion.

The output of the DAC is continuously compared with the input voltage. So as long
as the Vdac is less than the input voltage, the output of the comparator will be high,
and the clock pulses will be applied to the counter. Hence, the output of the DAC
will increase gradually in the staircases fashion. At the instant when Vdac is greater
than the input voltage, the output of the comparator will be low and no clock pulse
will be applied to the counter. As soon as the comparator will become low, through
the control circuit, the output of the comparator will get latched and the counter will
get RESET.

This latched output is directly proportional to the input voltage. After this procedure
the new conversion starts i.e., the new input value will get sampled, and once again
the conversion starts. The conversion time depends on the magnitude of the input
voltage.

Advantages:
The counter-type ADC is simple and easy to use. It is very accurate and the precision
can be increased by increasing the number of bits. While there are many complicated
ADCs on the market, a counter-type ADC has a fair balance of accurate output and
cheap hardware costs.

Disadvantages:
The disadvantage of this counter is that every time a new conversion starts, then the
counter will get RESET i.e., it always starts from 0 onwards.
2. Simulate the circuit for a flash ADC and briefly explain its working.
Ans:
Flash analog to digital converter is the fastest type of ADC among all the ADCs. It
is also known as a parallel analog-to-digital converter. It comprises high-speed
comparators and resistive voltage divider circuits with a parallel encoder.

The following are the simulations performed on Proteus.

Figure 2: Simulation of Flash ADC

A flash-type ADC produces an equivalent digital output for the corresponding
analog input.

Working:
In the above circuit, we have comparators, resistors, not gates, and a priority
encoder. Since we have designed a 3-bit flash ADC, the total number of
comparators required is 2𝑛𝑛 − 1 = 23 − 1 = 7(n=3 for 3 bit ADC). The 8X3
priority encoder available on the proteus comes with NOT gate at its pins so,
we have used NOT gates outside to nullify its effect.

The following table illustrates the working scenario of the system.

Input Comparator O/P Encoder O/p
Vin C1 C2 C3 C4 C5 C6 C7 D2 D1 D0
0-1V 1 1 1 1 1 1 1 0 0 0
1-2V 0 1 1 1 1 1 1 0 0 1
2-3V 0 0 1 1 1 1 1 0 1 0
3-4V 0 0 0 1 1 1 1 0 1 1
4-5V 0 0 0 0 1 1 1 1 0 0
5-6V 0 0 0 0 0 1 1 1 0 1
6-7V 0 0 0 0 0 0 1 1 1 0
>7V 0 0 0 0 0 0 0 1 1 1

The comparator compares the input voltage with the reference voltage(voltage drop
at each point). As long as the input voltage Vin is greater than the voltage drop
present at the respective input terminal. The output will be 0 when Vin is less than
the voltage drop. All the outputs from the comparators are connected as inputs of
the 8X3 priority encoder. This priority encoder produces a binary code(digital
output), which is corresponding to the high-priority input. Therefore, the output of
the priority encoder gives the binary equivalent(digital output) of external analog
input voltage. Here, we have the input voltage of 6.5V means the output should be
110 which can be verified from the above simulation.
3. Simulate the circuit for a DAC of your choice and briefly explain its working.
Ans:
Binary Weighted DAC
Binary-weighted DAC produces an analog output, which is almost equal to the
binary input by using binary-weighted resistors in the inverting adder circuit.

The following is the simulation snippet of the Binary Weighted DAC.

Figure 3: Binary Weighted DAC Simulation

Working:
This DAC transforms a particular binary code into an equivalent analog signal. If
the binary code given at the input is altered continuously, the output will change at
well. In the above circuit, there are resistors, two inverting op-amps, and logic states.
The logic states give 5V when the state is set high(1) and gives 0 volts when low(0).
The non-inverting terminal of the op-amp is connected to the ground. According to
the virtual ground concept, the voltage at the inverting terminal of the op-amp is the
same as that of the voltage present at its non-inverting terminal. So, the voltage at
the inverting terminal will be 0V. Similarly, the second non-inverting amplifier is
placed just to invert the output of the first op-amp.

The value of resistors is so arranged like 2KΩ, 4KΩ, 8KΩ, and 16KΩ so that Vout
will be obtained as:

Vout = -Vref(b1 𝟐𝟐−𝟏𝟏 + b2 𝟐𝟐−𝟐𝟐 + b3 𝟐𝟐−𝟑𝟑 + b4 𝟐𝟐−𝟒𝟒 )

Where b1, b2, b3, and b4 are the bits at the input.
Here Vref = 5V since the logic states give 5V when high.

On calculation for the different bits, we expect the following outputs.

Inputs Output Voltage
b1 b2 b3 b4 Vout
0 0 0 0 0V
0 0 0 1 0.3125V
0 0 1 0 0.625V
0 0 1 1 0.9375V
0 1 0 0 1.25V
0 1 0 1 1.5625V
0 1 1 0 1.875V
0 1 1 1 2.1875V
1 0 0 0 2.5V
1 0 0 1 2.8125V
1 0 1 0 3.125V
1 0 1 1 3.4375V
1 1 0 0 3.75V
1 1 0 1 4.0625V
1 1 1 0 4.375V
1 1 1 1 4.6875V

In the above circuit, we have used bits 1111 and obtained the output as 4.6875.

Similarly, checking for bit 1010, we should get an output voltage of 3.125V.

Hence, the output is verified.