energies

Article
Coordination Control Method Suitable for Practical
Engineering Applications for Distributed Power Flow
Controller (DPFC)
Mengmeng Xiao and Shaorong Wang *
School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan 430074,
China; xiaomengmeng@hust.edu.cn
* Correspondence: wsrwy96@vip.sina.com




Received: 27 October 2018; Accepted: 30 November 2018; Published: 4 December 2018


Abstract: To control multiple series units of distributed power flow controller (DPFC), a hierarchical
control method is proposed. This coordination control system consists of a coordination controller
and multiple series unit controllers. According to the demand of power flow ordered by a dispatch
center, the corresponding series-compensated voltage is calculated by a high-level controller and
transferred to each series unit controller. Comparing the targeted compensated voltage with actual
injected voltage, the modulation signal of the converter will be modified to change the power
flow accurately. The DPFC system model is built in Power Systems Computer Aided Design/
Electromagnetic Transients including DC (PSCAD/EMTDC). The simulation result indicates that the
proposed hierarchical control method is effective and can be considered as an option for practical
engineering applications in the future.

Keywords: AC transmission; distributed power flow controller; hierarchical coordination control;

series compensated voltage

1. Introduction
The mechanically controlled AC power transmission systems, including the use of high-power
electronics, advanced control centers, and communication links, were proposed in 1986 by N.G.
Hingorani from American Electric Power Research Institute (EPRI) [1–3]. For a simple flexible AC
transmission system (FACTS) parallel device or a simple FACTS series device, only the reactive power
can be exchanged if the energy storage unit is not disposed on the DC capacitor side within the FACTS
device. That is, its effect is equivalent to a tunable inductor or an adjustable capacitor. As a consequence,
it is limited and not flexible enough for regulating the power flow of the transmission line.
The conception of a unified power-flow controller (UPFC) was proposed in 1991 by Dr. L.
Gyugyi [4,5] and has been extensively studied to date [6–11]. The UPFC can be regarded as the
combination of shunt and series FACTS linked by a common DC. Generally, the shunt device is a static
synchronous compensator (STATCOM), while the series device is an example of a static synchronous
series compensator (SSSC). Bidirectional active power can flow between the parallel and series units
via the DC-bus capacitor to realize ‘four quadric’ power-flow regulation. Additionally, the active
power flow and reactive power flow of the transmission line can be controlled independently, which
matches its “universal” mind for control. However, the parallel and series units of UPFC are installed
centrally; as a consequence, many land resources are required for the installation. The series side
is integrated into one unit, which causes a large fold line change in the voltage distribution of the
transmission line. Besides this, the requirement for the insulation is high due to the direct electrical
connection of the parallel and series units. The aforementioned factors have led research workers to
rethink UPFC from the aspects of project cost, ease of operation and maintenance.

Energies 2018, 11, 3406; doi:10.3390/en11123406 www.mdpi.com/journal/energies

Energies 2018, 11, 3406 2 of 15

Prof. Deepak Divan proposes the concept of distributed FACTS (D-FACTS) [12–14]. As a member
of the DFACTS family, the distributed static series compensator (DSSC) has been studied widely [15–19].
Multiple DSSCs are sparsely hung onto the transmission line through a single-turn transformer (STT).
As a single-phase inverter with small capacity, the DSSC can be designed into a simple structured
device with low insulation cost and easy installation. The control principle of DSSC is similar to that of
SSSC, both of which control the power flow effectively by changing the line reactance flexibly.
The idea of a distributed power flow controller (DPFC) was proposed in 2007, as a new component
within the FACTS family by Zhihui Yuan from Delft University of Technology [20–22]. DPFC is derived
from UPFC. DPFC can be considered as a UPFC without a common DC link between the shunt and
series converters. A parallel unit of the DPFC is installed in a central area while the series units of
DPFC employ multiple distributed series units similar to DSSC. In UPFC, the active power support
of the series unit is transported by a common DC link. In DPFC, however, the DC power channel is
removed and replaced by the transmission power line. Due to the lower impedance characteristic of
the third harmonic compared with higher-frequency harmonics, the third harmonic active power is
chosen as an energy conversion medium. The parallel unit absorbs the base-frequency active power
from the bus line and converts it into third harmonic active power. The third harmonic active power
then is injected to the transmission line and flows along the line. The distributed series units control the
exchange between the 3rd harmonic active power and base-frequency active power. Simultaneously,
the responding voltages will be generated and injected into the transmission line. In our research, we
only care about the base frequency voltage for base frequency power flow control. Thus, later in this
paper, the series-compensated voltage indicates the base-frequency series-compensated voltage.
There are different research results about DPFC from different aspects of application. In [23–25],
DPFC was used to improve power quality problems during voltage sag and swell conditions. In [26],
taking the constraints of DPFC, an optimal scheduling model is established to realize wind power
spillage minimization. However, the generation of the reference base-frequency voltage is not clear.
In [27], by introducing an MMC (modular multilevel converter) at the shunt side of the DPFC, a new
topology of DPFC is proposed. References [28,29] proposed a specific power flow control method:
taking the terminal voltage of the transmission line as a reference, this technique requires high-speed
communication links to transfer the real-time waveform of the terminal voltage to multiple series unit
controllers. From the point view of engineering applications, this power flow control method is not
practical and needs to be improved.
To address the above issue, this paper proposes a hierarchical coordination control method for
DPFC series units. Taking advantage of the fact that the DPFC series unit is able to collect the real-time
phase of the transmission line current, the phase difference between the fundamental frequency line
current and the terminal voltage of the transmission line can be reflected by a sine wave generator
within the DPFC series unit. Therefore, the waveform of the real-time phase of the terminal voltage
can be reproduced correctly during a control period. In this way, a high-speed communication link
is not required. In addition, a wide area measurement system (WAMS) is introduced to transfer the
receiving-end voltage of the transmission line back to the upper-level controller.
The rest of paper is structured as follows. The basic principle of DPFC is presented in Section 2.
In Section 3, the coordination control system is discussed. The computation of the reference
series-compensated voltage is introduced in detail, and the lower-level series-unit control scheme is
depicted. In Section 4, simulation results in PSCAD/EMTDC are used to demonstrate the effectiveness
of the proposed coordination control method, and these are compared with the state-of-the-art methods
for DPFC power flow control. In Section 5, conclusions and future work are presented.

2. Basic Principle of the DPFC

A parallel FACTS device and many distributed series FACTS devices constitute a DPFC. The
structure of a DPFC is shown in Figure 1. In the following, the parallel FACTS device is called a parallel
 Energies 2018, 11, 3406 3 of 15
Energies 2018, 11, 3406 3 of 15
A parallel FACTS device and many distributed series FACTS devices constitute a DPFC. The
structure of a DPFC is shown in Figure 1. In the following, the parallel FACTS device is called a
unit parallel
while the series
unit whileFACTS devices
the series FACTSare calledare
devices series
calledunits.
seriesThe parallel
units. unit is
The parallel located
unit at the
is located sending
at the
end of the transmission line, and series units are distributed along the transmission line.
sending end of the transmission line, and series units are distributed along the transmission line.

Figure
Figure 1. 1.Structure
Structureof
ofaa distributed
distributed power
powerflow controller
flow (DPFC).
controller (DPFC).

As shown
As shown in Figure
in Figure 1, 1,T1T1and
andT2T2are
are delta-wye
delta-wye grounded
grounded transformers
transformers TheThe
deltadelta
side side
of theof the
transformer is blocked for the third harmonic current while the wye grounded side is allowed for
transformer is blocked for the third harmonic current while the wye grounded side is allowed for
flowing 3rd harmonic current; thus, the energy channel of third harmonic active power is formed,
flowing 3rd harmonic current; thus, the energy channel of third harmonic active power is formed,
which makes the active power exchange between the parallel unit and series units of the DPFC
whichpossible. the active power exchange between the parallel unit and series units of the DPFC possible.
makes
The The
parallel unit
parallel of of
unit the
theDPFC
DPFCisiscomposed
composed of oftwo
twoback-to-back
back-to-back voltage
voltage source
source converters
converters (VSCs).(VSCs).
VSC1VSC1
is a three-phase converter
is a three-phase converter which
which is is
responsible
responsibleforformaintaining
maintaining the bus
bus voltage
voltageand
andkeeping
keeping the
the DC capacitor
DC capacitor voltagevoltage
stable.stable.
VSC2 VSC2
is aissingle-phase
a single-phaseconverter,
converter, which
whichisisused
usedto generate a constant
to generate a constant
thirdthird harmonic
harmonic current.
current. Thus,Thus,the the parallel
parallel unitunit of the
of the DPFCDPFC plays
plays thethe role
role of of absorbing
absorbing the
the activepower
active
frompower
the bus,from thethen
and bus, and then converting
converting it to theitthird
to theharmonic
third harmonic active
active power.
power. TheThe third
third harmonicactive
harmonic
active power is injected into the transmission line and taken in by the DPFC series units as active
power is injected into the transmission line and taken in by the DPFC series units as active power
power support. After that, the base-frequency active power is generated by the power exchange
support. After that, the base-frequency active power is generated by the power exchange control in
control in the series units.
the series units.
• • • •
In Figure
In Figure V 1 Vand
1, 1, V 2 Vrepresent
1 and 2 represent thevoltage
the voltage at
at the
the sending-end
sending-endand receiving-end
and of theof the
receiving-end
• •
transmission line,
transmission line, respectively. I 3I 3is is
respectively. thetheequivalent
equivalent third
third harmonic current.P1, PQ11,, Q
harmonic current. P2 , Q
P21,, and and
2 Q2
indicate the the
indicate power flow
power at at
flow thethesending-end
sending-end and andreceiving-end
receiving-end of of
thethe transmission
transmission line, line, respectively.
respectively.
•• • •
EachEach
DPFC series
DPFC unit
series generates
unit a acompensated
generates voltage V
compensated voltage Vseisei(i(i==1,1,2, 2,
3, 3,
…,. n), n), and
. . ,and allVthe
all the V sei values
sei values
•
form a final compensated voltage V se• . Xline is the equivalent impedance of the transmission line.
form a final compensated voltage Vse . Xline•is the equivalent impedance of the transmission line.
By injecting the compensated voltage V•se , the active and reactive power of the transmission line
By injecting
can be controlled. theequivalent
The compensatedphasor Vse , the of
voltagediagram active
the and
DPFCreactive power ofin
is expressed theFigure
transmission
2. line
Energies
can 2018, 11, 3406 The equivalent phasor diagram of the DPFC is expressed in Figure 2.
be controlled. 4 of 15

Figure 2. The working principle of the DPFC.

• Figure 2. The working principle of the DPFC.
In Figure 2, V se represents the integrated compensated voltage, δ represents the phase angle
• •• • •
se δ V 1 , and (δ + ρ) indicates the
where V 1 surpasses VV2 , ρ stands for the phase angle where V se surpasses
In Figure 2, represents the integrated compensated voltage, represents the phase angle
• • • •
where V1 surpasses V2 , ρ stands for the phase angle where Vse surpasses V1 , and (δ + ρ)
• •
indicates the phase angle where Vse surpasses V 2 . X Σ=X T1+X line+X T2 denotes the total impedance
of the AC transmission power system, where X T1 and X T2 represent the impedance of the
Energies 2018, 11, 3406 4 of 15

• •
phase angle where V se surpasses V 2 . XΣ = XT1 + Xline + XT2 denotes the total impedance of the AC
transmission power system, where XT1 and XT2 represent the impedance of the transformer T1 and T2,
respectively. Thus, the natural power flow of the transmission line is expressed as

V1 V2 sin δ
P20 = (1)
XΣ

V1 V2 cos δ − V2 2
Q20 = (2)
XΣ
With DPFC series units, the power flow becomes

• ∗ V V2 sin δ + Vse × V2 sin(δ + ρ)

 
P2 = Re V2 I1 = 1 (3)
XΣ

• ∗ V1 V2 cos δ + Vse × V2 sin(δ + ρ) − V2 2

 
Q2 = Im V2 I1 = (4)
XΣ
• •
V 1 and V 2 can be regarded as constant during a certain period of time in the actual power system
operation, and so the increment of active and reactive power flow at the receiving-end can be written
as follows:
Vse × V2 sin(δ + ρ)
∆P2 = (5)
XΣ
Vse × V2 cos(δ + ρ)
∆Q2 = (6)
XΣ
Based on the above equations, it is obvious that the power flow of the transmission line can be
controlled efficiently by changing the magnitude value and phase angle of the series-compensated
voltage slightly and flexibly.

3. Coordination Control System of a DPFC

The proposed coordination control system of a DPFC consists of an upper-level controller, a
parallel unit controller and multiple series unit controllers. The schematic diagram of this control
system is depicted in Figure 3.
In Figure 3, Edcsh_ref is the reference value of the DC capacitor voltage in the parallel unit while
I3_ref indicates the referenced third harmonic frequency. The control method for the parallel unit can
be found in [20–22]; thus, the control scheme of the coordination control method for the series unit is
mainly discussed in this research work.
 Energies 2018, 11, 3406 5 of 15

be 2018,
Energies found11,in3406
[20–22]; thus, the control scheme of the coordination control method for the series unit is 5 of 15
mainly discussed in this research work.

• • •
•
I = I1+ I 3
I1

•
I3

V2
Pset γ •
tan -1
I1
Qset •

Pset / 3 V2
•
V1 nX Tse
•
V2 Z0 I set
•
I0 I set ∠γ
M se_ ref
θ se_ref

Figure The
3. 3.
Figure Thestructure
structure of
of the coordinationcontrol
the coordination control system
system of aof a DPFC.
DPFC.

3.1. The Computation of Reference Compensated Voltage

3.1. The Computation of Reference Compensated Voltage
According to the
According demand
to the demandofofpower flow P
power flow Pset and QQsetordered
set and orderedbyby
thethe dispatch
dispatch center,
center, and the
and the
• • • set
• • •
states of transmission line V 1 , V 2 and I 1 attained by WAMS, the corresponding series-compensated
states
• of transmission line V1 , V2 and I1 attained by WAMS, the corresponding series-
voltage V se_ref is calculated
• by an upper-level controller. The calculation process is as follows:
compensated voltage V se_ref is calculated by an upper-level controller. The calculation process is as
• follows:
Setting the number of DPFC series units to be n, the total base-frequency impedance between the
sending-end and receiving-end of the power transmission system is Z0 , the short circuit reactance
• Setting the number of DPFC series units to be n, the total base-frequency impedance between
of each XTsereceiving-end
series unit isand , and the initial current
powerphasor of transmission
system is line is short circuit
the sending-end of the transmission , the Z0
reactance of each series unit is X Tse , and the initial
• current
• phasor of transmission line is
• V1 − V2
I• 0 = • • (7)
VZ− V+ nXTse
1 0 2
I0 = (7)
Z 0 +nX Tse
•
• Corresponding to the target power flow, Iset and α represent the RMS value of I 1• and phase angle
• • •
Corresponding to the target power flow, I set and α represent the RMS value of I 1 and phase
that I 1 leads V 2 , respectively.
• •
angle that I1 leads V 2 , respectively. 
• • ∗

Pset = Re V2 Iset = V2 Iset cos α (8)

• • ∗
 
Qset = Im V2 Iset = V2 Iset sin α (9)
 Energies 2018, 11, 3406 6 of 15

 • • ∗
Energies 2018, 11, 3406 Pset = Re V 2 I set  = V 2 I set cos α (8)6 of 15
 

 • • ∗
• ∗ Q set = Im V 2 I set  = V 2 I set sin α • (9)
where Iset denotes the conjugate complex of the targeted current
line Iset .
Supposing
• ∗ that the voltage phasors at the sending-end and receiving-end
• of the transmission
where I denotes the conjugate complex of the targeted
system are unchanged during one control cycle, then we have
set current line I set .
Supposing that the voltage phasors at the sending-end and receiving-end of the transmission
system are unchanged during one control cycle, then P
we
sethave
Iset = (10)
V
P2 cos α
I set = set
(10)
2
V cos α
α = arctan ( Qset /Pset ) (11)
α = a rc tan ( Q se t / Pse t ) (11)
•
• The corresponding series-compensated voltage generated by each DPFC series unit is V se_ref =
• The corresponding series-compensated voltage generated
• by each DPFC series unit is
Mse_ref• ∠θse_ref , where Mse_ref is the RMS value of the V se_ref• and θse_ref is the phase angle that
• V se_ref =M se_ref ∠θ se_ref , where Mse_ref • is the RMS value of the V se_ref and θse_ref is the phase•angle
V se_ref surpasses
•
the voltage phasor V 2 . From•the view of the total system, the effect of V se_ref can
that V se_ref
be regarded as an equivalent
surpasses the voltage phasor V 2 . Z
series impedance set injected
From the viewby of each series
the total unit.the
system, Then, another
effect of
•
expression of the transmission line is
V se_ref can be regarded as an equivalent series impedance Zset injected by each series unit. Then,
another expression of the transmission line is • •
• V − V2
I set = • 1• (12)
• V1 0− +
Z V2 nZset
I set = (12)
Z 0 +nZ set
According to the obvious assumption and analysis, the series-compensated voltage is
According to the obvious assumption and analysis, the series-compensated voltage is
• • •
• • V 1• − V•
− Z• I
V se_ref =• •
Zset Iset = V 1 − V 22− Z0 I set0 set = Mse_ref ∠θse_ref (13) (13)
V se_ref = Zset Iset = n =Mse_ref ∠θse_ref
n
•
• •
•
• At
•
the initial stable state t = t , the phase angle that I surpasses V is ϕ, and all these
At the initial stable state t = 0t0, the phase angle that I 1 1surpasses V 2 is2 ϕ , and all these
measurements are saved in the upper-level controller.
measurements are saved in the upper-level controller.
• The
• RMS value
The RMS and
value andphase
phase angle
angle ofofthethe corresponding
corresponding series-compensated
series-compensated voltage voltage Mse_ref ,
M se_ref , θ se_ref
andthe
θse_refand thephase
phaseangle
angleϕ ϕ are
aretransferred
transferredto toeach
each series unit via a power line
series unit via a power line carrier carrier
communication link.
communication link.

3.2. The
3.2.Control Scheme
The Control of DPFC
Scheme Series
of DPFC Units
Series Units
The structure of the
The structure of DPFC series
the DPFC unit
series is isshown
unit shownin
inFigure 4.
Figure 4.

Figure
Figure 4. The
4. The structureof
structure ofthe
the DPFC
DPFC series
seriesunit.
unit.

The series unit of the DPFC consists of a single-turn transformer (STT), a single-phase inverter,
an associated controller, and a built-in communication model. The SST uses the transmission line
as the secondary winding, inserting compensated voltage into the power line. Each unit of DPFC is
controlled by power line carrier communication.
 The reference value of the compensated voltage M se_ref and θse_ref are transferred to the DPFC
series unit via power line carrier (PLC) communication link. In a phase reproducer, the real-time
phase of the reference voltage θ ref will be generated, leveraging the advantage that the real-time
phase of the transmission line base-frequency current can be captured by series units. The actual
Energies 11,the
2018,of
value 3406 θse are acquired and converted to a digital signal by the7 of 15
compensated voltages M se and
analog-to-digital converter (ADC) unit. By comparing the real-time reference values M se_ref and θ ref
withDPFC
The actualseries M sehas
valuesunit andtheθtask
se
, theofproportional-integral
maintaining the DC(PI) controller
capacitor within
voltage andthe power flowto the
responding
control
reference loopeffectively.
signal will generate a compensated
The control scheme phase
forand
theaDPFC
magnitude
seriescorrection factor tothe
unit including modify the
single-phase
modulation signal v
locked loop (SPLL), DC capacitor
mod 1
of the base-frequency compensated voltage.
voltage control and power flow control loop is depicted in Figure 5.

Edc
I3 θ pll 3
vmod 3
vmod
I1
θ pll vmod1

M se_ref M se_ref M se
θse_ref ϕ θ ref θse

Figure 5. The
Figure working
5. The principle
working ofof
principle the
theDPFC
DPFCseries
series unit controller.Single-phase
unit controller. Single-phase locked
locked looploop (SPLL):
(SPLL):
single-phase lockedlocked
single-phase loop. ADC:
loop. analog-to-digital converter.
ADC: analog-to-digital SPWM:SPWM:
converter. sinusoidal pulse-width
sinusoidal modulation
pulse-width
(PWM).modulation (PWM).

Based on the
The reference comparison
value of the actual value
of the compensated with the
voltage reference
Mse_ref and value
θse_refofare
thetransferred
DC capacitortovoltage
the DPFC
in the DPFC series unit, the DC-voltage control loop will generate the modulation
series unit via power line carrier (PLC) communication link. In a phase reproducer, the real-time signal v mod 3
to
maintain the DC capacitor voltage. Consequently, the output of the AC/DC
phase of the reference voltage θref will be generated, leveraging the advantage that the real-time converter equals the
phasemutual
of thecontrol v modbase-frequency
effects ofline
transmission 1
and v mod 3 . current can be captured by series units. The actual
value of the compensated voltages Mse and θse are acquired and converted to a digital signal by the
3.2.1. The Single-Phase Locked Loop (SPLL)
analog-to-digital converter (ADC) unit. By comparing the real-time reference values Mse_ref and θref
with actual The adopted
values Msephase
and θlocked
se , theloop method is based on(PI)
proportional-integral the controller
literature [30]. However,
within the literature
the power flow control
[30] directly integrates the angular frequency to obtain the phase-locked output,
loop will generate a compensated phase and a magnitude correction factor to modify the modulation which easily leads
to the saturation of the integral link. Therefore, the above method is improved in this paper, which
signal vmod1 of the base-frequency compensated voltage.
can effectively prevent the integral saturation phenomenon.
Based on the comparison of the actual value with the reference value of the DC capacitor voltage
The single-phase locked loop here is designed to track the frequency and phase of the base-
in the DPFC series unit,• the DC-voltage control loop • will generate the modulation signal vmod3 to
frequency
maintain the DCcurrent I 1 and
capacitor third harmonic
voltage. current Ithe
Consequently, 3 . The measured
output of thevalue
AC/DC of the converter
line currentequals
phase the
•
mutual control effects of vmod1 and vmod3 .
is obtained by current transformer (CT). As shown in Figure 6, the third harmonic current I3 and
3.2.1. The Single-Phase Locked Loop (SPLL)
The adopted phase locked loop method is based on the literature [30]. However, the literature [30]
directly integrates the angular frequency to obtain the phase-locked output, which easily leads to
the saturation of the integral link. Therefore, the above method is improved in this paper, which can
effectively prevent the integral saturation phenomenon.
The single-phase locked loop here is designed to track the frequency and phase of the
• •
base-frequency current I 1 and third harmonic current I 3 . The measured value of the line current
•
phase is obtained by current transformer (CT). As shown in Figure 6, the third harmonic current I 3
•
and base-frequency current I 1 are separated by the filter, and then their phases are locked by the
single-phase locked loop (SPLL) in the DPFC series unit. The outputs of SPLL for the base-frequency
current and SPLL for third harmonic current are expressed as follows:

θpll = ωt + θpll0 (14)

θpll3 = ω3 t + θpll30 (15)

 base-frequency current I 1 are separated by the filter, and then their phases are locked by the single-
phase locked loop (SPLL) in the DPFC series unit. The outputs of SPLL for the base-frequency current
and SPLL for third harmonic current are expressed as follows:

θpll =ωt +θpll0 (14)

Energies 2018, 11, 3406 8 of 15
θpll3 =ω3t +θpll30 (15)

Figure
Figure 6. 6.The
Thescheme
scheme of
of the
the DPFC
DPFCseries
seriesunit
unitcontroller.
controller.

3.2.2.3.2.2.
The The Reproduced
Reproduced Real-Time
Real-Time Phasefor
Phase forReference
Reference Series-Compensated
Series-Compensated Voltage
Voltage
The time
The time when
when thethe programofofthe
program thephase
phase locked
lockedlooploopofof
thethe
lineline
current is started
current is marked
is started as t as
is marked
= 0. Recording a certain zero-crossing point of the fundamental frequency
t = 0. Recording a certain zero-crossing point of the fundamental frequency current phasor current phasor of theof the
transmission line as t1, at this time, the phase of the line current is measured as ϕi , and then the phase
transmission line as t1 , at this time, the phase of the line current is measured as ϕi , and then the phase
• •
of V 2ofat V 2 atttime
time = t1 tis= t1 is
ϕ u = ϕi − ϕ (16)
ϕu =ϕi −ϕ (16)
•
The real-time phase of V 2 can
• be attained by
The real-time phase of V2 can be attained by
Z t
+ tt1 ωdt
β u β=u =ϕϕuu + ωdt (17) (17)
t1
•
Then, the real-time phase of the reference series-compensated voltage V se_ref
• can be denoted as
Then, the real-time phase of the reference series-compensated voltage V se_ref can be denoted as
θref =βu +θse_ref =ϕu +tt1 ωZdt+
t θse_ref (18)
θref = β u + θse_ref = ϕu + ωdt+θse_ref (18)
Considering that DPFC series units have the advantaget1 of capturing the real-time phase of the
transmission line current, the waveform of the real-time phase of the terminal voltage can be
Considering that aDPFC
reproduced during controlseries
period,units
whichhave thepractical
is very advantage of capturing
for engineering the real-time phase of
applications.
the transmission line current, the waveform of the real-time phase of the terminal voltage can be
reproduced during
3.2.3. The a control
DC Capacitor period,
Voltage which is very practical for engineering applications.
Control
The DC capacitor voltage control loop is shown in Figure 6. By comparing the actual DC
3.2.3. The DC Capacitor Voltage Control
capacitor voltage Edc with the reference DC capacitor voltage Edcsh_ref , the PI controller will generate
The DC capacitor
the magnitude voltage
value of the control loopsignal
modulation is shown
v mod 3in Figure 6. By comparing the actual DC capacitor
. To simulate the dynamic characteristics of the
voltage E dc
converter, a first-order inertial loop is introduced for DCEcapacitor
with the reference DC capacitor voltage dcsh_ref , the PI controller
voltage will generate
control. To avoid causing the
magnitude value of the modulation signal vmod3 . To simulate the dynamic characteristics of the
converter, a first-order inertial loop is introduced for DC capacitor voltage control. To avoid causing
extra voltage changes or power loss, the series unit is required to exchange only the active power of
the third harmonic with the transmission line. Hence, the modulation signal vmod3 should be the same
or inverse to the phase of the third harmonic current of the transmission line.
Thus, the DC-voltage control loop generates the modulation signal vmod3 for the third harmonic
frequency voltage. The third harmonic active power generated by the parallel unit can change
according to the demand for active power of the DC side to maintain the voltage of the DC capacitor
in series units.
 Energies 2018, 11, 3406 9 of 15

extra voltage changes or power loss, the series unit is required to exchange only the active power of
the third harmonic with the transmission line. Hence, the modulation signal v mod 3 should be the
same or inverse to the phase of the third harmonic current of the transmission line.
Energies 2018, 11, 3406 9 of 15
Thus, the DC-voltage control loop generates the modulation signal v mod 3 for the third harmonic
frequency voltage. The third harmonic active power generated by the parallel unit can change
3.2.4.according
The Powerto the demand
Flow for active power of the DC side to maintain the voltage of the DC capacitor
Control
in series units.
SPWM (sinusoidal PWM) control is adopted by the series unit. The relationship between the RMS
value3.2.4.
(root-mean-square) of the inverter output voltage and the DC capacitor voltage is
The Power Flow Control
SPWM (sinusoidal PWM) control is adopted √ by the series unit. The relationship between the
2
Vse = output
RMS value (root-mean-square) of the inverter ksevoltage
mse Edc and the DC capacitor voltage is (19)
2
where kse represents the ratio of STT, mse is V 2
the
se
= fundamental
kse mse E dc frequency voltage modulation (19) ratio, and
Edc is the DC capacitor voltage. 2
In fact,ksethe
where phase ofthe
represents the control
ratio of STT, mse is the
reference voltage signalfrequency
fundamental of the series unitmodulation
voltage port will ratio,
be shifted
afterand E dc is
passing through
the DC the inductor-capacitor
capacitor voltage. (LC) filter. In addition, due to the active power loss, the
amplitude In of the
fact, theseries
phase fundamental frequency
of the control reference voltage
voltage signalactually injected
of the series intowill
unit port thebetransmission
shifted after line
is smaller than the reference value. This will lead to deviations in the flow control. Therefore,
passing through the inductor-capacitor (LC) filter. In addition, due to the active power loss, the it is
amplitude
necessary of the the
to correct series fundamentalfrequency
fundamental frequencycompensation
voltage actuallyvoltage
injectedmodulation
into the transmission
signal byline is the
taking
smaller than
measurement the mean
of the reference value.
value This will
correction andleadthetophase
deviations in the flow control. Therefore, it is
compensation.
necessary
The targettoand correct the value
actual fundamental frequency compensation
of the compensated voltage are voltage
sent tomodulation signal by
the comparison taking after
module
the measurement of the mean value correction and the phase compensation.
being conversed and processed in the ADC unit. Then, the PI controller generates the compensated
The target and actual value of the compensated voltage are sent to the comparison module after
phase and magnitude correction factor to modify the modulation signal vmod1 . The modulating signal
being conversed and processed in the ADC unit. Then, the PI controller generates the compensated
for compensated base-frequency voltage is modified as follows: v
phase and magnitude correction factor to modify the modulation signal mod 1 . The modulating signal
for compensated base-frequency voltage is modified as follows:
vmod1 = k Me mse_ref sin(θref − e) (20)
vmod1 =kMemse_ref sin (θref − e) (20)
where k Me is the magnitude modified factor and e represents the correction for the phase. mse_ref
where kMe is the magnitude modified factor and e represents the correction for the phase. mse_ref
denotes the modulation ratio of the fundamental frequency voltage.
denotes
Accordingthe modulation ratioanalysis,
to the above of the fundamental
integrating frequency
the four voltage.
control modules together, the detailed
According to the above analysis, integrating the four control modules together, the detailed
scheme for the DPFC series unit can be depicted in Figure 6, where ω f f represents the rated angular
scheme for the DPFC series unit can be depicted in Figure 6, where ω ff represents the rated angular
frequency for fundamental-frequency components, and ω f f 3 represents the rated angular frequency
frequency for fundamental-frequency components, and ω ff3 represents the rated angular frequency
for third harmonic components. Fcn1, Fcn2, Fcn3, Fcn5and Fcn7 are PI controllers. Fcn4, Fcn6 and
for third harmonic components. Fcn1, Fcn2, Fcn3, Fcn5and Fcn7 are PI controllers. Fcn4, Fcn6 and
Fcn8 are first-order inertia blocks. G, G1 and G2 represent the gain of the first-order inertia blocks.
Fcn8 are first-order inertia blocks. G, G1 and G2 represent the gain of the first-order inertia blocks.
4. The Simulation and Analysis of the DPFC Coordination Control System
4. The Simulation and Analysis of the DPFC Coordination Control System
4.1. Simulation of the DPFC Control System
4.1. Simulation of the DPFC Control System
The The
model of the
model transmission
of the transmissionsystem
system including DPFCsis is
including DPFCs shown
shown in Figure
in Figure 7. It7.
is It is built
built by theby the
software tool PSCAD/EMTDC 4.2.1. The parallel unit is equivalent to the third harmonic
software tool PSCAD/EMTDC 4.2.1. The parallel unit is equivalent to the third harmonic current current
source and and
source the the
series units
series of of
units DPFC
DPFCare
arebuilt
built as
as detailed models.
detailed models.

Figure 7. The simulation model of the DPFC.

Figure 7. The simulation model of the DPFC.

4.1.1. Test Case 1

The device parameters of the DPFC are listed in Table 1.
Energies 2018, 11, 3406 10 of 15

Table 1. DPFC device parameters.

Items Parameter
System fundamental frequency 50 Hz
•
Magnitude of third harmonic current I 3 6A

Number of series units 10

• •
Magnitude of V 1 and V 2 380 V

Phase angle of voltage at sending-end δ 8.92◦

Phase angle of voltage at receiving-end 0◦
Transformer T1 380 V/380 V, 1 kVA, 0.1 p.u, ∆-YN
Transformer T2 380 V/380 V, 1 kVA, 0.1 p.u, YN-∆
Single-turn transformer of series unit 20 V/100 V, 0.5 kVA, 0.1 p.u
Reference value of DC capacitor voltage 20 V
Value of DC capacitor of VSC in series unit 2200 µF
LC filter of VSC in series unit 1.33 mH, 100 µF
Switch frequency of Insulated-gate bipolar transistor (IGBT) 2100 Hz
Zline Rline = 0.279 Ω, Lline = 0.0127 H
Initial phase angle ϕ 5.03◦
Starting time for the breaker of series unit 0.5 s
Starting time for the power flow control 2.5 s
t = 2.5–5.0 s Pset1 = 800 W, Qset1 = −100 Var
Targeted power flow
t = 5.0–10.0 s Pset2 = 1000 W, Qset2 = −100 Var

The corresponding parameters for the control loops of DPFC series unit are shown in Table 2.

Table 2. Tuning parameters for the control loops.

Fcn1 Fcn2 Fcn3 Fcn4

kp = 5 k p1 = 5 k p2 = 10 G = 0.1
k I = 5 × 10ˆ−5 s k I1 = 5 × 10ˆ−5 s k I2 = 0.2 s T = 0.02 s
Fcn5 Fcn6 Fcn7 Fcn8
k p3 = 10 G1 = 0.2 k p4 = 0.95 G2 = 1
k I3 = 0.005 s T1 = 0.02 s k I4 = 0.5 s T2 = 0.02 s

The simulation results of the DPFC coordination control system are depicted in Figure 8.
Figure 8a shows the power flow at the receiving-end of the transmission system by employing
the proposed control method. At time t = 3.5 s, Pr and Qr are stable at 799.83 W and −100.66 Var,
respectively. At time t = 6.0 s, Pr and Qr are at a new stable state at 999.978 W and −98.25 Var,
respectively. Considering the setting value given in Table 2, the power flow control is effective.
Figure 8a also shows the power flow at the receiving end of the transmission system by using
the state of art (SOA). At time t = 3.5 s, SOAPr and SOAQr are stable at 800.14 W and −98.11 Var,
respectively. At time t = 6.0 s, SOAPr and SOAQr are at a new stable state 1000.42 W and −99.998 Var,
respectively. Considering the setting value given in Table 2, the power flow control is effective.
Comparing the proposed method with the SOA according to the simulation results of the
independent active power flow control, it is indicated that both are effective and the control effects
are similar.
 k I = 5×10^-5 s k I 1 = 5×10^-5 s k I 2 = 0.2 s T = 0.02 s
Fcn5 Fcn6 Fcn7 Fcn8
k p 3 = 10 G1 = 0.2 k p 4 = 0.95 G2 = 1
k I 3 = 0.005 s T1 = 0.02 s k I 4 = 0.5 s T2 = 0.02 s
Energies 2018, 11, 3406 11 of 15
The simulation results of the DPFC coordination control system are depicted in Figure 8.

8
1200 6 Pse3
1000 Pse
800 Pr
4
(W,Var)

(W)
600 Qr
400 SO APr
SO AQ r 2
200
0
-200
0
t/s -2 t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Energies 2018, 11, 3406 11 of 15
(a) (b)

14
20 12 Et1
Edc Ese1
10
15 Edcref 8
(V)

(V)
10 6
4
5
2
0 t/s 0 t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
(c) (d)
170
120 PLL1 120 PLL3
70 PHIa1 PHIa3
(degree)
(degree)

20 20
-30
-80 -80
-130
-180 t/s -180 t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
(e) (f)

2 120 PHse
PHref
(degree)

20
(V)

Mse
1 Mseref
-80

t/s -180 t/s

0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
(g) (h)
Figure
Figure 8. The
8. The simulation
simulation resultsofofthe
results theDPFC
DPFC control
control system.
system.(a)(a)Three-phase power
Three-phase flow flow
power at theat the
receiving-end; (b) exchange of active power flow in the series unit; (c) DC capacitor
receiving-end; (b) exchange of active power flow in the series unit; (c) DC capacitor voltage voltage of each
of each
series unit; (d) magnitude of voltage of the single-turn transformer (STT); (e) SPLL result of the base-
series unit; (d) magnitude of voltage of the single-turn transformer (STT); (e) SPLL result of the
frequency line current by fast Fourier transform (FFT) component extraction; (f) SPLL result of the
base-frequency line current by fast Fourier transform (FFT) component extraction; (f) SPLL result of
third harmonic current by FFT component extraction; (g) the magnitude of compensated voltage for
the third harmonic current by FFT component extraction; (g) the magnitude of compensated voltage
each series unit; (h) the phase angle of compensated voltage for each series unit.
for each series unit; (h) the phase angle of compensated voltage for each series unit.
Figure 8a shows the power flow at the receiving-end of the transmission system by employing
Figure 8b displays
the proposed controlthe exchange
method. of the
At time t =third
3.5 s,harmonic
Pr and Qr active power
are stable flow PWse3and
at 799.83 and−100.66
base-frequency
Var,
power flowAtPse1
activerespectively. fort each
time = 6.0 series unit.QIt
s, Pr and is worth
r are at a newnoting that
stable Pse3at6=999.978
state Pse1 forWthe
andreason
−98.25that
Var,active
power loss of VSC
respectively. at the third
Considering the harmonic
setting value and base
given in frequency
Table 2, the are
power notflow
equal. Combining
control this power
is effective.
exchangeFigure
process8a also
withshows
the DC thecapacitor
power flow at the receiving
voltage in Figureend 8c,ofitthe transmission
is verified thatsystem by using
the third harmonic
the state of art (SOA). At time t = 3.5 s, SOAP and SOAQ are stable
frequency active power is used for building and maintaining the voltage of the DC capacitor.
r r at 800.14 W and −98.11 Var,
respectively. At time t = 6.0 s, SOAP r and SOAQr are at a new stable state 1000.42 W and −99.998 Var,
Figure 8c indicates the DC capacitor voltage Edc of VSC. Edc grows dramatically and then remains
stablerespectively. Considering the setting value given in Table 2, the power flow control is effective.
at the reference value 20 V, which verifies the validity of DC-voltage control.
Comparing the proposed method with the SOA according to the simulation results of the
Figure 8d represents the magnitudes of the base-frequency voltage at the primary side and
independent active power flow control, it is indicated that both are effective and the control effects
secondary side of STT. Et1 is the primary-side voltage while Ese1 is the secondary-side voltage. At t =
are similar.
3.5 s, Et1 = 3.6068bVdisplays
Figure and Ese1the = exchange
0.626 V. At t = third
of the 6.0 s,harmonic
Et1 = 8.643 V and
active powerEse1 = 1.607
flow V.base-frequency
Pse3 and The ratio of STT is
20:100 (secondary side to primary side); however, the ratio between the actual
active power flow Pse1 for each series unit. It is worth noting that Pse3 ≠ Pse1 for the reason that voltage Ese1active
and Et1 is
not strictly equal to 1:5. Therefore, a modification for the modulation
power loss of VSC at the third harmonic and base frequency are not equal. Combining signal v mod1 is needed.
this power
exchange process with the DC capacitor voltage in Figure 8c, it is verified that the third harmonic
frequency active power is used for building and maintaining the voltage of the DC capacitor.
Figure 8c indicates the DC capacitor voltage Edc of VSC. Edc grows dramatically and then
remains stable at the reference value 20 V, which verifies the validity of DC-voltage control.
Figure 8d represents the magnitudes of the base-frequency voltage at the primary side and
secondary side of STT. Et1 is the primary-side voltage while Ese1 is the secondary-side voltage. At t
 is 20:100 (secondary side to primary side); however, the ratio between the actual voltage Ese1 and Et1
is not strictly equal to 1:5. Therefore, a modification for the modulation signal v mod 1 is needed.
Figure 8e,f display the SPLL results of the line current by FFT (fast Fourier transform) component
extraction. Both the phases of base-frequency and the third harmonic line current can be locked
quickly and accurately.
Figure
Energies 2018, 11, 3406 8g,h indicate the magnitude and phase angle of the base-frequency series-compensated 12 of 15
voltage for each DPFC series unit. At t = 3.5 s, the actual values are M se = 0.626 V and θse = −42.365°
while the setting values are M se_ref = 0.627 V and θ se_ref = −42.502°. At t = 6.5 s, the actual values are
M se 8e,f
Figure display
= 1.607 θse SPLL
V and the results
= −54.068° ofthe
while thesetting
line current by M
values are FFT se_ref
(fast Fourier
= 1.607 θ se_ref = −53.665°.
V and transform) component
extraction. Both the phases of base-frequency and the third harmonic
Thus, the control of the base-frequency series-compensated voltage is effective. line current can be locked quickly
and accurately.
4.1.2. Test Case 2
Figure 8g,h indicate the magnitude and phase angle of the base-frequency series-compensated
The target
voltage for each DPFC power flows
series areAt
unit. changed
t = 3.5tos,Pset3
the = 800 W and
actual Qset3 =are
values −100M Var from
se = t = 2.5
0.626 V and = −42.365◦
to 7.0θssewhile
these are Pset4 = 800 W and Qset4 = −50 Var from t = 7.0 to 10.0 s. The ◦ simulation
while the setting values are Mse_ref = 0.627 V and θse_ref = −42.502 . At t = 6.5 s, the actual values results are shown in are
Figure 9.
Mse = 1.607 V and θse = −54.068 while the setting values are Mse_ref = 1.607 V and θse_ref = −53.665◦ .
◦
Figure 9a shows the power flow at the receiving end of the transmission system by employing
Thus, the
thecontrol
proposed of control
the base-frequency
method. At time series-compensated
t = 3.5 s, Pr and Qr are voltage
stable is at effective.
802.59 W and −101.81 Var,
respectively. At time t = 8.0 s, Pr and Qr are at a new stable state of 802.86 W and −50.43 Var,
4.1.2. Test Case 2 Considering the given setting value, the power flow control is effective.
respectively.
Figure 9a also indicates the power flow at the receiving-end of the transmission system by using
The target power flows are changed to Pset3 = 800 W and Qset3 = −100 Var from t = 2.5 to 7.0 s
the state of art (SOA). At time t = 3.5 s, SOAPr and SOAQr are stable at 800.14 W and −98.11 Var,
while these are Pset4
respectively.
= 800 W and Qset4r and
At time t = 8.0 s, SOAP
= −SOAQ
50 Varr are
from t = 7.0 to 10.0 s. The simulation results are
at a new stable state of 800.01 W and −49.997
shown in Figure 9.
Var, respectively. Considering the given setting value, the power flow control is effective.

1000 8
800 Pse3
6
600 Pr Pse
Qr 4
(W,Var)

400
(W)
SO APr
200 SO AQ r
2
0
-200 0
t/s -2 t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
(a) (b)
25 4

20
Edc Et1
15
Ese1
(V)
(V)

Edcref 2
10
5
0 t/s 0 t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
(c) (d)
170
120 PLL1 120 PLL3
70 PHIa1 PHIa3
(degree)

(degree)

20 20
-30
-80 -80
-130
-180 -180 t/s
t/s
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Energies 2018, 11, 3406 13 of 15
(e) (f)

0.8
0.6
Mse
(V)

0.4 Mseref

0.2

0 t/s
0 1 2 3 4 5 6 7 8 9 10
(g) (h)
Figure 9. The simulation results of the DPFC control system. (a) Three-phase power flow at the
Figure 9. The simulation results of the DPFC control system. (a) Three-phase power flow at the
receiving-end; (b) exchange of active power flow in the series unit; (c) DC capacitor voltage of each
receiving-end; (b) exchange of active power flow in the series unit; (c) DC capacitor voltage of each
series unit; (d) magnitude of voltage of STT; (e) SPLL result of base-frequency line current; (f) SPLL
series unit;
result(d)
of magnitude
third harmonicofcurrent;
voltage(g)ofthe
STT; (e) SPLL
magnitude of result of base-frequency
compensated voltage; (h) theline current;
phase angle of(f) SPLL
result ofcompensated
third harmonic
voltage.current; (g) the magnitude of compensated voltage; (h) the phase angle of
compensated voltage.
Therefore, it is verified that both the proposed method and SOA method are effective for the
independent reactive power flow control. Additionally, the effects of these two methods are similar.
Figure 9b displays the exchange of the third harmonic active power flow Pse3 with base-
frequency active power flow Pse1 for each series unit. It is worth to noting that the power exchange
process is consistent with the tendency of the DC capacitor voltage in Figure 9c; hence, it is indicated
that the third harmonic frequency active power is used for building and maintaining the voltage of
the DC capacitor.
Figure 9c indicates the DC capacitor voltage E of VSC. E can still stay stable at 20 V when
Energies 2018, 11, 3406 13 of 15

Figure 9a shows the power flow at the receiving end of the transmission system by employing
the proposed control method. At time t = 3.5 s, Pr and Qr are stable at 802.59 W and −101.81 Var,
respectively. At time t = 8.0 s, Pr and Qr are at a new stable state of 802.86 W and −50.43 Var,
respectively. Considering the given setting value, the power flow control is effective.
Figure 9a also indicates the power flow at the receiving-end of the transmission system by using
the state of art (SOA). At time t = 3.5 s, SOAPr and SOAQr are stable at 800.14 W and −98.11 Var,
respectively. At time t = 8.0 s, SOAPr and SOAQr are at a new stable state of 800.01 W and −49.997 Var,
respectively. Considering the given setting value, the power flow control is effective.
Therefore, it is verified that both the proposed method and SOA method are effective for the
independent reactive power flow control. Additionally, the effects of these two methods are similar.
Figure 9b displays the exchange of the third harmonic active power flow Pse3 with base-frequency
active power flow Pse1 for each series unit. It is worth to noting that the power exchange process
is consistent with the tendency of the DC capacitor voltage in Figure 9c; hence, it is indicated that
the third harmonic frequency active power is used for building and maintaining the voltage of the
DC capacitor.
Figure 9c indicates the DC capacitor voltage Edc of VSC. Edc can still stay stable at 20 V when the
target power flow changes, which verifies the validity of the DC capacitor voltage control.
Figure 9d represents the magnitudes of the base-frequency voltage at the primary side and
secondary side of STT. Et1 is the primary-side voltage while Ese1 is the secondary-side voltage. At t =
3.5 s, Et1 = 3.691 V and Ese1 = 0.641 V. At t = 8.0 s, Et1 = 3.545 V and Ese1 = 0.612 V. The ratio of STT is
20:100 (secondary side: primary side); however, the ratio between the actual voltage Ese1 and Et1 is not
strictly equal to 1:5. Therefore, a correction for the modulation signal vmod1 is necessary.
Figure 9e,f display the SPLL results of the line current extracted by FFT. It is verified that both the
phases of the base-frequency and third harmonic line current can be locked quickly with high precision.
Figure 9g,h indicate the magnitude and phase angle of the base-frequency series-compensated
voltage generated by each DPFC series unit. At t = 3.5 s, the actual values are Mse = 0.641 V and θse =
−42.271◦ while the setting values are Mse_ref = 0.642 V and θse_ref = −42.401◦ . At t = 8.0 s, the actual
values are Mse = 0.612 V and θse = −65.776◦ while the setting values are Mse_ref = 0.612 V and θse_ref =
−65.281◦ . The control of the base-frequency series-compensated voltage is verified to be effective.

4.2. Comparison of the Proposed Method with the State-of-the-Art

Comparing the proposed method with the SOA in [28] based on the simulation results of power
flow control in Figures 8a and 9a in Section 4.1, it is indicated that the control effect of the proposed
and existing method are similar in independent active and reactive power flow control.
It should be mentioned that the starting time of the simulation in PSCAD/EMTDC for the phasors
of terminal voltage and line current are the same; thus, both the initial phases of the terminal voltage
and line current are measurable. In the actual operation system, however, there is no way to acquire
the initial phase angle of the terminal voltage except for the phase difference between two phasors.
The SOA takes the real-time phase of the terminal voltage as the input angle of the inverse Park’s
transformation and generates corresponding reference values of the series-compensated voltage. Thus,
the real-time phase of the terminal voltage must be provided for power flow control in multiple series
units by high-speed communication link, which is not practical for the actual transmission system.
Using the proposed real-time phase reproducer of the terminal voltage, only the initial difference
between the terminal voltage and line current is needed by leveraging the real-time phase of line
current locally at the lower control scheme. Hence, the proposed method is much more suitable
for practical engineering applications due to the limitations of communication speed, which is not
considered in the existing method.
Energies 2018, 11, 3406 14 of 15

5. Conclusions
A coordination control method for DPFC series units has been proposed and verified in this paper.
The waveform of the real-time phase of the terminal voltage can be reproduced correctly during a
control period within the DPFC series units, and so a high-speed communication link is not required
for the real-time power flow control. Hence, it is much more practical for engineering applications. To
control the series-compensated voltage exactly, measures to modify the magnitude and angle of the
modulation signal through PI control loops have been taken. The control parameters of each series
unit are the same to avoid the interaction’s inverse impact on multiple series unit. Simulation results
from PSCAD/EMTDC have indicated that the proposed power flow control method is effective. By
comparing the proposed method with the SOA in simulation and considering the speed limitations
of the communication link in an actual transmission system, it can be concluded that the proposed
method is more suitable for practical engineering applications with an equivalent control effect to
the SOA. In future research work, experimental testing will be carried out to verify the proposed
method further.

Author Contributions: Supervision, S.W.; Investigation and Formal analysis, M.X.; Research ideas and innovative
schemes, S.W. and M.X.; Writing and Revising, M.X.; Project administration, S.W. and M.X.; Resources and
Funding acquisition, S.W.
Funding: The authors would like to thank for the sponsorship offered by State Grid Science & Technology Project
of China (52150016000Y).
Conflicts of Interest: The authors declare no conflict of interest.

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