1766
6, JUNE 2021
An Efficient BCH Decoder for WBAN Applications
Huang-Chang Lee
Abstract— In this work, a Bose-Chaudhuri-Hocquenghem
(BCH) code decoder based on the Meggitt algorithm is imple-
mented for wireless body area network (WBAN) applications.
Compared to other implementations based on the popular
Peterson algorithm, the proposed decoder has the extra capability
of checking the syndrome for the decoding result, and is able to
detect 20 times more failed decoding results without introducing
additional complexity. When the proposed decoder is used as
the hard-decision decoder (HDD) core of a Chase-2 decoder, the
bit-error rate (BER) performance can be improved by about
0.3 dB because of the reduction in undetectable errors. Based
on a comparison of the indices for corrected bits and those of
the flipping bits, a test pattern reduction technique is proposed
for the Chase-2 decoder that does not sacrifice the error-rate
performance. The synthesis results show that the hardware
complexity for the HDD core can be reduced by more than 50%
using a 90 nm standard cell technology.
Index Terms— BCH code, wireless body area network
(WBAN), cyclic code, Chase-2 decoder.
I. I NTRODUCTION
T HE IEEE 802.15.6 standard is planned for wireless body
area network (WBAN) applications [1], and adopts the
(63,51) Bose-Chaudhuri-Hocquenghem (BCH) code [2] and
its shortened (31,19) code in order to enhance the reliability
of data transmission. Many decoders have been implemented
for WBAN applications [3], [4] [5], and most are based on the
Peterson algorithm [6]. The syndrome corresponding to the
received vector, which is termed the ‘initial syndrome’ in this
letter, is first computed by the decoder, then the coefficients
for the error location polynomial (ELP) are derived based
on the syndrome. The roots of the ELP that indicate the
locations of the error bits can be found using the Chien search
process. A failed decoding attempt occurs when the received
vector contains more errors than the correction capability. If a
failed decoding attempt is detected, a re-transmission can be
requested and there may be a better opportunity for the correct
data to be successfully received. For decoders based on the
Peterson algorithm, a failed decoding attempt is detected when
an ELP that has valid roots cannot be derived from the initial
syndrome [3], [5], [7].
Thanks to the fact that BCH codes are also cyclic codes,
the decoder implementated in this work is based on the
Meggitt algorithm [8], which allows a more reliable detection
for the failed decoding attempt that is achieved by checking
the syndrome corresponding to the decoding results. This
Manuscript received January 27, 2021; revised February 23, 2021; accepted
March 9, 2021. Date of publication March 17, 2021; date of current version
June 10, 2021. The associate editor coordinating the review of this letter and
approving it for publication was X. Jiang.
The author is with the Department of Electrical Engineering, Chang Gung
University, Taoyuan 33302, Taiwan, and also with Chang Gung Memorial
Hospital, Taoyuan 33302, Taiwan (e-mail: akula.lee@gmail.com).
Digital Object Identifier 10.1109/LCOMM.2021.3066246
1558-2558 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 08:06:03 UTC from IEEE Xplore. Restrictions apply.
IEEE COMMUNICATIONS LETTERS, VOL. 25, NO.
syndrome can be termed the ‘final syndrome’. A non-zero
final syndrome indicates that the decoding result is incorrect,
however, checking the final syndrome is not an intrinsic
feature of the Peterson algorithm. In the proposed decoder, the
syndromes corresponding to a predetermined set of correctable
error patterns are stored in the decoder, and the errors are
sequentially corrected by cyclically shifting the received vector
stored in a first-in-first-out (FIFO) buffer. The final syndrome
is derived once all the cyclically shifted versions of the
received vector are processed. Notification of a failed decoding
attempt is given if the final syndrome is non-zero. By using the
proposed decoder based on the Meggitt algorithm, the number
of detectable failed decoding attempts increases by more than
20 times.
Based on the Chase-2 decoder [9], many BCH decoders
for WBAN applications are able to provide a soft-decision
decoder (SDD) result [3], [4], and their hard-decision decoder
(HDD) cores are based on the Peterson algorithm. It is possible
that a candidate that has a non-zero final syndrome is selected
as the decoding result from the Chase-2 decoder. When the
HDD core is replaced with the proposed decoder based on the
Meggitt algorithm, an invalid candidate can be rejected when
it is detected as a failed decoding attempt. The simulation
results show that the bit-error rate (BER) performance can be
improved by about 0.3 dB with the assistance of the reduction
in undetectable errors. In addition, a test pattern reduction
technique is proposed for the Chase-2 decoder. By comparing
the indices of the bits corrected in the first decoding attempt
with those of the flipping bits, the number of test pattern can
be reduced and the error-rate performance can be maintained.
The HDD core is realized using 90 nm CMOS standard cell
technology. The synthesis result shows that the total area of
the design is about 2100 μm2 , which is equivalent to about
750 2-input NAND gates. Compared to the implementation
based on the Peterson algorithm, which occupies about 5200
μm2 when using the same technology, the proposed decoder
only requires a hardware complexity of about 41%.
II. BCH C ODES AND THE P ETERSON A LGORITHM
A BCH code is a subclass of a cyclic linear block code. For
an (N, K) cyclic code, a length-K information sequence u is
encoded to a length-N codeword v, which can be respectively
represented as polynomials of degrees N and K, The encoding
process can be represented as v(X) = u(X)g(X), where
g(X) is the generator polynomial for the code, and X N + 1 =
h(X)g(X), then all cyclically shifted versions of v(X) are
also codewords.
The (63, 51) BCH code is constructed from GF(26 ), and the
code length is equal to N = 26 − 1. Its generator polynomial
g(X) is the LCM of the two minimum polynomials, Φ1 (X)
 LEE: EFFICIENT BCH DECODER FOR WBAN APPLICATIONS
and Φ3 (X). When the Peterson algorithm is applied to decod-
ing the BCH code, the first step is to compute the syndrome.
The received vector r can be denoted as r(X) = v(X)+e(X),
where e(X) is the error pattern. Divide r(X) by Φ1 (X)
and Φ3 (X), the syndrome components corresponding to the
remainders s1 (X) and s3 (X). These are combined as the
syndrome s = [s1 , s3 ]. Since all codewords are multiples of
g(x), they must also be multiples of both Φ1 (X) and Φ3 (X).
A non-zero syndrome indicates that the received vector is not
a codeword. The second step is identifying the coefficients of
the ELP based on the syndrome. The (63, 51) BCH code is
designed to correct two errors, and its ELP is represented as
a degree-2 polynomial:
δ(X) = 1 + δ1 X + δ2 X 2 ,
where δ1 = s1 and δ2 = (s31 + s3 )/s1 . The final step is
to identify the roots of the ELP by substituting all GF(26 )
elements into (1), where the substitution process is known as
the Chien search. Each root of the ELP is corresponds to a
single error bit index. It can be observed that when
s1 = 0, s3 = 0,
the coefficient δ2 cannot be derived, and consequently the roots
of the ELP presented in (1) cannot be evaluated. In this case,
the decoding process should be aborted, and a failed decoding
is altered [2].
III. T HE P ROPOSED M EGGITT-BASED D ECODING
Although the constraint from (2) is popular in many
decoders based on the Peterson algorithm, it is only able to
detect a small number of the total failed decoding attempts.
Let αj of GF(26 ) denote the value of the syndrome component
s1 (X) corresponding to the error occuring at the j-th bit of
the receiver. When a vector containing three errors occurs at
the positions of j1 , j2 and j3 is received, s1 (X) = 0 only
happens if αj1 +αj2 +αj3 = 0, i.e., αj3 = αj1 +αj2 . However,
consider that j1 and j2 are fixed, for the other 60 j3 values, this
uncorrectable vector cannot be detected by (2). In other words,
Eq. (2) can only detect about 1/61 = 0.0164 uncorrectable
vectors. The simulation results show that the constraint from
(2) is only able to detect less than 2% of the total number of
failed decoding attempts.
It can be expected that, if the final syndrome correspond-
ing to the decoding result is derived, more failed decoding
attempts will be detected. According to our experiments, a
non-zero final syndrome can be used to detect more than 50%
of the failed decoding attempts. According to our experiment
for those received vectors containing three error bits, the final
syndrome cannot detect the failed decoding attempts when
only the received vectors decoded as the other codewords are
different to the transmitted codewords.
Since deriving the final syndrome is not an intrinsic feature
of the Peterson decoder, the proposed decoder presented
in this work is based on the Meggitt algorithm, which is
suitable for short cyclic codes that have a small correction
capability.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 08:06:03 UTC from IEEE Xplore. Restrictions apply.
1767
A. Decoding Algorithm for the Proposed HDD Core
Based on the Meggitt algorithm, the BCH code is decoded
as a cyclic code. The received vector stored in a FIFO
buffer is cyclically shifted, and the error patterns are shifted
at the same time. Since all cyclically shifted versions of a
codeword are also codewords, the decoder is designed to
identify any error located in the final register of the FIFO
buffer, i.e., X N −1 , for the stored vector. This means that only
those syndromes corresponding to the patterns that have an
error located at X N −1 need to be recorded in the decoder,
and all the correctable patterns can be detected when one of
their errors is shifted to X N −1 .
After the initial syndrome is derived, the syndromes cor-
(1) responding to the cyclically shifted versions of the received
vector can be obtained. For instance, let r(1) (X) denote the
one digit cyclic shift right version on the received vector r(X),
(1)
and s1 (X) denotes the remainder after dividing r(1) (X) by
(1)
Φ1 (X). The following equations show that s1 (X) can be
derived from s1 (X):
r(1) (X) = rN −1 + r0 X + · · · + rN −2 X N −1
(2) = rN −1 + r0 X + · · · + rN −2 X N −1
+rN −1 X N + rN −1 X N
= rN −1 + Xr(X) + rN −1 X N
= rN −1 (X N + 1) + Xr(X)
= rN −1 Φ1 (X)h(X) + X(Φ1 (X)a(X) + s1 (X))
= rN −1 Φ1 (X)h(X) + XΦ1 (X)a(X) + Xs1 (X)
= Φ1 (X)(rN −1 h(X) + Xa(X))
(1)
+Φ1 (X)a(X) + s1 (X). (3)
The last two rows of the previous equation show that
(1)
Xs1 (X) = Φ1 (X)a(X) + s(1) (X), then s1 (X) can also be
derived as the remainder of Xs1 (X) being divided by Φ1 (X),
where multiplying X by s1 (X) is equal to shifting s1 (X) by
(1)
one digit. Similarly, the syndrome s3 (X) corresponding to
Φ3 (X) can be derived from s3 (X).
Then, it can be expected that if s is the syndrome cor-
responding to a correctable error pattern e, then the syn-
dromes s(1) , s(2) , · · · , s(N −1) corresponding to all the N − 1
cyclic shift versions of e can be derived from s, where
(n) (n)
s(n) = [s1 , s3 ], n = 1, 2, · · · , N − 1. This means that,
as long as s is stored in the decoder, all error patterns
e(1) , e(2) , · · · , e(N −1) can be detected by cyclically shifting
the received vector stored in the FIFO buffer.
B. Chase-2 Decoding Based on the Proposed HDD Core
The frame error rate (FER) performance for both the (63,51)
and (31,19) codes are presented in Fig. 1, where BPSK
modulation is used and the signal is transmitted through
the AWGN channel. The rates of undetectable errors are
also demonstrated. Because less than 2% of the total failed
decoding attempts can be detected using the constraint in
(2), the undetectable error rate is almost identical to the
FER. For detections using the final syndrome, more than 50%
of the failed decoding attempts can be identified, then the
 1768
Fig. 1. FER and undetectable error rates for a (63, 51) BCH code and its
(31, 19) shortened code.
corresponding undetectable error rate is significantly lower
than the FER.
Many of the BCH decoders proposed for WBAN appli-
cations are able to provide an SDD performance using the
Chase-2 algorithm [3], [4]. The proposed decoder based on
the Meggitt algorithm can also be used as the HDD core and
can be embedded in a Chase-2 decoder. In a Chase-2 decoder,
the t least reliable bits (LRB) for the received vector r are
identified. All flipping combinations for these t LRB bits are
collected as the total number of 2t test patterns. The HDD
decoder is applied to all 2t test patterns, and the results are
the decoding candidates. The decoding candidate that has the
shortest Euclidean distance to the received signal y is selected
as the decoding result, where the received vector r is the hard-
decision result of y.
It is possible that the decoding candidate that has the
shortest Euclidean distance has a non-zero final syndrome.
This candidate will be selected as the decoding result for
the Chase-2 decoder containing an HDD core based on the
Peterson algorithm even it is not a codeword. This fault can
be avoided if the HDD core is replaced with the proposed
decoder based on the Meggitt algorithm. A stricter constraint
for the Chase-2 decoder can be introduced by selecting the
candidate that has the shortest Euclidean distance as well as a
zero final syndrome. If the final syndromes for all candidates
are non-zero, then the candidate that has the shortest Euclidean
distance is selected.
The improvement achieved by using the stricter constraint
is shown in Fig. 2. The BER performance for the Chase-2
decoder when using different HDD cores is compared. The
results from [3] are referred to for the HDD core based on
the Peterson algorithm. With the assistance of the stricter
constraint, the Chase-2 decoder using the proposed HDD core
based on the Meggitt algorithm is able to provide an additional
coding gain of 0.3 dB for both the (63,51) and (31,19) codes
when the BER is close to 10−5 .
C. Modified Chase-2 Decoding for Test Pattern Reduction
Since the BCH code adopted in the WBAN standard has the
correction capability of t = 2, when the Chase-2 decoder is
considered, there are a total of 22 = 4 test patterns generated
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 08:06:03 UTC from IEEE Xplore. Restrictions apply.
IEEE COMMUNICATIONS LETTERS, VOL. 25, NO. 6, JUNE 2021
Fig. 2. BER performance for the (63, 51) BCH code and its (31, 19) shortened
code.
TABLE I
R EDUCTION IN T EST PATTERNS
by flipping two least reliable bits in the received vector r.
In most case, multiple test patterns may be decoded as the
same codes, and the number of test patterns required to be
evaluated can be reduced by comparing the indices of the
corrected bits and the flipping bits, and, hence, reducing the
complexity of the Chase-2 decoder.
Let Im1 and Im2 denote the indices of the flipping bits.
The original hard decision vector r is denoted as the test
pattern T00 , and the corresponding decoding result is v̂00 .
The test pattern T01 and T10 are generated by individually
flipping the bits located at Im1 and Im2 . When both bits are
flipped, the corresponding test pattern is T11 The decoding
results corresponding to T01 , T10 , and T11 are denoted as
v̂01 , v̂10 , and v̂11 , respectively. Following the first decoding
attempt, the test patterns for the Chase-2 decoder can be
reduced by comparing the indices of the corrected bits and
the flipping bits. The details of the test pattern reduction are
shown in Table I.
The first row of Table I shows that when there is no bit
needed to be corrected in r, i.e., both s1 and s3 are all-zero
vectors, the decoding process can be immediately terminated,
and there is no requirement to decode any test patterns.
When a non-zero s1 or s3 is detected, the first decoding
attempt is applied to T00 . In the case that a single error bit is
corrected, the decoding result v̂00 is derived by flipping the
bit located at the Ic1 of r. If Ic1 is equal to Im1 or Im2 , there
is no need to evaluate any additional test patterns. Because the
Hamming distances between v̂00 and all the remaining three
 LEE: EFFICIENT BCH DECODER FOR WBAN APPLICATIONS
Fig. 3. Average number of test patterns required for different reduction
strategies.
test patterns are less than the correction capability t = 2,
and all the test patterns will be decoded to the same result.
However, if Ic1 is neither Im1 nor Im2 , then the distances
between v̂00 and T10 and that between v̂00 and T10 are both
2, and the distance between v̂00 and T11 is 3, meaning that,
only T11 needs to be evaluated.
In the case where two errors are corrected, the decoding
result v̂00 is derived by flipping the bits located at Ic1 and Ic2
of T00 . When the sets of the corrected bits and the flipping bits
are exactly the same, i.e., v̂00 = T11 , the distances between
v̂00 and all the remaining three test patterns are less than 2,
and no additional test patterns need to be evaluated. If one of
the corrected bits is not included in the set of flipping bits, then
an additional test pattern needs to be evaluated. For instance,
when only one of Ic1 or Ic2 is equal to Im1 , but neither of
Ic1 or Ic2 is equal to Im2 , then the distance between v̂00 and
T01 is 1, and the distance between v̂00 and T11 is 2. Only T10
generated by flipping the bit located at Im1 of r is required to
be evaluated, where the distance between v̂00 and T10 is 3.
A similar case occurs when only one of Ic1 or Ic1 is equal to
Im2 . In this case, the additional test pattern is T01 . These two
cases are listed in the fifth and the sixth rows of Table I.
Finally, when the sets of the corrected bits and the flip-
ping bits are non-overlapping, then all test patterns must be
evaluated.
The number of required test patterns for the Chase-2
decoder being applied to the (63, 51) BCH code and the (31,
19) shortened BCH code are shown in Fig. 3. They are com-
pared to the results from [3], where the reduction technique is
based on [7]. It can be observed that, for a practical SNR range
larger than 3-dB, the method listed in Table I is able to reduce
more test patterns. The proposed method illustrated in Table I
is based on the minimum distance property of the code, and
is expected to reduce the test pattern for the Chase-2 decoder
without sacrificing the error-rate performance.
IV. I MPLEMENTATION R ESULTS
A. Decoder Structure
The implementation of the proposed decoder is shown
in Fig. 4 and contains three major parts: the ‘Syndrome
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 08:06:03 UTC from IEEE Xplore. Restrictions apply.
1769
Generator’, the ‘Error Detector’, and the ‘FIFO Buffer’. The
decoding process is executed sequentially and requires a
maximum of 2N clock cycles. The signal ‘Code Selection’ is
used to select N = 63 for the (63, 51) BCH code or N = 31
for the shortened (31, 19) code. Following the N -th clock
cycle, the received vector r(X) is totally loaded into the ‘FIFO
Buffer’ and the initial syndrome s = [s1 , s3 ] is simultaneously
generated by the ‘Syndrome Generator’. The signal ‘All Bits
Loaded’ then switches the MUXs. During the subsequent N
clock cycles, the cyclically shifted versions of the received
vector r(1) (X), r(2) (X), · · · , r(N −1) (X) are sequentially gen-
erated in the ‘FIFO Buffer’. At the same time, the correspond-
ing syndromes s(1) (X), s(2) (X), · · · , s(N −1) (X) are derived
by the ‘Syndrome Generator’.
Since the (63, 51) code is expected to correct t = 2 error
bits, the ‘Error Detector’ is a combinational logic block that
is designed to check whether any syndromes corresponding to
the error patterns have errors equal to or less than 2. These pat-
terns are collected in the set E = {(X 62 ), (X 0 + X 62 ), (X 1 +
X 62 ), · · · , (X 61 +X 62 )}. All the patterns contained in E have
an error located at X 62 . As long as a syndrome corresponding
to any of the error patterns in E is generated by the ‘Syndrome
Generator’, the signal ‘Error Detected’ is triggered by the
combinational logic of the ‘Error Detector’. The logic result
‘1’ is sent to flip the digit located at X 62 in the ‘FIFO Buffer’
and update the corresponding syndrome. With the assistance
of the cyclic shifting of the ‘FIFO Buffer’ and the ‘Syndrome
Generator’, the detection is able to cater for all correctable
error patterns.
B. Hardware Realization
A sequential decoder for the same (63, 51) BCH code
that is implemented based on the Peterson algorithm is
shown in Fig. 6 in [5]. When compared to the proposed
implementation based on the Meggitt algorithm, as shown
in Fig. 4, the ‘FIFO Buffer’ and the ‘Syndrome Generator’
are essential for both decoders. The ‘Chain-Search’ and the
‘Key-Equation Solver’ blocks for the design presented in [5]
are replaced with the ‘Error Detector’ block in the proposed
decoder. The ‘Error Detector’ cooperates with the ‘FIFO
Buffer’ and the ‘Syndrome Generator’, and the cyclic-shift
operation for the ‘FIFO Buffer’ in the Meggitt algorithm
corresponds to the substitution of the ‘Chain search’ in the
Peterson algorithm. Additional sequential logic elements are
required for the ‘Chain-Search’. In contrast, ‘Error Detector’
can be constructed using only combinational logic and com-
pactly realized with the assistance of the synthesis tools. The
‘Error Detector’ block occupies about 525 μm2 when it is
realized in 90 nm standard technology, which is equivalent to
187 2-input NAND gates.
The synthesis results are shown in Table II, and the
comparisons with other studies are also provided. Since 2N
clock cycles are required in order to complete the decoding
process without triggering early termination, then, in the
worst case, 126 clock cycles are required in order to provide
51 information bits when using the (63,51) BCH code. For
the shortened (31,19) code, 62 clock cycles are required in
order to provide 19 bits. To provide the 10 Mbps throughput
 1770
Fig. 4. The proposed decoder for WBAN applications based on the Meggitt algorithm.
TABLE II
H ARDWARE R EALIZATION C OMPARISON
requirement specified in the IEEE 802.15.6 standard, sample
rates of 24.71 MHz and 32.63 MHz are respectively needed
for the (63,51) and the (31,19) codes. The proposed decoder is
designed to operate at a clock frequency of 50 MHz. The area
occupied and the power consumption are listed in Table II.
Compared to the decoder based on the Peterson algorithm
presented in [5], the area occupied by the proposed design
based on the Meggitt algorithm is reduced to about 41%.
Although the decoder described in [5] consumes less power,
the value is measured at a clock rate of 487.5 kHz, which is too
slow for WBAN applications, and will need to be increased by
15 times in order to support the required 10 Mbps throughput.
In general cases, decoders based on the Peterson algorithm
can be efficiently realized, since they are able to exploit the
advantage of the structure of the BCH codes constructed from
the Galois field. However, the BCH codes adopted in the
IEEE 802.15.6 standard have a maximum length of N = 63
bits, and only t = 2 error bits are expected to be corrected,
meaning that the Meggitt algorithm could be a more suitable
option.
V. C ONCLUSION
An efficient decoder based on the Meggitt algorithm is
designed for BCH codes intended for WBAN applications.
A hardware complexity of only 41% is required compared
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR. Downloaded on November 09,2022 at 08:06:03 UTC from IEEE Xplore. Restrictions apply.
IEEE COMMUNICATIONS LETTERS, VOL. 25, NO. 6, JUNE 2021
to conventional decoders based on the Peterson algorithm.
Since the final syndrome corresponding to the decoding result
is available, the proposed decoder is able to reduce the
number of undetectable errors by more than 50%. When the
Peterson algorithm is used to implement the HDD core for
the Chase-2 decoder, a candidate that has a non-zero final
syndrome is possibly being selected as the decoding result.
This type of error can be avoided if an HDD core based on
the Meggitt algorithm is used. Then the Chase-2 decoder has
the HDD core based on the proposed decoder can provide
an additional coding gain of 0.3 dB. Using the proposed
test pattern reduction technique, the complexity of the Chase-
2 decoder can be further reduced without sacrificing error-rate
performance.
R EFERENCES
[1] Information Technology—Telecommunications and Information
Exchange Between Systems—Local and Metropolitan Area Networks—
Part 15-6: Wireless Body Area Network, International Standard
ISO/IEC/IEEE 8802-15-6:2017(E), Oct. 2017. [Online]. Available:
http://www.ieee802.org/15/pub/TG6.html
[2] S. B. Wicker, Error Control Systems for Digital Communication and
Storage. Englewood Cliffs, NJ, USA: Prentice-Hall, 1994.
[3] C.-H. Yang, T.-Y. Huang, M.-R. Li, and Y.-L. Ueng, “A 5.4 µW soft-
decision BCH decoder for wireless body area networks,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 61, no. 9, pp. 2721–2729, Sep. 2014.
[4] B. Jung, T. Kim, and H. Lee, “Low-complexity non-iterative soft-
decision BCH decoder architecture for WBAN applications,” JSTS, J.
Semicond. Technol. Sci., vol. 16, no. 4, pp. 488–496, Aug. 2016.
[5] P. K. Manchi, R. Paily, and A. K. Gogoi, “Low-power digital baseband
transceiver design for UWB physical layer of IEEE 802.15.6 standard,”
IEEE Trans. Ind. Informat., vol. 13, no. 5, pp. 2474–2483, Oct. 2017.
[6] W. Peterson, “Encoding and error-correction procedures for the bose-
chaudhuri codes,” IEEE Trans. Inf. Theory, vol. IT-6, no. 4, pp. 459–470,
Sep. 1960.
[7] G. Chen, L. Cao, L. Yu, and C. Chen, “Test-pattern-reduced decoding
for turbo product codes with multi-error-correcting eBCH codes,” IEEE
Trans. Commun., vol. 57, no. 2, pp. 307–310, Feb. 2009.
[8] J. Meggitt, “Error correcting codes and their implementation for data
transmission systems,” IEEE Trans. Inf. Theory, vol. IT-7, no. 4,
pp. 234–244, Oct. 1961.
[9] D. Chase, “A class of algorithms for decoding block codes with channel
measurement information,” IEEE Trans. Inf. Theory, vol. IT-18, no. 1,
pp. 170–182, Jan. 1972.