5 4 3 2 1

Wistron Confidential

D
Silverton / SilverOak D

2014-12-09
REV : 0 (X-build)

C C

B B

Wistron Confidential document, Anyone can not

Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
01_Cover
Size Document Number Rev
A3 SILVERTON/SILVEROAK 0
Date: Tuesday, December 09, 2014 Sheet 1 of 61
5 4 3 2 1
 5 4 3 2 1

Project Name: Silverton

Project Code: 4PD03P010001
PCB No: 14238
Block Diagram
DDR3L-RS 2GB
MIPI LCD System Power
SK HYNIX 1333MHz
D
H5TC4G63AFR-PBR Intel MIPI-DSI A AUO 1920*1200 B101UAN01.7
AUO 1280*800 B101EAN01.5
PMIC PSND9039
D

12-14
Bay Trail T-CR 23
INPUTS OUTPUTS
+VSYS +V_VNN
e-Compass I2C AUX Gyro + G Sensor DDI0 +V_VCC
AK8963C-GP38 MPU-6500 I2C 2 HDMI CONN +VDDQ
38 26 +V1P0SX
+V1P0A
+V1P8A
Touch Screen
EC WIFI/BT Combo I2S 1 Valleyview-T I2C3 Wacom 39
+V3P3A_PMIC
+V2P85S
1X2 AW-NB177NF UART1
NPCE948LA0BX-GP
41
2X2 WM-BAN-BM-10_L SDIO2
SOC MIPI-CSI 1 5M Rear Camera
+VRTC
+AVDD_CAM
17-18
17mmx17mm I2C 1
LiteOn:13P2BA520A +V1P8_Rear
V1P8SX_2
22
I2C +V3P3A_TP
Light sensor I2C 2 +VSDIO
FUEL GAUGE CM32181 38 MIPI-CSI 2 1.22M Front Camera +VSD
Battery BQ27510DRZR LiteOn:13P2SF130B +V3P3A
Hall sensor I2C 1
22 LCM_VDD_3V3
PACK (1S2P) -G3 44 S-5712ACDL1
C
38 HALL_SENSOR_INT C
+V1P8A +V1P2Sx
SDMMC3 Micro SD Conn. +V1P2A
31 RT9040GQW-2-GP
Charger 40 I2C 0
BQ24297RGER-GP 22-nm INPUTS OUTPUTS
1CH SPEAKER
Quad Core/ Z3735F 1W +VDDQ +VDDQ_VTT
USB PHY ULPI BUS BGA DDR3L-RS-1333 I2C 1 AUDIO CODEC
TUSB1210 CHARGER
USB Switch 42 Realtek Digital Mic
TS3USB221RSER ALC5672-CGT-GP WM7211IMS 30 BQ24297
uUSB I2S 0
42
42 INPUTS OUTPUTS
USB HUB USB0 HEADPHONE & MIC 5V / VBAT +VSYS
USB CONN GL850G (Combo Jack) 25 5V BOOST
43 0x38 29
43
DOCK BOARD SY7066QMC-GP
USB1
48
3G/LTE USIM INPUTS OUTPUTS
I2C_2 3G/LTE Module uSIM
31 +VSYS +V5P0_BOOST
B I2C 4 Telit 3V3 BUCK
B

xN930 M.2 USB 1 SY8010ZDEC-GP

PMIC SVID 20

TI PMIC_PWRGD I2C_0 INPUTS OUTPUTS

NFC Module
PSND9039 WNC DFCN-4 19
+VSYS +3V3_A
PMIC_INT PCB LAYER
Power rails I2C_2 SAR sesor LDI 8L
45-46 SX9500IULTRT 21 L1:Top L5:Signal
intel L2:GND
L3:Signal
L6:Signal
L7:GND
VIBRATOR_PWM debug signal L4:GND L8:Bottom
VIBRATOR 3-10 XDP CONN
36
34
X701
OSC-25MHZ
X702
OSC-32.768KHZ UART_3 Debug CONN
EMMC
34
SPI_0

A
eMMC SPI NOR A

Winbond Wistron Confidential document, Anyone can not

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Samsung W25Q64FWZPIG application without get Wistron permission

8MB
KLMBG4GEAC-B031 33
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
16 02_Block Diagram
Size Document Number Rev
A2 SILVERTON/SILVEROAK 0
Date: Monday, September 15, 2014 Sheet 2 of 61
5 4 3 2 1
 5 4 3 2 1

SOC MEM SECTION : 1&2

M0_DATA[0..63] 12,13
CPU1A 1 OF 9
M24 D18 M0_DATA0
12,14 M0_CA0 DRAM0_MA0 DRAM0_DQ0 M0_DATA1
D L23 B18 D
12,14 M0_CA1 DRAM0_MA1 DRAM0_DQ1 M0_DATA2
N23 A21
12,14 M0_CA2 DRAM0_MA2 DRAM0_DQ2 M0_DATA3
M20 C18
12,14 M0_CA3 DRAM0_MA3 DRAM0_DQ3 M0_DATA4
M22 A22
12,14 M0_CA4 DRAM0_MA4 DRAM0_DQ4 M0_DATA5
L22 B20
12,14 M0_CA5 DRAM0_MA5 DRAM0_DQ5 M0_DATA6
K24 A18
12,14 M0_CA6 DRAM0_MA6 DRAM0_DQ6 M0_DATA7
N25 B22
12,14 M0_CA7 DRAM0_MA7 DRAM0_DQ7 M0_DATA8
J25 C20
12,14 M0_CA8 DRAM0_MA8 DRAM0_DQ8 M0_DATA9
H24 D23
12,14 M0_CA9 DRAM0_MA9 DRAM0_DQ9 M0_DATA10
N20 E19
12,14 M0_CA10 DRAM0_MA10 DRAM0_DQ10 M0_DATA11
K25 E23
12,14 M0_CA11 DRAM0_MA11 DRAM0_DQ11 M0_DATA12
M25 D22
12,14 M0_CA12 DRAM0_MA12 DRAM0_DQ12 M0_DATA13
M23 E22
12,14 M0_CA13 DRAM0_MA13 DRAM0_DQ13 M0_DATA14
H25 E20
12,14 M0_CA14 DRAM0_MA14 DRAM0_DQ14 M0_DATA15
K23 D20
DRAM0_MA15 DRAM0_DQ15 M0_DATA16
E25
DRAM0_DQ16 M0_DATA17
A20 A23
12 M0_DM0 DRAM0_DM0 DRAM0_DQ17 M0_DATA18
D21 C23
12 M0_DM1 DRAM0_DM1 DRAM0_DQ18 M0_DATA19
D25 F25
12 M0_DM2 DRAM0_DM2 DRAM0_DQ19 M0_DATA20
F19 B24
12 M0_DM3 DRAM0_DM3 DRAM0_DQ20 M0_DATA21
AC24 D24
13 M0_DM4 DRAM0_DM4 DRAM0_DQ21 M0_DATA22
V24 B23
13 M0_DM5 DRAM0_DM5 DRAM0_DQ22 M0_DATA23
Y22 F24
13 M0_DM6 DRAM0_DM6 DRAM0_DQ23 M0_DATA24
T23 F20
13 M0_DM7 DRAM0_DM7 DRAM0_DQ24 M0_DATA25
F21
DRAM0_DQ25 M0_DATA26
N22 G20
12,14 M0_RASB DRAM0_RAS# DRAM0_DQ26 M0_DATA27
P20 H23
12,14 M0_CASB DRAM0_CAS# DRAM0_DQ27 M0_DATA28
P21 G21
12,14 M0_WEB DRAM0_WE# DRAM0_DQ28 M0_DATA29
J21
C DRAM0_DQ29 M0_DATA30 C
M21 J20
12,14 M0_BS0 DRAM0_BS0 DRAM0_DQ30 M0_DATA31
N19 H22
12,14 M0_BS1 DRAM0_BS1 DRAM0_DQ31 M0_DATA32
K22 AD24
12,14 M0_BS2 DRAM0_BS2 DRAM0_DQ32 M0_DATA33
AB25
DRAM0_DQ33 M0_DATA34
P22 Y24
12,14 M0_CS0_B DRAM0_CS0# DRAM0_DQ34 M0_DATA35
AE23
DRAM0_DQ35 M0_DATA36
P23 AA25
DRAM0_CS2# DRAM0_DQ36 M0_DATA37
AC23
DRAM0_DQ37 M0_DATA38
AD23
DRAM0_DQ38 M0_DATA39
G22 Y25
12,14 M0_CKE0 DRAM0_CKE0 DRAM0_DQ39 M0_DATA40
G23 V23
DRAM0_CKE1 DRAM0_DQ40 M0_DATA41
F23 T24
DRAM0_CKE2 DRAM0_DQ41 M0_DATA42
F22 W22
DRAM0_CKE3 DRAM0_DQ42 M0_DATA43
W23
DRAM0_DQ43 M0_DATA44
P24 R23
12,14 M0_ODT0 DRAM0_ODT0 DRAM0_DQ44 M0_DATA45
R22
DRAM0_DQ45 M0_DATA46
P25 V22
DRAM0_ODT2 DRAM0_DQ46 M0_DATA47
T25
DRAM0_DQ47 M0_DATA48
AB22
DRAM0_DQ48 M0_DATA49
J23 AC22
12,14 M0_CLK0_DP DRAM0_CKP0 DRAM0_DQ49 M0_DATA50
J22 Y19
12,14 M0_CLK0_DN DRAM0_CKN0 DRAM0_DQ50 M0_DATA51
AD22
+VDDQ DRAM0_DQ51 M0_DATA52
AA22
12,14 M0_DRAMRSTB DRAM0_DQ52 M0_DATA53
K20 Y23
DRAM0_CKP2 DRAM0_DQ53
1

K21 Y20 M0_DATA54

DRAM0_CKN2 DRAM0_DQ54
1

R304 Y21 M0_DATA55

D301 DRAM0_DQ55 M0_DATA56
DY DRAM0_DQ56
T22
4K7R1F-GP AZ5725-01FDR7G-GP T20 M0_DATA57
DRAM0_DQ57 M0_DATA58
U19 W20
B DRAM0_DRAMRST# DRAM0_DQ58 M0_DATA59 B
V20
2

DRAM0_DQ59 M0_DATA60
U21
CPU_VREF DRAM0_DQ60 M0_DATA61
AD20 W21
DRAM_VREF DRAM0_DQ61 M0_DATA62
U20
DRAM0_DQ62
1

R305 T21 M0_DATA63

DRAM0_DQ63
1

4K7R1F-GP C301 D19 M0_DQS0_DP 12

SCD1U10V1KX-GP DRAM0_DQSP0
C19 M0_DQS0_DN 12
DRAM0_DQSN0
DY link to PMIC C22 M0_DQS1_DP 12
2

DRAM0_DQSP1
46 DRAM_PWROK AC20 C21 M0_DQS1_DN 12
DRAM_VDD_S4_PWROK DRAM0_DQSN1
46 VCCA_PWROK AB20 C24 M0_DQS2_DP 12
DRAM_CORE_PWROK DRAM0_DQSP2
C25 M0_DQS2_DN 12
DRAM0_DQSN2
H20 M0_DQS3_DP 12
DDR3_ODTPU DRAM0_DQSP3
AE22 H19 M0_DQS3_DN 12
DDR3_DQPU DRAM_RCOMP2 DRAM0_DQSN3
AE20 AC25 M0_DQS4_DP 13
DRAM_RCOMP1 DRAM0_DQSP4
R301 1

DDR3_CMDPU AE21 AB24 M0_DQS4_DN 13

DRAM_RCOMP0 DRAM0_DQSN4
R302 1

V25
162R1F-GP

DRAM0_DQSP5 M0_DQS5_DP 13
U25
29D4R1F-GP

23D2R2F-GP

DRAM0_DQSN5 M0_DQS5_DN 13
2 R303

AB23 M0_DQS6_DP 13
DRAM0_DQSP6
AA23 M0_DQS6_DN 13
2

DRAM0_DQSN6
U22 M0_DQS7_DP 13
2

DRAM0_DQSP7
U23 M0_DQS7_DN 13
DRAM0_DQSN7
VALLEYVIEW-T-2-GP
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
03_CPU (LPDDR3)
Size Document Number Rev
A3 SILVERTON/SILVEROAK 0
Date: Tuesday, December 09, 2014 Sheet 3 of 61
5 4 3 2 1
 5 4 3 2 1

SOC : DDI 0&1 / MIPI-DIS/MIPI-CSI/MIPI-GPIO

D D
CPU1B 2 OF 9
AB4 U7
26 DDI0_TX0_DP DDI0_TXP0 DDI1_TXP0
AB3 U6
HDMI 26
26
26
DDI0_TX0_DN
DDI0_TX1_DP
DDI0_TX1_DN
AB2
AA1
Y2
DDI0_TXN0
DDI0_TXP1
DDI0_TXN1 eDP
DDI1_TXN0
DDI1_TXP1
DDI1_TXN1
V5
V4
T1
26 DDI0_TX2_DP DDI0_TXP2 DDI1_TXP2
Y1 U1
26 DDI0_TX2_DN DDI0_TXN2 DDI1_TXN2
Y4 U4
26 DDI0_TX3_DP DDI0_TXP3 DDI1_TXP3
Y3 U5
26 DDI0_TX3_DN DDI0_TXN3 DDI1_TXN3
Y5 +V1P8A_SOC
DDI1_AUXP R401
W6
DDI1_AUXN 1KR1J-GP
E14 B12 DDI1_HPD# 1 2
26 DDI0_HPD DDI0_HPD DDI1_HPD

26 DDI0_DDCDATA D13
DDI0_DDCDATA
26 DDI0_DDCCLK
C13
DDI0_DDCCLK DDI1_VDDEN
B14 TP_ID1 39 DVT-1
A14
DDI1_BKLTEN SOC_LCM_BKLT_EN 23
A13
DDI1_BKLTCTL SOC_LCM_VDD_EN 23

R405
402R2F-GP
1 2 DDI_ROMP_P AA3
DDI_ROMP_N DDI_RCOMP_P
AA4
DDI_RCOMP_N

C
MIPI Display C
M5
23 MDSI_A_CLKN
23 MDSI_A_CLKP
P5
P4
MDSI_A_CLKN
MDSI_A_CLKP
MCSI1_CLKN
MCSI1_CLKP
M6
MCSI_1_CLK_DN
MCSI_1_CLK_DP
22
22 Rear Camera
P3 MCSI_1_DATA0_DN 22
MCSI1_DN0
T4 P2 MCSI_1_DATA0_DP 22
23 MDSI_A_DN_0 MDSI_A_DN0 MCSI1_DP0
T3 M1 MCSI_1_DATA1_DN 22
23 MDSI_A_DP_0 MDSI_A_DP0 MCSI1_DN1
R4 N1 MCSI_1_DATA1_DP 22
23 MDSI_A_DN_1 MDSI_A_DN1 MCSI1_DP1
R3 M4
23 MDSI_A_DP_1 MDSI_A_DP1 MCSI1_DN2
T6 M3
23 MDSI_A_DN_2 MDSI_A_DN2 MCSI1_DP2
T5 L3
23 MDSI_A_DP_2 MDSI_A_DP2 MCSI1_DN3
P6 L4
23 MDSI_A_DN_3 MDSI_A_DN3 MCSI1_DP3
N6
23 MDSI_A_DP_3 MDSI_A_DP3
K4
MCSI2_CLKN
MCSI2_CLKP
K5
MCSI_2_CLK_DN
MCSI_2_CLK_DP
22
22 Front Camera
K6 MCSI_2_DATA_DN 22
MCSI2_DN0
J6 MCSI_2_DATA_DP 22
MCSI2_DP0

K1 MCSI_COMP R404 1 2 150R1F-GP

MCSI_RCOMP
Closed to SOC
D17
GPIO_S0_NC15 CHG_CE_N 40
B16
GPIO_S0_NC16 CAMERA_R_VCM_PD 22
C15
GPIO_S0_NC17 CAMERA_1_RESET# 22
C14
GPIO_S0_NC18 CAMERA_2_RESET# 22
C17
R403 1 GPIO_S0_NC19 WLAN_DEVICE_RESET 17
2 150R1F-GP MDSI_COMP P1 C16
MDSI_RCOMP GPIO_S0_NC20 WIFI_CHIP_EN 17
D16 TP_ID2 39 DVT-1
B GPIO_S0_NC21 B
Closed to SOC F17
MDSI_A_TE GPIO_S0_NC22
D15
AMBER_LED_EN 48
GPIO_S0_NC23
D14
WIRELESS_LED_EN 48
DVT-1
F18
GPIO_S0_NC24 BT_WAKE 17,18
E17
GPIO_S0_NC25 BT_DEV_EN 18
E16
GPIO_S0_NC26 TOUCH_RESET# 39
VALLEYVIEW-T-2-GP

Wistron Confidential document, Anyone can not

Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
04_CPU (eDP/HDMI/MIPI)
Size Document Number Rev
A3 SILVERTON/SILVEROAK 0
Date: Tuesday, December 09, 2014 Sheet 4 of 61
5 4 3 2 1
 5 4 3 2 1

SOC : eMMC/SD/GPIO/I2S

CPU1C 3 OF 9
32 VOLUME_DOWN_CPU AB6
GPIO_S0_SC000
32 VOLUME_UP_CPU AA6
GPIO_S0_SC001
D Y6 D
40 CHG_OTG GPIO_S0_SC002
AC3
S_RCOMP_P
AC4
S_RCOMP_N

AE8
16 EMMC_CLK MMC1_CLK
16 EMMC_DATA_0 AB7 AC5 SKU_ID_1
MMC1_D0 GPIO_S0_SC003
16 EMMC_DATA_1 AC7
16
16
EMMC_DATA_2
EMMC_DATA_3
AC8
AB9
MMC1_D1
MMC1_D2
MMC1_D3
eMMC
16 EMMC_DATA_4 AA9 AA5 SD3_CD#_AA5 R502 1 2 1KR1J-GP MC1CD# 31
MMC1_D4 GPIO_S0_SC007
16 EMMC_DATA_5 AA8
MMC1_D5 C501
16 EMMC_DATA_6 Y8 1 2 SCD1U6D3V1KX-GP
MMC1_D6
16 EMMC_DATA_7 Y7
MMC1_D7
AB8
16 EMMC_CMD MMC1_CMD HDA_RCOMP R506 1
AD8 AE14 2 49D9R1F-GP Closed to SOC
16 EMMC_RESET# MMC1_RST# AUDIO_RCOMP
Y16
Closed to SOC R501 1 2 49D9R1F-GP EMMC_RCOMP AE6
MMC1_RCOMP Codec I2S0_CLK
I2S0_FRM
I2S0_DATAOUT
Y14
AA14
I2S_0_CLK
I2S_0_FS
I2S_0_TXD
29
29
29
AE9 Y13 I2S_0_RXD 29
17,18 SDIO2_CLK SD2_CLK I2S0_DATAIN
17,18
17,18
SDIO2_DATA_0
SDIO2_DATA_1
AB11
AB10
SD2_D0 WIFI I2S1_CLK
AC13
AC14
I2S_1_CLK 18

C
17,18
17,18
SDIO2_DATA_2
SDIO2_DATA_3
AC10
AD10
SD2_D1
SD2_D2
SD2_D3_CD#
BT I2S1_FRM
I2S1_DATAOUT
I2S1_DATAIN
AB14
Y10
I2S_1_FS
I2S_1_TXD
I2S_1_RXD
18
18
18 C
17,18 SDIO2_CMD AC9
SD2_CMD BIAS_OVER_R R503 1
U17 2 10KR1J-GP +V1P8A_SOC Flash Descriptor Override Strap
GPIO_S0_SC65 R505 1 2 10KR1J-GP 0=Override
DY 1=Normal Operation
AC12
31 MC1CK SD3_CLK

31 MC1DA0 AC11
SD3_D0
AB13 1 2
31
31
31
MC1DA1
MC1DA2
MC1DA3
AA12
AA13
SD3_D1
SD3_D2
SD3_D3
uSD R509
FLASH_REWRITE 41

0R1J-GP
MC1CD# R510 1 2 0R1J-GP SD3_CD#_Y12 Y12 DVT-1
SD3_CD#
AB12
31 MC1CM SD3_CMD
Y9 F16
19 NFC_DWL_REQ SKU_ID_4 SD3_1P8EN PROCHOT#
AA10
DVT-1 SD3_PWREN#
R504 1 2 49D9R1F-GP SDIO3_RCOMP AE10
SD3_RCOMP
Closed to SOC
VALLEYVIEW-T-2-GP

B
NFC ID (GPIOC_3) WWAN ID (GPIOC_41) EMMC ID1 EMMC ID2 B

H: with NFC H: with WWAN GPIOC_74 GPIOC_75

L: without NFC L: without WWAN
+V1P8A_SOC +V1P8A_SOC +V1P8A_SOC +V1P8A_SOC
2

2
R508 R731 R720 config R721
10KR1J-GP config 10KR1J-GP config 10KR1J-GP 10KR1J-GP config
1

1
SKU_ID_1 SKU_ID_4
7 SKU_ID_3 7 SKU_ID_2
2

2
R507 R730 R719 R718
10KR1J-GP config 10KR1J-GP config 10KR1J-GP config 10KR1J-GP config
1

1
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A A

DVT-2 DVT-2 DVT-2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
05_CPU (SD/eMMC/AUDIO)
Size Document Number Rev
A3 SILVERTON/SILVEROAK 0
Date: Tuesday, December 09, 2014 Sheet 5 of 61
5 4 3 2 1