Comparators, Multiplexing, Time Division Multiplexing

1. Logic Gates
2. Signal Processing Logic Gates
3. Boolean Algebra
4 Integrated Circuits
5 Classification of IC
6 K-map and logic design
7 Combinational logic modules
 Binary Comparators
Binary comparators, also called digital comparators or logic
comparators, are combinational logic circuits that are used for
testing whether the value represented by one binary word is greater
than, less than, or equal to the value represented by another binary
word. Basically it ccompares the magnitude of two binary numbers
for the purpose of establishing whether one is greater than, equal
to, or less than the other.
A comparator makes use of a cascade connection of identical
subnetworks similar to the case of the parallel adder
Two basic types of comparator can be used.
• Equality comparators.
• Magnitude comparators.
 Equality Comparator
An equality comparator, such as that illustrated in Figure is the simplest multi-bit logic
comparator, and can be used for such circuits as electronic locks and security devices where a
binary password consisting of multiple bits is input to the comparator to be compared with
another preset word.

In Figure, a logic 1 will be present at the output if the two input words match, otherwise the
output remains at 0. Therefore there is only one input combination that is correct, and the
more bits the input words possesses, the more possible wrong combinations there are. With
extra circuitry for counting, additional security may be provided by limiting the number of
tries before the input is inhibited.

The circuit of the equality comparator consists of an exclusive NOR gate (XNOR) per pair of
input bits. If the two inputs are identical (both 1s or both 0s) an output of logic 1 is obtained.
The outputs of the XNOR gates are then combined in an AND gate, the output of which will
be 1, only when all the XNOR gates indicate matched inputs.
 1 bit magnitude comparator in hindi
https://www.youtube.com/watch?v=q8gVPkyVDlc

2-Bit Comparator
https://www.youtube.com/watch?v=BhUUmbz76P0

Comparators Part 1
https://www.youtube.com/watch?v=hoSrJv47RaI

Comparators Part 2
https://www.youtube.com/watch?v=5QAHUV1dmfc

4 Bit Comparator - Part 1- Easy to Understand

https://www.youtube.com/watch?v=ajLdwiF7dG4
 Magnitude Comparator

The magnitude comparator can also be used to indicate equality, but has a further two outputs,
one that is logic 1 when word A is greater than word B, and another that is logic 1 when word
A is less than word B. Magnitude comparators therefore form the basis of decision making in
logic circuits. Any logical problem can be reduced to one or more (sometimes many) yes/no
decisions based on a pair of compared values.

A simple 1-bit magnitude comparator is shown in Figure Gate 1 produces the function A>B
and gate 3 gives A<B while gate 2 is an XNOR gate giving an equality output.
This basic circuit for a magnitude comparator may be extended for any number of bits but the
more bits the circuit has to compare, the more complex the circuit becomes.

Integrated circuit magnitude comparators are available that can be used to provide
comparisons between multi-bit words. One such IC is the 74HC85 CMOS 4-bit magnitude
comparator from Philips Semiconductors (NXP) shown in Fig 4.3.3. This IC compares two 4-
bit words and provides an output on pins 5, 6 and 7 that indicate whether the input words are
equal, or if not, whether A or B has the higher numerical value.
4 Bit Comparator - Part 1- Easy to Understand

https://www.youtube.com/watch?v=ajLdwiF7dG4
Binary Comparators
Binary Comparators
Binary Comparators
Binary Comparators
Multiplexers and decoders are used when many lines of information are
being gated and passed from one part of a circuit to another.
A multiplexer (MUX), also known as a data selector, is a combinational
network containing up to 2n data inputs, n control inputs, and an output
(see Figure 4.27). The MUX allows one of the 2n to be selected as the
output. The control lines are used to make this selection. A MUX with 2n
input lines and n selection lines (referred to as a 1-of-2n MUX) may be
wired to realize any Boolean function of n+1 variables.
 https://www.youtube.com/watch?v=FKvnmxte98A

4X1 Multiplexer

https://www.youtube.com/watch?v=g1Lfz1XgrH8

8X1 Multiplexer
https://www.youtube.com/watch?v=b0z7YKKCCyY
Multiplexing is when multiple data signals share a common propagation
path. Time multiplexing is when different signals travel along the same
wire but at different times. These devices have data and address lines, and
usually include an enable/disable input. When the device is disabled the
output is locked into some particular state and is not affected by the inputs.

Figure 4.28 shows the gate arrangement for the multiplexer in Figure 4.27.
Multiplexers provide the designer with numerous choices without the
need for minimizing logic for a particular application. They are also quite
fast in operation, but are more expensive than basic logic gates.
 Time-Division Multiplexing (TDM)
In frequency division multiplexing, all signals operate at the same time with
different frequencies, but in Time-division multiplexing all signals operate with
same frequency at different times. This is a base band transmission system, where
an electronic commutator sequentially samples all data source and combines them
to form a composite base band signal, which travels through the media and is
being demultiplexed into appropriate independent message signals by the
corresponding commutator at the receiving end. The incoming data from each
source are briefly buffered. Each buffer is typically one bit or one character in
length. The buffers are scanned sequentially to form a composite data stream. The
scan operation is sufficiently rapid so that each buffer is emptied before more data
can arrive. Composite data rate must be at least equal to the sum of the individual
data rates. The composite signal can be transmitted directly or through a modem.
The multiplexing operation is shown in Fig. 2.7.7
As shown in the Fig 2.7.7 the composite signal has some dead space between the
successive sampled pulses, which is essential to prevent interchannel cross talks. Along
with the sampled pulses, one synchronizing pulse is sent in each cycle. These data
pulses along with the control information form a frame. Each of these frames contain a
cycle of time slots and in each frame, one or more slots are dedicated to each data
source. The maximum bandwidth (data rate) of a TDM system should be at least
equal to the same data rate of the sources.
Synchronous TDM is called synchronous mainly because each
time slot is preassigned to a fixed source. The time slots are
transmitted irrespective of whether the sources have any data to
send or not. Hence, for the sake of simplicity of implementation,
channel capacity is wasted. Although fixed assignment is used
TDM, devices can handle sources of different data rates. This is
done by assigning fewer slots per cycle to the slower input devices
than the faster devices. Both multiplexing and demultiplexing
operation for synchronous TDM are shown in Fig. 2.7.8.