Slow Learner Assignment (CAT 1)

1. a. Simplify the following expression using Boolean Algebra 𝐹 = 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑏𝑒𝑓 + 𝑐𝑑𝑒𝑔+ 𝑎𝑑𝑒𝑓.

1. b. Consider the Boolean function, 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = 𝑤𝑦 + 𝑥𝑦 + 𝑤 ′𝑥𝑦𝑧 + 𝑤 ′𝑥 ′𝑦 + 𝑥𝑧 + 𝑥 ′𝑦 ′ 𝑧 ′ . Simplify

using K-map and identify the complete set of essential prime implicants?

1. c. Simplify the following Boolean expression using Boolean algebra. 𝐴 ′𝐵(𝐷 ′ + 𝐶 ′𝐷) + 𝐵(𝐴 + 𝐴 ′𝐶𝐷) (to
one literal)

2. a. Simplify each of the following expressions using consensus theorem

𝐹 = (A + B + E ) (E + F + G) (A + B + F +G).

2. b. Convert the given expression in SOP and POS canonical form 𝐹(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵)(𝐵 + 𝐶)(𝐴 + 𝐶)

2. c. Simplify the following using K-Map and draw the logic diagram using only NAND gates.
F(a,b,c,d) =𝑎𝑐 ′𝑑 ′ + 𝑎 ′ 𝑐 + 𝑎𝑏𝑐 + 𝑎𝑏 ′ 𝑐 + 𝑎 ′ 𝑐 ′𝑑 ′.

3. Minimize the Boolean function F(A,B,C,D) = Σm(0,1,3,5,8,11)+ Σdm (2,7,10,15) using K map in both SOP
as well as POS forms and implement using only NAND gates.

4. a. Find the result of the following expression X = 4’b1010; Y = 4’b1101; Z = 4’b10x1

a) ~X
b) X ^ Y
c) (X ^ ~ Y) && Z
d) X<< 2
e) {2{Y}}

4. b. Write the expansion results (y) for the given formats.

//let x = 4'b1010 y =&x
//let x = 4’b1010, z = 4’b0000 y= x | z
// let x = 4’b1100 y = x << 2
//let a = 1’b1, b = 2’b00, c = 2’b10, d = 3’b110 y = {a, b, c, d, 3’b001}
//let a = 1’b1, b = 2’b00, c = 2’b10, d = 3’b110 y = { 4{a}, 2{b}, c }

5. a. A switching circuit has two control inputs (A & B), two data inputs (C & D), and one output (Z). The
circuit performs one of the logic operations on the two data inputs. The function performed depends on
the control inputs:

i. Derive a truth table for Z.

ii. Use a Karnaugh map to find a minimum AND - OR gate circuit to realize Z.

5. b. Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When
the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is
4, 5, 6, or 7, the binary output is one less than the input. Write the Verilog code using data flow modelling
for the designed circuit.
6. a. For the given logic circuit,

(a) Write gate-level verilog code for 'ha' module

(b) Write data flow verilog code for 'hb' module
(c) Write structural level verilog code for 'Main' module by instantiating 'ha' and 'hb' module.

6. b. Write Verilog code for the following logic diagram shown in Figure. Consider A as addend and B as
augend.

7. a. Design a half subtractor using 2:4 Decoder and a OR gate

7. b. Implement the following multiple output Boolean functions F1(A,B,C)=Σm(0,4,7)+ Σdm(2,3),

F2(A,B,C)= Σm(1,5,6) and F3(A,B,C)= Σm(0,2,4,6) with suitable decoder and external gates.