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Transaction Layer
Outline
PCIe Basic
◦ Topology
◦ Configuration Header
◦ Enumeration
Transaction Layer
◦ Transaction Layer Packet(TLP)
◦ TLP Header
◦ TLP Type
◦ Flow control
◦ Virtual channel / Traffic class
◦ Ordering
PCIe Basic
◦ Topology
◦ Configuration space
◦ Enumeration
Topology
PCIe interfaces connected by a Link.
◦ Link : A point-to-point connection. Only two interfaces
can be connected on link, and no loop.
Component:
◦ Root Complex
◦ Switch
◦ Bridge
◦ EndPoint
Root Complex
Interface between CPU/PCIE bus/Memory
Requester/Completer
◦ Requester : initiates requests
◦ Completer: Services requests
Configuration Header-1
There are registers in devices or bridges
that stores information or status of
devices.
Physical Layer
◦ The spec divides the Physical Layer discussion into two
portions:
◦ logical part : 8b/10 encode, scrambling, serializing…etc.
◦ electrical part : Driving differential signal
Transaction Layer Packet(TLP)-1
Transaction Layer Packet(TLP)-2
Types of requests
◦ Indicates the types of requests from requester.
ex. An endpoint wants to write memory, raises
and memory write request.
Routing
◦ Indicates the target of requests. Includes where the TLP
should be delivered.
Ordering
◦ When multiple requests reached a switch. Decide witch
one should pass first.
TLP Header
Format (Fmt)
Type
Traffic Class(TC)
2 or 3DW Could be changed
Attribute(Attr)
Lightweight Notification(LN)
TLP Hint(TH)
TLP Digest(TD)
Poisoned Data(EP)
Address Type(AT)
Length
TLP Header – Format & Type
Fmt & Type field represents the basic of this TLP.
TLP Header has two types, 3DW, 4DW or w/ prefix.
Fmt[2:0]: T T L
◦ Fmt[2] : If set, TLP w/ prefix. 9 8 N
Type[5:0]
◦ Field is encoded for type of TLP from TLP initiator. Ex. Read memory, write
configuration etc.
TLP Types-1
MRd
MWr
Memory
TLP types can be sorted roughly by 5 categories MrdLk
◦ IO Read/Write AtomicOps
◦ Read/Write data from/to an Legacy EP.
IORd
◦ Memory Read/Write Read/Write IO
◦ Read/Write data from/to main memory.
IOWr
CfgRd0
◦ Configuration Read/Write Type0
◦ Read/Write configuration register of Eps. CfgWr0
◦ Type0 for EPs, Type1 for bridge Configuration
CfgRd1
Type1
◦ Message CfgWr1
◦ RC uses Message TLP to control or read status of EP/Switch.
◦ This TLP type takes place of sideband signals of Legacy bus.
Msg
Message
MsgD
◦ Completion
◦ Indicate the TLP is serving the requester’s TLP. Cpl
Completion
CplD
TLP Types-2
4DW or 3DW
With data?
AtomicOPs
Implicit routing
◦ Message
Address Routing
Address routing used for
◦ IO
◦ Memory
With TH set
Attribute Field
Attr[2] : ID-Based Ordering
Attr[1] : Relaxed Ordering
Attr[0] : No Snoop
A
T T L AR
R
9 8
r N rr
TAG
To represents a no data payload TLP,
length field need to cooperate with DW
BE field.
TLP Header – DW BE
DW Byte Enable is 8-bit field.
TAG
10b : Address is translated into physical address.
Tag
Tag generated by Requester, and it must be
unique for all outstanding Requests that require a
Completion for that Requester.
T T L
Tag and Requester ID consist Transaction ID. 9 8 N
TAG
Transaction ID
IO request
IO Requests is made for Legacy devices.
TLP type filed 00010b = IO request.
Fmt[2] indicates the TLP if w/ data.
IO request is always 3DW.
IO request’s TC is always 000b.
Length for IO request always 1DW.
Last DW BE must be all 0.
Memory Request
Type can be:
◦ 00000b : Memory Read/Write
◦ 00001b : Memory Read Locked
Three categories :
◦ Posted Transactions
◦ Non-Posted Transactions
◦ Completions
Responsibility
◦ Devices Report Available Buffer Space
◦ Receivers Register Credits
◦ Transmitters Check Credits
Data Link Layer Packet(DLLP)
Byte0[5:4]
◦ 00b : Posted
◦ 01b : Non-posted
◦ 10b : Completion
VC ID
◦ Indicates the VC will be updated
HdrFC field
◦ It’s 8-bit field and support 127 unit as a maximum.
DataFC field
◦ It’s 12-bit field and support 2047 unit as a maximum.
Flow Control-4
Transmitter Elements
◦ Transactions Pending Buffer
◦ Credits Consumed counter
◦ Credit Limit counter
◦ Flow Control Gating Logic
Receiver Elements
◦ Flow Control Buffer
◦ Credit Allocated
◦ Credits Received counter
Counters Roll Over
Virtual Channel
VCs are hardware buffers that act as queues for
outgoing packets.