Naga Nithesh Ghattamaneni

Phone no: 7075555920

Email id: naganithesh4@gmail.com

Professional Summary

 More than 2 Years of experience as VLSI DFT Engineer.

 Working experience in Scan insertion, Pattern generation coverage and simulation.
 Having experience in stuck-at, at-speed pattern generation with compression.
 Simulated the ATPG patterns on different stages of the project.
 Validating vectors through simulations.

Professional Experience

 Worked as DFT Engineer for Chipsil Technologies from Nov , 2020 to present

Skill Sets

 Tools : Mentor – Tessent Shell, FastScan, TestKompress

Cadence – SimVision
 Programming Languages : TCL, Understanding on Verilog.
 Operating Systems : Linux and Windows.

Projects

Project : Rockley photonics client Project Unitah 2.0

Details: : Implementation of SCAN, ATPG
Role : DFT Design Engineer
Ownership:
 ATPG pattern generation with compressed patterns for stuck at fault.
 Worked in improving the coverage aspects.
Responsibilities:
 Scan Insertion & Pattern Generation for block level.
 Coverage Analysis for block level.
 .Pattern simulation and debug.

Project : Rockley photonics client Project Unitah 1.0

Details : Scan Insertion & ATPG pattern generation
Role : DFT Design Engineer
Responsibilities:
• Scan Insertion & ATPG pattern generation and simulation.
Academic Qualifications

 Bachelor of Technology from Mahatma Gandhi Institute of Technology and Engineering in 2019.