Design Methodology for Sigma-Delta Modulators

based on a Genetic Algorithm using

Hybrid Cost Functions
J. L. A. de Melo, B. Nowacki, N. Paulino and J. Goes
UNINOVA/CTS, Departamento de Engenharia Electrotécnica
Faculdade de Ciências e Tecnologia - Universidade Nova de Lisboa
Campus FCT/UNL, 2829-516 Caparica, Portugal
E-mail: research@joaodemelo.com

Abstract—The design of Sigma-Delta modulators (Σ∆Ms) en-
compasses different variables that need to be optimized together
in order to maximize the performance. The design task is even
more complex due to the non-linear behavior of the quantizer.
Typically, a linearized model of the quantizer is used to obtain
linear equations that predict the performance of the modulator,
which may cause significant discrepancies between the predicted
and actual behavior of Σ∆Ms. To better predict the behavior
of a given design solution, we propose a design methodology
for Σ∆Ms based on a genetic algorithm (GA) that uses both
linear equations and simulations: the design solution is evaluated
using the equations and, if the performance is good enough, it
will be evaluated trough simulation. This hybrid cost function
allows to use a GA with a large population and, therefore,
obtains the best possible design solution. The hybrid cost function
takes thermal noise, quantization noise, voltage swing variations
and stability of the modulator into account. Furthermore, it
also selects the design solution that is the most insensitive to
component variations. The design of a continuous-time (CT) and
a discrete-time (DT) Σ∆M are given as proof-of-concept.
I. I NTRODUCTION
Σ∆Ms are very attractive for the design of high resolu-
tion analog-to-digital converters (ADCs) mainly due to their
insensitivity to components variations. This type of ADCs
has a wide range of applications ranging from audio to
communications and, despite their long use, they are still
intensively investigated [1].
The performance of Σ∆Ms can be improved by increas-
ing the order of the modulator, either using a single loop
architecture or using a cascade architecture (MASH). The
last approach usually requires a more stringent performance
from the constituting components (amplifiers), while the first
requires a more complex design procedure, which can become
very challenging, and only the designer’s experience does
not suffice in achieving the optimal design. To solve this
difficult problem, a reliable tool that takes into account several
specifications simultaneously is needed.
Σ∆Ms may be implemented either in CT or DT. One
method to design a CT Σ∆M is based on the equivalent
DT loop filter. Matching the equivalence between the DT
and CT filters, the coefficients of the CT loop filter can
be mathematically obtained [2]. Another method for the de-
sign of the loop filter, direct CT synthesis method, is based
on ordinary loop filters (e.g., Butterworth, Chebyshev, etc.),
which relies on the noise transfer function (NTF) [2]. Since
these methods are focused on filter design, they can not
achieve a direct and efficient design when many specifications
(e.g., thermal noise, output swing, area, etc.) are intended. In
[3], a vertical integrated tool which optimizes the building
blocks using statistical techniques and innovative heuristics is
proposed. Unfortunately, the proof-of-concept is only based
on DT Σ∆Ms and the heuristics demand some designer’s
previous experience. In [4], the authors present a voltage
swing and distortion reduction scheme applied to 2nd order
modulators. Despite being a simple method, the technique does
not consider other specifications and is architecture-dependent.
A robust design for CT Σ∆Ms is investigated in [5], where the
NTF variation is minimized against component mismatches.
Instead of optimizing a given set of specifications over known
architectures, an efficient design may be achieved by exploring
new ones, as presented in [6].
In this paper we present a general design methodology
for Σ∆Ms based on a GA using hybrid cost functions. The
performance of a given Σ∆M can be assessed using equations
derived from its transfer functions (TFs), which are based
on a linearized model of the loop quantizer. However, these
equations are not very accurate at predicting problems such
as instability or distortion in the Σ∆M. An alternative is
to run a simulation of the Σ∆M including the quantizer, in
order to determine its exact behavior. This approach is very
computation intensive and requires a long time. Therefore,
the adopted solution is an hybrid one: first, the performance
of a given Σ∆M is accessed using equations and only if
the performance is acceptable, then an accurate simulation
is executed. Moreover, a given Σ∆M is tested by randomly
changing its component values using the expected tolerance of
the selected technology. This allows to verify if a given design
solution is sensitive to component variations.
II. P ROPOSED D ESIGN M ETHODOLOGY
The proposed design methodology is based on a GA and its
design flow is illustrated in Fig. 1. A conceptually similar idea

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 Spec. &
Design Space Def. Coarse total fitness fT is obtained as the product of N partial fitnesses,
Evaluation
Random Initial fi , each one depending on the i-th specification, si , as follows
Population
Result within N
no
speci?
Y
Classification
(fitness)
fT = fi (si ). (1)
yes i=1
Fine
Sort Evaluation
where the functions fi (si ) may assume two forms, depending
Reproduction
Classification on the desired target: maximize (2) or minimize (3) (e.g.
(Coarse vs Fine)
maximize the SNDR and minimize the area).
no
Last no
Last fi (si ) = 1 − e−wi (si /s̃i ) (2)
Generation? Chromosome?
yes

Values yes fi (si ) = e−wi (si /s̃i ) (3)

Fig. 1. Design flow of the proposed design methodology.
applied to simple analog circuits (e.g., amplifiers and filters)
is presented in [7]. The design flow assumes that a given
Σ∆M architecture and its desired specifications are initially
provided, the Σ∆M is defined by a chromosome containing,
among others, values of the resistors and capacitors used in the
modulator. These values define the design space, which is lim-
ited by the maximum and minimum value that each component
can assume. Initially, a population consisting of N randomly
generated chromosomes is created. Each chromosome (defin-
ing a Σ∆M) is evaluated and its fitness is calculated based on
the desired specifications. The fitness value is used to sort the
chromosomes of the population, and a new population is then
created from the old one. The new chromosomes are created by
randomly selecting two parents from the old population, the
probability of a given chromosome being selected as parent
depends on its rank in the population, the new chromosome
The si and s̃i represent the achieved and desired specification,
respectively. The variable wi is a weight factor used to
prioritize a given partial fitness.
III. C ASE S TUDY I: A 3 RD ORDER 1.5- BIT CT Σ∆M
In this section we present a 3 order 1.5-bit CT Σ∆M rd
with distributed and local resonator feedbacks, shown Fig. 2,
as a case study to highlight the differences between the
conventional and proposed design methods applied to this
architecture. This architecture allows distributing the zeros of
the NTF inside the signal bandwidth. The different coefficients
of this modulator can be calculated using the direct CT
synthesis method where NTF is designed to be a Chebychev
type II filter with a cut-off frequency value that is determined
in order to obtain both a stable circuit and a good SNDR value.


is obtained by randomly combining the chromosomes of both k1  k2 k3 dout ( n )

ADC
k0   
parents and then changing each value by adding a random s  TS s  TS s  TS 1.5-bit
vin ( s )   
value (mutation). This procedure is repeated during a given b1 b2 b3 (a)
yout ( s )
DAC
number of generations. 1.5-bit

C1 Rf 4
In order to evaluate the fitness of each chromosome, it is C2
1

necessary to determine its SNDR and others parameters (e.g., R1 C3 vt vt
R2
R3
output swing, area, etc.). The existence of the quantizer in the vin ( s ) Amp1
Amp 2 1.5-bit
Latched
dout ( n )
modulator complicates this task. Using a linearized model it Amp3
Rf 1

Comparator
Rf 2

vout ( s )
Rf 3

& Logic
is possible to obtain relatively simple equations that allow to yout ( s )

predict the SNDR of the modulator, however, these equations (b)

can introduce significant errors, especially in the case of large  vref  vref
input signals. In the case of modulators with orders larger than  vref  vref

two it is also very difficult to predict if the modulator is stable.

By simulating a behavior model of the modulator that includes Fig. 2. Block diagram (a) and electrical schematic (b) of the 3rd order 1.5-bit
CT Σ∆M with distributed and local resonator feedbacks.
the non-linear quantizer it is possible to obtain a much more
reliable prediction of the SNDR value, however the simulation
time is very long and would result in an unacceptable long A. Proposed Design Method
optimization time. The adopted solution first performs a coarse
The considered design specifications are thermal and quan-
evaluation, where equations are used to predict the SNDR
tization noises, total harmonic distortion (THD), output swing
value and the potential instability of the Σ∆M. This produces
(OS) of the stages, area, and components variations. The
a coarse fitness value and, if this value is larger than a
quantization noise power is calculated using:
certain value, the Σ∆M undergoes a fine evaluation using
2∆2
Z Bw
simulation, to obtain better SNDR and stability estimations. PQ = |NTF(f )|2 df (4)
The fitness value of the chromosomes that undergoes the fine 12fS 0

evaluation is by design always larger than the fitness value The total thermal noise power, PRT , is defined as the sum of
of the chromosomes that only undergo coarse evaluation. The K partial thermal noise powers, PRi , due to the i-th resistor,

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 140 140

Ri , as follows: 120 2% instable cases 120 1.6% instable cases

K (not showed)
X (not showed)

Number of occurrences
PRT = PRi (5)

Number of occurrences
100 100

i=1 80 80

4kT
Z Bw 60 60
PRi = |HRi (f )|2 df (6)
Ri 0 40 40

20 20
where HRi (f ) represents the thermal NTF from the i-th
0 0
resistor to the modulator’s output. The area of the circuit 88 90 92 94
SNDR [dB]
96 98 92 93 94 95 96 97
SNDR [dB]
98 99 100 101

is determined only considering the area densities of the (a) (b)

capacitors and resistors for the selected technology. Firstly, Fig. 4. Histogram of the SNDR obtained through 500 cases MC analysis
a coarse pre-selection is done based on the NTF and the (high-level model). Direct CT synthesis method (a) and proposed method (b).
Jury-Lee’s criterion in order to choose the potentially better 3500 4000 8
x 10
4

OS11 OS21
chromosomes. Next, based on the previous pre-selection, all 3000 OS12
3500
OS22 7
OS3
OS32
1

specifications are evaluated with the following total fitness 3000 6

Number of occurrences
2500
2500 5
function 2000
2000 4
1500
1500 3
fT = f1 (SNDRQ )·f2 (SNRT )·f3 (OS1 )·f4 (OS2 )·f5 (OS3 )·f6 (A) (7) 1000
1000 2
500 500 1
where f1 and f2 follows the form of (2) and fi for i = 0 0 0
-1 -0.5 0 0.5 1 -1.5 -1 -0.5 0 0.5 1 1.5 -2 -1 0 1 2
3, 4, 5, 6, assume the form of (3). The partial fitness f1 is OS1 [V] OS2 [V] OS3 [V]

(a) (b) (c)

evaluated based on simulations and SNDRQ represents the
signal-to-noise (only due to quantization noise) and distortion Fig. 5. Histogram of the OS of the 1st (a), 2nd (b) and 3rd (c) integrator, for
the Direct CT synthesis method (OSx1 ) and the proposed method (OSx2 ).
ratio. In f2 , the SNRT means the signal-to-noise (only due
to thermal noise) ratio calculated based on (5). Each fi for TABLE I
PASSIVE COMPONENT VALUES AND SPECIFICATIONS OBTAINED .
i = 3, 4, 5, represents the evaluation of the OS of the stages
Parameter R1 R2 R3 Rf 1 Rf 2
and, finally, f6 as the area partial fitness. In order to take the Values1 259kΩ 16.7kΩ 16.7kΩ 92.6kΩ 26.3kΩ
components variations into account, a few Monte Carlo (MC) Values2 116kΩ 80.5kΩ 49.2kΩ 36.1kΩ 84.5kΩ
cases are run for each chromosome and the total fitness is Parameter Rf 3 Rf 4 C1 C2 C3
Values1 14.8kΩ 6.95MΩ 30.0pF 30.0pF 30.0pF
updated based on the average of the resulting fitnesses. Values2 88.3kΩ 6.54MΩ 34.4pF 19.8pF 18.7pF
B. Simulations Results Specif. SNDR OS1max OS2max OS3max area [mm2 ]
Values1 93.2dB 0.54V 1.33V 1.71V 0.0976
Values2 96.3dB 0.81V 0.55V 0.35V 0.0801
0
SNDR = 93.2 dB
-20 f S  2 MHz 1
SNDR2 = 96.3 dB
-40 f in  1.98 kHz IV. C ASE S TUDY II: A 3 RD ORDER S WITCH C APACITOR
-60
Ain  0 dBV (SC) Σ∆M USING ULTRA INCOMPLETE SETTLING (UIS)
Magnitude [dB]

BW  18 kHz
-80
If a SC circuit is operating in the UIS condition (Ts 
-100

-120
-140
-160
-180
1 2 3 4
10 10 10 10
Frequency [Hz]
Fig. 3. Output spectrum of the 3rd order 1.5-bit CT Σ∆M (215 points FFT
using a Blackman-Harris window).
Fig. 3 shows the simulated (electrical transient-noise sim-
ulation) output spectrum of the 3rd order 1.5-bit CT Σ∆M
designed with the direct CT synthesis method (SNDR1 ) and
with the proposed method (SNDR2 ). The modulator (Fig. 2(b))
was simulated using a single pole model for the amplifiers and
ideal logic. The amplifiers have a DC gain of 60 dB, a GBW
of 30 MHz and slew rate of 10 V/µs. Fig. 4 depicts MC
analyses for both designs for process component variations of
3σR = 15% and 3σC = 15% (Gaussian distributions). Fig. 5
shows the OS ranges of the integrators. Table I summarizes
the passive component and specifications obtained, with the
direct CT synthesis method (Values1 ) and the proposed method
(Values2 ), showing that the proposed achieves better SNDR,
area, and good OSs for a 0.13µm 1.2 V CMOS technology.
Ron · C), it can behave as a passive DT integrator with losses
(passive DT 1st order filter) [8], whose TF is equal to
H(z) = (vout (z))/(vin (z)) = (α · z −1/2 )/(1 − β · z −1 ) (8)
5 6
10 10
where α = Ts /(Ron ·C) and β = 1−α. A 3rd order SC Σ∆M
can be built using three of these integrators as shown in Fig. 6.
The output amplitude of each integrator is necessarily small
(due to α  1). In order to avoid charge redistribution between
contiguous integrators two gain stages are used (G2 and G3 :
ideal representation of a differential pair circuit loaded by
resistors R2 and R3 respectively). Furthermore the comparator
amplifies the small amplitude signal at the output of the third
integrator into a digital level (1.1 V or 0 V) producing the
output bit stream b. The circuit from Fig. 6(b) was used to
prove the proposed design methodology, where all its elements
are ideal.
A. Proposed Design Method
Although the presented Σ∆M is a DT circuit, its perfor-
mance is affected by similar factors as CT modulator, such
as jitter noise or mismatch of R and C elements. Refer-
ring to Fig. 1 the specification contains sampling frequency

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 ETNSH ETN1 ETN2 ETN3 Ecomp Equant TABLE II
1 1  z
1
2 2 z
1
2 3  z
1
2 PASSIVE COMPONENT VALUES AND GAIN COEFFICIENTS .
+ z 2 + G2 + G3 + + Gcomp +
Vin - 1  1  z 1 - 1   2  z 1 - 1   3  z 1 b
Parameter R1 R2 R3 C1 C2 C3
1 1
Gb1 Gb2 z 1 Gb3 Values 30kΩ 44kΩ 103kΩ 5.19pF 3.94pF 7.94pF
(a) z 2 z 2

Parameter CSH G1 G2 Gb1 Gb2 Gb3

S/H 1st Integr. Buffer + 2nd Integr. Buffer + 3rd Integr. Values 7pF 7.8 9.8 0.4 0.3 0.4
F1 F2 R1 F1 R2 F1 F2 R3 F2
SET b 0 100
Gcomp D Q SNDR = 75 dB
Vin 90
+ + + + -20
CSH VC1 C1 VC2 C2 VC3 C3 80
VSH b
Q
- gm1.VC1 - gm2.VC2 - F2 CLR

Number of occurrences
- 70
DFF -40

Magnitude [dB]
60
b.F2 F1 b.F2 b.F1 F2 b.F1 b.F2 F1 b.F2 -60 50
(b) -Vref1 Vref1 -Vref2 Vref2 -Vref3 Vref3 40
-80
30
Fig. 6. Block diagram (a) and a simplified single-ended version of the Σ∆M -100
20
circuit (b). 10

fS = 100 MHz, modulator bandwidth BW = 700 kHz
and desired value of SNDR (which defines fitness fT ), and
design space definition consists of maximum and minimum
components values. Each chromosome (containing parameters
from TABLE II) undergoes a classification process. Its first
stage is a coarse evaluation in which stability condition (based
on position of roots within unit circle) is checked and SNDR
is calculated, with use of following noise powers: PQ -
quantization (represented in Fig. 6(a) as Equant ), PT herm -
thermal (represented in Fig. 6(a) as ET N 1 , ET N 2 and ET N 3 )
and PComp - comparator (Ecomp ). The PQ is given by (4),
PT herm is given by (9) (derived in [8]) and PComp by (10)
2kT
Z Bw
PT hermi =
Ci αi fS
2(σcomp )2
PComp =
fS
in which noise value, σcomp was obtained from electrical
transient-noise simulation of a real comparator circuit [8].
Next, the value of SNDR is used to obtain fT , which is
calculated from (2). When the modulator is considered stable
and resulting fT is sufficiently good (previously defined value)
the fine evaluation is performed. In this case chromosome is
evaluated by a DT behavioral model of Σ∆M. Using this
model the modulator simulation is performed a few times
with randomly changed parameters of chromosome (using a
Gaussian variable with a 3σ value of 15% for Ri and Ci and
4% for Gi ). Then, average SNDR and final fT are calculated.
B. Simulation Results
The optimized modulator design parameters are summarized
in TABLE II. An electrical transient-noise simulation shows
that the obtained Σ∆M circuit achieves a peak SNDR of
75 dB, a peak SNR of 76.5 dB (for BW = 700 kHz). The
FFT of the output signal of the Σ∆M for an input signal with
differential amplitude of 300 mV is shown in Fig. 7(a). A
MC analysis was performed on the optimized Σ∆M in order
to determine the sensitivity of the Σ∆M to the variation of
its coefficients with process (3σ value of 15% for Ri and
Ci and 4% for Gi ). Fig. 7(b) depicts histogram showing the
distribution of the SNDR. One can notice that in all of the
cases SNDR is larger than 74.5 dB.
-120 0
10
4
10
5
10
6
10
7 74.5 75 75.5 76 76.5 77 77.5 78
SNDR [dB]
Frequency [Hz]
(a) (b)
Fig. 7. Output spectrum of the 3rd order DT Σ∆M (79 kHz input signal),
THD (7 harm.) = −80.3 dB (214 points FFT using a Hann window) (a).
Histogram of the SNDR (500 cases MC analysis using high-level model) (b).
V. C ONCLUSION
A design methodology for Σ∆Ms based on a GA using
hybrid cost functions was proposed. In order to obtain more
accurate and fast predictions of the performance of a Σ∆M,
the evaluation is divided into a coarse (fast) and fine (slow)
evaluation, and only the Σ∆M that achieves good coarse
performance undergoes the fine evaluation, which is simulation
based. The use of hybrid cost functions decreased the com-
|NTFT hermi (f )|2 df (9)
0 putation time about 15% for the CT Σ∆M and about 35%
Z Bw for the DT design. This difference (between CT and DT time
|NTFComp (f )|2 df (10) improvement) occurs because in the case of the DT Σ∆M the
0
stability of the modulator is better predicted using equations.
ACKNOWLEDGMENT
This work was supported by the Portuguese Foundation for Science
and Technology (CTS multiannual funding) through the PIDDAC Program
funds, project IMPACT (PTDC/EEA-ELC/101421/2008) and Ph.D. Grants
(SFRH/BD/72362/2010 and SFRH/BD/71313/2010).
R EFERENCES
[1] J. de la Rosa, “Sigma-delta modulators: Tutorial overview, design guide,
and state-of-the-art survey,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 58, pp. 1–21, Jan. 2011.
[2] R. W. Adams and R. Schreier, “Stability theory for Σ∆ modulators,”
in Delta-Sigma Data Converters Theory, Design and Simulation, S. R.
Norsworthy, R. Schreier, and G. C. Temes, Eds. New York: IEEE Press.,
1996, ch. 4, pp. 141–164.
[3] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, and J. Huertas, “A
vertically integrated tool for automated design of ∆Σ modulators,” IEEE
J. Solid-State Circuits, vol. 30, pp. 762–772, Jul. 1995.
[4] W. M. Koe and F. Maloberti, “Feed-forward path and gain-scaling -
a swing and distortion reduction scheme for second order sigma-delta
modulator,” in Proc. IEEE Int. Symp. Circuits Systems (ISCAS’04), May
2004, pp. 413–16.
[5] B. De Vuyst, P. Rombouts, J. De Maeyer, and G. Gielen, “The nyquist
criterion: A useful tool for the robust design of continuous-time Σ∆
modulators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 416–
420, Jun. 2010.
[6] H. Tang and A. Doboli, “High-level synthesis of ∆Σ; modulator topolo-
gies optimized for complexity, sensitivity, and power consumption,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, pp. 597–607,
Mar. 2006.
[7] N. Paulino, J. Goes, and A. Steiger-Garcao, “Design methodology for
optimization of analog building blocks using genetic algorithms,” in Proc.
IEEE Int. Symp. Circuits Systems (ISCAS’01), May 2001, pp. 435–438.
[8] B. Nowacki, N. Paulino, and J. Goes, “A 1.2 V 300 µW second-order
switched-capacitor ∆Σ modulator using ultra incomplete settling with 73
dB SNDR and 300 kHz BW in 130 nm CMOS,” in ESSCIRC’11, Sep.
2011, pp. 271–274.

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