Experiment No.

: 02

Name of The Experiment: Introduction to Programmable Logic Controller and

design different logic gate using PLC.

Objectives:
 To get introduced to PLC.
 To learn about ladder diagram.
 To learn how to design a ladder diagram using PLC software (LOGO).
 To make logic gates using PLC.
 To make counter using PLC.
 To make Timer using PLC.

Theory:
PLC stands for Programmable Logic Controller. A programmable logic
controller (PLC) is an industrial solid-state computer that monitors inputs and
outputs and makes logic-based decisions for automated processes or machines. It
was introduced to eliminate issues such as high-power consumption that arose
from the use of relays to control manufacturing processes.

The programmable logic controller receives information from connected

input devices and sensors, processes the received data, and triggers required
outputs as per its pre-programmed parameters. Based on its inputs and outputs, a
PLC can easily monitor and record runtime data like operating temperature,
machine productivity, generation of alarms when a machine fails, automatic start
and stop processes and more. This means that PLCs are robust and flexible
manufacturing process control solutions that are adaptable to most applications.

PLC consists of a programmed microprocessor whose program is written on

a computer and later downloaded via a cable to the PLC. The program is stored in
a non-volatile PLC memory. Most PLCs today use one of the following 5
programming languages: Ladder Diagram, Structured Text, Function Block
Diagram, Instruction List, or Sequential Function Charts. Ladder Diagram is the
most common one. In it, symbols represent opening and closing relays, counters,
timers, shift registers, and mathematical operations. The symbols are arranged into
the desired program routine. Rules in ladder logic are termed “rungs.” Each rung
has a single output, but a single input can be found in more than one rung. The
programming can be done using programming software. In this experiment we will
be using WPLSOFT for our logic gate design.
 In this experiment, we will be designing 3 types of logic gates and TIMER &
COUNTER circuits using WPLSOFT software.

OR Gate:
The output of an OR Gate only returns “LOW” when all of its inputs are at a
logic level “0”. In other words, any “HIGH” input will give a “HIGH”, logic level
“1” output.

Truth Table

Input 1 Input 2 Output

0 0 0
0 1 1
1 0 1
1 1 1

Circuit Diagram

When Input 1 = “0”, Input 2 = “0” and Output = “0”

When Input 1 = “0”, Input 2 = “1” and Output = “1”

When Input 1 = “1”, Input 2 = “0” and Output = “1”

When Input 1 = “1”, Input 2 = “1” and Output = “1”

AND Gate:
The output state of AND Gate only returns “LOW” when any of its inputs are
at a logic level “0”. In other words, any “LOW” input will give a “LOW” output.

Truth Table

Input 1 Input 2 Output

0 0 0
0 1 0
1 0 0
1 1 1

Circuit Diagram

When Input 1 = “0”, Input 2 = “0” and Output = “0”

When Input 1 = “0”, Input 2 = “1” and Output = “0”

When Input 1 = “1”, Input 2 = “0” and Output = “0”

When Input 1 = “1”, Input 2 = “1” and Output = “1”

NOT Gate:
NOT Gates are single input devices which have an output of logic level “1”
when input is logic level “0” and output of logic level “0” when input is logic level
“1”. In other words, it inverts the input signal.

Truth Table

Input Output
0 1
1 0

Circuit Diagram

When Input = “0” and Output = “1”

 When Input = “1” and Output = “0”

PLC Counter:
A PLC Counter is a function in PLC programming that is used to measure things
like how many times an event has happened in a process or how many times a product
has been produced.

Siemens PLC Counter Block:

In Siemens PLC we have three types of counter functions,

 Up Counter
 Down Counter
 Up and Down Counter
These are the blocks that are used as a counter in PLC ladder logic. All counter blocks have some
inputs and some outputs.

Inputs,

 CU – Count Up Input
 CD – Count Down Input
 S – Set Input for presetting counter
 PV – Value for presetting counter
 R – Reset Input

Outputs,

 Q – Status of Counter
 CV – Current counter value
 CV_BCD – Current counter value in BCD coded

Up Counter(S_CU):

For each pulse at Count Up(CU) bit, the current Counter Value(CV) will be increased by 1. When
there is a pulse at Set input(S), it will set Presetting Value(PV) at the current Counter Value(CV).

When there is a pulse at Reset input(R), the counter block will get reset and the current counter value
is set at 0 again.

Down Counter(S_CD):

For each pulse at Count Down(CD) bit, the current Counter Value(CV) will be decreased by 1. When
there is a pulse at Set input(S), it will set Presetting Value(PV) at the current Counter Value(CV).
When there is a pulse at Reset input(R), the counter block will get reset and the current counter value
is set at 0 again.

Up Down Counter(S_CUD):

At each pulse at Count Up(CU) bit, it will increase the current Counter Value(CV), and each pulse at
Count Down(CD) bit, will decrease the current Counter Value(CV).

When there is a pulse at the Set input(S), it will set Presetting Value(PV) at the current Counter
Value(CV).

When there is a pulse at Reset input(R), the counter block will get reset and the current Counter value
is set at 0 again.

Circuit For UP Counter:

Initial State:

Count Done:

PLC Timer:
Timer plays a significant role to control the operation for a specific period of time. As a very basic
example, we require a timer to control the transition from star to delta function in a star-delt electrical
motor starter.

There are lots of applications where timers are used in PLC programming.

Siemens PLC Timer Block

These are the blocks used as a timer in Siemens PLC ladder logic.

Each timer block has bits like S, R, Q and words like TV, BI, and BCD.

S ⇒ Set bit to trigger the timer block

R ⇒ Reset bit to reset the timer block.

Q ⇒ Status bit of a Timer block.

TV ⇒ Preset Time Value of Timer block.

BI ⇒ Remaining Time Value in an Integer format.

BCD ⇒ Remaining Time Value in BCD format.

Allen Bradley PLC Timer Block

These are the blocks uses as a Timer block in Allen Bradley PLC.

 
Each timer block has EN, DN, and TT bits.

Simulation of Timer Circuit:

Initial state:

Final State:

Discussion and Conclusion:

From this experiment, we got a crystal-clear idea about programming PLC using ladder diagram.
Here we designed three types of logic gates using WPLSOFT software. Also, we designed the
counter and timer. PLC Counter is a function in PLC programming that is used to measure things
and Timer plays a significant role to control the operation for a specific period of time. All the
outputs were same as shown in the truth tables and no error was found. The software was easy to
use. No bugs were found and no crashes occurred while simulation