Professional Documents
Culture Documents
Digital Electronics
Analysis and Synthesis
Rajat Chakraborty
Lecturer
Dept. of EEE, BUET
Analysis
❖ Analysis - To determine the function performed by an existing network
Given
Network
Synthesis
❖ Synthesis - To design a new network that implements a desired functional behaviour
Find
Network
Analysis Technique
Truth Table
Input Node Output
❖ LSB (𝑥2 ) changes (oscillates between 0 and 1) the most while MSB (𝑥1 ) changes
the least
❖ Total number of inputs = 2𝑛 where n= number of input bits
❖ Show the intermediate nodes
Timing Diagram
❖ LSB (𝑥2 ) changes the most (time period small) while MSB (𝑥1 ) changes the least
(time period large)
❖ Use 2X time period for every next bit from LSB
❖ Show the intermediate nodes
XOR Gate
Circuit Symbol
𝐿 = 𝑥𝑦ത + 𝑥𝑦
ҧ
Truth Table
Basic Gate Implementation
❖ If both inputs are same output is 0, if the inputs are different output is 1
❖ Symbol - ⊕ , ^
𝐿 =𝑥⊕𝑦
Circuit Symbol
Truth Table
❖ If both inputs are same output is 1, if the inputs are different output is 0
Steps:
➢ Form a truth table (make sure you have given all the inputs)
❖ 𝑠2 = 𝑋𝑂𝑅 → Output is 0 when both inputs are same, output is 1 when inputs differ
More on XOR
Modulo 2 addition
❖ For many input XOR gate consider it as a modulo 2 addition
Example:
𝐹𝑖𝑣𝑒 𝑖𝑛𝑝𝑢𝑡 𝑥𝑜𝑟: 𝟏 ⊕ 𝟎 ⊕ 𝟏 ⊕ 𝟏 ⊕ 𝟏 =? ? ?
1. 1+ 0 + 1 + 1 + 1 = 4
2. 4 ÷ 2 → Remainder is 0. So the output is 0.
❖ In another way, we can say that if the number of 1 is even the o/p is 0 and if the
number of 1 is odd o/p is 1
Summary