Analog Technologies, Inc.

TECEV103

TEC CONTROLLER EVALUATION KIT TECEV103

(updated 06/17/04)
Our TEC controller modules can be evaluated conveniently by using this evaluation kit TECEV103 which comes with an
evaluation board, TECEVB103 and a TEC controller module of TEC -A1 (there is no internal compensation network in side).
The main purpose of using the evaluation board is to tune the compensation network on the board for match ing the
characteristics of users’ thermal load. The objectives of the tuning are to minimize the response time of the thermal control
loop and the dynamic temperature tracking errors, while keeping the control loop stable.
1. Connection
For For
To power supply multimeter oscilloscope
To A/D, D/A, and/or microprocessor probing probing
5V Imax = 2A To TEC To Thermistor

TECN TECN
+5V GND TEC- TEC+ Rth GND

TECP LEDC TECP

LEDA
TEC
RTH Controller RTH
Temp. good Vlim Power
On On
S3
Off Off
LED
TMPS
TMPS

CMPIN CMPO
Ri

Rp
TMPO
TMPO Cd Ci
Rd

CIRP
CDRD
VDR VDR
3V CLHT

Cd Ci
0 0
TMPGD 4.7uF 330nF 1uF 82nF TMPGD
3.3uF 470nF 820nF 100nF
S1 S2
2.2uF 680nF 680nF 150nF
1.5uF 820nF 470nF 220nF
1uF 330nF

SDNG SDNG
Wi Wd Wp W1 W2 W3
2M 500K 2M 5K 5K 20K

GND GND

Figure 1 TEC Controller Evaluation Board TECEV103

2352 Walsh Ave. Santa Clara, CA 95051. U. S. A. Tel.: (408) 748-9100, Fax: (408) 748-9111 www.analogtechnologies.com

 Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 1
 Analog Technologies, Inc. TECEV103

Figure 2 TECEV103 Photo

Figure 1 shows the layout of the evaluation board and Figure
2 shows its photo.
These are the procedures for the adjustment.
1. Set up basic connections. Connect a 5V DC power
supply and the TEC terminals in the right polarity as
indicated onto the board. Connect the thermistor
terminals to the board, there is no polarity requirement.
Turn the two switches, for Vlim and Power, to the off
positions (down side). Check the evaluation board
connections, making sure that they are all correctly
connected. Turn on the Power side switch and see how
the Controller works.
2. Tune the compensation network. The purpose for this
step is to match the controller compensation network
with the thermal load characteristics thus that the
response time and temperature tracking error are
minimized. Adjust the potentiometer W1 to ch ange

2352 Walsh Ave. Santa Clara, CA 95051. U. S. A. Tel.: (408) 748-9100, Fax: (408) 748-9111 www.analogtechnologies.com

Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 2
 Analog Technologies, Inc. TECEV103

the set -point temperature TMPS just a small amount, frequency goes down. It determines the cut -off
simulating a step function . At the same time, connect frequency be low which the TEC controller will start
an oscilloscope at the VDR test pin (on the right side having a large open loo p gain. The higher the open loop
of the evaluation board), set it to a scrolling mode (0.2 gain, the smaller the tracking error will be.
Second/Division or slower) and monitor the waveform
d. Cd*Ri determines the corner frequency , ω2=1/(Cd*Ri),
of VDR as TMPS is fed by a step function signal . The
where the differential component starts picking up (see
circuit in the compensati on network is shown in
Figure 4), as the frequency goes up.
Figure 3 below.
e. Cd*Rd determines the corner frequency , ω3=1/(Cd*Rd),
Rd Rp where the differential component starts getting flat. It
determines the cut -off frequency above which the TEC
Cf Ci
controller will give extra weight or gain in response.
Cd
Ri f. Cf*Rp determines the corner frequency , ω4=1/(Cf*Rp),
−
where the differential component starts rolling down .
TMPO
Since this frequency is way higher than being needed for
VDR controlling the TEC, ω4 does not need to be tuned. The
TMPS + capacitor is built into the TEC controller module, not
the evaluation board.
Figure 3 Compensation network To start the tuning, turn off the differential circuit by setting
Cd Open. Turn W1 quickly by a small angle, back and forth,
The transfer function of the compensation network, defined approximately 5 seconds per change. Set Ci to 1uF, set Ri to
as H(ω)=VDR(ω)/TMPO(ω), is shown in figure 4. 1M, and increase the rati o of Rp/Ri as much as possible,
provided the loop is stable, i.e. there are no oscillations seen
H(ω )
in VDR. Then, minimize Ci as much as possible, provided
the loop is stable. The next step is to minimize Rd and
Gd maximize Cd while maintaining about 10% overshoot found
in VDR. Optimum result can be obtained after diligent and
0.71Gd
patient tuning. The tuning is fun and important.
1.41Gp When the TEC controller is used for driving a TEC to
Gp stabilize the temperature of a diode laser, there is no need to
turn on the laser diod e while tuning the TEC controller. To
ω1 ω2 ω3 ω4 ω simulate the active thermal load given by the laser diode,
setting the set -point temperature low er than the room
temperature is enough.
Figure 4 Transfer Function of the Compensation Network
For a typical laser head used in EDFA’s or laser transmitters
In principle, these are the impacts of the components to the
(found in DWDM appl ications, for instance), Ri = 1MΩ, Rp
tuning results:
= 1MΩ, Ci = 680nF, Cd = 1.5µF, and Rd = 250kΩ. These
a. Rp/Ri determines the gain for the proportional values may vary, depending on the characteristics of a
component of the feedback signal which is from the particular thermal load.
thermistor, Gp = Rp/Ri, in the control loop, the higher
To be conservative in stability, use larger Ci and larger Ri;
the gain, the smaller the short term error in the target
To have quicker response, use smaller Rd and larger Cd.
temperature (which is of the cold side of the TEC)
compared with the set -point temperature, but the higher The closer to the TEC the thermistor is mounted, the easier
the tendency of the loop’s instability. to have the loop stabilized, the shorter the rise time and the
settling time of the response will be.
b. Rp/Rd determines the gain for the differential
component, Gd = Rp/(Rd//Ri) ≈ Rp/Rd, where symbol 3. After tuning, the values of the capacitors for Cd and Ci
“//” stands for two resistor s in parallel, since Ri >> Rd, can be read off the capacitor selection switches. The
Rd//Ri = Rd. The higher the gain, the shorter the rise values of the resistors, Ri, Rd and Rp, can be measured
time of the response, the more the oversh oot and/or the by an Ohm -meter by connecting to the resistor pins. As
undershoot will be. seen in the photo of Figure 2, Ri can be read off between
TMPO and CMPIN test points; Rd can be read off
c. Ci*Rp determines the corner frequency , ω1= 1/(Ci*Rp),
where the integral component starts picking up, as the

2352 Walsh Ave. Santa Clara, CA 95051. U. S. A. Tel.: (408) 748-9100, Fax: (408) 748-9111 www.analogtechnologies.com

Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 3
 Analog Technologies, Inc. TECEV103

between CMPIN and CDRD test points; Rp can be read f. To control the TEC voltage directly by using a DAC,
off between CMPIN and CIRP test points. connect VDR to the output of the DAC and use this formula:
TEC voltage = 2.5V – VDR (V).
4. After the compensation network is tuned properly, we
can now adjust set -point temperature to see if the TEC g. To shut down the TEC controller by using a
controller can drive the target temperature to a certain microprocessor, turn off the Power switch, connect SDN test
range and with high stability . Turn the temperature set - point (2nd row from the bottom side, on both left and right
point TMPS potentiometer W1 while monitoring its columes.) to one of its digital outputs. When pulling low,
output voltage at TMPS test point (4th row on either left the TEC controller is shut off. When pulling high SDN, the
or right side of the board), watch the LED: when it turns TEC controller is turned on.
to green, the target temperature is locked to the set -point
h. The evaluation schematic is given in Figure 5.
temperature within 0.1 °C or less. The relationship
between the set -point voltage vs. the set -point Using the TEC controller for more applications not
temperature is given in the datasheet. After seeing the described here, and/or having any questions, please free to
LED lock into the set -point temperature, VDR should be contact us.
a const ant voltage as shown in the oscilloscop e and the
voltage between TMPS and TMPO should be very small,
less than 10mV. When a standard TEC controller is
used, the 10mV represent a 0.07° temperature error.
5. Set output voltage limit.
6. To know more parameters of the TEC controller.
a. To know the actual target temperature, use a voltage meter
to measure the voltage between the TMP O and the GND
pins, the reading result is: target temperature = 15 °C +
(TMPO voltage (V))*6.67 °C for approximation (see the
curve in the TEC controller data sheet).
b. To know how hard the TEC is working, measure the
voltage VDR by a voltage meter o r an ADC, TEC voltage =
2.5V – VDR. When the TEC voltage (from the calculation)
is positive, it is in cooling mode; when the TEC voltage is
negative, it is in heating mode. Cool/ Heat Balance CLHT
can be adjusted by W2. TEC maximum voltage can be
reduced by reducing W3, make sure Vlim switch is now
turned to the on position.
c. To try other values of capacitors not provided by the
evaluation board for the capacitors in the compensation
network, turn the capacitor switches you want to try to the
top point, the “0” position, connect the component to the
corresponding soldering pads as marked on the evaluation
board.
d. To shut down the TEC controller, turn the Power switch
to the “Off” position, see Figure 2.
e. To control the set -point temperature directly by using a
DAC, set the set -point temperature POT W1 to the middle
point (25 °C), on which the TMPS is about 1.5V, the half
value of the reference voltage, connect TMPS test point to
the output of the DAC and use this formula for
approximation when the input voltage is between 0V and
3V:
set-point temperature (°C) = 15 °C + (TMP O voltage
(V))*6.67°C. The maximum voltage allowed is Vps (pow er
supply). See the curve in the TEC controller data sheet.

2352 Walsh Ave. Santa Clara, CA 95051. U. S. A. Tel.: (408) 748-9100, Fax: (408) 748-9111 www.analogtechnologies.com

Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 4
 Analog Technologies, Inc. TECEV103

TMPO
1
WI 2M
3 Ri CMPIN WP 2M
3 1
CMPO
Left Side Right Side Top Side

Rp SPL1 THL1 THR1 TT1 SPR1 SPT1

2
RI 1 1 1 1 1 1
1 2 TECN S_Pad TECN TECN TECN TECN S_Pad 5V L_Pad
TEC- TEC- TEC- TEC- TEC- 5V
RP SPL2 THL2 THR2 TT2 SPR2 SPT2
1 2

S1 CD1 330nF CI1

Ci 82nF S2
ST9P
TECP
1
S_Pad TECP
1
TECP
1
TECP
1
TECP
1
S_Pad PGND
1
L_Pad
TEC+ TEC+ TEC+ TEC+ TEC+ 0V
1 2 1 2 1 1
SPL3 THL3 THR3 TT3 SPR3 SPT3
1 1 1 1 1 1
CD2 470nF CI2 100nF RTH S_Pad RTH RTH RTH RTH S_Pad TECN L_Pad
2 2 1 1 2 3 2 1 2 RTH
RTH RTH RTH RTH TEC-
WD 500K SPL4 THL4 THR4 TT4 SPR4 SPT4
CD3 680nF CI3 150nF
1 1 1 1 1 1
3 2 1 2 1 3 TMPS S_Pad TMPS TMPS TMPS TMPS S_Pad TECP L_Pad
TMPS TMPS TMPS TMPS TMPS TEC+
CD4 820nF CI4 220nF
SPL5 THR5 TT5 SPR5 SPT5
4 2 1 2 1 4
1 1 1 1 1
TMPO S_Pad TMPO TMPO TMPO S_Pad RTH S_Pad
CD5 1uF CI5 330nF TMPO
RD TMPO TMPO TMPO RTH-1
5 2 1 1 2 2 1 5
SPL6 THL6 THR6 TT6 SPR6 SPT6
1 1 1 1 1 1
0 CD6 1.5uF CI6 470nF 0 VDR S_Pad VDR VDR VDR VDR S_Pad GND S_Pad
6 1 2 2 1 6 VDR
VDR VDR VDR VDR RTH-2(GND)
SPL7 THL7 THR7 TT7 SPR7
CD7 2.2uF CI7 680nF
1 1 1 1 1
7 1 2 2 1 7 TMPGD S_Pad TMPGD TMPGD TMPGD TMPGD S_Pad
TMPGD TMPGD TMPGD TMPGD TMPGD
CD8 3.3uF CI8 820nF
ST9P SPL8 THL8 THR8 TT8 SPR8
8 1 2 1 2 8
1 1 1 1 1
SDN S_Pad SDN SDN SDN SDN S_Pad
CD9 4.7uF
9 2 1 Rd CI9 1uF
1 2 9
SDN SDN SDN SDN SDN
Cd GND
1
SPL9
S_Pad GND
1
THL9
GND
1
THR9
GND
1
TT9
GND
1
SPR9
S_Pad
10 10 GND GND GND GND GND
CD CI
2 1 1 2
LEDA LEDC 3V CHB LEDA LEDC
Bottom Side

1
1

S_Pad

S_Pad
THM1 THM2 THM3 THM4 THM5 THM6 THM7 THM8 THM9
TMPO CDRD CMPIN CIRP CMPO LEDA LEDC 3V CLHT
SPM1 SPM2
U1 TECA1 LEDA LEDC
1 16
TMPGD TEMPGD VPS 5V 3V 5V CHB W3 S3
5V
20K
2 15 2 3 LEDC LEDA
3V 3V GNDP PGND SDN
3

W1 W2 LED1 R3 1K
3 14 2 2 1 3 1 4
TMPS TEMPSP GNDP TMPS VDR 1 2 1 2
5K 5K N1206-4 5V
4 13
GND TECNEG TECN SML-LX2832SUGC
1

5 12 1 R2 2
1 2 R4 TECEV-103
1

VDR TECCRT TECPOS TECP Q1 1

R1 TMPGD
6 11 100 10K 100K
CMPO VTEC RTH RTH
MMBT6428
2

7 10
2

CMPIN CMIN GND

8 9
TMPO TEMP SDNG SDN

Figure 5 Evaluation Board Schematic

2352 Walsh Ave. Santa Clara, CA 95051. U. S. A. Tel.: (408) 748-9100, Fax: (408) 748-9111 www.analogtechnologies.com

Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 5