2013 International Conference on Advanced Electronic Systems (ICAES)

Design and Implementation of Single Precision

Pipelined Floating Point Co-Processor

Manisha Sangwan A Anita Angeline

PG Student, M.Tech VLSI Design Professor
SENSE, VIT University SENSE, VIT University
Chennai, India - 600048 Chennai, India -600048
manishasangwan47@gmail.com

Abstract—Floating point numbers are used in various Sign Bit: It defines whether the number the number is
applications such as medical imaging, radar, telecommunications
positive or negative. If it is 0 then number is positive else
Etc. This paper deals with the comparison of various arithmetic
modules and the implementation of optimized floating point
negative.
ALU. Here pipelined architecture is used in order to increase the Exponent: Both positive and negative values are
performance and the design is achieved to increase the operating represented by this field. To do this, a bias is added to the
frequency by 1.62 times. The logic is designed using Verilog actual exponent in order to get the stored exponent. [10] For
HDL. Synthesis is done on Encounter by Cadence after timing single precision this value is 127 and for double precision
and logic simulation. this value is 1023.
Mantissa: mantissa bit consists of both implicit leading bit
Keywords—CLA; clock-cycles; GDM; HDL; IEEE 754; and fractional part it is represented in the form of 1.f where 1
pipelining; verilog is implicit and f is fractional part mantissa is also known as
significant.
I. INTRODUCTION
II. IMPLEMENTATION
These days the use of computers has been incorporated in
many applications such as medical imaging, radar, audio A. Adder and Subtractor
system design, signal processors, industrial control,
telecommunications and other applications. There are Algorithm
many key factors that are considered before choosing the
number system. Those preferred factors are computational
capabilities required for the application, processor and system
costs, accuracy, complexity and performance attributes. Over
the years the designers moved from fixed point to floating
point operations due to wide range along with the ability of
floating point numbers to represent a very small number to a
very large number but at the same time accuracy of
floating point numbers is less. So trade off has to be done to
get the optimized architecture.
Almost twenty years ago IEEE 754 standard was
adopted for floating point numbers. This single precision
standard is for 32-bit number and the double precision is for
64- bit number.
The storage layout consists of three components: the sign,
the exponent and mantissa. The mantissa includes implicit
Fig. 1. Block diagram of Floating Point Adder and Subtractor
leading bit and the fractional part.
In adders the propagation of carry from one adder block
TABLE I. FLOATING POINT REPRESENTATION
to another block consumes a lot of time but Carry Look Ahead
Sign Exponent Fractional Bias (CLA) adder save this propagation time by generating and
Single Precision 1[31] 8[30-23] 23[22-00] 127 propagating this carry simultaneously in the consecutive
Double Precision 1[63] 11[62-52] 52[62-52] 1023 blocks. So, for faster operation this carry look ahead adder
is used.

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 2013 International Conference on Advanced Electronic Systems (ICAES)

Fig. 3. Block diagram of Floating Point Division

S[i] = X[i] ْ Y[i] ْ C[i]
For division process Goldsmith (GDM) algorithm is
G[i] = X[i] * Y[i] used. For this algorithm to be applied needs both the inputs to
P[i] = X[i] +Y[i] be normalized first. In this both the multiplication of inputs is
independent of each other, so can be executed in parallel,
C[i+1] = X[i] * Y[i] + X[i] * C[i] + Y[i] * C[i] C[i+1] = G[i] + P[i] *
therefore it will increase the latency.
G[i] + P[i] * P[i-1] * C[i-1]
Algorithm for GDM for Q = A/B using k iterations:
B. Multiplication
Algorithm • B !=0, |e0| < 1
• Initialize N = A, D = B, R = (1-e0) / B
• For I = 0 to k
• N = N*R
• D = D*R
• R=2–D
• End for
• Q=N
Return Q

Fig. 2. Block diagram of Floating Point Multiplier
Multiplication is an important block for ALU. With
high speed and low power multipliers there comes the
complexity so, we need to do the trade off between these
to get the optimized algorithm with the regularity of
layout. There are different algorithms available for
multiplication such as Booth, modified booth, Wallace,
Bough Wooley, Braun multipliers. But issue with multipliers
is speed and regular layout so keeping both the parameters in
mind modified booth algorithm was chosen. It is a powerful
algorithm for signed-number multiplication, which treats both
positive and negative numbers uniformly.
C. Division
Algorithm
D. Pipelining
The speed of execution of any instruction can be varied by
a number of methods like, using a faster circuit technology to
build a processor or to arrange the hardware in such a way so
that multiple operations can be performed at the same
time. [11] By using pipelining multiple operations can be
performed simultaneously without changing the execution
time of an instruction. As shown in example below, in
sequential execution the third instruction will be executed at
sixth clock cycle but in pipelined architecture the same
instruction will be executed at fourth clock cycle and we’ll be
saving two clock cycles at the end where, F is fetching block
and E is execution block. Therefore, as the number of
instruction count will be increasing we’ll be saving more
clock cycles.
1 2 3 4 5 6
F1 E1 F2 E2 F3 E3
|______I1______| |_______I2______| |_______I3______|
Fig. 4. Sequential Execution

Clock Cycles: 0 1 2 3 4
F1 E1
F2 E2
F3 E3
Fig. 5. Pipelined Execution

III. FUNCTIONAL AND TIMING VERIFICATION

The functional verification is done using both Cadence and
Xilinx along with that the arithmetic results are verified
theoretically. Timing analyses, power analyses and area
analyses are done using both Cadence and Xilinx.



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 2013 International Conference on Advanced Electronic Systems (ICAES)

A. Adder and Subtractors

In addition and subtraction, all the sign, exponential and
fractional bits are operated separately and then the
exponents are shifted accordingly to equate the exponents
then this addition operation is done on fractional bits. The
final result is combined to make the output of 32 bits [Fig 6].

Fig. 6. Simulation Waveform for Adder and Subtractor

B. Multiplier
In multiplication block, the exponents are added and the
fractional bits are multiplied according to the algorithm. To Fig. 9. ALU Layout
get the sign of the result, the XOR operation is performed on
both the input sign bits. Finally all the bits are clubbed to get
the final result [Fig 7]. IV. SYNTHESIS RESULT
Synthesis results are shown in the table 2, shown below.

TABLE II. COMPARATIVE ANALYSIS OF BOTH EXISTING AND

PROPOSED DESIGN

Existing Proposed
Leakage power 2.880282 —W 3.50267 —W
Dynamic Power 11.377751 mW 16.14882 mW
Total power 11.380632 mW 16.15232 mW
Gate counts 2881 3712
Fig. 7. Simulation Waveform for Multiplier Frequency 225.65 MHz 367.654 MHz
Critical path 4.43164 nsec 2.70 nsec
C. Division Logic utilization 1% (466/38000) 4%(1780/46560)
The exponents are subtracted and the fractional bits are IOS 44% (130/296) 65% (157/ 240)
multiplied and subtracted according to the GDM algorithm Area 75436 97194
and continues iterations are done to get the closest result, for
sign bit XOR operation is performed on the sign bits of inputs.
This block is most time and area consuming [Fig 8]. V. CONCLUSION
In this paper various arithmetic modules are implemented
and then various comparative analyses are done. Ultimately
these individual blocks are clubbed to make Floating point
based ALU in a pipelined manner to minimize the power and
to increase the operating frequency at the same time. These
comparative analyses are done on cadence and Xilinx both.
Simulation results are verified theoretically. Verilog HDL
(Hardware Description Language) is used to design the whole
ALU block. In existing design, total power is 11.380632 mW
that is 0.70458 times less as compared to the proposed design
Fig. 8. Simulation Waveform for Division but the operating frequency is 1.67 times more than the
existing design. Along with that the gate count is increased
D. ALU Layout and area is also increased because of number of iterations used
In Fig 9, the final layout of the circuit is shown. in the algorithm.



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 2013 International Conference on Advanced Electronic Systems (ICAES)

VI. FUTURE WORK

Optimization of source code to decrease the area and gate
counts will improve the reliability. Low power techniques
could be incorporated to obtain better trade off.
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