Assignment 2

TCS704

GraphicEra Deemed to be University

SEVEN SEMESTER, 2022

Campus: Dehradun

COMPUTER SCIENCE ENGINEERING

Advanced Computer Architecture

(Last Date for submission of this Assignment: 4 November 2022)

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NOTE: Answer All questions.

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1. Explain 3C’s with suitable example.
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2. List and explain advanced optimization of cache performance.

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3. Discuss how process are protected from each other through virtual memory.
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4. Discuss the cross cutting issues in design of memory hierarchy.

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5. What are the major hurdles of pipelining? Illustrate the branch hazards in detail.

6. What are the techniques used to reduce branch costs? Explain both static and dynamic branch prediction
used for same.

7. What are data dependencies? Mention the different types of data dependencies. Explain name depen-
dencies, with example.

8. Explain the states in 2-bit prediction scheme used for dynamic branch prediction.

9. Consider an non-pipelined processor. Assume that it has a 1ns clock cycle and that it uses 4 cycles for
ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of
these operations are 40%, 20%, and 40% respectively. Suppose that due to clock skew and setup, pipelining
the processor adds 0.2 ns of overhead to the clock. Ignoring any latency impact, how much speedup in the
instruction execution rate will we gain from a pipeline?

10. Consider a non pipelined machine with 6 execution stages of lengths 50 ns, 50 ns, 60 ns, 60 ns, 50 ns,
and 50 ns.
(a) Find the instruction latency on this machine.
(b) How much time does it take to execute 100 instructions.