A B C D E

Compal Confidential
Model Name : JM40-HR
File Name : LA-7231P
1 1

2 Compal Confidential 2

JM40-HR M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P-GS/GV-OP
3 3

2010-02-22
REV:1.0
ZZZ
Part Number Description

DAZ0IO00100
P4LJ0_PCB
PCB P4LJ0 LA-7231P LS-7231P/7233P/7235P/7237P

ZZZ
Part Number Description

DC30100DT00 DC_IN_CABLE_90W
4 P4LJ0_DCIN_CABLE_90W 4
90W@

ZZZ
Part Number Description

DC30100DS00 DC_IN_CABLE_65W Security Classification Compal Secret Data Compal Electronics, Inc.
P4LJ0_DCIN_CABLE_65W 2010/09/28 2011/09/28 Title
65W@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 1 of 57

A B C D E
 A B C D E

P4LJ0 Block Diagram Fan Control

page 38

1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE

PEG(DIS) Intel Memory BUS(DDRIII)
VRAM * 8 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
Nvidia N12P-GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 11,12
DDR3 973pin BGA 1.5V DDRIII 1066/1333
Processor
64*16
128*16 page22~30 DC/QC 35W
EDP SV
(reserved)
page 32
rPGA989
page 4~10
HDMI(Reserved Only) USB 2.0 conn x2 Bluetooth CMOS Camera Mini Card
FDI x8 DMI x4
Conn (WWAN,SIM)
USB port 0,1 on USB/B USB port 13 USB port 10 USB port 9,12 on 3G/B
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
page 37 page 37 page 31 page 37
page 33 page 32 page 31 2.7GT/s 1GB/s x4
3.3V 48MHz
2 USBx14 2

HDMI(UMA/Optimus) LVDS(UMA/Optimus)
Intel
CRT(UMA/Optimus) HD Audio 3.3V 24MHz

TMDS(UMA/Optimus) Cougar Point-M

100MHz
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
HDA Codec
port 4 port 3 port 2 port 1 SATA x 6 100MHz 989pin BGA CX20584
page 43
(GEN1 1.5GT/S ,GEN2 3GT/S) page 13~21 SPI
USB 3.0 controller MINI Card x1 LAN(GbE)
UPD720200AF1 WLAN
USB port 8 AR8151
+ Charger page 46 page 37 page 35
SPI ROM x1
port 2 page 14
Card Reader port 0
SATA HDD SATA CDROM
RTS5209 RJ45
USB 3.0 Conn. Conn. Int. Speaker DMIC MIC Jack HP/SPDIF
3 page 38 page 36 page 34 page 34 LPC BUS 3

conn x1 33MHz
on USB/B Jack on USB/B
page 46 page 43 page 43 page 37 page 37

Sub-board ENE KB930

page 39
LS-7231P LS-7237P
RTC CKT. Power/B Door/B
page 41 page 40
page 13
Touch Pad Int.KBD
page 40 page 40

Power On/Off CKT. LS-7235P/7236P

page 40 USB_Auido/B
USB Port0,1 page 37
BIOS ROM
page 39
DC/DC Interface CKT. LS-7233P
4
page 45 FUN/B 4

page 41

Power Circuit DC/DC LS-7234P

page 47~55 3G Security Classification Compal Secret Data Compal Electronics, Inc.
USB Port9,12 page 37 Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 2 of 57
A B C D E
 A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power Plane Description S1 S3 S5 Full ON HIGH HIGH HIGH HIGH ON ON ON ON

VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VSDGPU +1.05VSDGPU power rail for GPU ON OFF OFF
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF Board ID/ Project ID Table for AD channel
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Vcc 3.3V +/- 5%
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF 0 0 0 V 0 V 0 V
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
2 2
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision
UMA Only UMAO@
0 0.1
N12P-GS GS@
1 0.2
N12P-GV GV@
EC SM Bus1 address EC SM Bus2 address 2 0.3
Discrete(OPTIMUS) OPT@
3 1.0
Device Address Device Address
VRAM X76@
4
Smart Battery 0001 011X b
Blue Tooth BT@
5
AR8151 8151@
6
Connector CONN@
7
Unpop @
PCH SM Bus address
3 3
Device Address

Clock Generator (9LVS3199AKLFT,

Project ID Table USB Port Table
1101 0010b
RTM890N-631-VB-GRT) 3 External
DDR DIMM0 1001 000Xb
Project ID Project Name USB 2.0 USB 1.1 Port USB Port
DDR DIMM2 1001 010Xb
0 P3LJ0
0 USB/B (Right Side)
1 P4LJ0 UHCI0
1 USB/B (Right Side)
2 P5LJ0
2
3 P3LS0 UHCI1
3
4 P4LS0 EHCI1
4
5 P5LS0 UHCI2
5
6
6
7 UHCI3
7
8 Mini Card(WLAN)
UHCI4
9 Mini Card(WWAN)
10 Camera
EHCI2 UHCI5
11
4 4
12 SIM Card
UHCI6
13 Blue Tooth

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 3 of 57
A B C D E
 5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
+1.05VS_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils

1
R1 - typical impedance = 14.5 mohms
24.9_0402_1%

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14
PEG_RX#[1] M35
15 DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12
15 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35
15 DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11

DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_GTX_C_HRX_N6
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_GTX_C_HRX_N5
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N[0..15] 22
E32 PEG_GTX_C_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_P[0..15] 22
G22 D33 PEG_GTX_C_HRX_N3
15 DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31 PEG_GTX_C_HRX_N2
C 15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PEG_HTX_C_GRX_N[0..15] 22 C
F20 B33 PEG_GTX_C_HRX_N1

PCI EXPRESS* - GRAPHICS

15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PEG_HTX_C_GRX_P[0..15] 22
C21 C32 PEG_GTX_C_HRX_N0
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
PEG_RX[1] L35
K34 PEG_GTX_C_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_GTX_C_HRX_P11
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_GTX_C_HRX_P10
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_GTX_C_HRX_P9
15 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_GTX_C_HRX_P5
15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_GTX_C_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3
PEG_RX[12] D34
A22 E31 PEG_GTX_C_HRX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_GTX_C_HRX_P1
15 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_GTX_C_HRX_P0
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C1 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C2 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_HTX_GRX_N13 C3 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N13
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C4 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 C5 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N11
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C6 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
15 FDI_FSYNC1 J17 K28 PEG_HTX_GRX_N9 C7 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N9
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C8 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N8
PEG_TX#[7] J30 1 2
15 FDI_INT H20 J28 PEG_HTX_GRX_N7 C9 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N7
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C10 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N6
eDP_COMPIO and ICOMPO signals PEG_TX#[9] H29 1 2
1

15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C11 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N5

should be shorted near balls R2 H17
FDI0_LSYNC PEG_TX#[10]
E29 PEG_HTX_GRX_N4 C12 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
B and routed with typical 24.9_0402_1%
PEG_TX#[12] F27 PEG_HTX_GRX_N3 C13 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N3 B
D28 PEG_HTX_GRX_N2 C14 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N2
impedance <25 mohms PEG_TX#[13] PEG_HTX_GRX_N1 C15 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N1
F26 1 2
2

PEG_TX#[14] PEG_HTX_GRX_N0 C16 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N0

PEG_TX#[15] E25 1 2
EDP_COMP A18 eDP_COMPIO PEG_HTX_GRX_P15 C17 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P15
A17 eDP_ICOMPO PEG_TX[0] M28 1 2
31 EDP_HPD# B16 M33 PEG_HTX_GRX_P14 C18 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P14
eDP_HPD PEG_TX[1] PEG_HTX_GRX_P13 C19 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P13
PEG_TX[2] M30 1 2
L31 PEG_HTX_GRX_P12 C20 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P12
PEG_TX[3] PEG_HTX_GRX_P11 C21 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P11
31 EDP_AUXP C15 eDP_AUX PEG_TX[4] L28 1 2
31 EDP_AUXN D15 K30 PEG_HTX_GRX_P10 C22 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P10
eDP_AUX# PEG_TX[5] PEG_HTX_GRX_P9 C23 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P9
K27 1 2
eDP

PEG_TX[6] PEG_HTX_GRX_P8 C24 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P8

PEG_TX[7] J29 1 2
C17 J27 PEG_HTX_GRX_P7 C25 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P7
31 EDP_TXP0 eDP_TX[0] PEG_TX[8]
F16 H28 PEG_HTX_GRX_P6 C26 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P6
31 EDP_TXP1 eDP_TX[1] PEG_TX[9]
C16 G28 PEG_HTX_GRX_P5 C27 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P5
eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 C28 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P4
G15 eDP_TX[3] PEG_TX[11] E28 1 2
F28 PEG_HTX_GRX_P3 C29 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P3
PEG_TX[12] PEG_HTX_GRX_P2 C30 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P2
31 EDP_TXN0 C18 eDP_TX#[0] PEG_TX[13] D27 1 2
E16 E26 PEG_HTX_GRX_P1 C31 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P1
31 EDP_TXN1 eDP_TX#[1] PEG_TX[14]
D16 D25 PEG_HTX_GRX_P0 C32 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P0
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]

SUYIN_100361HK988_SANDY BRIDGE
CONN@
Typ- suggest 220nF. The change in AC
capacitor value from 100nF to 220nF is to
enable compatibility with future platforms
having PCIE Gen3 (8GT/s)
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 4 of 57

5 4 3 2 1
 5 4 3 2 1

D D

For eDP

CLK_CPU_DPLL_R R25 1 EDP@ 2 0_0402_5% CLK_CPU_DPLL 14

CLK_CPU_DPLL#_R R26 1 EDP@ 2 0_0402_5% CLK_CPU_DPLL# 14
If support EDP
1. Mount R25, R26
JCPU1B 2. Remove R30, R31

C C
A28 CLK_CPU_DMI
BCLK CLK_CPU_DMI 14
C26 A27 CLK_CPU_DMI#

MISC

CLOCKS
17 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 14

AN34 SKTOCC#
+1.05VS_VCCP CLK_CPU_DPLL_R R30 1 LVDS@ 2 1K_0402_5%
Processor Pullups DPLL_REF_CLK A16
A15 CLK_CPU_DPLL#_R R31 1 LVDS@ 2 1K_0402_5% +1.05VS_VCCP
DPLL_REF_CLK#
R28 2 1 62_0402_5% H_PROCHOT#
T5 PAD @ H_CATERR# AL33 CATERR#
R32
0_0402_5%

THERMAL
1 2 H_PECI_ISO AN33 R8 H_DRAMRST#
18,39 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
R34 2 1 10K_0402_5% H_CPUPWRGD_R R36

DDR3
MISC
56_0402_5%
39,50 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R33 2 1 140_0402_1%
PROCHOT# SM_RCOMP[0] SM_RCOMP1 R35
SM_RCOMP[1] A5 2 1 25.5_0402_1%
R38 A4 SM_RCOMP2 R37 2 1 200_0402_1%
0_0402_5% SM_RCOMP[2]
1 2 H_THEMTRIP#_R AN32
18 H_THRMTRIP# THERMTRIP#
PU/PD for JTAG signals +1.05VS_VCCP

+3VS Buffered reset to CPU XDP_TMS R39 @

2 1 51_0402_5%
PRDY# AP29
AP27 XDP_TDI_R R40 2 @ 1 51_0402_5%
PREQ# +3VS
+1.05VS_VCCP R42 AR26 XDP_TCK XDP_TDO R41 2 @ 1 51_0402_5%
TCK
1

C35 0_0402_5% AR27 XDP_TMS

PWR MANAGEMENT
TMS

JTAG & BPM

B 0.1U_0402_16V4Z H_PM_SYNC_R XDP_TRST# XDP_TCK R43 @ B
15 H_PM_SYNC 1 2 AM34 PM_SYNC TRST# AP30 2 1 51_0402_5%
1

1
2

R44 R48 AR28 XDP_TDI_R R17 XDP_TRST# R46 2 @ 1 51_0402_5%

75_0402_5% 0_0402_5% TDI XDP_TDO 1K_0402_5%
TDO AP26
18 H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33 UNCOREPWRGOOD
5

U1 R49
2

2
1 43_0402_1% R51
P

NC BUFO_CPU_RST#
Y 4 1 2 BUF_CPU_RST# 130_0402_5%
DBR# AL35 DBRESET#_R 1 R50 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15
PLT_RST# 2 PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8
A SM_DRAMPWROK
G

SN74LVC1G07DCKR_SC70-5
@ AT28
3

R52 BPM#[0]
BPM#[1] AR29
0_0402_5% AR30
BUF_CPU_RST# BPM#[2]
PLT_RST# 17,35,38,39,44 AR33 AT30
2

RESET# BPM#[3]
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32

+3VALW
Follow DG 0.71
SUYIN_100361HK988_SANDY BRIDGE
+1.5V_CPU_VDDQ CONN@
1

+3VS C36
0.1U_0402_16V4Z
1
2

R61
U2 200_0402_5%
R62 74AHC1G09GW_TSSOP5
5

10K_0402_5%
2

1 2 1
P

A B PM_SYS_PWRGD_BUF A
O 4
15 PM_DRAM_PWRGD 2 A
G

1
3

C215
1U_0402_6.3V6K R63
@ 39_0402_5%
2 @
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2

D
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
SUSP 2 Q2
46,53 SUSP
G 2N7002E_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
S @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
3

Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 5 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

11 DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 11 12 DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 12

SA_CLK#[0] AA6 M_CLK_DDR#0 11 SB_CLK#[0] AD2 M_CLK_DDR#2 12
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA 11 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 11 A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 12
D DDR_A_D5 DDR_B_D5 D
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 11 A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 12
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA 11 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_B_D22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# 11 K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# 12
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# 11 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 11 N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 12
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] M_ODT1 11 SB_DQ[30] SB_ODT[1] M_ODT3 12

DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 11 AN3 SB_DQ[36] DDR_B_DQS#[0..7] 12
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] 11 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 SA_DQ[60] DDR_A_MA[0..15] 11 AT12 SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
11 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 12 DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_MA8 DDR_B_MA8 B
11 DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 12 DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
11 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 12 DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
11 DDR_A_WE# SA_WE# SA_MA[15] 12 DDR_B_WE# SB_WE# SB_MA[15]

SUYIN_100361HK988_SANDY BRIDGE CONN@ SUYIN_100361HK988_SANDY BRIDGE CONN@

+1.5V

@ R64
1

0_0402_5%
1 2 R65
1K_0402_5%

R66
2

1K_0402_5%
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# 11,12

Q3
2

BSS138_NL_SOT23-3
R67
G
2

4.99K_0402_1%
1

A A

11,12,14 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

1

C37
0.047U_0402_16V7K 2010/09/28 2011/09/28 Title
Issued Date Deciphered Date
SCHEMATIC, MB LA-7231P
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 6 of 57

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R69
1K_0402_1%

2
D D

JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

RSVD28 L7 1: Normal Operation; Lane # definition matches

RSVD29 AG7 CFG2 socket pin map definition
AK28 CFG[0] RSVD30 AE7
AK29 CFG[1] RSVD31 AK2
CFG2 AL26 W8 0:Lane Reversed
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4]
RSVD32
*
CFG5 AL29 AT26 CFG4
CFG6 CFG[5] RSVD33
AL30 CFG[6] RSVD34 AM33

1
CFG7 AM31 AJ27
CFG[7] RSVD35
AM32 CFG[8]
AM30 R70
CFG[9] 1K_0402_1%
AM28 CFG[10]
AM26 EDP@

2
CFG[11]
AN28 CFG[12]
AN31 CFG[13] RSVD37 T8
AN26 CFG[14] RSVD38 J16
AM27 CFG[15] RSVD39 H16
AK31 CFG[16] RSVD40 G16
AN29 CFG[17]
Display Port Presence Strap

C AJ31 change to VAXG_VAL_SENSE C

RSVD41 AR35 1 : Disabled; No Physical Display Port
T6 PAD @ AJ31 AT34 CFG4
AH31 change to VSSAXG_VAL_SENSE T7 PAD @ VAXG_VAL_SENSE RSVD42 attached to Embedded Display Port
AH31 VSSAXG_VAL_SENSE RSVD43 AT33
AJ33 change to VCC_VAL_SENSE T8 PAD @ AJ33 AP35
VCC_VAL_SENSE RSVD44
AH33 change to VSS_VAL_SENSE T9 PAD @ AH33 AR34 0 : Enabled; An external Display Port device is
VSS_VAL_SENSE RSVD45
* connected to the Embedded Display Port
AJ26 RSVD5
RSVD6 and RSVD7 had changed to

RESERVED
SA_DIMM_VREFDQ and SB_DIMMVREFDQ CFG6
RSVD46 B34
11 SA_DIMM_VREFDQ SA_DIMM_VREFDQ B4 A33
SB_DIMM_VREFDQ RSVD6 RSVD47 CFG5
12 SB_DIMM_VREFDQ D1 RSVD7 RSVD48 A34
RSVD49 B35

1
SA_DIMM_VREFDQ RSVD50 C35
1

R73 R74
SB_DIMM_VREFDQ F25 1K_0402_1% 1K_0402_1%
RSVD8
For Future CPU M3 support, R71
1K_0402_1%
R72
1K_0402_1%
F24 RSVD9
@ @
F23
Sandey bridge not supportM3,

2
RSVD10
D24 AJ32
2

RSVD11 RSVD51
Check list1.0&CRB say can NC G25
G24
RSVD12 RSVD52 AK32
RSVD13
E23 RSVD14
D23 RSVD15
C30 AH27 PAD T10
RSVD16 VCC_DIE_SENSE
A31 RSVD17
B30 RSVD18
B29 RSVD19
PCIE Port Bifurcation Straps
+3VS D30 AN35
RSVD20 RSVD54
B31 RSVD21 RSVD55 AM35
1

A30 11: (Default) x16 - Device 1 functions 1 and 2 disabled

B
R75
10K_0402_5%
C29
RSVD22
RSVD23
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
@
VCCIO_SEL J20
disabled
1 2

RSVD24
B18 RSVD25 RSVD56 AT2 01: Reserved - (Device 1 function 1 disabled ; function
VCCIO_SEL A19 AT1
R76 VCCIO_SEL RSVD57
AR1
2 enabled)
10K_0402_5% RSVD58
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
@ J15 RSVD27
2

KEY B1
CFG7
VCCIO_SEL

1
R77
1/NC : (Default) +1.05VS_VTT 1K_0402_1%
A19 * 0: +1.0VS_VTT SUYIN_100361HK988_SANDY BRIDGE
@

2
CONN@

VCCIO_SEL For 2012 CPU support

RSVD26 had changed the name to VCCIO_SEL
Need PH +3VS 10K at +1.05VS_VTT source PEG DEFER TRAINING
for 2012 processor +1.05V and +1.0V select
1: (Default) PEG Train immediately following xxRESETB
CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 7 of 57
5 4 3 2 1
 5 4 3 2 1

SV type CPU JCPU1F POWER

+CPU_CORE
QC 94A
+1.05VS_VCCP
DC 53A 8.5A
AG35 VCC1
AG34 AH13 +1.05VS_VCCP
VCC2 VCCIO1

1
10U_0805_6.3V6M
C40

10U_0805_6.3V6M
C41

10U_0805_6.3V6M
C42

10U_0805_6.3V6M
C38

10U_0805_6.3V6M
C43

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AG33 VCC3 VCCIO2 AH10

1
AG32 VCC4 VCCIO3 AG10

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53
AG31 AC10

2
VCC5 VCCIO4
AG30 Y10

2
D VCC6 VCCIO5 D
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12

1
10U_0805_6.3V6M
C54

10U_0805_6.3V6M
C39

10U_0805_6.3V6M
C55

10U_0805_6.3V6M
C56

10U_0805_6.3V6M
C57

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2V_Y

330U_D2_2V_Y
AF33 VCC13 VCCIO12 J11 @ @

C62

C63
AF32 H14 + +
VCC14 VCCIO13

C58

C59

C60

C61
AF31 H12

2
VCC15 VCCIO14
AF30 H11

2
VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12

PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
+CPU_CORE
AD33 VCC23 VCCIO22 F11 Cap quantity follow 43890_HR_CHKLST_Rev07
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
1

1
22U_0805_6.3V6M
C65

22U_0805_6.3V6M
C66

22U_0805_6.3V6M
C67

22U_0805_6.3V6M
C68

22U_0805_6.3V6M
C69

22U_0805_6.3V6M
C70

22U_0805_6.3V6M
C71

22U_0805_6.3V6M
C72
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 D12
2

2
VCC30 VCCIO28
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
1

1
22U_0805_6.3V6M
C73

22U_0805_6.3V6M
C74

22U_0805_6.3V6M
C75

22U_0805_6.3V6M
C76

22U_0805_6.3V6M
C77

22U_0805_6.3V6M
C78

22U_0805_6.3V6M
C79

22U_0805_6.3V6M
C80
AC28 VCC38 VCCIO36 A14
C C
AC27 VCC39 VCCIO37 A13
AC26 A12
2

2
VCC40 VCCIO38
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48
AA27 VCC49
AA26 VCC50
+CPU_CORE +1.05VS_VCCP +1.05VS_VCCP
Y35

CORE SUPPLY
VCC51
Y34 VCC52
Y33 VCC53

1
Y32 VCC54
Y31 R78 R79
VCC55
330U_D2_2V_Y
C81

330U_D2_2V_Y
C82

330U_D2_2V_Y
C83

330U_D2_2V_Y
C84

330U_D2_2V_Y

Y30 130_0402_5% 75_0402_5%

VCC56
1

Y29 VCC57
C85

+ + + + + Y28

2
VCC58
Y27 VCC59
Y26 R80
2

VCC60 43_0402_1%
V35 VCC61
V34 AJ29 H_CPU_SVIDALRT# 1 2

SVID
VCC62 VIDALERT# VR_SVID_ALRT# 54
V33 AJ30 H_CPU_SVIDCLK R81 1 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK 54
V32 AJ28 H_CPU_SVIDDAT R82 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT 54
V31 VCC65
V30 VCC66
V29 VCC67
V28 VCC68
V27 VCC69 Place the PU
V26
B
U35
VCC70 resistors B
VCC71 close to VR
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80 +CPU_CORE
Place the PU
R35 VCC81 resistors
R34 VCC82
R33 VCC83
close to CPU

1
R32 VCC84
R31 R83
VCC85 100_0402_1%
R30 VCC86
R29 VCC87
R28

SENSE LINES

2
VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R R84 1 2 0_0402_5%
VCCSENSE 54
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R85 1 2 0_0402_5%
VSSSENSE 54
P35 VCC91
P34 VCC92

1
P33 VCC93
P32 B10 R86
VCC94 VCCIO_SENSE VCCIO_SENSE 53
P31 A10 VSSIO_SENSE 100_0402_1%
VCC95 VSSIO_SENSE VSSIO_SENSE 53
P30 VCC96
P29

2
VCC97
P28 VCC98
P27 VCC99
P26 VCC100

A A

SUYIN_100361HK988_SANDY BRIDGE CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 8 of 57
5 4 3 2 1
 5 4 3 2 1

D D

+VGFX_CORE QC 33A JCPU1G

POWER
DC 26A
AT24 AK35

SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE 54
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 54
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AT21 VAXG3
1

1
C95

C89

C90

C96

C91

C92
AT20 VAXG4 +1.5V_CPU_VDDQ
AT18 VAXG5
AT17
2

2
VAXG6
AR24 VAXG7

1
C
AR23 VAXG8 +V_SM_VREF should C
AR21 R94
AR20
VAXG9 have 20 mil trace width 1K_0402_5%
VAXG10
AR18

VREF
VAXG11
AR17

2
VAXG12 +V_SM_VREF
AP24 VAXG13 SM_VREF AL1
AP23 VAXG14

1
AP21 VAXG15

1
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AP20 C101 R95
VAXG16
1

1
C93

C97

C98

C94

C99

C100
AP18 0.1U_0402_16V4Z 1K_0402_5%
VAXG17
AP17

2
VAXG18
AN24
2

2
VAXG19
AN23 VAXG20
AN21 VAXG21
AN20 +1.5V_CPU_VDDQ +1.5VS
VAXG22
AN18

DDR3 -1.5V RAILS

VAXG23 @ JP2
AN17 VAXG24 10A
AM24 AF7 1 2

GRAPHICS
VAXG25 VDDQ1
AM23 VAXG26 VDDQ2 AF4
AM21 AF1 PAD-OPEN 4x4m
VAXG27 VDDQ3

1
330U_D2_2V_Y

330U_D2_2V_Y

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AM20 VAXG28 VDDQ4 AC7
1

1
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@ @ @ @ @ AM18 AC4 + C114

VAXG29 VDDQ5
1

1
C102

C103

C104

C105

C106

C107

C108

C109

C110

C111

C112

C113
+ + AM17 AC1 330U_D2_2V_Y
VAXG30 VDDQ6
AL24 Y7

2
VAXG31 VDDQ7
AL23 Y4
2

VAXG32 VDDQ8
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
AL18 VAXG35 VDDQ11 U4
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
Vaxg AK21
AK20
VAXG39 VDDQ15 P1
B VAXG40 B
AK18 VAXG41
‧ Can connect to GND if motherboard only AK17 VAXG42
AJ24
supports external graphics and if GFX VR is not AJ23
VAXG43
VAXG44
stuffed in a common motherboard design, AJ21 VAXG45
AJ20
‧ VAXG can be left floating in a common AJ18
VAXG46
VAXG47
motherboard design (Gfx VR keeps VAXG from AJ17 VAXG48 +VCCSA
AH24 6A
floating) if the VR is stuffed VAXG49

SA RAIL
AH23 VAXG50
AH21 M27 +VCCSA
VAXG51 VCCSA1
AH20 VAXG52 VCCSA2 M26
AH18 VAXG53 VCCSA3 L26

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M
AH17 J26 @ R96 1 2 0_0402_5% VCCSA_SENSE
VAXG54 VCCSA4

1
VCCSA5 J25

1
C115

C116

C117

C118
VCCSA6 J24
H26 + C119

2
VCCSA7 330U_D2_2V_Y
VCCSA8 H25

2
R97 1 2 0_0402_5%
1.8V RAIL

VSSSA_SENSE 52
+1.8VS R98 1.5A
0_0805_5%
1 2 +1.8VS_VCCPLL B6 H23
VCCPLL1 VCCSA_SENSE VCCSA_SENSE 52
A6
MISC

VCCPLL2
330U_D2_2V_Y
C120

10U_0805_6.3V6M
C121

1U_0402_6.3V6K
C122

1U_0402_6.3V6K
C123

A2 VCCPLL3
1

1
1

+ C22 H_FC_C22
FC_C22
C24 VCCSA_VID1 52
2

VCCSA_VID1
2

1
R99 R100
A SUYIN_100361HK988_SANDY BRIDGE 10K_0402_5% 0_0402_5% A
CONN@ 1 @

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 9 of 57
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
C C
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3
AM2 VSS55 VSS135 AB29 H10 VSS213
AM1 VSS56 VSS136 AB28 H9 VSS214
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217
AL25 VSS60 VSS140 Y8 H5 VSS218
AL22 VSS61 VSS141 Y6 H4 VSS219
AL19 VSS62 VSS142 Y5 H3 VSS220
AL16 VSS63 VSS143 Y3 H2 VSS221
AL13 VSS64 VSS144 Y2 H1 VSS222
B B
AL10 VSS65 VSS145 W35 G35 VSS223
AL7 VSS66 VSS146 W34 G32 VSS224
AL4 VSS67 VSS147 W33 G29 VSS225
AL2 VSS68 VSS148 W32 G26 VSS226
AK33 VSS69 VSS149 W31 G23 VSS227
AK30 VSS70 VSS150 W30 G20 VSS228
AK27 VSS71 VSS151 W29 G17 VSS229
AK25 VSS72 VSS152 W28 G11 VSS230
AK22 VSS73 VSS153 W27 F34 VSS231
AK19 VSS74 VSS154 W26 F31 VSS232
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 VSS76 VSS156 U8
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

SUYIN_100361HK988_SANDY BRIDGE SUYIN_100361HK988_SANDY BRIDGE

CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 10 of 57
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
M3 support R102
0_0402_5%
R101
1K_0402_1%
1 @ 2 +1.5V +1.5V
7 SA_DIMM_VREFDQ
JDIMM1

2
+DIMM0_VREF 1 2
VREF_DQ VSS1 DDR_A_DQS#[0..7] 6
3 4 DDR_A_D4
VSS2 DQ4

2.2U_0603_6.3V6K

0.1U_0402_16V4Z
S

D
3 1 DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5 DDR_A_DQS[0..7] 6

C124

C125
Q8 DDR_A_D1 7 8
BSS138_NL_SOT23-3 R103 DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10 DDR_A_D[0..63] 6

1
@ 1K_0402_1% DDR_A_DQS0

G
11 12

2
DM0 DQS0
6,12,14 DRAMRST_CNTRL_PCH 13 14 DDR_A_MA[0..15] 6

2
DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 16

2
D DDR_A_D3 DQ2 DQ6 DDR_A_D7 D
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,12
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DQ10 DQ14
All VREF traces should DDR_A_D11 35 DQ11 DQ15 36 DDR_A_D15 Layout Note:
37 38
have 10 mil trace width DDR_A_D16 39
VSS13 VSS14
40 DDR_A_D20 Place near JDIMM1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 +1.5V
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48

1U_0402_6.3V6K
C126

1U_0402_6.3V6K
C127

1U_0402_6.3V6K
C128

1U_0402_6.3V6K
C129
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52

1
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29

2
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
+1.5V

6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 6

CKE0 CKE1

10U_0603_6.3V6M
C130

10U_0603_6.3V6M
C131

10U_0603_6.3V6M
C132

10U_0603_6.3V6M
C133

10U_0603_6.3V6M
C134

10U_0603_6.3V6M
C135

10U_0603_6.3V6M

330U_D2_2V_Y
C C
75 VDD1 VDD2 76

C137
77 78 DDR_A_MA15 @
NC1 A15

C136
DDR_A_BS2 79 80 DDR_A_MA14 +
6 DDR_A_BS2 BA2 A14
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11

2
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
6 M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1 M_CLK_DDR1 6
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
6 M_CLK_DDR#0 103 CK0# CK1# 104 M_CLK_DDR#1 6 +1.5V
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 6
111 VDD13 VDD14 112

1
6 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# 6
DDR_A_CAS# WE# S0# M_ODT0 R104
6 DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 6
117 118 1K_0402_1%
DDR_A_MA13 VDD15 VDD16 M_ODT1
119 A13 ODT1 120 M_ODT1 6 Layout Note:
6 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122

2
123
S1# NC2
124 Place near JDIMM1.203,204
VDD17 VDD18 +VREF_CA
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C138

0.1U_0402_16V4Z
C139
DDR_A_D33 131 132 DDR_A_D37 +0.75VS
DQ33 DQ37 R105
133 VSS29 VSS30 134

1
DDR_A_DQS#4 135 136 1K_0402_1%
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B DDR_A_D38 B
139 140

2
VSS32 DQ38

1U_0402_6.3V6K
C140

1U_0402_6.3V6K
C141

1U_0402_6.3V6K
C142

1U_0402_6.3V6K
C143
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144

1
145 146 DDR_A_D44
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150

2
DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 For EMI
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 +1.5V
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190

1
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63 C207 C212 C214
193 DQ59 DQ63 194
195 196

2
VSS51 VSS52
197 SA0 EVENT# 198
+3VS 199 200 D_CK_SDATA 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDDSPD SDA D_CK_SDATA 12,14
201 202 D_CK_SCLK 0.1U_0402_16V4Z
A SA1 SCL D_CK_SCLK 12,14 A
+0.75VS 203 VTT1 VTT2 204 +0.75VS
<Address: 00>
1
0.1U_0402_16V4Z
C144

2.2U_0603_6.3V6K
C145

10K_0402_5%
R114

10K_0402_5%
R115

205 G1 G2 206
2
1

DIMM_A Reverse H:8mm

FOX_AS0A621-J8RG-7H
CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

1

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 11 of 57
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
M3 support R116
0_0402_5% R117
1 @ 2 1K_0402_1% +1.5V +1.5V
7 SB_DIMM_VREFDQ
JDIMM2
+DIMM1_VREF 1 2

2
VREF_DQ VSS DDR_B_D4
3 VSS DQ4 4

2.2U_0603_6.3V6K
C146

0.1U_0402_16V4Z
C147
S

D
3 1 DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5 DDR_B_DQS#[0..7] 6

1
Q9 DDR_B_D1 7 8
BSS138_NL_SOT23-3 DQ1 VSS DDR_B_DQS#0
9 VSS DQS0# 10 DDR_B_DQS[0..7] 6
@ R118 DDR_B_DQS0

G
11 12

2
1K_0402_1% DM0 DQS0
6,11,14 DRAMRST_CNTRL_PCH 13 VSS VSS 14 DDR_B_D[0..63] 6
DDR_B_D2 15 16 DDR_B_D6

2
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18 DDR_B_MA[0..15] 6
D D
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS VSS 26
DDR_B_DQS#1 27 28
DQS1# DM1
All VREF traces should DDR_B_DQS1 29 DQS1 RESET# 30 DDR3_DRAMRST# DDR3_DRAMRST# 6,11
31 32
have 10 mil trace width DDR_B_D10 33
VSS VSS
34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 38 +1.5V
DDR_B_D16 VSS VSS DDR_B_D20
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 VSS VSS 44

1U_0402_6.3V6K
C148

1U_0402_6.3V6K
C149

1U_0402_6.3V6K
C150

1U_0402_6.3V6K
C151
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48

1
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54

2
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70 Layout Note:
71 72
VSS VSS +1.5V Place near JDIMMB

6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 6

CKE0 CKE1
75 VDD VDD 76

10U_0603_6.3V6M
C152

10U_0603_6.3V6M
C153

10U_0603_6.3V6M
C154

10U_0603_6.3V6M
C155

10U_0603_6.3V6M
C156

10U_0603_6.3V6M
C157

10U_0603_6.3V6M
77 78 DDR_B_MA15 @
NC A15

C158
C DDR_B_BS2 DDR_B_MA14 C
6 DDR_B_BS2 79 BA2 A14 80

1
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86

2
A9 A7
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
6 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3 M_CLK_DDR3 6
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
6 M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 6 +1.5V
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 6
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
6 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 6
111 VDD VDD 112 Layout Note:

1
6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_CS2_DIMMB# 6
DDR_B_CAS# 115
WE# S0#
116 M_ODT2 R119 Place near JDIMMB.203,204
6 DDR_B_CAS# CAS# ODT0 M_ODT2 6
117 118 1K_0402_1% +0.75VS
DDR_B_MA13 VDD VDD M_ODT3 <BOM Structure>
119 A13 ODT1 120 M_ODT3 6
6 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122

2
S1# NC
123 VDD VDD 124
125 126 +VREF_CB
TEST VREF_CA

1U_0402_6.3V6K
C160

1U_0402_6.3V6K
C161

1U_0402_6.3V6K
C162

1U_0402_6.3V6K
C163
127 VSS VSS 128

1
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
2.2U_0603_6.3V6K
C164

0.1U_0402_16V4Z
C165
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 R120
133 134

2
VSS VSS

1
DDR_B_DQS#4 135 136 1K_0402_1%
DDR_B_DQS4 DQS4# DM4 <BOM Structure>
137 DQS4 VSS 138
139 140 DDR_B_D38

2
DDR_B_D34 VSS DQ38 DDR_B_D39
141 DQ34 DQ39 142
B DDR_B_D35 B
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
153 154 DDR_B_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
+3VS +3VS DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 VSS DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
1

0.1U_0402_16V4Z
C166

2.2U_0603_6.3V6K
C167

185 186 DDR_B_DQS#7

VSS DQS7#
1

R129 187 188 DDR_B_DQS7

10K_0402_5% DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
2

DDR_B_D59 DQ58 DQ62 DDR_B_D63

193 194
2

DQ59 DQ63
195 VSS VSS 196
197 SA0 EVENT# 198
199 200 D_CK_SDATA
VDDSPD SDA D_CK_SDATA 11,14
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 11,14
+0.75VS 203 VTT VTT 204 +0.75VS
1

A A
205 GND1 GND2 206
R130 207 208
10K_0402_5% BOSS1 BOSS2

FOX_AS0A621-U4RG-7H
2

CONN@

<Address: 01> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

DIMM_B Reverse type H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 12 of 57
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
R131 10M_0402_5%

32.768KHZ_12.5PF_Q13MC14610002
1

4
Y1

OSC

OSC
18P_0402_50V8J

1
C169
NC

C168 NC 18P_0402_50V8J
2

2
D D

+3VS

SERIRQ R134 2 1 10K_0402_5%

+RTCVCC JCMOS1
0_0603_5% U3A PCH_SATALED# R136 2 1 10K_0402_5%

1
R132 1 2 1M_0402_5% SM_INTRUDER# @
+RTCVCC C170 PCH_RTCX1 A20 C38 LPC_AD0 PCH_GPIO21 R139 2 1 10K_0402_5%
RTCX1 FWH0 / LAD0 LPC_AD0 39
R133 1 2 330K_0402_5% PCH_INTVRMEN 1U_0603_10V6K A38 LPC_AD1
LPC_AD1 39

2
FWH1 / LAD1

LPC
PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 39
LPC_AD3
INTVRMEN C37 LPC_AD3 39

2
PCH_RTCRST# FWH3 / LAD3
1 2 D20 RTCRST#
H：Integrated VRM enable R137 20K_0402_5% LPC_FRAME#
* L：Integrated VRM disable 1 2 PCH_SRTCRST# G22 SRTCRST#
FWH4 / LFRAME# D36 LPC_FRAME# 39
R138 20K_0402_5% E36
LDRQ0#

RTC
0_0603_5%
JME1
(INTVRMEN should always be pull high.) SM_INTRUDER# K22 K36
INTRUDER# LDRQ1# / GPIO23

1
C171 @ PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 39
+3VS 1U_0603_10V6K INTVRMEN SERIRQ

2
SPI ROM FOR ME ( 4MByte )

2
R135 1 @ 2 1K_0402_5% HDA_SPKR AM3 SATA_PRX_DTX_N0 34
HDA_BIT_CLK SATA0RXN
N34 HDA_BCLK SATA0RXP AM1 SATA_PRX_DTX_P0 34

SATA 6G
HIGH= Enable ( No Reboot ) AP7 HDD +3VS
SATA0TXN SATA_PTX_DRX_N0 34
LOW= Disable (Default) HDA_SYNC
* L34 HDA_SYNC SATA0TXP AP5 SATA_PTX_DRX_P0 34
PCH_SPI_WP# R142 1 2 3.3K_0402_5%
HDA_SPKR T10 AM10
+3VALW_PCH 42 HDA_SPKR SPKR SATA1RXN
R140 AM8
1K_0402_5% HDA_RST# SATA1RXP PCH_SPI_HOLD# R144 1 3.3K_0402_5%
K34 HDA_RST# SATA1TXN AP11 2
2 @ 1 HDA_SDOUT AP10
R141 SATA1TXP
C 0_0402_5% 42 HDA_SDIN0 HDA_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7 SATA_PRX_DTX_N2 34 Please short PJP35 R145
C

39 HDA_SDO 2 1 SATA2RXP AD5 SATA_PRX_DTX_P2 34

G34 AH5 ODD +3VS 0_0402_5%
HDA_SDIN1 SATA2TXN SATA_PTX_DRX_N2 34
PCH_SPI_SO_R 2PCH_SPI_SO
HDA_SDO C34
SATA2TXP AH4 SATA_PTX_DRX_P2 34 C172 1
HDA_SDIN2

IHDA
ME debug mode,this signal has a weak internal PD SATA3RXN AB8 1 2
Low = Disabled (Default) U4
* High = Enabled [Flash Descriptor Security Overide]
A34 HDA_SDIN3 SATA3RXP
SATA3TXN
AB10
AF3 0.1U_0402_16V4Z 8 VCC VSS 4
SATA3TXP AF1
HDA_SDOUT A36 PCH_SPI_WP# 3
HDA_SDO W

SATA
+3VALW_PCH Y7
SATA4RXN PCH_SPI_HOLD# 7
SATA4RXP Y5 HOLD
R143 2 1 1K_0402_5% HDA_SYNC C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN PCH_SPI_CS# 1 PCH_SPI_CS#_R
SATA4TXP AD1 2 1 S
This signal has a weak internal pull-down N32 R149 0_0402_5%
HDA_DOCK_RST# / GPIO13 PCH_SPI_CLK 1 PCH_SPI_CLK_R
SATA5RXN Y3 2 6 C
R153 Y1 R150 0_0402_5%
On Die PLL VR Select is supplied by 51_0402_5% SATA5RXP
AB3 PCH_SPI_SI 1 2 PCH_SPI_SI_R 5 2 PCH_SPI_SO_R
1.5V when sampled high PCH_JTAG_TCK SATA5TXN R154 0_0402_5% D Q
* 1.8V when sampled low
2 1 J3 JTAG_TCK SATA5TXP AB1
W25Q32BVSSIG
PCH_JTAG_TMS H7 Y11 R156 +1.05VS_PCH
Needs to be pulled High for Huron River platfrom JTAG_TMS SATAICOMPO

JTAG
PCH_JTAG_TDI SATA_COMP
37.4_0402_1% P/N:SA00003K800
K5 JTAG_TDI SATAICOMPI Y10 1 2

R147 PCH_JTAG_TDO H1 C173

33_0402_5% JTAG_TDO R157 +1.05VS_PCH 22P_0402_50V8J R158
SATA3RCOMPO AB12
42 HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK 49.9_0402_1% @ 33_0402_5%
R148 AB13 SATA3_COMP 1 2 2 1 1 @ 2PCH_SPI_CLK_R
33_0402_5% SATA3COMPI
42 HDA_SYNC_AUDIO 1 2 HDA_SYNC_R Reserve for EMI
R151 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
33_0402_5% SPI_CLK SATA3RBIAS R162 750_0402_1%
B B
42 HDA_RST_AUDIO# 1 2 HDA_RST# PCH_SPI_CS# Y14 SPI_CS0#
R155
33_0402_5% T1 SPI_CS1#
SPI

42 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_R SATALED# P3 PCH_SATALED#

PCH_SATALED# 41
PCH_SPI_SI V4 V14 PCH_GPIO21
SPI_MOSI SATA0GP / GPIO21
PCH_SPI_SO U3 P1 PCH_GPIO19
+3VALW_PCH +3VALW_PCH +3VALW_PCH SPI_MISO SATA1GP / GPIO19 +3VS

COUGARPOINT_FCBGA989~D
1

1
R159 R160 R161 R674
200_0402_5% 200_0402_5% 200_0402_5% 4.7K_0402_5%
@ @ @ @
2

2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_GPIO19
1

R163 R165
Prevent back drive issue. Prevent back drive issue. Debug Port DG 1.2 PH 4.7K +3VS
R164
100_0402_1% 100_0402_1% 100_0402_1% +3VS +3VS
@ @ @
Q10 Q65
2

2
G

BSS138_NL_SOT23-3 BSS138_NL_SOT23-3

HDA_SYNC_R 3 1HDA_SYNC HDA_SDOUT_R 3 1HDA_SDOUT

S

W=20mils trace width 10mil W=20mils 1 @ 2 1 @ 2

+RTCBATT +CHGRTC +RTCVCC R152 R768
A D1 0_0402_5% 0_0402_5% A
R166 2
1K_0402_5%
1

2 1 1

3 R747
1M_0402_5%
BAS40-04_SOT23-3 1 Security Classification Compal Secret Data Compal Electronics, Inc.
2

C174
0.1U_0402_16V4Z 2010/09/28 2011/09/28 Title
Issued Date Deciphered Date
9/29 DG1.5
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 13 of 57
5 4 3 2 1
 5 4 3 2 1

U3B +3VALW_PCH

35 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 LID_SW_OUT# R173 1 2 10K_0402_5%

PCIE_PRX_DTX_P1 PERN1 LID_SW_OUT#
35 PCIE_PRX_DTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12 LID_SW_OUT# 39
PCIE LAN C175 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 DRAMRST_CNTRL_PCH R167 1 2 1K_0402_5%
35 PCIE_PTX_C_DRX_N1 PETN1
C176 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
35 PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SMBCLK 37

37 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA PCH_SMBDATA 37 PCH_SMBCLK R168 1 2 2.2K_0402_5%

PCIE_PRX_DTX_P2 PERN2 SMBDATA
37 PCIE_PRX_DTX_P2 BF34 PERP2
Mini Card C177 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 PCH_SMBDATA R169 1 2 2.2K_0402_5%
37 PCIE_PTX_C_DRX_N2 PETN2
C178 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32
37 PCIE_PTX_C_DRX_P2 PETP2

SMBUS
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 6,11,12
38 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 BG36 PCH_GPIO74 R170 1 2 10K_0402_5%
PCIE_PRX_DTX_P3 PERN3
38 PCIE_PRX_DTX_P3 BJ36 PERP3 SML0CLK C8
D C179 PCIE_PTX_DRX_N3 D
Card Reader 38 PCIE_PTX_C_DRX_N3 1 2 0.1U_0402_10V7K AV34 PETN3
C180 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 AU34 G12 PCH_SML1CLK R171 1 2 2.2K_0402_5%
38 PCIE_PTX_C_DRX_P3 PETP3 SML0DATA

44 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 BF36 PCH_SML1DATA R172 1 2 2.2K_0402_5%

PCIE_PRX_DTX_P4 PERN4
44 PCIE_PRX_DTX_P4 BE36 PERP4
USB3.0 C181 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_GPIO74
44 PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C182 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34 PCH_GPIO47 R174 1 2 10K_0402_5%
44 PCIE_PTX_C_DRX_P4 PETP4
E14 PCH_SML1CLK
SML1CLK / GPIO58

PCI-E*
BG37 PERN5
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA / GPIO75
AY36 PETN5 For DDR
BB36 PETP5
+3VS +3VS
BJ38 PERN6
R175 2 1 10K_0402_5% PCH_GPIO18 BG38 R177
PERP6

Controller
AU36 M7 4.7K_0402_5%
PETN6 CL_CLK1

2
R176 2 1 10K_0402_5% PCH_GPIO20 AV36 1 2 +3VS
PETP6

Link
R181 2 1 10K_0402_5% PCH_GPIO26 BG40 T11 PCH_SMBDATA 6 1 D_CK_SDATA D_CK_SDATA 11,12
PERN7 CL_DATA1
BJ40 PERP7
+3VALW_PCH AY40 Q11A
PETN7 DMN66D0LDW-7_SOT363-6 R179
BB40 PETP7 CL_RST1# P10
R178 2 1 10K_0402_5% PCH_GPIO73 4.7K_0402_5%

5
BE38 PERN8 1 2 +3VS
R180 2 1 10K_0402_5% PCH_GPIO25 BC38 PERP8 PCH_SMBCLK D_CK_SCLK
AW38 PETN8 3 4 D_CK_SCLK 11,12
AY38 PETP8 Q11B
R182 2 1 10K_0402_5% PCH_GPIO44 M10 PCH_GPIO47 DMN66D0LDW-7_SOT363-6
PEG_A_CLKRQ# / GPIO47
Y40 CLKOUT_PCIE0N
R183 2 1 10K_0402_5% PCH_GPIO45 Y39 CLKOUT_PCIE0P
CLKOUT_PEG_A_N AB37

CLOCKS
C R184 PCH_GPIO46 PCH_GPIO73 C
2 1 10K_0402_5% J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
+3VS
CLK_PCIE_MINI1# AB49 AV22 CLK_CPU_DMI#
37 CLK_PCIE_MINI1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
CLK_PCIE_MINI1 AB47 AU22 CLK_CPU_DMI Pull up at EC side.
37 CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
Mini Card

2
37 MINI1_CLKREQ# R187 2 1 0_0402_5% PCH_GPIO18 M1 PCIECLKRQ1# / GPIO18 CLK_CPU_DPLL#
CLKOUT_DP_N / CLKOUT_BCLK1_N AM12 CLK_CPU_DPLL# 5
AM13 CLK_CPU_DPLL 120MHz for eDP. PCH_SML1DATA 6 1 EC_SMB_DA2 EC_SMB_DA2 22,39
CLKOUT_DP_P / CLKOUT_BCLK1_P CLK_CPU_DPLL 5
CLK_PCIE_USB30# AA48
44 CLK_PCIE_USB30# CLKOUT_PCIE2N
USB3.0 CLK_PCIE_USB30 AA47 Q12A
44 CLK_PCIE_USB30 CLKOUT_PCIE2P
BF18 CLK_BUF_CPU_DMI# DMN66D0LDW-7_SOT363-6
CLKIN_DMI_N

5
44 USB30_CLKREQ# R190 2 1 0_0402_5% PCH_GPIO20 V10 BE18 CLK_BUF_CPU_DMI
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
PCH_SML1CLK 3 4 EC_SMB_CK2 EC_SMB_CK2 22,39
CLK_PCIE_LAN# Y37 BJ30 CLKIN_DMI2#
35 CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_DMI2_N
PCIE LAN CLK_PCIE_LAN Y36 BG30 CLKIN_DMI2 Q12B
35 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_DMI2_P DMN66D0LDW-7_SOT363-6
35 LAN_CLKREQ# R193 1 2 0_0402_5% PCH_GPIO25 A8 PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M#
CLKIN_DOT_96N G24
E24 CLK_BUF_DREF_96M
CLK_PCIE_CARD# CLKIN_DOT_96P
38 CLK_PCIE_CARD# Y43 CLKOUT_PCIE4N
Card Reader CLK_PCIE_CARD Y45 CLK_BUF_CPU_DMI# R196 1 2 10K_0402_5%
38 CLK_PCIE_CARD CLKOUT_PCIE4P
AK7 CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI R197 1 2 10K_0402_5%
R198 CLKIN_SATA_N / CKSSCD_N
38 CARD_CLKREQ# 1 2 0_0402_5% PCH_GPIO26 L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5 CLK_BUF_PCIE_SATA
CLKIN_DMI2# R199 1 2 10K_0402_5%
CLKIN_DMI2 R200 1 2 10K_0402_5%
V45 K45 CLK_BUF_ICH_14M
CLKOUT_PCIE5N REFCLK14IN CLK_BUF_DREF_96M# R201 10K_0402_5%
V46 CLKOUT_PCIE5P 1 2
CLK_BUF_DREF_96M R202 1 2 10K_0402_5%
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 17
CLK_BUF_PCIE_SATA# R203 1 2 10K_0402_5%
B CLK_BUF_PCIE_SATA R204 10K_0402_5% B
1 2
CLK_PEG_VGA# AB42 V47 XTAL25_IN
22 CLK_PEG_VGA# CLKOUT_PEG_B_N XTAL25_IN
CLK_PEG_VGA AB40 V49 XTAL25_OUT CLK_BUF_ICH_14M R207 1 2 10K_0402_5%
22 CLK_PEG_VGA CLKOUT_PEG_B_P XTAL25_OUT
PEG_CLKREQ#_R E6 R208 +1.05VS_PCH
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP
V40 CLKOUT_PCIE6N
V42 XTAL25_IN
CLKOUT_PCIE6P
PCH_GPIO45 T13 XTAL25_OUT 1 2
PCIECLKRQ6# / GPIO45 R209 1M_0402_5%
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43 CLK_FLEX0 @ T12
V37 Y2
FLEX CLOCKS

CLKOUT_PCIE7P
CLKOUTFLEX1 / GPIO65 F47 2 1
PCH_GPIO46 K12 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47 25MHZ_20PF_7A25000012

1
AK14 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 K49 DGPU_PRSNT# C183 C184
+3VS 27P_0402_50V8J 27P_0402_50V8J

2
COUGARPOINT_FCBGA989~D

1
R214
10K_0402_5%
+3VALW_PCH
UMAO@

2
DGPU_PRSNT#
1

2
R216
10K_0402_5%
GPIO67 R218 R219 C186
VGA_ON 17,25,46,55 DGPU_PRSNT# 10K_0402_5% 33_0402_5% 22P_0402_50V8J
A OPT@ CLK_PCI_LPBACK @ @ 1 A
2 1 2
2

Q13
OPTIMUS 0

1
2

2N7002E_SOT23-3 R220
G

OPT@ 0_0402_5% Pull high @ VGA side Reserve for EMI please close to UH4
PEG_CLKREQ#_R 1 3 1 OPT@ 2
UMA 1
PEG_CLKREQ# 22
D

S
1

R221 R222
for safe 2.2K_0402_5%
@
2.2K_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
SCHEMATIC, MB LA-7231P
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 14 of 57
5 4 3 2 1
 5 4 3 2 1

D D

U3C

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
4 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 4
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
4 DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 4
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
4 DMI_CTX_PRX_P2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 4
4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 4
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 4
4 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
R223 1 2 0_0402_5% DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
+3VS DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 +RTCVCC
DMI_CRX_PTX_P2 AY18
4 DMI_CRX_PTX_P2 DMI2TXP
5

DMI_CRX_PTX_P3 AU18
4 DMI_CRX_PTX_P3 DMI3TXP
AW16 FDI_INT
VCC

FDI_INT FDI_INT 4
39 PCH_PWROK 1 DSWODVREN R224 2 1 330K_0402_5%
IN1 SYS_PWROK +1.05VS_PCH FDI_FSYNC0
OUT 4 BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 4
2 R225 2 @ 1 330K_0402_5%
GND

54 VGATE IN2
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
U5 R226 49.9_0402_1% DSWODVREN - On Die DSW VR Enable
MC74VHC1G08DFT2G_SC70-5 RBIAS_CPY FDI_LSYNC0
1 2 BH21 AV14 FDI_LSYNC0 4 * H：Enable
3

C @ R227 750_0402_1% DMI2RBIAS FDI_LSYNC0 C

L：Disable
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 4
R228 2 1 10K_0402_5% SYS_PWROK within 500mil of the
PCH
A18 DSWODVREN
DSWVRMEN

System Power Management

not support Deep S4,S5 DPWROK mux with PWROK
Have internal PU SUSACK#_R C12 E22 PCH_RSMRST#_R check list1.0 P.42
SUSACK# DPWROK R230
0_0402_5%
5 XDP_DBRESET# 1 2 XDP_DBRESET#_R K3 SYS_RESET# WAKE# B9 WAKE# 1 2 PCH_PCIE_WAKE# 35,37,44
R231 R229 0_0402_5%
0_0402_5% +3VALW_PCH
SUSACK#_R 2 @ 1 SUSWARN#_R SYS_PWROK P12 N3 PCH_GPIO32
SYS_PWROK CLKRUN# / GPIO32 WAKE# R232 1 2 10K_0402_5%

PCH_PWROK 1 2 PCH_PWROK_R L22 G8 SUS_STAT# @ T15 PCH_GPIO29 R234 1 2 10K_0402_5%

R233 0_0402_5% PWROK SUS_STAT# / GPIO61
+3VS
L10 N14 SUSCLK R750 1 2 8.2K_0402_5%
APWROK SUSCLK / GPIO62 SUSCLK 39
@ T16
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PCH_GPIO32 R236 1 @ 2 10K_0402_5%
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 39
@ T17
39 PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4# EC team suggestion
RSMRST# SLP_S4# PM_SLP_S4# 39
R237 0_0402_5% South Bridge side must have
@ T18 pull-low 10K on this pin(GPIO32)
SUSWARN#_R K16 F4 PM_SLP_S3#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 39
+3VS
B PBTN_OUT#_R SLP_A# @ T64 Can be left NC when IAMT is not B
39 PBTN_OUT# 1 2 E20 PWRBTN# SLP_A# G10
R239 2 1 200_0402_5% PM_DRAM_PWRGD R238 0_0402_5% support on the platfrom
D2
39,46,48 ACIN 1 2 PCH_ACIN H20 G16 PM_SLP_SUS# @ T19 not support Deep S4,S5 can NC
ACPRESENT / GPIO31 SLP_SUS#
PCH EDS1.2 P.74
+3VALW_PCH RB751V-40_SOD323-2 @ T20
PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
R240 2 1 10K_0402_5% SUSWARN#_R

R241 2 1 200K_0402_5% PCH_ACIN RI# A10 K14 PCH_GPIO29

RI# SLP_LAN# / GPIO29
R242 2 1 10K_0402_5% PCH_GPIO72
COUGARPOINT_FCBGA989~D
R243 2 1 10K_0402_5% RI#

R244 2 1 10K_0402_5% PCH_RSMRST#_R

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 15 of 57
5 4 3 2 1
 5 4 3 2 1

D D

R246
100K_0402_5%
1 2

U3D
ENBKL J47 AP43
39 ENBKL L_BKLTEN SDVO_TVCLKINN
31 PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45

31 DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42

SDVO_STALLP AM40
PCH_LCD_CLK T40
31 PCH_LCD_CLK L_DDC_CLK
PCH_LCD_DATA K47 AP39
31 PCH_LCD_DATA L_DDC_DATA SDVO_INTN
CTRL_CLK SDVO_INTP AP40 SDVO_CTRLDATA strap pull high
T45
CTRL_DATA P39
L_CTRL_CLK at level shift page
2.37K_0402_1% L_CTRL_DATA
R247 2 1 LVDS_IBG AF37 P38 SDVO_SCLK
LVD_IBG SDVO_CTRLCLK SDVO_SCLK 33
AF36 M39 SDVO_SDATA
LVD_VBG SDVO_CTRLDATA SDVO_SDATA 33
+3VS
0_0402_5% LVD_VREF AE48
R248 LVD_VREFH
1 2 2.2K_0402_5% CTRL_CLK R249 2 1 AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
R250 1 2 2.2K_0402_5% CTRL_DATA AT40 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD 33
PCH_TXCLK- AK39
31 PCH_TXCLK- LVDSA_CLK#

LVDS
PCH_TXCLK+ AK40 AV42 PCH_DPB_N0 PCH_DPB_N0 33
31 PCH_TXCLK+ LVDSA_CLK DDPB_0N
AV40 PCH_DPB_P0 PCH_DPB_P0 33 HDMI D2
+3VS PCH_TXOUT0- DDPB_0P PCH_DPB_N1
31 PCH_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45 PCH_DPB_N1 33

Digital Display Interface

PCH_TXOUT1- AM47 AV46 PCH_DPB_P1 PCH_DPB_P1 33 HDMI D1
C 31 PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P C
R470 1 2 2.2K_0402_5% PCH_LCD_CLK PCH_TXOUT2- AK47 AU48 PCH_DPB_N2 PCH_DPB_N2 33
31 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
AJ48 AU47 PCH_DPB_P2 PCH_DPB_P2 33 HDMI D0
R471 1 LVDSA_DATA#3 DDPB_2P
2 2.2K_0402_5% PCH_LCD_DATA
DDPB_3N AV47 PCH_DPB_N3 PCH_DPB_N3 33
PCH_TXOUT0+ AN47 AV49 PCH_DPB_P3 PCH_DPB_P3 33 HDMI CLK
31 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ AM49
31 PCH_TXOUT1+ LVDSA_DATA1
PCH_TXOUT2+ AK49
31 PCH_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42

AF40 LVDSB_CLK#
+3VS AF39 AP47
LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
R251 1 2 2.2K_0402_5% PCH_CRT_CLK AH45 AT38
LVDSB_DATA#0 DDPC_HPD
AH47 LVDSB_DATA#1
R252 1 2 2.2K_0402_5% PCH_CRT_DATA AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
R253 1 2 150_0402_1% PCH_CRT_B AH49 BA47
LVDSB_DATA1 DDPC_2N
AF47 LVDSB_DATA2 DDPC_2P BA48
R254 1 2 150_0402_1% PCH_CRT_G AF43 BB47
LVDSB_DATA3 DDPC_3N
DDPC_3P BB49
R255 1 2 150_0402_1% PCH_CRT_R

PCH_CRT_B N48 M43

32 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
PCH_CRT_G P49 M36
32 PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
PCH_CRT_R T49
32 PCH_CRT_R CRT_RED

DDPD_AUXN AT45

CRT
PCH_CRT_CLK T39 AT43
32 PCH_CRT_CLK CRT_DDC_CLK DDPD_AUXP
PCH_CRT_DATA M40 BH41
32 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD
B B
DDPD_0N BB43
32 PCH_CRT_HSYNC PCH_CRT_HSYNC M47 BB45
PCH_CRT_VSYNC CRT_HSYNC DDPD_0P
32 PCH_CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
CRT_IREF T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
1

COUGARPOINT_FCBGA989~D
R256
1K_0402_0.5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 16 of 57
5 4 3 2 1
 5 4 3 2 1

U3E
+3VS AY7
NV_CE#0
NV_CE#1 AV7
RP1 BG26 AU3
PCI_PIRQA# TP1 NV_CE#2
8 1 BJ26 TP2 NV_CE#3 BG4
7 2 PCI_PIRQD# BH25
PCI_PIRQC# TP3
6 3 BJ16 TP4 NV_DQS0 AT10
5 4 PCI_PIRQB# BG16 BC8
TP5 NV_DQS1
AH38 TP6
8.2K_0804_8P4R_5% AH37 AU2
TP7 NV_DQ0 / NV_IO0
AK43 TP8 NV_DQ1 / NV_IO1 AT4
D RP2 D
AK45 TP9 NV_DQ2 / NV_IO2 AT3
8 1 PCH_GPIO55 C18 AT1
PCH_GPIO51 TP10 NV_DQ3 / NV_IO3
7 2 N30 TP11 NV_DQ4 / NV_IO4 AY3
6 3 PCH_GPIO5 H3 AT5
PCH_GPIO52 TP12 NV_DQ5 / NV_IO5
5 4 AH12 TP13 NV_DQ6 / NV_IO6 AV3

NVRAM
AM4 TP14 NV_DQ7 / NV_IO7 AV1
8.2K_0804_8P4R_5% AM5 BB1
TP15 NV_DQ8 / NV_IO8
Y13 TP16 NV_DQ9 / NV_IO9 BA3
RP3 K24 BB5
PCH_GPIO53 TP17 NV_DQ10 / NV_IO10
8 1 L24 TP18 NV_DQ11 / NV_IO11 BB3
7 2 PCH_GPIO2 AB46 BB7
PCH_GPIO4 TP19 NV_DQ12 / NV_IO12
6 3 AB45 TP20 NV_DQ13 / NV_IO13 BE8

RSVD
5 4 ODD_DA# BD4
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15 BF6
8.2K_0804_8P4R_5%
B21 TP21 NV_ALE AV5
R185 M20 AY1 DF_TVS
10K_0402_5% TP22 NV_CLE
AY16 TP23
1 OPT@ 2 VGA_ON BG46 TP24 NV_RCOMP AV10 DMI Termination Voltage

NV_RB# AT8 Set to Vcc when HIGH

DF_TVS
BE28 TP25 NV_RE#_WRB0 AY5 Set to Vss when LOW
BC30 TP26 NV_RE#_WRB1 BA2
R258 1 2 8.2K_0402_5% DGPU_HOLD_RST# BE32 TP27
R259 1
BJ32 TP28 NV_WE#_CK0 AT12 DG1.2 CRB1.0 PH 2.2K series 1K
2 100K_0402_5% PLT_RST# BC28 TP29 NV_WE#_CK1 BF3
BE30 TP30
BF32 +1.8VS
TP31 USB20_N0
BG32 TP32 USBP0N C24 USB20_N0 37
AV26 TP33 USBP0P A24 USB20_P0
USB20_P0 37 USB/B (Right side)

1
BB26 C25 USB20_N1
TP34 USBP1N USB20_N1 37
C
AU28 TP35 USBP1P B25 USB20_P1
USB20_P1 37 USB/B (Right side) R260
2.2K_0402_5%
C
AY30 TP36 USBP2N C26
AU26 TP37 USBP2P A26
AY26 K28

2
TP38 USBP3N DF_TVS
AV28 TP39 USBP3P H28 2 1 H_SNB_IVB# 5
AW30 E28 R261 1K_0402_5%
TP40 USBP4N
USBP4P D28
USBP5N C28 CLOSE TO THE BRANCHING POINT
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA#
PCI_PIRQB#
K40 PIRQA# USBP7N N28 Some PCH config not support USB port 6 & 7.
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 37
PCI_PIRQD# G38 PIRQD# USBP8P K30 USB20_P8
USB20_N9
USB20_P8 37 Mini Card (WLAN)
USBP9N G30 USB20_N9 37 +3VALW_PCH
DGPU_HOLD_RST# C46 REQ1# / GPIO50 USBP9P E30 USB20_P9
USB20_P9 37 Mini Card (3G)

USB
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 31
14,25,46,55 VGA_ON
VGA_ON E40 REQ3# / GPIO54 USBP10P A30 USB20_P10
USB20_P10 31 CMOS Camera (LVDS) USB_OC2#
RP4
Boot BIOS Strap bit1 BBS1 USBP11N L32 4 5
PCH_GPIO51 D47 K32 USB_OC5# 3 6
PCH_GPIO53 GNT1# / GPIO51 USBP11P USB20_N12 USB_OC3#
Boot BIOS E42 GNT2# / GPIO53 USBP12N G32 USB20_N12 37 2 7
PCH_GPIO55 F46 E32 USB20_P12 Mini Card (SIM card) USB_OC0# 1 8
Bit11 Bit10 Destination GNT3# / GPIO55 USBP12P USB20_P12 37
C32 USB20_N13
USBP13N USB20_N13 37
PCH_GPIO2 USBP13P A32 USB20_P13
USB20_P13 37 Bluetooth 10K_1206_8P4R_5%
0 1 Reserved G42 PIRQE# / GPIO2
GNT1#/ ODD_DA# G40
34 ODD_DA# PIRQF# / GPIO3
1 0 PCI PCH_GPIO4 C42 C33 USBRBIAS 1 2
GPIO51 PCH_GPIO5 D44
PIRQG# / GPIO4 USBRBIAS# R262 22.6_0402_1% RP5
PIRQH# / GPIO5
1 1 SPI Within 500 mils USB_OC1#
USB_OC4#
4 5
USBRBIAS B33 3 6
0 0 LPC T21 @ K10 USB_OC7# 2 7
B PME# USB_OC6# B
1 8
PLT_RST# C6 A14 USB_OC0#
5,35,38,39,44 PLT_RST# PLTRST# OC0# / GPIO59 USB_OC0# 37
K20 USB_OC1# 10K_1206_8P4R_5%
OC1# / GPIO40 USB_OC2#
OC2# / GPIO41 B17
CLK_PCI_LPBACK R263 2 1 22_0402_5% CLK_PCI0 H49 C16 USB_OC3#
14 CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
CLK_PCI_LPC R264 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
39 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
T22 @ CLK_PCI2 J48 A16 USB_OC5#
T23 @ CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 CLKOUT_PCI3 OC6# / GPIO10 D14
T24 @ CLK_PCI4 H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14

COUGARPOINT_FCBGA989~D
R265
0_0402_5%
2 @ 1
+3VS

+3VS
5

5
R266
VCC

PLT_RST# 1 100_0402_5%

VCC
IN1
OUT 4 1 OPT@ 2 PLTRST_VGA# 22
PLT_RST# 1 IN1
DGPU_HOLD_RST# 2 4
GND

IN2 OUT PLT_RST_BUF# 37

2

GND
IN2
1

1
R268 R269
3

U6 100K_0402_5% 100K_0402_5%
MC74VHC1G08DFT2G_SC70-5 OPT@ U7 3
OPT@ MC74VHC1G08DFT2G_SC70-5
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 17 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

R279 2 UMAO@ 1 10K_0402_5% OPTIMUS_EN#

R643 1 OPT@ 2 10K_0402_5%

+3VS
GPIO38
OPTIMUS_EN#
ODD_EN# R275 1 2 10K_0402_5%
D * OPTIMUS 0 EC_KBRST# R276 1 2 10K_0402_5% D

Non-OPTIMUS 1

GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
* H：On-Die PLL voltage regulator enable
L：On-Die PLL Voltage Regulator disable U3F

+3VALW_PCH PCH_GPIO0 T7 C40 ODD_EN#

BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 34
R485 1 @ 2 4.7K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69 @ T26
TACH1 / GPIO1 TACH5 / GPIO69
R272 2 @ 1 PCH_GPIO28 DGPU_HPD_INT# H36 C41 PCH_GPIO70 @ T27 +3VS
33 DGPU_HPD_INT# TACH2 / GPIO6 TACH6 / GPIO70
1K_0402_5%
39 EC_SCI# EC_SCI# E38 A40 PCH_GPIO71
TACH3 / GPIO7 TACH7 / GPIO71

2
Debug Port DG 1.2 PH 4.7K +3VALW_PCH EC_SMI# R273
39 EC_SMI# C10 GPIO8
Deep S4,S5 wake event signal +3VS
10K_0402_5%
PCH_GPIO12 C4
RTC alarm,Power BTN,GPIO27 LAN_PHY_PWR_CTRL / GPIO12

1
PCH_GPIO27 (Have internal Pull-High) 44 SMIB SMIB G2 GPIO15 A20GATE P4 GATEA20 39

1
Deep S4,S5 wake event signal +3VS R283 PCH_PECI_R @
No use PD to GND Check list1.0 P.70 Modify R03 PECI AU16 1 2 H_PECI 5,39

CPU/MISC
10K_0402_5% PCH_GPIO16 U2 0_0402_5% R274
SATA4GP / GPIO16 EC_KBRST#
RCIN# P5 EC_KBRST# 39

GPIO
C R277 PCH_GPIO27 DGPU_PWROK C
1 2 10K_0402_5% R841 D40 TACH0 / GPIO17 PROCPWRGD AY11 H_CPUPWRGD 5
+3VSDGPU 10K_0402_5%

6
OPT@ PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# 5
Q74A SCLOCK / GPIO22 THRMTRIP# R278 390_0402_5%

1
2

DMN66D0LDW-7_SOT363-6 PCH_GPIO24 E8 T14

R842 OPT@ GPIO24 / MEM_LED INIT3_3V# INIT3_3V
2
100K_0402_5% PCH_GPIO27 E16 GPIO27
3
+3VS This signal has weak internal
OPT@

1
PCH_GPIO28 P8 PU, can't pull low
1

R270 GPIO28
2 1 10K_0402_5% PCH_GPIO0 Q74B
NC_1 AH8
5 DMN66D0LDW-7_SOT363-6 BT_ON# K1
37 BT_ON# STP_PCI# / GPIO34
1 OPT@ AK11
C185 NC_2
K4
4

1U_0402_6.3V6K GPIO35
NC_3 AH10
R280 1 2 10K_0402_5% PCH_GPIO1 OPT@ ODD_DETECT# V8
2 34 ODD_DETECT# SATA2GP / GPIO36
NC_4 AK10 Intel schematic reviwe recommand.
R281 1 2 10K_0402_5% DGPU_HPD_INT# WWAN_OFF# M5
37 WWAN_OFF# SATA3GP / GPIO37
NC_5 P37
R282 1 2 10K_0402_5% PCH_GPIO16 If GPIO36,37 did not OPTIMUS_EN# N2 SLOAD / GPIO38
use, it can not PU and PCH_GPIO39 M3
reserved PD resistor SDATAOUT0 / GPIO39
R284 1 2 10K_0402_5% PCH_GPIO22 for MRC0.9. PCH_GPIO48 V13 BG2 @ T28
SDATAOUT1 / GPIO48 VSS_NCTF_15
R285 1 2 100K_0402_5% WWAN_OFF# WL_OFF# V3 BG48 @ T29
37 WL_OFF# SATA5GP / GPIO49 VSS_NCTF_16
R286 CRB1.0 PH200K to +3VS
1 2 200K_0402_5% ODD_DETECT# PCH_GPIO57 D6 GPIO57 VSS_NCTF_17 BH3 @ T30

R287 1 2 10K_0402_5% PCH_GPIO39 BH47 @ T31

VSS_NCTF_18
R288 1 2 10K_0402_5% BT_ON# T32 @ A4 BJ4 @ T33
VSS_NCTF_1 VSS_NCTF_19
B R289 B
1 2 10K_0402_5% PCH_GPIO48 T34 @ A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 @ T35

R290 1 2 10K_0402_5% WL_OFF# T36 @ A45 BJ45 @ T37

VSS_NCTF_3 VSS_NCTF_21

NCTF
T38 @ A46 BJ46 @ T39
VSS_NCTF_4 VSS_NCTF_22
Follow P5WE0 R02
T40 @ A5 BJ5 @ T41
VSS_NCTF_5 VSS_NCTF_23
T42 @ A6 BJ6 @ T43 +3VS
VSS_NCTF_6 VSS_NCTF_24
T44 @ B3 C2 @ T45
VSS_NCTF_7 VSS_NCTF_25

1
+3VALW_PCH
T46 @ B47 C48 @ T87 R567
R291 PCH_GPIO12 VSS_NCTF_8 VSS_NCTF_26
1 2 10K_0402_5% 10K_0402_5%
T47 @ BD1 D1 @ T48 X76@
R292 VSS_NCTF_9 VSS_NCTF_27
1 2 1K_0402_5% SMIB

2
T49 @ BD49 D49 @ T50 PCH_GPIO71
R293 VSS_NCTF_10 VSS_NCTF_28
1 2 10K_0402_5% PCH_GPIO57 CRB1.0 PH10K to +3VALW

2
GPIO24 Unmultiplexed T51 @ BE1 E1 @ T52
R294 VSS_NCTF_11 VSS_NCTF_29
1 2 10K_0402_5% PCH_GPIO24 NOTE: GPIO24 configuration R604
register bits are not cleared by T53 @ BE49 E49 @ T88 10K_0402_5%
VSS_NCTF_12 VSS_NCTF_30 X76@
CF9h reset event.
T54 @ BF1 F1 @ T55

1
VSS_NCTF_13 VSS_NCTF_31
T56 @ BF49 F49 @ T89
VSS_NCTF_14 VSS_NCTF_32

COUGARPOINT_FCBGA989~D
GPIO71
PCH_GPIO71
A A
VRAM 800 MHz 0
VRAM 900 MHz 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 18 of 57
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS_VCCP JP3 +1.05VS_PCH U3G POWER +3VS S0 Iccmax
PAD-OPEN 4x4m L1 Voltage Rail Voltage Current
@ 1300mA 4.7UH_LQM18FN4R7M00D_20% (A)
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001

1
10U_0805_6.3V6M
C188

1U_0402_6.3V6K
C189

1U_0402_6.3V6K
C190

1U_0402_6.3V6K
C187

0.01U_0402_16V7K
C191

0.1U_0402_10V7K
C192

10U_0805_6.3V6M
C193
AD21 C216

CRT
VCCCORE[3]

1
AD23 U47 10U_0805_6.3V6M
VCCCORE[4] VSSADAC @ V5REF
AF21 5 0.001

VCC CORE

2
VCCCORE[5]
AF23

2
D VCCCORE[6] D
AG21 VCCCORE[7]
AG23 V5REF_Sus 5 0.001
VCCCORE[8]
AG24 VCCCORE[9] 1mA VCCALVDS AK36 +3VS
AG26 VCCCORE[10]
AG27 AK37 Vcc3_3 3.3 0.266
VCCCORE[11] VSSALVDS
AG29 VCCCORE[12]
AJ23 VCCCORE[13]

LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VccADAC 3.3 0.001
AJ27 +1.8VS
VCCCORE[15] L2
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38
AJ31 0.1UH_MLF1608DR10KT_10%_1608 VccADPLLA 1.05 0.08
VCCCORE[17] +VCCTX_LVDS
60mA VCCTX_LVDS[3] AP36 2 1
+1.05VS_PCH

1
22U_0805_6.3V6M
AP37 0.1uH inductor, 200mA VccADPLLB 1.05 0.08
VCCTX_LVDS[4] C194 C195
AN19 VCCIO[28]

C196
0.01U_0402_16V7K 0.01U_0402_16V7K

2
VccCore 1.05 1.3
T57 @ +VCCAPLLEXP BJ22 VCCAPLLEXP +3VS
This pin can be left as no connect in VCC3_3[6] V33 VccDMI 1.05 0.042

HVCMOS
AN16
On-Die VR enabled mode (default). VCCIO[15]

1
AN17 VCCIO[16]
VccIO 1.05 2.925
V34 C197
VCC3_3[7]
0.1U_0402_10V7K

2
AN21 VCCIO[17]
VccASW 1.05 1.01
AN26 <BOM Structure>
VCCIO[18] VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
+1.05VS_PCH AP21 +1.05VS_PCH VccDSW 3.3 0.003
C VCCIO[20] C
AP23 VCCIO[21] VCCDMI[1] AT20
VccpNAND 1.8 0.19

1
DMI
10U_0805_6.3V6M
C198

1U_0402_6.3V6K
C199

1U_0402_6.3V6K
C200

1U_0402_6.3V6K
C201

1U_0402_6.3V6K
C202

AP24 VCCIO[22]
1

VCCIO
C203
AP26 20mA AB36 1U_0402_6.3V6K VccRTC 3.3 6 uA

2
VCCIO[23] VCCIO[1]
2

AT24 VCCIO[24] VccSus3_3 3.3 0.119

AN33 VCCIO[25] VccSusHDA 3.3 / 1.5 0.01
AN34 VCCIO[26] VCCPNAND[1] AG16
+3VS +1.8VS
VccVRM 1.8 / 1.5 0.16

NAND / SPI
BH29 VCC3_3[3] 190mA VCCPNAND[2] AG17
1

C205 VccCLKDMI 1.05 0.02

0.1U_0402_10V7K AJ16
VCCPNAND[3]

1
C206
2

+VCCAFDI_VRM AP16 0.1U_0402_10V7K VccSSC 1.05 0.095

VCCVRM[2]
AJ17

2
VCCPNAND[4]
T77 @ +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VCCFDIPLL
+1.05VS_PCH
AP17 VccALVDS 3.3 0.001
VCCIO[27]
V1
FDI

20mA VCCSPI +3VS

AU20 VccTX_LVDS 1.8 0.06
VCCDMI[2]
1

1
C795 C208
B 1U_0402_6.3V6K COUGARPOINT_FCBGA989~D 1U_0402_6.3V6K B
2

+VCCAFDI_VRM 2
+1.5VS

R307 2 1 0_0603_5% +VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 19 of 57
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS R309 +1.05VS_PCH R310 VCC3_3 = 266mA detal waiting for newest spec
0_0805_5% 0_0603_5%
1 @ 2 2 @ 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L3 +5VALW R751
10UH_LB2012T100MR_20% 0_0603_5%
1 2 +3VS_VCC_CLKF33 +3VALW_PCH 2 @ 1
U3J POWER

1
+1.05VS_PCH

10U_0805_10V4Z
C209

1U_0402_6.3V6K
C210
Q64
AO3413L_SOT23-3 +5VALW_PCH
AD49 VCCACLK VCCIO[29] N26

1
2

1
C211 P26 3 1

D
0.1U_0402_10V7K VCCIO[30] C213
T16 3mA

2
VCCDSW3_3

0.1U_0402_10V7K
C816

20K_0402_5%
R752
D
P28 1U_0402_6.3V6K D

G
2
VCCIO[31]

1
1

2
T78 @ +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]

VCCIO[33] T29 35,46 PCH_PWR_EN#

+3VS_VCC_CLKF33 +3VALW_PCH 2
T38

2
VCC3_3[5]
T23
T79 @ +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2

0.1U_0402_10V7K
C217

0.1U_0402_10V7K
C218
VCCSUS3_3[8] T24 Place C217 near T23 pin

1
+5VALW_PCH +3VALW_PCH
+1.05VS_PCH AL29 VCCIO[14] Place C218 near P24 pin
VCCSUS3_3[9] V23

USB

2
T80 @ +VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] R319 D3
P24 100_0402_5% RB751V-40_SOD323-2
VCCSUS3_3[6] +1.05VS_PCH
AA19

1
VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26
+1.05VS_PCH AA21 1010mA
VCCASW[2]

1
AA24 1mA V5REF_SUS M26 +PCH_V5REF_SUS C219
VCCASW[3]

Clock and Miscellaneous

0.1U_0603_25V7K

2
1

1
22U_0805_6.3V6M
C220

22U_0805_6.3V6M
C221
AA26 VCCASW[4]
AN23 +VCCA_USBSUS @ T81
DCPSUS[4]
AA27

2
VCCASW[5]
VCCSUS3_3[1] AN24 +3VALW_PCH
AA29 VCCASW[6]
+5VS +3VS
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
C +3VALW_PCH C

1
1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225
AC27 R323 D4
VCCASW[9] 100_0402_5% RB751V-40_SOD323-2
N20

PCI/GPIO/LPC
VCCSUS3_3[2]
AC29 1
2

2
VCCASW[10]
N22

1
VCCSUS3_3[3] C226 +PCH_V5REF_RUN
AC31 VCCASW[11]
P20 1U_0402_6.3V6K
VCCSUS3_3[4]

1
2
AD29 VCCASW[12]
P22 C227
VCCSUS3_3[5] 1U_0603_10V6K
AD31

2
VCCASW[13] +3VS
+1.05VS_PCH W21 AA16
L5 VCCASW[14] VCC3_3[1]

1
0.1U_0402_10V7K

0.1U_0402_10V7K
C233

0.1U_0402_10V7K
C228
10UH_LB2012T100MR_20% W23 W16 Place C228 near AA16.W16 pin
VCCASW[15] VCC3_3[8]

C234
1 2 +1.05VS_VCCA_A_DPL
Place C233 near T34 pin
W24 T34

2
VCCASW[16] VCC3_3[4] Place C234 near AJ2 pin
1 2 +1.05VS_VCCA_B_DPL W26
L6 VCCASW[17]
220U_B2_2.5VM_R35
C229

1U_0402_6.3V6K
C230

220U_B2_2.5VM_R35
C231

1U_0402_6.3V6K
C232

10UH_LB2012T100MR_20% W29 VCCASW[18]

1

1
1

+ + W31 AJ2
VCCASW[19] VCC3_3[2] +1.05VS_PCH
W33
2

VCCASW[20]
VCCIO[5] AF13

1
+VCCRTCEXT N16 DCPRTC C235
VCCIO[12] AH13
1

C236 1U_0402_6.3V6K

2
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14
VCCVRM[4] VCCIO[13]
2

B B
VCCIO[6] AF14
+1.05VS_VCCA_A_DPL BD47 VCCADPLLA 80mA

SATA
AK1 +VCCSATAPLL @ T82
+1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
BF47 VCCADPLLB 80mA
+1.05VS_PCH
AF11 +VCCAFDI_VRM
VCCVRM[1]
AF17 VCCIO[7]
AF33 +1.05VS_PCH
+1.05VS_PCH VCCIO[8] 55mA
1U_0402_6.3V6K
C237

AF34 VCCIO[9] VCCIO[2] AC16

1

AG34 VCCIO[11]
VCCIO[3] AC17
1

1
+1.05VS_PCH
1U_0402_6.3V6K
C238

C241
2

AG33 AD17 1U_0402_6.3V6K

VCCIO[10] 95mA VCCIO[4]
1
1U_0402_6.3V6K
2

2
C240

+VCCSST V16 +1.05VS_PCH

2

DCPSST
0.1U_0402_10V7K
1

C242

T83 @ +1.05VM_VCCSUS T17 T21 +VCCME_22 R335 2 1 0_0603_5%

DCPSUS[1] VCCASW[22]
V19
2

DCPSUS[2]
MISC

+1.05VS_PCH V21 +VCCME_23 R336 2 1 0_0603_5%

VCCASW[23]
CPU

+V_CPU_IO BJ8 V_PROC_IO 1mA +VCCME_21 R338

VCCASW[21] T19 2 1 0_0603_5%
1

+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C244

0.1U_0402_10V7K
C245

0.1U_0402_10V7K
C246

A22 P32 +VCCSUSHDA R339 2 1 0_0603_5%

RTC

10mA VCCSUSHDA
2

VCCRTC
HDA
1U_0402_6.3V6K
C247

0.1U_0402_10V7K
C248

0.1U_0402_10V7K
C249
1

COUGARPOINT_FCBGA989~D C250
A 0.1U_0402_16V4Z A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/09/28 2011/09/28 Title
Issued Date Deciphered Date SCHEMATIC, MB LA-7231P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 20 of 57
5 4 3 2 1
 5 4 3 2 1

U3I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
D U3H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

COUGARPOINT_FCBGA989~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 21 of 57
5 4 3 2 1
 A B C D E

U8A

4 PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1 R514 1 OPT11@2 100K_0402_5% GPIO I/O FUNCTION

PEX_RX0 GPIO0
4 PEG_HTX_C_GRX_N0 AN17 PEX_RX0_N GPIO1 K2 VGA_HDMI_DET 33
4 PEG_HTX_C_GRX_P1 AN19 PEX_RX1 GPIO2 K3
4 PEG_HTX_C_GRX_N1 AP19 PEX_RX1_N GPIO3 H3 GPIO1 IN HPD_C
4 PEG_HTX_C_GRX_P2 AR19 PEX_RX2 GPIO4 H2
4 PEG_HTX_C_GRX_N2 AR20 PEX_RX2_N GPIO5 H1 GPU_VID0 39,55
4 PEG_HTX_C_GRX_P3 AP20 PEX_RX3 GPIO6 H4 GPU_VID1 39,55 GPIO5 OUT GPU_VID0
4 PEG_HTX_C_GRX_N3 AN20 PEX_RX3_N GPIO7 H5 GPU_VID2 55
4 PEG_HTX_C_GRX_P4 AN22 H6 R340 2 OPT@ 1 10K_0402_5% +3VSDGPU
PEX_RX4 GPIO8 R341 2 OPT@
4 PEG_HTX_C_GRX_N4 AP22 PEX_RX4_N GPIO9 J7 1 10K_0402_5% GPIO6 OUT GPU_VID1
4 PEG_HTX_C_GRX_P5 AR22 PEX_RX5 GPIO10 K4
4 PEG_HTX_C_GRX_N5 AR23 K5 R762 0_0402_5%
PEX_RX5_N GPIO11 +3VSDGPU
2 OPT@ 1 R342 GPIO7 OUT GPU_VID2

GPIO
4 PEG_HTX_C_GRX_P6 AP23 PEX_RX6 GPIO12 H7
1 10K_0402_5% 1
4 PEG_HTX_C_GRX_N6 AN23 PEX_RX6_N GPIO13 J4
4 PEG_HTX_C_GRX_P7 AN25 PEX_RX7 GPIO14 J6 2 OPT@ 1
4 PEG_HTX_C_GRX_N7 AP25 L1 Q68 GPIO8 IN OVERT
PEX_RX7_N GPIO15

2
G
4 PEG_HTX_C_GRX_P8 AR25 L2 R763 2N7002E_SOT23-3
PEX_RX8 GPIO16 0_0402_5% OPT@
4 PEG_HTX_C_GRX_N8 AR26 PEX_RX8_N GPIO17 L4
4 PEG_HTX_C_GRX_P9 AP26 M4 2 @ 1 NV_PERFORMANCE_R 3 1 NV_PERFORMANCE 39 GPIO9 IN ALERT
PEX_RX9 GPIO18

D
4 PEG_HTX_C_GRX_N9 AN26 PEX_RX9_N GPIO19 L7
AN28 L5 Replace GPIO 12 with GPIO 18.
4 PEG_HTX_C_GRX_P10 PEX_RX10 GPIO20 When : B stage platforms
4 PEG_HTX_C_GRX_N10 AP28 PEX_RX10_N GPIO21 K6
+3VSDGPU
GPIO12 IN Reserve for VPS
4 PEG_HTX_C_GRX_P11 AR28 PEX_RX11 GPIO22 L6
4 PEG_HTX_C_GRX_N11 AR29 PEX_RX11_N GPIO23 M6
4 PEG_HTX_C_GRX_P12 AP29 M7 Q16A GPIO18 IN Reserve for VPS
PEX_RX12 GPIO24

2
4 PEG_HTX_C_GRX_N12 AN29 DMN66D0LDW-7_SOT363-6
PEX_RX12_N OPT@
4 PEG_HTX_C_GRX_P13 AN31 PEX_RX13 MIOA_D0_NC N1
4 PEG_HTX_C_GRX_N13 AP31 P4 I2CS_SCL 1 6
PEX_RX13_N MIOA_D1_NC EC_SMB_CK2 14,39
4 PEG_HTX_C_GRX_P14 AR31 PEX_RX14 MIOA_D2_NC P1
4 PEG_HTX_C_GRX_N14 AR32 PEX_RX14_N MIOA_D3_NC P2
4 PEG_HTX_C_GRX_P15 AR34 PEX_RX15 MIOA_D4_NC P3
AP34 T3 +3VSDGPU
4 PEG_HTX_C_GRX_N15 PEX_RX15_N MIOA_D5_NC
MIOA_D6_NC T2
T1 Q16B
MIOA_D7_NC

5
PEG_GTX_C_HRX_P0 C251 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P0 AL17 U4 DMN66D0LDW-7_SOT363-6
PEG_GTX_C_HRX_N0 C252 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N0 AM17 PEX_TX0 MIOA_D8_NC OPT@
1 2 PEX_TX0_N MIOA_D9_NC U1

PCI EXPRESS
PEG_GTX_C_HRX_P1 C253 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P1 AM18 U2 I2CS_SDA 4 3
PEX_TX1 MIOA_D10_NC EC_SMB_DA2 14,39
PEG_GTX_C_HRX_N1 C254 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N1 AM19 U3
PEG_GTX_C_HRX_P2 C255 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P2 AL19 PEX_TX1_N MIOA_D11_NC
1 2 PEX_TX2 MIOA_D12_NC R6
PEG_GTX_C_HRX_N2 C256 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N2 AK19 T6

DVO
PEG_GTX_C_HRX_P3 C257 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P3 AL20 PEX_TX2_N MIOA_D13_NC
1 2 PEX_TX3 MIOA_D14_NC N6
PEG_GTX_C_HRX_N3 C258 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N3 AM20 +3VSDGPU
PEG_GTX_C_HRX_P4 C259 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P4 AM21 PEX_TX3_N
1 2 PEX_TX4 MIOB_D0_NC Y1
PEG_GTX_C_HRX_N4 C260 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N4 AM22 Y2 I2CS_SCL R343 1 OPT@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_P5 C261 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P5 AL22 PEX_TX4_N MIOB_D1_NC I2CS_SDA R344 OPT@ 2.2K_0402_5%
1 2 PEX_TX5 MIOB_D2_NC Y3 1 2
2 PEG_GTX_C_HRX_N5 C262 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N5 AK22 I2CH_SCL R345 OPT@ 2.2K_0402_5% 2
4 PEG_GTX_C_HRX_N[0..15] 1 2 PEX_TX5_N MIOB_D3_NC AB3 1 2
PEG_GTX_C_HRX_P6 C263 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P6 AL23 AB2 I2CH_SDA R346 1 OPT@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_N6 C264 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N6 AM23 PEX_TX6 MIOB_D4_NC I2CB_SCL R347 OPT@ 2.2K_0402_5%
1 2 PEX_TX6_N MIOB_D5_NC AB1 1 2
4 PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_P7 C265 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P7 AM24 AC4 I2CB_SDA R348 1 OPT@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_N7 C266 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N7 AM25 PEX_TX7 MIOB_D6_NC I2CC_SCL R349 OPT@ 2.2K_0402_5%
1 2 PEX_TX7_N MIOB_D7_NC AC1 1 2
PEG_GTX_C_HRX_P8 C267 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P8 AL25 AC2 I2CC_SDA R350 1 OPT@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_N8 C268 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N8 AK25 PEX_TX8 MIOB_D8_NC
1 2 PEX_TX8_N MIOB_D9_NC AC3
PEG_GTX_C_HRX_P9 C269 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P9 AL26 AE3 I2CA_SCL R351 1 OPT@ 2 2.2K_0402_5%
PEG_GTX_C_HRX_N9 C270 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N9 AM26 PEX_TX9 MIOBD_10_NC I2CA_SDA R352 1 OPT@
1 2 PEX_TX9_N MIOB_D11_NC AE2 2 2.2K_0402_5%
PEG_GTX_C_HRX_P10 C271 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P10AM27 U6
PEG_GTX_C_HRX_N10 C272 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N10AM28 PEX_TX10 MIOB_D12_NC
1 2 PEX_TX10_N MIOB_D13_NC W6
PEG_GTX_C_HRX_P11 C273 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P11 AL28 Y6
PEG_GTX_C_HRX_N11 C274 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N11 AK28 PEX_TX11 MIOB_D14_NC
1 2 PEX_TX11_N
PEG_GTX_C_HRX_P12 C275 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P12 AK29 N3
PEG_GTX_C_HRX_N12 C276 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N12 AL29 PEX_TX12 MIOA_HSYNC_NC
1 2 PEX_TX12_N MIOA_VSYNC_NC L3
PEG_GTX_C_HRX_P13 C277 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P13AM29
PEG_GTX_C_HRX_N13 C278 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N13AM30 PEX_TX13
1 2 PEX_TX13_N MIOB_HSYNC_NC W1
PEG_GTX_C_HRX_P14 C279 1 2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P14AM31 W2
PEG_GTX_C_HRX_N14 C280 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N14AM32 PEX_TX14 MIOB_VSYNC_NC
1 2 PEX_TX14_N
PEG_GTX_C_HRX_P15 C281 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_P15 AN32
PEG_GTX_C_HRX_N15 C282
1
1
2
2 OPT@ 0.1U_0402_10V7K PEG_GTX_HRX_N15 AP32 PEX_TX15 MIOA_DE_NC N2
P5
External Spread Spectrum OSC_OUT R356 1 @ 2 22_0402_5% XTAL_OUTBUFF
PEX_TX15_N MIOA_CTL3_NC
MIOA_VREF_NC N5

1
U9
Y5 1 6 R357
MIOB_DE_NC REFOUT VSS
+3VSDGPU 1 OPT@ 2 14 CLK_PEG_VGA AR16 PEX_REFCLK MIOB_CTL3_NC W3 10K_0402_5%
R358 10K_0402_5% AR17 AF1 2 5 OSC_SPREAD OPT@
14 CLK_PEG_VGA# PEX_REFCLK_N MIOB_VREF_NC XOUT MODOUT
14 PEG_CLKREQ# AR13

2
PEX_CLKREQ_N R359 1 OPT@
MIOA_CLKIN_NC N4 2 10K_0402_5% OSC_OUT 3 XIN/CLKIN VDD 4 +3VSDGPU
AJ17 PEX_TSTCLK_OUT MIOA_CLKOUT_NC R4

1
2 OPT@ 1 AJ18 PEX_TSTCLK_OUT_N
OSC_SPREAD R361 1 @ 2 22_0402_5% XTAL_SSIN
R360 200_0402_1% AE1 R362 1 OPT@ 2 10K_0402_5% ASM3P2872AF-06OR_TSOT-23-6 C283
MIOB_CLKIN_NC

1
V4 @ 0.1U_0402_16V4Z

2
3 MIOB_CLKOUT_NC @ 3
17 PLTRST_VGA# AM16 PEX_RST_N
2 OPT@ 1 AG21 PEX_TERMP MIOA_CLKOUT_NC_N T4 R364
L8 R365 2.49K_0402_1% W4 10K_0402_5%
BLM18PG300SN1D_2P MIOB_CLKOUT_NC_N OPT@

2
+1.05VSDGPU OPT@ under GPU
+GPU_PLLVDD
150mA MIOACAL_PD_VDDQ_NC U5
2 1 AE9 PLLVDD MIOACAL_PU_GND_NC T5 If External Spread Spectrum not stuff then stuff resistor
OPT@ OPT@ @ OPT@ OPT@ OPT@ OPT@ AF9 AA7
SP_PLLVDD MIOBCAL_PD_VDDQ_NC
1

MIOBCAL_PU_GND_NC AA6
4700P_0402_25V7K
22U_0805_6.3V6M

10U_0603_6.3V6M
C284

C285

C286

C287

C288

C289

C290
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AD9 VID_PLLVDD
CLK
2

XTALIN B1
XTALOUT XTAL_IN
B2 XTAL_OUT DACA_RED AM15
DACA_GREEN AM14
XTAL_OUTBUFFD1 AL14
XTAL_SSIN XTAL_OUTBUFF DACA_BLUE
D2 XTAL_SSIN
DACA_HSYNC AM13
DACA_VSYNC AL13

I2CS_SCL E2 AJ12 R367 1 OPT@ 2 10K_0402_5%

I2CS_SDA I2CS_SCL DACA_VDD @ C814 0.1U_0402_16V4Z
E1 I2CS_SDA DACA_VREF AK12 1 2

I2CC_SCL E3
DACA_RSET AK13 @ R744 1 2 124_0402_1%
Option Component
I2CC_SDA I2CC_SCL
E4 I2CC_SDA DACB_RED AK4
DACs

DACB_GREEN AL4
I2CB_SCL G3 AJ4 U8
XTALOUT @ XTALIN I2CB_SDA I2CB_SCL DACB_BLUE
I2C

G2 I2CB_SDA
R370 1M_0402_5% AM1
I2CA_SCL DACB_HSYNC
G1 I2CA_SCL DACB_VSYNC AM2
I2CA_SDA G4 I2CA_SDA R368 2 OPT@ 1 10K_0402_5%
2 1 DACB_VDD AG7
I2CH_SCL F6 AK6 @ C296 1 2 0.1U_0402_16V4Z N12P-GV-B-A1_BGA973
4 Y3 I2CH_SDA I2CH_SCL DACB_VREF @ R369 1 4
G6 I2CH_SDA DACB_RSET AH7 2 124_0402_1% GV@
1

27MHZ_16PF_X5H027000FG1H SA00004JO10
C297 OPT@ C298
22P_0402_50V8J 22P_0402_50V8J N12P-GS-A1_BGA973 N12P-GV-B-A1_BGA973: SA00004GY00
2

OPT@ OPT@ GS@ N12P-GV-OP-B-A1_BGA973: SA00004JO10

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BL B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 04, 2011 Sheet 22 of 57
A B C D E
 A

VRAM Interface 27

27
MDA[15..0]

MDA[31..16]
MDA[15..0]

MDA[31..16] 29 MDC[15..0]
MDC[15..0]

MDC[31..16]
MDA[47..32] 29 MDC[31..16]
28 MDA[47..32] MDC[47..32]
MDA[63..48] 30 MDC[47..32]
28 MDA[63..48] MDC[63..48]
30 MDC[63..48]

U8B U8C
CMDA[30..0] 27,28 CMDC[30..0] 29,30
Part 2 of 7 U30 CMDA0 Part 3 of 7 F18 CMDC0
MDA0 FBA_CMD0 CMDA1 MDC0 FBC_CMD0 CMDC1
L32 FBA_D0 FBA_CMD1 V30 B13 FBC_D0 FBC_CMD1 E19
MDA1 N33 U31 CMDA2 MDC1 D13 D18 CMDC2
MDA2 FBA_D1 FBA_CMD2 CMDA3 MDC2 FBC_D1 FBC_CMD2 CMDC3
L33 FBA_D2 FBA_CMD3 V32 A13 FBC_D2 FBC_CMD3 C17
MDA3 N34 T35 CMDA4 MDC3 A14 F19 CMDC4
MDA4 FBA_D3 FBA_CMD4 CMDA5 MDC4 FBC_D3 FBC_CMD4 CMDC5
N35 FBA_D4 FBA_CMD5 U33 C16 FBC_D4 FBC_CMD5 C19
MDA5 P35 W32 CMDA6 MDC5 B16 B17 CMDC6
MDA6 FBA_D5 FBA_CMD6 CMDA7 MDC6 FBC_D5 FBC_CMD6 CMDC7
P33 FBA_D6 FBA_CMD7 W33 A17 FBC_D6 FBC_CMD7 E20
MDA7 P34 W31 CMDA8 MDC7 D16 B19 CMDC8
MDA8 FBA_D7 FBA_CMD8 CMDA9 MDC8 FBC_D7 FBC_CMD8 CMDC9
K35 FBA_D8 FBA_CMD9 W34 C13 FBC_D8 FBC_CMD9 D20
MDA9 K33 U34 CMDA10 MDC9 B11 A19 CMDC10
MDA10 FBA_D9 FBA_CMD10 CMDA11 MDC10 FBC_D9 FBC_CMD10 CMDC11
K34 FBA_D10 FBA_CMD11 U35 C11 FBC_D10 FBC_CMD11 D19
MDA11 H33 U32 CMDA12 MDC11 A11 C20 CMDC12
MDA12 FBA_D11 FBA_CMD12 CMDA13 MDC12 FBC_D11 FBC_CMD12 CMDC13
G34 FBA_D12 FBA_CMD13 T34 C10 FBC_D12 FBC_CMD13 F20
MDA13 G33 T33 CMDA14 MDC13 C8 B20 CMDC14
MDA14 FBA_D13 FBA_CMD14 CMDA15 MDC14 FBC_D13 FBC_CMD14 CMDC15
E34 FBA_D14 FBA_CMD15 W30 B8 FBC_D14 FBC_CMD15 G21
MDA15 E33 AB30 CMDA16 MDC15 A8 F22 CMDC16
MDA16 FBA_D15 FBA_CMD16 CMDA17 MDC16 FBC_D15 FBC_CMD16 CMDC17
G31 FBA_D16 FBA_CMD17 AA30 E8 FBC_D16 FBC_CMD17 F24
MDA17 F30 AB31 CMDA18 MDC17 F8 F23 CMDC18
MDA18 FBA_D17 FBA_CMD18 CMDA19 MDC18 FBC_D17 FBC_CMD18 CMDC19
G30 FBA_D18 FBA_CMD19 AA32 F10 FBC_D18 FBC_CMD19 C25
MDA19 G32 AB33 CMDA20 MDC19 F9 C23 CMDC20
MDA20 FBA_D19 FBA_CMD20 CMDA21 MDC20 FBC_D19 FBC_CMD20 CMDC21
K30 FBA_D20 FBA_CMD21 Y32 F12 FBC_D20 FBC_CMD21 F21
MDA21 K32 Y33 CMDA22 MDC21 D8 E22 CMDC22
MDA22 FBA_D21 FBA_CMD22 CMDA23 MDC22 FBC_D21 FBC_CMD22 CMDC23
H30 FBA_D22 FBA_CMD23 AB34 D11 FBC_D22 FBC_CMD23 D21
MDA23 K31 AB35 CMDA24 MDC23 E11 A23 CMDC24
MDA24 FBA_D23 FBA_CMD24 CMDA25 MDC24 FBC_D23 FBC_CMD24 CMDC25
L31 FBA_D24 FBA_CMD25 Y35 D12 FBC_D24 FBC_CMD25 D22
MDA25 L30 W35 CMDA26 MDC25 E13 B23 CMDC26

MEMORY INTERFACE C
MEMORY INTERFACE

MDA26 FBA_D25 FBA_CMD26 CMDA27 MDC26 FBC_D25 FBC_CMD26 CMDC27

M32 FBA_D26 FBA_CMD27 Y34 F13 FBC_D26 FBC_CMD27 C22
MDA27 N30 Y31 CMDA28 MDC27 F14 B22 CMDC28
MDA28 FBA_D27 FBA_CMD28 CMDA29 MDC28 FBC_D27 FBC_CMD28 CMDC29
M30 FBA_D28 FBA_CMD29 Y30 F15 FBC_D28 FBC_CMD29 A22
MDA29 P31 W29 CMDA30 MDC29 E16 A20 CMDC30
MDA30 FBA_D29 FBA_CMD30 MDC30 FBC_D29 FBC_CMD30
R32 FBA_D30 FBA_CMD31 Y29 F16 FBC_D30 FBC_CMD31 G20
MDA31 R30 MDC31 F17
FBA_D31 DQMA[3..0] 27 FBC_D31 DQMC[3..0] 29
MDA32 AG30 P32 DQMA0 MDC32 D29 A16 DQMC0
MDA33 FBA_D32 FBA_DQM0 DQMA1 MDC33 FBC_D32 FBC_DQM0 DQMC1
AG32 FBA_D33 FBA_DQM1 H34 F27 FBC_D33 FBC_DQM1 D10
MDA34 AH31 J30 DQMA2 MDC34 F28 F11 DQMC2
MDA35 FBA_D34 FBA_DQM2 DQMA3 MDC35 FBC_D34 FBC_DQM2 DQMC3
AF31 FBA_D35 FBA_DQM3 P30 DQMA[7..4] 28 E28 FBC_D35 FBC_DQM3 D15 DQMC[7..4] 30
MDA36 AF30 AF32 DQMA4 MDC36 D26 D27 DQMC4
MDA37 FBA_D36 FBA_DQM4 DQMA5 MDC37 FBC_D36 FBC_DQM4 DQMC5
AE30 FBA_D37 FBA_DQM5 AL32 F25 FBC_D37 FBC_DQM5 D34
MDA38 AC32 AL34 DQMA6 MDC38 D24 A34 DQMC6
MDA39 FBA_D38 FBA_DQM6 DQMA7 MDC39 FBC_D38 FBC_DQM6 DQMC7
AD30 FBA_D39 FBA_DQM7 AF35 E25 FBC_D39 FBC_DQM7 D28
MDA40 AN33 MDC40 E32
FBA_D40 DQSA#[3..0] 27 FBC_D40 DQSC#[3..0] 29
MDA41 AL31 L35 DQSA#0 MDC41 F32 B14 DQSC#0
FBA_D41 FBA_DQS_RN0 FBC_D41 FBC_DQS_RN0
A

MDA42 AM33 G35 DQSA#1 MDC42 D33 B10 DQSC#1

MDA43 FBA_D42 FBA_DQS_RN1 DQSA#2 MDC43 FBC_D42 FBC_DQS_RN1 DQSC#2
AL33 FBA_D43 FBA_DQS_RN2 H31 E31 FBC_D43 FBC_DQS_RN2 D9
1 MDA44 AK30 N32 DQSA#3 MDC44 C33 E14 DQSC#3
DQSA#[7..4] 28 DQSC#[7..4] 30
1

MDA45 FBA_D44 FBA_DQS_RN3 DQSA#4 MDC45 FBC_D44 FBC_DQS_RN3 DQSC#4

AK32 FBA_D45 FBA_DQS_RN4 AD32 F29 FBC_D45 FBC_DQS_RN4 F26
MDA46 AJ30 AJ31 DQSA#5 MDC46 D30 D31 DQSC#5
MDA47 FBA_D46 FBA_DQS_RN5 DQSA#6 MDC47 FBC_D46 FBC_DQS_RN5 DQSC#6
AH30 FBA_D47 FBA_DQS_RN6 AJ35 E29 FBC_D47 FBC_DQS_RN6 A31
MDA48 AH33 AC34 DQSA#7 MDC48 B29 A26 DQSC#7
MDA49 FBA_D48 FBA_DQS_RN7 MDC49 FBC_D48 FBC_DQS_RN7
AH35 FBA_D49 DQSA[3..0] 27 C31 FBC_D49 DQSC[3..0] 29
MDA50 AH34 L34 DQSA0 MDC50 C29 C14 DQSC0
MDA51 FBA_D50 FBA_DQS_WP0 DQSA1 MDC51 FBC_D50 FBC_DQS_WP0 DQSC1
AH32 FBA_D51 FBA_DQS_WP1 H35 B31 FBC_D51 FBC_DQS_WP1 A10
MDA52 AJ33 J32 DQSA2 MDC52 C32 E10 DQSC2
MDA53 FBA_D52 FBA_DQS_WP2 DQSA3 MDC53 FBC_D52 FBC_DQS_WP2 DQSC3
AL35 FBA_D53 FBA_DQS_WP3 N31 DQSA[7..4] 28 B32 FBC_D53 FBC_DQS_WP3 D14 DQSC[7..4] 30
MDA54 AM34 AE31 DQSA4 MDC54 B35 E26 DQSC4
MDA55 FBA_D54 FBA_DQS_WP4 DQSA5 MDC55 FBC_D54 FBC_DQS_WP4 DQSC5
AM35 FBA_D55 FBA_DQS_WP5 AJ32 B34 FBC_D55 FBC_DQS_WP5 D32
MDA56 AF33 AJ34 DQSA6 MDC56 A29 A32 DQSC6
MDA57 FBA_D56 FBA_DQS_WP6 DQSA7 MDC57 FBC_D56 FBC_DQS_WP6 DQSC7
AE32 FBA_D57 FBA_DQS_WP7 AC33 B28 FBC_D57 FBC_DQS_WP7 B26
MDA58 AF34 MDC58 A28
MDA59 FBA_D58 MDC59 FBC_D58
AE35 FBA_D59 FBA_WCK0 P29 C28 FBC_D59 FBC_WCK0 G14
MDA60 AE34 R29 MDC60 C26 G15
MDA61 FBA_D60 FBA_WCK0_N MDC61 FBC_D60 FBC_WCK0_N
AE33 FBA_D61 FBA_WCK1 L29 D25 FBC_D61 FBC_WCK1 G11
MDA62 AB32 M29 MDC62 B25 G12
MDA63 FBA_D62 FBA_WCK1_N MDC63 FBC_D62 FBC_WCK1_N
AC35 FBA_D63 FBA_WCK2 AG29 A25 FBC_D63 FBC_WCK2 G27
FBA_WCK2_N AH29 FBC_WCK2_N G28
+FB_PLLAVDD_0 AG27 AD29 +1.5VSDGPU G24
FB_DLLAVDD_0 FBA_WCK3 FBC_WCK3
AF27 FB_PLLAVDD_0 FBA_WCK3_N AE29 2 OPT@ 1 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25
40.2_0402_1% R371
+FB_PLLAVDD_1 J19 2 OPT@ 1 L27
FB_DLLAVDD_1 40.2_0402_1% R372 FBCAL_PU_GND
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 27 FBC_CLK0 E17 CLKC0 29
FBA_CLK0_N T31 CLKA0# 27 2 OPT@ 1 M27 FBCAL_TERM_GND FBC_CLK0_N D17 CLKC0# 29
J27 60.4_0402_1% R373
FBA_DEBUG0 T30 FB_VREF_NC FBB_DEBUG0
FBA_DEBUG0 FBA_CLK1 AC31 CLKA1 28 G19 FBC_DEBUG0 FBC_CLK1 D23 CLKC1 30
FBA_DEBUG1 T29 AC30 CLKA1# 28 FBB_DEBUG1 G16 E23 CLKC1# 30
FBA_DEBUG1 FBA_CLK1_N FBB_DEBUG1 FBC_CLK1_N

N12P-GS-A1_BGA973 N12P-GS-A1_BGA973
GS@ GS@

L11 L10
BLM18PG330SN1_2P BLM18PG330SN1_2P
OPT@ OPT@
+1.5VSDGPU +FB_PLLAVDD_0 2 1 +FB_PLLAVDD_1 2 1
+1.05VSDGPU +1.05VSDGPU
60.4_0402_1%
2 OPT@ 1 FBA_DEBUG0
R374
100mA OPT@ OPT@ OPT@ OPT@ OPT@
100mA OPT@ OPT@ OPT@ OPT@ OPT@
1

1
2 OPT@ 1 FBB_DEBUG0

C304

C308
10U_0805_6.3V6M

10U_0805_6.3V6M
1U_0603_10V6K

1U_0603_10V6K
C299

C300

C301

C302

C303

C305

C306

C307
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
60.4_0402_1% R375
2

2
2 OPT@ 1 FBA_DEBUG1
10K_0402_5% R376
2 OPT@ 1 FBB_DEBUG1
10K_0402_5% R377

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/09/28 2011/09/28 Title
Issued Date Deciphered Date SCHEMATIC, MB LA-7231P

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BL B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 04, 2011 Sheet 23 of 57
A
 5 4 3 2 1

MULTI LEVEL STRAPS

For GB2-128 & GB2b-128 colayout....
+3VSDGPU +3VSDGPU

U8D

1
15K_0402_1%
45.3K_0402_1%

34.8K_0402_1%
GV@ GS@

15K_0402_1%
45.3K_0402_1%
Part 4 of 7
+3VSDGPU

10K_0402_1%
AM11 A2 OPT@ @ @ @
IFPA_TXC NC_0
AM12 IFPA_TXC_N NC_1 A7

R378

R379

R380

R381

R382

R383
AM8 B7

2
IFPA_TXD0 NC_2 R755 @
AL8 IFPA_TXD0_N NC_3 C5 1 2 10K_0402_5%
AM10 C7 STRAP4 R756 2 GV@ 1 10K_0402_5% STRAP0 ROM_SI
IFPA_TXD1 NC_4 STRAP1 ROM_SO
AM9 IFPA_TXD1_N NC_5 D5
AK10 D6 R759 1 @ 2 10K_0402_5% STRAP2 ROM_SCLK
D IFPA_TXD2 NC_6 STRAP3 R760 D
AL10 IFPA_TXD2_N NC_7 D7 2 GV@ 1 4.99K_0402_1%

1
AK11 E5 OPT@ GS@ X76@ GS@
IFPA_TXD3 NC_8

20K_0402_5%

10K_0402_1%

15K_0402_1%
45.3K_0402_1%

34.8K_0402_1%
AL11 E7 PGOOD R757 2 GV@ 1 10K_0402_5%
IFPA_TXD3_N NC_9

1
Option Component

24.9K_0402_1%
F4 @
NC_10 @
NC_11 G5

R388

R489

R389
AP13 H32

2
IFPB_TXC NC_12

R384

R385
AN13 J25 ROM_SCLK ---> R383 2 GV@ 1 4.99K_0402_1%

2
IFPB_TXC_N NC_13

R386
AN8 J26 STRAP2 ---> R386 2 GV@ 1 4.99K_0402_1%

2
IFPB_TXD4 NC_14 STRAP_REF2 R758
AP8 IFPB_TXD4_N NC_15 P6 2 GV@ 1 40.2K_0402_1%
AP10 IFPB_TXD5 NC_16 U7
AN10 IFPB_TXD5_N NC_17 V6
AR11 IFPB_TXD6 NC_18 Y4
AR10 IFPB_TXD6_N NC_19 AA4
AN11 IFPB_TXD7 NC_20 AB4
AP11 IFPB_TXD7_N NC_21 AB7
NC_22 AC5

NC
NC_23 AD6
33 VGA_HDMI_TXD2+ AM7 IFPC_L0 NC_24 AF6
33 VGA_HDMI_TXD2- AM6 IFPC_L0_N NC_25 AG6
33 VGA_HDMI_TXD1+ AL5 IFPC_L1 NC_26 AG20
33 VGA_HDMI_TXD1- AM5 IFPC_L1_N NC_27 AJ5
33 VGA_HDMI_TXD0+ AM3
AM4
IFPC_L2 NC_28 AK15
AL7
For N12P-GS strap table
33 VGA_HDMI_TXD0- IFPC_L2_N NC_29
33 VGA_HDMI_TXC+ AP1 IFPC_L3
AR2 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
33 VGA_HDMI_TXC- IFPC_L3_N
64M* 16* 8 Hynix R378 R385 R386 R388 R489 R383
AR8 N12P-GS 900 MHz 1GB SA000041S40 PU 45K PD 35K PD 25K NC NC PD 15K PD 10K PU 15K
IFPD_L0
AR7 IFPD_L0_N
AP7 64M* 16* 8 Samsung R378 R385 R386 R388 R489 R383
IFPD_L1 N12P-GS 900 MHz 1GB SA00004GS10 PU 45K PD 35K PD 25K NC NC PD 20K PD 10K PU 15K
AN7 IFPD_L1_N
AN5 IFPD_L2
C 128M* 16* 8 Hynix R378 R385 R386 R388 R489 R383 C
AP5 IFPD_L2_N
LVDS/TMDS

AR5 N12P-GS 900 MHz 2GB SA00003YO20 PU 45K PD 35K PD 25K NC NC PD 35K PD 10K PU 15K
IFPD_L3
AR4 IFPD_L3_N 128M* 16* 8 Samsung R378 R385 R386 R388 R489 R383
N12P-GS 900 MHz 2GB SA000047Q20 PU 45K PD 35K PD 25K NC NC PD 45K PD 10K PU 15K
AH6 IFPE_L0
AH5 IFPE_L0_N
AH4 IFPE_L1
AG4 IFPE_L1_N
AF4 IFPE_L2
AF5 IFPE_L2_N
AE6
AE5
IFPE_L3 For N12P-GV-OP-B-A1 strap table
IFPE_L3_N
D35 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
VDD_SENSE_0
AL2 IFPF_L0 VDD_SENSE_1 P7
+3VSDGPU AL3 AD20 N12P-GV 64M* 16* 4 Hynix R378 R385 R386 R760 R756 R388 R382 R383
IFPF_L0_N VDD_SENSE_2 VGAVCC_SENSE 55 OP-B-A1 900 MHz 512MB SA000041S40 PU 45K PD 35K PD 5K PD 5K PD 10K PD 15K PU 10K PU 5K
AJ3 IFPF_L1
AJ2 IFPF_L1_N
AJ1 N12P-GV 64M* 16* 4 Samsung R378 R385 R386 R760 R756 R388 R382 R383
IFPF_L2
1

AH1 AD19 Power delete the circuit of OP-B-A1 900 MHz 512MB SA00004GS10 PU 45K PD 35K PD 5K PD 5K PD 10K PD 20K PU 10K PU 5K
R394 R395 IFPF_L2_N GND_SENSE_0
AH2 E35
4.7K_0402_5% 4.7K_0402_5% AH3 IFPF_L3 GND_SENSE_1
R7
VGAVSS_SENSE, due to the
OPT@ OPT@ IFPF_L3_N GND_SENSE_2 connection isn't
differental.
2

33 VGA_HDMI_SCLK AP2 IFPC_AUX_I2CW_SCL

33 VGA_HDMI_SDATA AN3 IFPC_AUX_I2CW_SDA_N TEST
OPT@
AP4 AP35 R398 1 2 10K_0402_5%
IFPD_AUX_I2CX_SCL TESTMODE JTAG_TCK @ T58
AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14
B JTAG_TDI @ T59 B
JTAG_TDI AN14
AN16 JTAG_TDO @ T60 1 @ 2 R796
JTAG_TDO JTAG_TMS @ T61 10K_0402_5%
AE4 IFPE_AUX_I2CY_SCL JTAG_TMS AR14
AD4 AP16 JTAG_TRST @ T62
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N
N12P-GS-A1_BGA973 R399 2 OPT@ 1 10K_0402_5%
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N SERIAL
C3 ROM_CS# R400 1 OPT@ 2 10K_0402_5% +3VSDGPU
ROM_CS_N ROM_SI
ROM_SI D3
C4 ROM_SO
ROM_SO ROM_SCLK
ROM_SCLK D4

+3VSDGPU GENERAL A5 R401 2 OPT@ 1 36K_0402_1% if unuse this pin , pull down 36k
NC/SPDIF_NC
A4 BUFRST_N
N9 R402 2 OPT@ 1 40.2K_0402_1%
MULTI_STRAP_REF0_GND
1 OPT@ 2 AB5 CEC
R403 10K_0402_5% M9 R404 2 OPT@ 1 40.2K_0402_1%
STRAP0 W5 MULTI_STRAP_REF1_GND
STRAP1 W7 STRAP0
STRAP1 THERMDP B5
STRAP2 V7 B4
STRAP2 THERMDN

N12P-GS-A1_BGA_973P
GS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 24 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VSDGPU
R405
0_0805_5%

1
C309 1 @ 2
10U_0805_10V4Z
OPT@

2
Q17
AO3413L_SOT23-3
+3VALW OPT@ 100mil(1.5A)
3 1

D
1
D D

2
R406

1
100K_0402_5% R407

2
OPT@ C310 470_0603_5%

3VSdelay_gate
R408 10U_0805_10V4Z OPT@

2
1K_0402_5% OPT@

6 1
1 OPT@ 2

3
Q18A
R409 Q18B DMN66D0LDW-7_SOT363-6 23VSdelay_gate

1
1K_0402_5% DMN66D0LDW-7_SOT363-6 C311 OPT@
14,17,46,55 VGA_ON 1 OPT@ 2 5 OPT@ 0.1U_0603_25V7K

1
OPT@

2
1

4
C312
0.1U_0603_25V7K

2
OPT@

U8E
+1.5VSDGPU 7900mA Part 5 of 7 +1.05VSDGPU
J23 AG11 2200mA
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ FBVDDQ_0 PEX_IOVDDQ_0 OPT@
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12

1U_0402_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
J29 AG13 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@

C313

C314

C315

C318

C316
FBVDDQ_2 PEX_IOVDDQ_2
1

1
22U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C317

C321

1U_0402_6.3V6K

1U_0402_6.3V6K
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
C C
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16

C319

C320

C322

C323

C324

C325
AA31 AG17
2

2
FBVDDQ_5 PEX_IOVDDQ_5
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22 Under GPU
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24
+1.05VSDGPU
under GPU AE27
AJ28
FBVDDQ_10 PEX_IOVDDQ_10 AG25
AG26
FBVDDQ_11 PEX_IOVDDQ_11 OPT@
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14

4.7U_0603_6.3V6K
E21 AJ15 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
FBVDDQ_13 PEX_IOVDDQ_13

1
22U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C328

1U_0402_6.3V6K

1U_0402_6.3V6K
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21

C326

C327

C329

C330

C331

C332
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ G22 AJ22

2
FBVDDQ_16 PEX_IOVDDQ_16
1U_0402_6.3V6K
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z G8 AJ24
FBVDDQ_17 PEX_IOVDDQ_17 Under GPU
1

1
C333

G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25

H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
C334

C335

C336

C337

C338

J14 AK18
2

FBVDDQ_20 PEX_IOVDDQ_20 +1.05VSDGPU

J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23 2 1
J17 AK26 OPT@ L12
FBVDDQ_23 PEX_IOVDDQ_23

4.7U_0603_6.3V6K
J20 AL16 OPT@ OPT@ BLM18PG121SN1D_0603
FBVDDQ_24 PEX_IOVDDQ_24

1
C340

1U_0402_6.3V6K
0.1U_0402_16V4Z
OPT@
under GPU J21
J22
FBVDDQ_25
FBVDDQ_26

C339

C341
N27
2200 mA

2
FBVDDQ_27
P27 FBVDDQ_28 PEX_IOVDD_0 AK16
R27 AK17 +1.05VSDGPU
FBVDDQ_29 PEX_IOVDD_1
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 AK24 2 @ 1 R793
FBVDDQ_31 PEX_IOVDD_3 0_0603_5%
U29 FBVDDQ_32 PEX_IOVDD_4 AK27 Under GPU
V27 +3VSDGPU
FBVDDQ_33
V29 FBVDDQ_34
V34 2 OPT@ 1
B
W27
FBVDDQ_35
FBVDDQ_36 PEX_PLLVDD AG14 +PEX_PLLVDD 120mA OPT@ R410 B

4.7U_0603_6.3V6K
Y27 OPT@ OPT@ 0_0603_5%
FBVDDQ_37

1
+3VSDGPU

C343

1U_0402_6.3V6K
0.1U_0402_16V4Z
@ L13 440 mA 120mA

C342

C344
2 1 +IFPC_PLLVDD 10K_0402_5% 2 OPT@ 1 R411 AK9 AG19 +PEX_SVDD_3V3

2
BLM18PG331SN1D_2P 1K_0402_1% 2 @ IFPAB_PLLVDD PEX_SVDD_3V3
1 R412 AJ11 IFPAB_RSET PEX_SVDD_3V3_NC F7
@ @ @ @ OPT@ Unuse 10K PD
1U_0402_6.3V6K

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

10K_0402_5%
C346

10K_0402_5%2 OPT@ 1 R413 AG9 IFPA_IOVDD 120mA

C345

C347

C348

AG10 J10 +VDD33

IFPB_IOVDD VDD33_0
C349

J11 Under GPU

2

VDD33_1 +3VSDGPU
VDD33_2 J12
+IFPC_PLLVDD AJ9 J13 2 OPT@ 1
1K_0402_1% 2 @ IFPC_PLLVDD VDD33_3
1 R415 AK7 IFPC_RSET VDD33_4 J9 OPT@
R414

4.7U_0603_6.3V6K
OPT@ OPT@ OPT@ OPT@
0_0603_5%

C354
1U_0402_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+IFPC_IOVDD AJ8 IFPC_IOVDD
Under GPU P9

2
MIOA_VDDQ_NC_0

C350

C351

C352

C353
+IFPC_PLLVDD AC6 R9
L14 1K_0402_1% 2 @ IFPD_PLLVDD MIOA_VDDQ_NC_1
1 R416 AB6 IFPD_RSET MIOA_VDDQ_NC_2 T9
+1.05VSDGPU BLM18BB221SN1D_2P 570 mA MIOA_VDDQ_NC_3 U9

1
@ +IFPC_IOVDD AK8 OPT@
+IFPC_IOVDD IFPD_IOVDD R791
2 1
@ AA9 10K_0402_5%
Under GPU
MIOB_VDDQ_NC_0
4.7U_0603_6.3V6K

@ @ OPT@ Unuse 10K PD 10K_0402_5%2 OPT@ 1 R417 AJ6 AB9

IFPEF_PLLVDD MIOB_VDDQ_NC_1
1

10K_0402_5%
C357
1U_0402_6.3V6K

0.1U_0402_16V4Z

1K_0402_1% 2 @ 1 R418 AL1 W9

2
IFPEF_RSET MIOB_VDDQ_NC_2
C356

C358

C359

MIOB_VDDQ_NC_3 Y9
1

10K_0402_5%1 OPT@ 2 R419 AE7 OPT@

2

IFPE_IOVDD R792
AD7 IFPF_IOVDD 10K_0402_5%
2

A N12P-GS-A1_BGA973 A
GS@

Under GPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BL B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 04, 2011 Sheet 25 of 57
5 4 3 2 1
 5 4 3 2 1

D U8F D

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 V31 +VGA_CORE
GND_5 GND_101 +VGA_CORE
B24
B27
GND_6 GND_102 Y11
Y13
Under GPU U8G
GND_7 GND_103
B30 GND_8 GND_104 Y15 41.02A
B33 GND_9 GND_105 Y17 AB11 VDD_0 VDD_56 P21
Part 7 of 7

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
C2 Y19 AB13 P23

OPT@ C361

OPT@ C362

OPT@ C363

OPT@ C364

OPT@ C374

OPT@ C365

OPT@ C366

OPT@ C367
GND_10 GND_106 VDD_1 VDD_57
C34 GND_11 GND_107 Y21 AB15 VDD_2 VDD_58 P25

1
E6 GND_12 GND_108 Y23 AB17 VDD_3 VDD_59 R11
E9 GND_13 GND_109 Y25 AB19 VDD_4 VDD_60 R12
E12 AA2 AB21 R13

2
GND_14 GND_110 VDD_5 VDD_61
E15 GND_15 GND_111 AA5 AB23 VDD_6 VDD_62 R14
E18 GND_16 GND_112 AA11 AB25 VDD_7 VDD_63 R15
E24 GND_17 GND_113 AA12 AC11 VDD_8 VDD_64 R16
E27 GND_18 GND_114 AA13 AC12 VDD_9 VDD_65 R17
E30 GND_19 GND_115 AA14 AC13 VDD_10 VDD_66 R18
F2 GND_20 GND_116 AA15 AC14 VDD_11 VDD_67 R19

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.047U_0402_16V7K

0.047U_0402_16V7K

0.047U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
F31 AA16 AC15 R20

OPT@ C368

OPT@ C369

OPT@ C375

OPT@ C370

OPT@ C376

OPT@ C372

OPT@ C373
GND_21 GND_117 VDD_12 VDD_68

OPT@ C371
F34 GND_22 GND_118 AA17 AC16 VDD_13 VDD_69 R21

1
F5 GND_23 GND_119 AA18 AC17 VDD_14 VDD_70 R22
J2 AA19 AC18 R23

2
GND_24 GND_120 VDD_15 VDD_71
J5 AA20 AC19 R24

2
GND_25 GND_121 VDD_16 VDD_72
J31 GND_26 GND_122 AA21 AC20 VDD_17 VDD_73 R25
J34 GND_27 GND_123 AA22 AC21 VDD_18 VDD_74 T12
K9 GND_28 GND_124 AA23 AC22 VDD_19 VDD_75 T14
L9 GND_29 GND_125 AA24 AC23 VDD_20 VDD_76 T16

POWER
C C
M2 GND_30 GND_126 AA25 AC24 VDD_21 VDD_77 T18
M5 GND_31 GND_127 AA34 AC25 VDD_22 VDD_78 T20
M11 GND_32 GND_128 AB12 AD12 VDD_23 VDD_79 T22
M13 GND_33 GND_129 AB14 AD14 VDD_24 VDD_80 T24

0.22U_0603_16V7K

0.22U_0603_16V7K

0.22U_0603_16V7K
M15 AB16 AD16 V11

OPT@ C378
OPT@ C377

OPT@ C379
GND_34 GND_130 OPT@ VDD_25 VDD_81
M17 GND_35 GND_131 AB18 AD18 VDD_26 VDD_82 V13

1
M19 GND_36 GND_132 AB20 AD22 VDD_27 VDD_83 V15

1U_0603_10V6K
C380
M21 GND_37 GND_133 AB22 AD24 VDD_28 VDD_84 V17
M23 AB24 L11 V19

2
GND_38 GND_134 VDD_29 VDD_85
M25 GND_39 GND_135 AC9 L12 VDD_30 VDD_86 V21
M31 GND_40 GND_136 AD2 L13 VDD_31 VDD_87 V23
M34 GND_41 GND_137 AD5 L14 VDD_32 VDD_88 V25
GND

N11 GND_42 GND_138 AD11 L15 VDD_33 VDD_89 W11

N12 GND_43 GND_139 AD13 Put Under GPU L16 VDD_34 VDD_90 W12
N13 GND_44 GND_140 AD15 L17 VDD_35 VDD_91 W13
N14 GND_45 GND_141 AD17 L18 VDD_36 VDD_92 W14
N15 GND_46 GND_142 AD21 L19 VDD_37 VDD_93 W15
N16 GND_47 GND_143 AD23 L20 VDD_38 VDD_94 W16
N17 AD25 +VGA_CORE L21 W17
GND_48 GND_144 VDD_39 VDD_95
N18 GND_49 GND_145 AD31 L22 VDD_40 VDD_96 W18
N19 GND_50 GND_146 AD34 L23 VDD_41 VDD_97 W19
N20 GND_51 GND_147 AE11 L24 VDD_42 VDD_98 W20

47U_0805_4V6
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M
470U_V_2.5VM

470U_V_2.5VM

4.7U_0805_10V4Z
N21 AE12 L25 W21

OPT@ C386
OPT@ C857

OPT@ C381

OPT@ C382

OPT@ C383

OPT@ C384

OPT@ C385
GND_52 GND_148 VDD_43 VDD_99

1
N22 GND_53 GND_149 AE13 M12 VDD_44 VDD_100 W22

1
N23 AE14 + + M14 W23
GND_54 GND_150 VDD_45 VDD_101
N24 GND_55 GND_151 AE15 M16 VDD_46 VDD_102 W24
N25 AE16 M18 W25

2
GND_56 GND_152 VDD_47 VDD_103
P12 GND_57 GND_153 AE17 M20 VDD_48 VDD_104 Y12
P14 GND_58 GND_154 AE18 M22 VDD_49 VDD_105 Y14
P16 GND_59 GND_155 AE19 M24 VDD_50 VDD_106 Y16
P18 GND_60 GND_156 AE20 P11 VDD_51 VDD_107 Y18
P20 GND_61 GND_157 AE21 P13 VDD_52 VDD_108 Y20
B B
P22 GND_62 GND_158 AE22 P15 VDD_53 VDD_109 Y22
P24 GND_63 GND_159 AE23 P17 VDD_54 VDD_110 Y24
R2
R5
GND_64 GND_160 AE24
AE25
Change values from P19 VDD_55
GND_65 GND_161
R31 GND_66 GND_162 AG2 330u*1 to 470u*2.
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
T13 AG34 N12P-GS-A1_BGA973
GND_69 GND_165 GS@
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
A A
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

N12P-GS-A1_BGA973
GS@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BL B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 04, 2011 Sheet 26 of 57
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode E

Address
Mode C
Address 0..31 32..63
D 64Mx16 DDR3 *8==>1GB CMD3 CMD0 CKE_L D
CMD8 CMD1 A8 A8
CMD2 CMD2 CS0_L#
CMD21 CMD3 A7 A6
CMD24 CMD4 A2 A1
DQSA[7..0]
23,28 DQSA[7..0]
U10 U11 CMD5 A11 A9
DQSA#[7..0] CMD23
23,28 DQSA#[7..0]
+MEM_VREF0 M8 E3 MDA17 +MEM_VREF1 M8 E3 MDA0 CMD26 CMD6 A5 A4
DQMA[7..0] VREFCA DQL0 MDA18 VREFCA DQL0 MDA7
23,28 DQMA[7..0] H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA16 F2 MDA1 CMD7 A0 A12
MDA[63..0] CMDA7 DQL2 MDA23 CMDA7 DQL2 MDA4
CMD7
23,28 MDA[63..0] N3 A0 DQL3 F8 N3 A0 DQL3 F8
CMDA10 P7 H3 MDA22 CMDA10 P7 H3 MDA3 CMD8 CAS* CAS*
CMDA[30..0] CMDA24 A1 DQL4 MDA20 CMDA24 A1 DQL4 MDA6
CMD15
23,28 CMDA[30..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA6 N2 G2 MDA19 CMDA6 N2 G2 MDA2 CMD13 CMD9 BA1 A3
CMDA22 A3 DQL6 MDA21 CMDA22 A3 DQL6 MDA5
P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA26 P2 CMDA26 P2 CMD4 CMD10 A9 A11
CMDA5 A5 CMDA5 A5
R8 A6 R8 A6
+1.5VSDGPU CMDA21 R2 D7 MDA14 CMDA21 R2 D7 MDA31 CMD18 CMD11 CS0_H#
CMDA8 A7 DQU0 MDA10 CMDA8 A7 DQU0 MDA26
T8 A8 DQU1 C3 T8 A8 DQU1 C3
CMDA4 R3 C8 MDA15 CMDA4 R3 C8 MDA30 CMD29 CMD12 BA0 BA0
CMDA25 A9 DQU2 MDA8 CMDA25 A9 DQU2 MDA25
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
OPT@ CMDA23 R7 A7 MDA12 CMDA23 R7 A7 MDA27 CMD27 CMD13 BA2 A15
R420 CMDA9 A11 DQU4 MDA9 CMDA9 A11 DQU4 MDA28
N7 A12 DQU5 A2 N7 A12 DQU5 A2
240_0402_1% CMDA12 T3 B8 MDA13 CMDA12 T3 B8 MDA29 CMD6 CMD14 A3 BA1
CMDA14 A13 DQU6 MDA11 CMDA14 A13 DQU6 MDA24
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA30 M7 CMDA30 M7 CMD17 CMD15 CS1_H#
+MEM_VREF0 A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU
CMD19 CMD16 ODT_H
0.1U_0402_10V6K

C CMDA29 CMDA29 C
M2 BA0 VDD B2 M2 BA0 VDD B2
1

C387 OPT@

OPT@ CMDA13 N8 D9 CMDA13 N8 D9 CMD22 CMD17 A4 A5

R421 CMDA27 BA1 VDD CMDA27 BA1 VDD
M3 BA2 VDD G7 M3 BA2 VDD G7
240_0402_1% K2 K2 CMD12 CMD18 A13 A14
2

VDD VDD
VDD K8 VDD K8
VDD N1 VDD N1 CMD28 CMD19 WE* A10
CLKA0 J7 N9 CLKA0 J7 N9
CLKA0# CK VDD CLKA0# CK VDD
K7 CK VDD R1 K7 CK VDD R1 CMD10 CMD20 A1 A2
CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CMD25 CMD21 A10 WE*
+1.5VSDGPU CMDA0 K1 A1 CMDA0 K1 A1 CMD9 CMD22 A12 A0
CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD1 CMD23 CS1_L#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
OPT@ CMDA28 L3 D2 CMDA28 L3 D2 CMD11 CMD24 RAS* RAS*
WE VDDQ WE VDDQ
R422 310mAVDDQ E9 VDDQ E9
240_0402_1%
DQSA2 VDDQ F1
DQSA0
310mAVDDQ F1 CMD0 CMD25 ODT_L
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA1 C7 H9 DQSA3 C7 H9 CMD5 CMD26 A6 A7
+MEM_VREF1 DQSU VDDQ DQSU VDDQ
CMD16 CMD27 CKE_H
0.1U_0402_10V6K

DQMA2 E7 A9 DQMA0 E7 A9
DML VSS DML VSS
1

C388 OPT@

OPT@ DQMA1 D3 B3 DQMA3 D3 B3 CMD20 CMD28 RST RST

R423 DMU VSS DMU VSS
VSS E1 VSS E1
240_0402_1% G8 G8 CMD14 CMD29 A14 A13
2

DQSA#2 VSS DQSA#0 VSS

G3 DQSL VSS J2 G3 DQSL VSS J2
DQSA#1 B7 J8 DQSA#3 B7 J8 CMD30 CMD30 A15 BA2
DQSU VSS DQSU VSS
VSS M1 VSS M1
VSS M9 VSS M9 CMD31 Not Available
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 LOW HIGH
B RESET VSS RESET VSS B
VSS T1 VSS T1
ZQ0 L8 T9 ZQ1 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
23 CLKA0
OPT@ J1 B1 OPT@ J1 B1 CMDA3 R427 1 OPT@ 2 10K_0402_5% Command Bit Default Pull-down
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

R425 L1 B9 R426 L1 B9 CMDA0 R428 1 OPT@ 2 10K_0402_5%

OPT@ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ CMDA16 R430 OPT@ 10K_0402_5%
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 1 2 ODTx 10k
R429 L9 D8 L9 D8 CMDA20 R431 1 OPT@ 2 10K_0402_5%
2

2
160_0402_1% NCZQ1 VSSQ NCZQ1 VSSQ CMDA19 R432 OPT@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 1 2
E8 E8 RST 10k
2

VSSQ VSSQ
23 CLKA0# VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
X76@ X76@
X76
ZZZ ZZZ ZZZ ZZZ
+1.5VSDGPU +1.5VSDGPU

X7601@ X7603@ X7605@ X7607@

1000P_0402_50V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
OPT@ C390

OPT@ C391

OPT@ C392

OPT@ C393

OPT@ C394

OPT@ C395

OPT@ C396

OPT@ C397

OPT@ C398

OPT@ C399

C400

C401

C402

C403

C404

C405

C406

C407

C408
X76287BOL01 X76287BOL03 X76287BOL05 X76287BOL07
1

1
1Gx4 SAM 64M16 1Gx8 SAM 64M16 2Gx8 SAM 128M16 2Gx4 SAM 128M16
2

2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
ZZZ ZZZ ZZZ ZZZ

A X7602@ X7604@ X7606@ X7608@ A

X76287BOL02 X76287BOL04 X76287BOL06 X76287BOL08

1Gx4 HYN 64M16 1Gx8 HYN 64M16 2Gx8 HYN 128M16 2Gx4 HYN 128M16

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 27 of 57
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode E

Address
Mode C
Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD3 CMD0 CKE_L
CMD8 CMD1 A8 A8
D D
CMD2 CMD2 CS0_L#
U12 U13
CMD21 CMD3 A7 A6
+MEM_VREF2 M8 E3 MDA63 +MEM_VREF3 M8 E3 MDA41
VREFCA DQL0 MDA57 VREFCA DQL0 MDA45
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 CMD24 CMD4 A2 A1
DQMA[7..0] F2 MDA62 F2 MDA43
23,27 DQMA[7..0] DQL2 DQL2
CMDA9 N3 F8 MDA61 CMDA9 N3 F8 MDA44 CMD5 A11 A9
CMDA[30..0] CMDA24 P7
A0 DQL3
H3 MDA59 CMDA24 P7
A0 DQL3
H3 MDA42
CMD23
23,27 CMDA[30..0] A1 DQL4 A1 DQL4
CMDA10 P3 H8 MDA56 CMDA10 P3 H8 MDA47 CMD26 CMD6 A5 A4
DQSA#[7..0] CMDA13 A2 DQL5 MDA60 CMDA13 A2 DQL5 MDA40
23,27 DQSA#[7..0] N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA26 P8 H7 MDA58 CMDA26 P8 H7 MDA46 CMD7 A0 A12
DQSA[7..0] CMDA22 A4 DQL7 CMDA22 A4 DQL7 CMD7
23,27 DQSA[7..0] P2 A5 P2 A5
CMDA21 R8 CMDA21 R8 CMD8 CAS* CAS*
MDA[63..0] CMDA5 A6 MDA35 CMDA5 A6 MDA51
CMD15
23,27 MDA[63..0] R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDA8 T8 C3 MDA38 CMDA8 T8 C3 MDA52 CMD13 CMD9 BA1 A3
CMDA23 A8 DQU1 MDA34 CMDA23 A8 DQU1 MDA48
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA28 L7 C2 MDA36 CMDA28 L7 C2 MDA54 CMD4 CMD10 A9 A11
CMDA4 A10/AP DQU3 MDA33 CMDA4 A10/AP DQU3 MDA49
R7 A11 DQU4 A7 R7 A11 DQU4 A7
CMDA7 N7 A2 MDA37 CMDA7 N7 A2 MDA55 CMD18 CMD11 CS0_H#
+1.5VSDGPU CMDA14 A12 DQU5 MDA32 CMDA14 A12 DQU5 MDA50
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA12 T7 A3 MDA39 CMDA12 T7 A3 MDA53 CMD12 BA0 BA0
CMDA27 A14 DQU7 CMDA27 A14 DQU7 CMD29
M7 A15/BA3 M7 A15/BA3
OPT@ +1.5VSDGPU +1.5VSDGPU CMD13 BA2 A15
R434
CMD27
240_0402_1% CMDA29 M2 B2 CMDA29 M2 B2 CMD6 CMD14 A3 BA1
CMDA6 BA0 VDD CMDA6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CMDA30 M3 G7 CMDA30 M3 G7 CMD17 CMD15 CS1_H#
BA2 VDD BA2 VDD
VDD K2 VDD K2
+MEM_VREF2 K8 K8 CMD19 CMD16 ODT_H
VDD VDD
VDD N1 VDD N1
C409 OPT@
0.1U_0402_10V6K

OPT@ CLKA1 J7 N9 CLKA1 J7 N9 CMD22 CMD17 A4 A5

CK VDD CK VDD
1

R435 CLKA1# K7 R1 CLKA1# K7 R1

C 240_0402_1% CMDA16 CK VDD CMDA16 CK VDD C
K9 CKE/CKE0 VDD R9
+1.5VSDGPU
K9 CKE/CKE0 VDD R9
+1.5VSDGPU
CMD12 CMD18 A13 A14
2

CMD28 CMD19 WE* A10

CMDA19 K1 A1 CMDA19 K1 A1
CMDA18 ODT/ODT0 VDDQ CMDA18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD10 CMD20 A1 A2
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD25 CMD21 A10 WE*
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ WE VDDQ
+1.5VSDGPU
310mAVDDQ E9 310mAVDDQ E9 CMD9 CMD22 A12 A0
VDDQ F1 VDDQ F1
DQSA7 F3 H2 DQSA5 F3 H2 CMD1 CMD23 CS1_L#
DQSA4 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
OPT@ CMD11 CMD24 RAS* RAS*
R436
240_0402_1% DQMA7 E7 A9 DQMA5 E7 A9 CMD0 CMD25 ODT_L
DQMA4 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD5 CMD26 A6 A7
VSS G8 VSS G8
+MEM_VREF3 DQSA#7 G3 J2 DQSA#5 G3 J2 CMD16 CMD27 CKE_H
DQSA#4 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
C410 OPT@
0.1U_0402_10V6K

OPT@ M1 M1 CMD20 CMD28 RST RST

VSS VSS
1

R437 M9 M9
240_0402_1% VSS VSS
VSS P1 VSS P1 CMD14 CMD29 A14 A13
CMDA20 T2 P9 CMDA20 T2 P9
2

RESET VSS RESET VSS

VSS T1 VSS T1 CMD30 CMD30 A15 BA2
ZQ2 L8 T9 ZQ3 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD31 Not Available
1

1
OPT@
OPT@ J1 B1 R439 J1 B1 LOW HIGH
R438 NC/ODT1 VSSQ 243_0402_1% NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 D1 J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8
2

2
B NCZQ1 VSSQ NCZQ1 VSSQ B
VSSQ E2 VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
23 CLKA1
96-BALL 96-BALL
1

SDRAM DDR3 SDRAM DDR3

OPT@ K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
R441 X76@ X76@
160_0402_1%
2

23 CLKA1#
+1.5VSDGPU +1.5VSDGPU
C412

C413

C414

C415

C416

C417

C418

C419

C420

C421
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C422

C423

C424

C425

C426

C427

C428

C429

C430
1

1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
2

2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 28 of 57
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode E

Address
Mode C
Address 0..31 32..63

64Mx16 DDR3 *8==>1GB CMD3 CMD0 CKE_L

D
CMD8 CMD1 A8 A8 D

CMD2 CMD2 CS0_L#

CMD21 CMD3 A7 A6
DQSC[7..0] CMD4 A2 A1
23,30 DQSC[7..0] CMD24
DQSC#[7..0] U14 U15 CMD5 A11 A9
23,30 DQSC#[7..0] CMD23
DQMC[7..0] +MEM_VREF4 M8 E3 MDC21 +MEM_VREF5 M8 E3 MDC2 CMD6 A5 A4
23,30 DQMC[7..0] VREFCA DQL0 MDC19 VREFCA DQL0 MDC7
CMD26
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
MDC[63..0] F2 MDC16 F2 MDC0 CMD7 A0 A12
23,30 MDC[63..0]
CMDC7 N3
DQL2
F8 MDC17 CMDC7 N3
DQL2
F8 MDC5
CMD7
CMDC[30..0] CMDC10 A0 DQL3 MDC18 CMDC10 A0 DQL3 MDC3
23,30 CMDC[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3 CMD15 CMD8 CAS* CAS*
CMDC24 P3 H8 MDC20 CMDC24 P3 H8 MDC6
CMDC6 A2 DQL5 MDC23 CMDC6 A2 DQL5 MDC1
N2 A3 DQL6 G2 N2 A3 DQL6 G2 CMD13 CMD9 BA1 A3
CMDC22 P8 H7 MDC22 CMDC22 P8 H7 MDC4
CMDC26 A4 DQL7 CMDC26 A4 DQL7
P2 A5 P2 A5 CMD4 CMD10 A9 A11
CMDC5 R8 CMDC5 R8
+1.5VSDGPU CMDC21 A6 MDC13 CMDC21 A6 MDC31
R2 A7 DQU0 D7 R2 A7 DQU0 D7 CMD18 CMD11 CS0_H#
CMDC8 T8 C3 MDC8 CMDC8 T8 C3 MDC24
CMDC4 A8 DQU1 MDC14 CMDC4 A8 DQU1 MDC30
R3 A9 DQU2 C8 R3 A9 DQU2 C8 CMD29 CMD12 BA0 BA0
CMDC25 L7 C2 MDC9 CMDC25 L7 C2 MDC25
GS@ CMDC23 A10/AP DQU3 MDC12 CMDC23 A10/AP DQU3 MDC28
R7 A11 DQU4 A7 R7 A11 DQU4 A7 CMD27 CMD13 BA2 A15
R443 CMDC9 N7 A2 MDC11 CMDC9 N7 A2 MDC26
240_0402_1% CMDC12 A12 DQU5 MDC15 CMDC12 A12 DQU5 MDC29
T3 A13 DQU6 B8 T3 A13 DQU6 B8 CMD6 CMD14 A3 BA1
CMDC14 T7 A3 MDC10 CMDC14 T7 A3 MDC27
CMDC30 A14 DQU7 CMDC30 A14 DQU7
M7 A15/BA3 +1.5VSDGPU
M7 A15/BA3 +1.5VSDGPU
CMD17 CMD15 CS1_H#
+MEM_VREF4
CMD19 CMD16 ODT_H
0.1U_0402_10V6K

CMDC29 M2 B2 CMDC29 M2 B2
BA0 VDD BA0 VDD
1

GS@

GS@ CMDC13 N8 D9 CMDC13 N8 D9 CMD22 CMD17 A4 A5

C R444 CMDC27 BA1 VDD CMDC27 BA1 VDD C
M3 BA2 VDD G7 M3 BA2 VDD G7
240_0402_1% K2 K2 CMD12 CMD18 A13 A14
2

VDD VDD
VDD K8 VDD K8
C431

VDD N1 VDD N1 CMD28 CMD19 WE* A10

CLKC0 J7 N9 CLKC0 J7 N9
CLKC0# CK VDD CLKC0# CK VDD
K7 CK VDD R1 K7 CK VDD R1 CMD10 CMD20 A1 A2
CMDC3 K9 R9 CMDC3 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CMD25 CMD21 A10 WE*
CMDC0 K1 A1 CMDC0 K1 A1 CMD9 CMD22 A12 A0
CMDC2 ODT/ODT0 VDDQ CMDC2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDC11 J3 C1 CMDC11 J3 C1 CMD1 CMD23 CS1_L#
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
+1.5VSDGPU CMDC28 L3 D2 CMDC28 L3 D2 CMD11 CMD24 RAS* RAS*
WE VDDQ WE VDDQ
310mAVDDQ E9 VDDQ E9

DQSC2 VDDQ F1
DQSC0
310mAVDDQ F1 CMD0 CMD25 ODT_L
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
GS@ DQSC1 C7 H9 DQSC3 C7 H9 CMD5 CMD26 A6 A7
R445 DQSU VDDQ DQSU VDDQ
240_0402_1% CMD16 CMD27 CKE_H
DQMC2 E7 A9 DQMC0 E7 A9
DQMC1 DML VSS DQMC3 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD20 CMD28 RST RST
+MEM_VREF5 E1 E1
VSS VSS
VSS G8 VSS G8 CMD14 CMD29 A14 A13
0.1U_0402_10V6K

DQSC#2 G3 J2 DQSC#0 G3 J2
DQSL VSS DQSL VSS
1

GS@

GS@ DQSC#1 B7 J8 DQSC#3 B7 J8 CMD30 CMD30 A15 BA2

R446 DQSU VSS DQSU VSS
VSS M1 VSS M1
240_0402_1% M9 M9 CMD31 Not Available
2

VSS VSS
VSS P1 VSS P1
C432

CMDC20 T2 P9 CMDC20 T2 P9 LOW HIGH

RESET VSS RESET VSS
VSS T1 VSS T1
ZQ4 L8 T9 ZQ5 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1

1
GS@ J1 B1 GS@ J1 B1 Command Bit Default Pull-down
R447 NC/ODT1 VSSQ R448 NC/ODT1 VSSQ CMDC3 R449 GS@ 10K_0402_5%
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 1 2
243_0402_1% J9 D1 243_0402_1% J9 D1 CMDC0 R450 1 GS@ 2 10K_0402_5% ODTx 10k
NC/CE1 VSSQ NC/CE1 VSSQ CMDC16 R451 GS@ 10K_0402_5%
L9 D8 L9 D8 1 2
2

2
NCZQ1 VSSQ NCZQ1 VSSQ CMDC20 R452 GS@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 1 2
E8 E8 CMDC19 R453 1 GS@ 2 10K_0402_5% RST 10k
VSSQ VSSQ
VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
23 CLKC0 VSSQ G9 VSSQ G9
1

96-BALL 96-BALL
GS@ SDRAM DDR3 SDRAM DDR3
R455 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
160_0402_1% X76@ X76@
2

23 CLKC0# +1.5VSDGPU
+1.5VSDGPU
1000P_0402_50V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
GS@ C434

GS@ C435

GS@ C436

GS@ C437

GS@ C438

GS@ C439

GS@ C440

GS@ C441

GS@ C442

GS@ C443

C444

C445

C446

C447

C448

C449

C450

C451

C452
1

1
2

2
GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 29 of 57
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode E

Address
Mode C
Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD3 CMD0 CKE_L
D
CMD8 CMD1 A8 A8 D

CMD2 CMD2 CS0_L#

DQMC[7..0] CMD3 A7 A6
23,29 DQMC[7..0] CMD21
CMDC[30..0] CMD4 A2 A1
23,29 CMDC[30..0] CMD24
DQSC#[7..0] U16 U17 CMD5 A11 A9
23,29 DQSC#[7..0] CMD23
DQSC[7..0] +MEM_VREF6 M8 E3 MDC63 +MEM_VREF7 M8 E3 MDC42 CMD6 A5 A4
23,29 DQSC[7..0] VREFCA DQL0 MDC56 VREFCA DQL0 MDC43
CMD26
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
MDC[63..0] F2 MDC62 F2 MDC41 CMD7 A0 A12
23,29 MDC[63..0]
CMDC9 N3
DQL2
F8 MDC58 CMDC9 N3
DQL2
F8 MDC47
CMD7
CMDC24 A0 DQL3 MDC61 CMDC24 A0 DQL3 MDC40
P7 A1 DQL4 H3 P7 A1 DQL4 H3 CMD15 CMD8 CAS* CAS*
CMDC10 P3 H8 MDC59 CMDC10 P3 H8 MDC46
CMDC13 A2 DQL5 MDC60 CMDC13 A2 DQL5 MDC44
N2 A3 DQL6 G2 N2 A3 DQL6 G2 CMD13 CMD9 BA1 A3
CMDC26 P8 H7 MDC57 CMDC26 P8 H7 MDC45
CMDC22 A4 DQL7 CMDC22 A4 DQL7
P2 A5 P2 A5 CMD4 CMD10 A9 A11
CMDC21 R8 CMDC21 R8
+1.5VSDGPU CMDC5 A6 MDC34 CMDC5 A6 MDC48
R2 A7 DQU0 D7 R2 A7 DQU0 D7 CMD18 CMD11 CS0_H#
CMDC8 T8 C3 MDC36 CMDC8 T8 C3 MDC53
CMDC23 A8 DQU1 MDC35 CMDC23 A8 DQU1 MDC50
R3 A9 DQU2 C8 R3 A9 DQU2 C8 CMD29 CMD12 BA0 BA0
GS@ CMDC28 L7 C2 MDC38 CMDC28 L7 C2 MDC54
R457 CMDC4 A10/AP DQU3 MDC33 CMDC4 A10/AP DQU3 MDC49
R7 A11 DQU4 A7 R7 A11 DQU4 A7 CMD27 CMD13 BA2 A15
240_0402_1% CMDC7 N7 A2 MDC37 CMDC7 N7 A2 MDC52
CMDC14 A12 DQU5 MDC32 CMDC14 A12 DQU5 MDC51
T3 A13 DQU6 B8 T3 A13 DQU6 B8 CMD6 CMD14 A3 BA1
CMDC12 T7 A3 MDC39 CMDC12 T7 A3 MDC55
CMDC27 A14 DQU7 CMDC27 A14 DQU7
M7 A15/BA3 +1.5VSDGPU
M7 A15/BA3 +1.5VSDGPU
CMD17 CMD15 CS1_H#
+MEM_VREF6
CMD19 CMD16 ODT_H
GS@
0.1U_0402_10V6K

GS@ CMDC29 M2 B2 CMDC29 M2 B2

BA0 VDD BA0 VDD
1

R458 CMDC6 N8 D9 CMDC6 N8 D9 CMD22 CMD17 A4 A5

C 240_0402_1% CMDC30 BA1 VDD CMDC30 BA1 VDD C
M3 BA2 VDD G7 M3 BA2 VDD G7
K2 K2 CMD12 CMD18 A13 A14
C453
2

VDD VDD
VDD K8 VDD K8
VDD N1 VDD N1 CMD28 CMD19 WE* A10
CLKC1 J7 N9 CLKC1 J7 N9
CLKC1# CK VDD CLKC1# CK VDD
K7 CK VDD R1 K7 CK VDD R1 CMD10 CMD20 A1 A2
CMDC16 K9 R9 CMDC16 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CMD25 CMD21 A10 WE*
CMDC19 K1 A1 CMDC19 K1 A1 CMD9 CMD22 A12 A0
+1.5VSDGPU CMDC18 ODT/ODT0 VDDQ CMDC18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDC11 J3 C1 CMDC11 J3 C1 CMD1 CMD23 CS1_L#
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
GS@ CMDC25 L3 D2 CMDC25 L3 D2 CMD11 CMD24 RAS* RAS*
WE VDDQ WE VDDQ
R459
240_0402_1%
310mAVDDQ E9 310mAVDDQ E9
VDDQ F1 VDDQ F1 CMD0 CMD25 ODT_L
DQSC7 F3 H2 DQSC5 F3 H2
DQSC4 DQSL VDDQ DQSC6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD5 CMD26 A6 A7
+MEM_VREF7 CMD16 CMD27 CKE_H
DQMC7 E7 A9 DQMC5 E7 A9
GS@

DML VSS DML VSS

0.1U_0402_10V6K

GS@ DQMC4 D3 B3 DQMC6 D3 B3 CMD20 CMD28 RST RST

DMU VSS DMU VSS
1

R460 E1 E1
240_0402_1% VSS VSS
VSS G8 VSS G8 CMD14 CMD29 A14 A13
DQSC#7 G3 J2 DQSC#5 G3 J2
C454
2

DQSC#4 DQSL VSS DQSC#6 DQSL VSS

B7 DQSU VSS J8 B7 DQSU VSS J8 CMD30 CMD30 A15 BA2
VSS M1 VSS M1
VSS M9 VSS M9 CMD31 Not Available
VSS P1 VSS P1
CMDC20 T2 P9 CMDC20 T2 P9 LOW HIGH
RESET VSS RESET VSS
VSS T1 VSS T1
ZQ6 L8 T9 ZQ7 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B

1
1

J1 B1 GS@ J1 B1
GS@ NC/ODT1 VSSQ R462 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
R461 J9 D1 243_0402_1% J9 D1
243_0402_1% NC/CE1 VSSQ NC/CE1 VSSQ
23 CLKC1 L9 D8 L9 D8

2
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

VSSQ VSSQ
1

VSSQ E8 VSSQ E8
GS@ F9 F9
R464 VSSQ VSSQ
VSSQ G1 VSSQ G1
160_0402_1% G9 G9
VSSQ VSSQ
2

96-BALL 96-BALL
23 CLKC1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
X76@ X76@

+1.5VSDGPU
+1.5VSDGPU
GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C466

C467

C468

C469

C470

C471

C472

C473

C474
1

1
C456

C457

C458

C459

C460

C461

C462

C463

C464

C465
2

2
GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@

GS@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 30 of 57
5 4 3 2 1
 5 4 3 2 1

D +LCDVDD
LCD POWER CIRCUIT D
+3VALW +3VS
W=60mils

1
+INVPWR_B+ B+
R466 Place closed to JLVDS1 L15

1
300_0603_5% R467 C475 +LCDVDD FBMA-L11-201209-221LMA30T_0805
10K_0402_5% 4.7U_0805_10V4Z +3VS 2 1

2
L16

2
W=60mils FBMA-L11-201209-221LMA30T_0805

2
R468 2 1
1

1
Q19 D 1K_0402_5% S Q20 C476 C477 C478
2N7002E_SOT23-3 2 2 1 2 AO3413L_SOT23-3

1
G G 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z C479 C480 SM010014520 3000ma

2
S D 680P_0402_50V7K 68P_0402_50V8J 220ohm@100mhz DCR
3

1
1
C481 +LCDVDD
0.04

2
1 0.047U_0402_16V7K W=60mils
D Q21

2
PCH_ENVDD 2 2N7002E_SOT23-3
16 PCH_ENVDD
G

1
S C483
3
1

C482 0.1U_0402_16V4Z
R469 4.7U_0805_10V4Z

2
100K_0402_5%

LCD/LED PANEL Conn.

2

+INVPWR_B+
W=60mils JLVDS1
1 1
2 2
C C
3 3
4 4
DAC_BRIG 5
39 DAC_BRIG 5
DISPOFF# 6
INVTPWM 6
7 7
8 8
9 9
R783 U27 +3VS EDP_AUX_R 10
R474 1 DISPOFF# EDP_AUX#_R 10
1 2 1 OE# 39 BKOFF# 2 0_0402_5% 11 11
100K_0402_5% 5 12
VCC R475 1 EDP_TX1_R 12
2 10K_0402_5% 13 13
2 EDP_TX1#_R 14
16 DPST_PWM IN 14
15 15
4 INVTPWM C486 2 1 220P_0402_50V7K DAC_BRIG EDP_TX0_R 16
OUT EDP_TX0#_R 16
3 GND 17 17
1

C487 2 1 220P_0402_50V7K INVTPWM 18 18

74AHC1G125GW_SOT353-5 R476 PCH_TXCLK+ 19
16 PCH_TXCLK+ 19
10K_0402_5% C488 2 1 220P_0402_50V7K DISPOFF# PCH_TXCLK- 20
16 PCH_TXCLK- 20
PCH_TXOUT2+ 21
16 PCH_TXOUT2+ 21
PCH_TXOUT2- 22
16 PCH_TXOUT2-
2

22
23 23
PCH_TXOUT1+ 24
16 PCH_TXOUT1+ 24
PCH_TXOUT1- 25
16 PCH_TXOUT1- 25
26 26
PCH_TXOUT0+ 27
16 PCH_TXOUT0+ 27
PCH_TXOUT0- 28
16 PCH_TXOUT0- 28
16 PCH_LCD_DATA PCH_LCD_DATA 29
+LCDVDD +3VS PCH_LCD_CLK 29
16 PCH_LCD_CLK 30 30
31 31
W=60mils 32 32
33 33
B eDP EDP_HPD
34
35
34 B
+3VS 35
36 36 G1 41
R477 Near JLVDS1 37 42
+1.05VS_VCCP 1K_0402_5% R478 1 @ USB20_CMOS_P10 37 G2
17 USB20_P10 2 0_0402_5% 38 38 G3 43
1 EDP@ 2 17 USB20_N10
R479 1 @ 2 0_0402_5% USB20_CMOS_N10 39 39 G4 44
EDP_TXN0 0.1U_0402_16V7K EDP@ 2 1 C489 EDP_TX0#_R 40 45
4 EDP_TXN0 40 G5

1
4 EDP_HPD# EDP_TXP0 0.1U_0402_16V7K EDP@ 2 1 C490 EDP_TX0_R
4 EDP_TXP0
C492 C493 ACES_50398-04071-001
1

D EDP_TXN1 0.1U_0402_16V7K EDP@ 2 C491 EDP_TX1#_R 22P_0402_50V8J CONN@

4 EDP_TXN1 1 22P_0402_50V8J

2
Q22 2 EDP_HPD EDP_TXP1 0.1U_0402_16V7K EDP@ 2 1 C494 EDP_TX1_R @ @
4 EDP_TXP1
2N7002E_SOT23-3 G
1

EDP@ S 4 EDP_AUXN EDP_AUXN 0.1U_0402_16V7K EDP@ 2 1 C495 EDP_AUX#_R

3

R480 4 EDP_AUXP EDP_AUXP 0.1U_0402_16V7K EDP@ 2 1 C496 EDP_AUX_R

100K_0402_5%
EDP@
2

L45
USB20_N10 3 4 USB20_CMOS_N10
3 4

USB20_P10 2 1 USB20_CMOS_P10
2 1
WCM2012F2S-900T04_0805

Modify for LVDS Camera USB cancel twist issue

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 31 of 57
5 4 3 2 1
 A B C D E

1
ESD team Suggestion 1

+5VS W=40mils

2
+R_CRT_VCC +CRT_VCC
D8 F1
2 1.1A_6V_SMD1812P110TFW=40mils
1 1 2
D7 3
D6 PJDLC05C_SOT23-3 RB491D-YS_SOT23-3

1
PJDLC05C_SOT23-3 C497
0.1U_0402_16V4Z

2
UMA/Optimus CRT Connector
L17 L18
BLM18BA470SN1D_2P BLM18BA470SN1D_2P
PCH_CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1
16 PCH_CRT_R
L19 L20 6
BLM18BA470SN1D_2P BLM18BA470SN1D_2P T70 @ CRT_11 11
PCH_CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
16 PCH_CRT_G
L21 L22 7
BLM18BA470SN1D_2P BLM18BA470SN1D_2P 12
PCH_CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
16 PCH_CRT_B
8 G 16

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
13 G 17
1

1
3

1
C504

C505

C506
R481 R482 R483 9

C498

C499

C500

C501

C502

C503
150_0402_1% 150_0402_1% 150_0402_1% 14
4

2
10
2

2 2
15
T71 @ CRT_5 5

1
C507
SUYIN_070546FR015S297ZR
100P_0402_50V8J CONN@

2
SM010012010 300ma 120ohm@100mhz DCR 0.4
1 2 CRT_HSYNC_2
+CRT_VCC L23 MBC1608121YZF_0603 DSUB_12

C508 1 2 0.1U_0402_16V4Z R484 2 1 10K_0402_5% 1 2 CRT_VSYNC_2

1
L24 MBC1608121YZF_0603

1
5

C509 C510 DSUB_15

2
10P_0402_50V8J 10P_0402_50V8J C511
P

OE#

2
PCH_CRT_HSYNC 2 4 CRT_HSYNC_1 68P_0402_50V8J
16 PCH_CRT_HSYNC A Y

1
G

U18 C512
74AHCT1G125GW_SOT353-5 68P_0402_50V8J
3

2
+CRT_VCC

C513 1 2 0.1U_0402_16V4Z
5

1
P

OE#

PCH_CRT_VSYNC 2 4 CRT_VSYNC_1
16 PCH_CRT_VSYNC A Y
G

U19
74AHCT1G125GW_SOT353-5
3

+CRT_VCC
3 3

+3VS

1
R486 R487
4.7K_0402_5% 4.7K_0402_5%

2
2
G
PCH_CRT_DATA 3 1 DSUB_12
16 PCH_CRT_DATA

D
2
G
Q23
2N7002E_SOT23-3
16 PCH_CRT_CLK PCH_CRT_CLK 3 1 DSUB_15

D
PCH DDC PU 2.2K on Page 17 Q24
2N7002E_SOT23-3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 32 of 57
A B C D E
 5 4 3 2 1

R502 SM070001310 400ma 90ohm@100mhz DCR 0.3

0_0603_5%
1 @ 2 +HDMI_5V W=40mils
D HDMI_CLK+ R503 1 0_0402_5% HDMI_R_CK+ D
2
+HDMI_5V_OUT
D9 1 2
F2 L25 1 2
+5VS 2
1 1 2 WCM2012F2S-900T04_0805
3 @ 4 3
RB491D-YS_SOT23-3 1.1A_6V_SMD1812P110TF 4 3

1
HDMI_CLK- R504 1 2 0_0402_5% HDMI_R_CK-
C514
0.1U_0402_16V4Z +3VS

2
HDMI_TX0+ R505 1 2 0_0402_5% HDMI_R_D0+

1 1 2 2

1
L26
R506 WCM2012F2S-900T04_0805
UMA & Optimus 1.0 1M_0402_5%
UMA@
@ 4 4 3 3

2
C515 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX2- HDMI_TX0- R507 1 0_0402_5% HDMI_R_D0-

G
16 PCH_DPB_N0 2

2
16 PCH_DPB_P0 C516 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX2+
HDMI_HPD 1 3 PCH_DPB_HPD 16
C517 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX1- Q25 HDMI_TX1+ R508 1 2 0_0402_5% HDMI_R_D1+

S
16 PCH_DPB_N1
16 PCH_DPB_P1 C518 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX1+ UMA@ 2N7002E_SOT23-3

1
220P_0402_50V7K
UMA@ 1 2
1 2

C521
16 PCH_DPB_N2 C519 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX0- R509 L27
16 PCH_DPB_P2 C520 UMA@ 2 1 0.1U_0402_16V7K HDMI_TX0+ 100K_0402_5% WCM2012F2S-900T04_0805

2
@ 4 3
C522 UMA@ 2 HDMI_CLK- 4 3
16 PCH_DPB_N3 1 0.1U_0402_16V7K

2
16 PCH_DPB_P3 C523 UMA@ 2 1 0.1U_0402_16V7K HDMI_CLK+ HDMI_TX1- R510 1 2 0_0402_5% HDMI_R_D1-

HDMI_TX2+ R511 1 2 0_0402_5% HDMI_R_D2+

C C858 C
+3VSDGPU 0.1U_0402_16V4Z
NVIDA Recommand 10/08 1 1 2 2
OPT11@ L28
OPT1.1
Optimus 1.1 1 2 WCM2012F2S-900T04_0805
@ 4 3
+3VSDGPU 4 3
24 VGA_HDMI_TXD2-
C524 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX2- R794

5
C525 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX2+ 1K_0402_5% HDMI_TX2- R513 1 2 0_0402_5% HDMI_R_D2-
24 VGA_HDMI_TXD2+
2 2 OPT11@1

P
B
24 VGA_HDMI_TXD1-
C526 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX1- 22 VGA_HDMI_DET 4 Y
C527 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX1+ 1 HDMI_HPD
24 VGA_HDMI_TXD1+ A

G
HDMI_TX2- R515 1 UMA@ 2 680_0402_5% HDMI_GND
C528 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX0- U44 HDMI_TX2+ R516 1 UMA@ 2 680_0402_5%
24 VGA_HDMI_TXD0-

2
G
C529 OPT11@ 2 1 0.1U_0402_16V7K HDMI_TX0+ NC7SZ08P5X_NL_SC70-5
24 VGA_HDMI_TXD0+
OPT11@ HDMI_TX1- R517 1 UMA@ 2 680_0402_5%
C530 OPT11@ 2 1 0.1U_0402_16V7K HDMI_CLK- 3 1 DGPU_HPD_INT# 18 HDMI_TX1+ R518 1 UMA@ 2 680_0402_5%
24 VGA_HDMI_TXC-
C531 OPT11@ 1 0.1U_0402_16V7K HDMI_CLK+

D
24 VGA_HDMI_TXC+ 2
Q26 HDMI_TX0- R519 1 UMA@ 2 680_0402_5%
2N7002E_SOT23-3 HDMI_TX0+ R520 1 UMA@ 2 680_0402_5%
OPT11@
HDMI_CLK- R521 1 UMA@ 2 680_0402_5%
HDMI_CLK+ R522 1 UMA@ 2 680_0402_5%

UMA 680_0402_5%
+HDMI_5V_OUT DIS 499_0402_1%

1
D

+3VS 2
G
HDMI connector Q27 S

3
2N7002E_SOT23-3
2

+3VS D11 D12

RB751V-40_SOD323-2 RB751V-40_SOD323-2 JHDMI1
B R529 1 UMA@ 2 2.2K_0402_1% SDVO_SCLK HDMI_HPD B
19 HP_DET
+HDMI_5V_OUT 18 +5V
R530 1 UMA@ 2 2.2K_0402_1% SDVO_SDATA 17
Optimus 1.1 Option Component
2 1

2 1

DDC/CEC_GND
2.2K_0402_5%

2.2K_0402_5%

+3VS HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
R525 1 UMA@ 2 0_0402_5% 14
R523

R524

16 SDVO_SCLK Reserved
R527 1 UMA@ 2 0_0402_5% 13 R515 2 OPT11@
1 499_0402_1%
16 SDVO_SDATA CEC
HDMI_R_CK- 12 20 R516 2 OPT11@
1 499_0402_1%
CK- G1
2
G

11 21
1

1109 RF request HDMI_R_CK+ CK_shield G2 R517 2 OPT11@

1 499_0402_1%
10 CK+ G3 22
24 VGA_HDMI_SCLK R526 1 OPT11@2 0_0402_5% HDMI_SCLK_R 3 1 HDMI_SCLK HDMI_R_D0- 9 23 R518 2 OPT11@
1 499_0402_1%
D0- G4
S

8 D0_shield
2

1
G

Q28 HDMI_R_D0+ 7 R519 2 OPT11@

1 499_0402_1%
2N7002E_SOT23-3 C532 HDMI_R_D1- D0+ R520 2 OPT11@
1 499_0402_1%
6 D1-
R528 1 OPT11@2 0_0402_5% HDMI_SDATA_R 3 1 HDMI_SDATA 47P_0402_50V8J 5
24 VGA_HDMI_SDATA
2

@ HDMI_R_D1+ D1_shield R521 2 OPT11@

1 499_0402_1%
S

4 D1+
1

Pull high at VGA side Q29 HDMI_R_D2- 3 R522 2 OPT11@

1 499_0402_1%
2N7002E_SOT23-3 C533 D2-
2 D2_shield
47P_0402_50V8J HDMI_R_D2+ 1
2

@ D2+
Place closed to JHDMI1
SUYIN_100042GR019M23DZL
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 33 of 57
5 4 3 2 1
 5 4 3 2 1

D D

SATA HDD1 Conn.

CL 4.0 mm
JHDD1
1 1
13 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C534 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 C535 1 2
13 SATA_PTX_DRX_N0 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 3
4 4
SATA_PRX_DTX_N0 C536 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5
13 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C537 1 SATA_PRX_C_DTX_P0 5
13 SATA_PRX_DTX_P0 2 0.01U_0402_16V7K 6 6
7 7
8 +3VS
+3VS 8
9 9
10 10

1
11 C538
+5VS R531 11 0.1U_0402_16V4Z
12 12
0_0805_5% 13

2
+5VS_HDD1 13
1 2 14 14
15 15
16 16
17 17
18 18
19 +5VS_HDD1
19
20 20
C C
21 G1 100mils
22 G2
23 G3

10U_0805_10V4Z
C539

0.1U_0402_16V4Z
C541

1000P_0402_50V7K
C542
24 G4 1

1
C540
ACES_50406-02071-001
CONN@

2
2

1U_0402_6.3V6K

SATA ODD Conn.

JODD1
+5VS +5VS_ODD
R532 1
0_0805_5% C543 1 GND
13 SATA_PTX_DRX_P2 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P2 2 TX+
+VSB 1 @ 2 13 SATA_PTX_DRX_N2 C544 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N2 3 TX-
4 GND
C545 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N2 5
13 SATA_PRX_DTX_N2 RX-
D

6 C546 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 6

S

13 SATA_PRX_DTX_P2 RX+
2

5 4 7 +5VS_ODD
GND
1
1U_0402_6.3V6K
C547

R533 2 80mils
470K_0402_5% 1 Q30 R534 1 2 0_0402_5% ODD_DETECT#_R 8
18 ODD_DETECT# DP
SI3456DDV-T1-GE3_TSOP6 +5VS_ODD 9
G

+5VS_ODD
2

5V

10U_0805_10V4Z
C548

0.1U_0402_16V4Z
C550

1000P_0402_50V7K
C551
10 1
1

5V

1
B R535 0_0402_5% ODD_DA#_R C549 B
17 ODD_DA# 1 2 11 MD GND 14
12 GND GND 15
ODD_EN 13

2
GND 2
1

D
1.5M_0402_5%
R536

0.1U_0402_25V6
C552
1

2 SUYIN_127382FB013S266ZR 1U_0402_6.3V6K
18 ODD_EN#
G CONN@
Q31 S
3

2N7002E_SOT23-3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 34 of 57
5 4 3 2 1
 5 4 3 2 1

Power On strapping
Place Close to LAN chip
Pin Description Chip Default
+3V_LAN Check PU/PD on MB side H:Over Clock Enable LAN_MIDI0+ R537 1 2 @1 2 C553 1000P_0402_50V7K
LED0 49.9_0402_1%
L:Over Clock Disable *
H LAN_MIDI0- R538 1 2 1 2 C554 0.1U_0402_16V4Z
1 @ 2 PLT_RST# 49.9_0402_1%
R539 4.7K_0402_5% H:SWR Switch mode regulator Select LAN_MIDI1+ R540 1 2 @1 2 C555 1000P_0402_50V7K
AR8151-BL1A 49.9_0402_1%
1 2 LAN_WAKE# LED1 AR8151 Pin39 LAN_MIDI1- R542 1 2 1 2 C556 0.1U_0402_16V4Z
R541 4.7K_0402_5% *
H: switch regulator applied.
applies 49.9_0402_1%
switch mode LAN_MIDI2+ R543 1 8151@ 2 @1 2 C557 1000P_0402_50V7K
L: switch regulator isn't applied. 49.9_0402_1%
D
1 2 LAN_CLKREQ# regulator. LAN_MIDI2- R545 1 8151@ 2 1 2 C558 0.1U_0402_16V4Z D
R544 4.7K_0402_5% AR8152, Pin23 is CLKREQ 49.9_0402_1% 8151@
LAN_MIDI3+ R546 1 8151@ 2 @1 2 C559 1000P_0402_50V7K
Close to lan chip. 49.9_0402_1%
LAN_MIDI3- R547 1 8151@ 2 1 2 C560 0.1U_0402_16V4Z
49.9_0402_1% 8151@

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+

resister and cap
no overclocking
PD 5.1K Note 2 : C553, C555, C557, C559 reserved for EMI.
1 2
U20 LED0,1,2 intel Pull UP R548 5.1K_0402_5%
Place Close to Chip
PCIE_PRX_DTX_N1 C561 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38
14 PCIE_PRX_DTX_N1 TX_N LED_0 LAN_ACT 36
PCIE_PRX_DTX_P1 C562 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 39
23 R550 1 8152@ 2 LAN_CLKREQ#
LAN_LINK# 36
14 PCIE_PRX_DTX_P1 TX_P 8151-AL1A LED_2 0_0402_5%
PCIE_PTX_C_DRX_N1 36
14 PCIE_PTX_C_DRX_N1 RX_N
TRXN0 12 LAN_MIDI0- 36
PCIE_PTX_C_DRX_P1 35 11
14 PCIE_PTX_C_DRX_P1 RX_P TRXP0 LAN_MIDI0+ 36
15 +3VALW_PCH
TRXN1 LAN_MIDI1- 36
CLK_PCIE_LAN# R551 2 1 0_0402_5% CLK_PCIE_LAN#_R 32 14 R557
14 CLK_PCIE_LAN# REFCLK_N TRXP1 LAN_MIDI1+ 36
CLK_PCIE_LAN R549 2 1 0_0402_5% CLK_PCIE_LAN_R 33 18 0_1206_5%
14 CLK_PCIE_LAN REFCLK_P TRXN2 LAN_MIDI2- 36
TRXP2 17 LAN_MIDI2+ 36
LAN_RST# 2 21 2 1
PERST# TRXN3 LAN_MIDI3- 36
TRXP3 20 LAN_MIDI3+ 36
PCH_PCIE_WAKE# R552 1 @ 2 0_0402_5% LAN_WAKE# 3
15,37,44 PCH_PCIE_WAKE# WAKE#
EC_PME# R553 1 2 0_0402_5% 25 10 LAN_RBIAS 1 2 +3V_LAN R555 +3VALW
C 39 EC_PME# SMCLK RBIAS C
26 R554 2.37K_0402_1% 0_1206_5%
SMDATA
28 TEST_RST VDD33 1 40mils 2 @ 1
27 TESTMODE

C565

C567

C568
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
8152@ 40 +1.7_LX +1.7_LX 1 1 1 1
LAN_XTALO LX C566

S
1 2 7 XTLO 1 3
C563 0.1U_0402_16V4Z LAN_XTALI 8 Q37
XTLI +1.7_VDDCT 40mils @ AO3413L_SOT23-3

G
VDDCT 5 +1.7_VDDCT 2 2 2 2
1 2 C564 @

2
LAN_CLKREQ# 1 8151@ 2 4 0.1U_0402_16V4Z
14 LAN_CLKREQ#
R556 0_0402_5% CLKREQ#
DVDDL 24 +1.1_DVDDL 20mils PCH_PWR_EN#
PCH_PWR_EN# 20,46
37 +1.1_DVDDL
20mils +1.1_AVDDL 13
DVDDL_REG 1U_0402_6.3V6K
+1.1_AVDDL 19
AVDDL
AVDDL
20mils
+1.1_AVDDL 31 16 +2.7_AVDDH_R 1 8151@ 2 +2.7_AVDDH C565 & C566 Close pin1 < 200mil
+1.1_AVDDL AVDDL AVDDH +2.7_AVDDH R738 0_0402_5%
34 22
+1.1_AVDDL 6
AVDDL AVDDH
9 +2.7_AVDDH C567 & C568 Close pin < 400mil
AVDDL_REG AVDDH_REG

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
8151@ 8151@ 8151@
C569

C570

C571

C572

C574

C575

C577

C578

C579

C581
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 41 GND 1 1 1 1 1 1 2
C573 C576 C580
AR8151-BL1A-RL
8151@
2 2 2 2 2 2 2 2 2 2 2 2 1

8152 is LED2 Function (NC)

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
LAN_XTALI
Near Near Near Near Near Near Near Near Near Near
LAN_XTALO
Y4 Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 Pin37 Pin24
B B
1 2
33P_0402_50V8J

33P_0402_50V8J

25MHZ_20PF_7A25000012

1 1
C582

C583

2 2
Note: Place Close to LAN chip
L2 DCR< 0.15 ohm
Rate current > 1A
+1.7_VDDCT +1.7_LX

L30
1 2 40mils

1000P_0402_50V7K
4.7UH_SIA4012-4R7M_20%
+3V_LAN

10U_0805_10V4Z
0.1U_0402_16V4Z
C584 @ 1 1
0.1U_0402_16V4Z
1 2
@
U21 2 2
5

C585

C586

C587
@
2 B Configure Configure
P

PLT_RST# 4 LAN_RST#
5,17,38,39,44 PLT_RST# Y
1 A Pin4 R556 C563 Pin23 R550
G

Pull low 100K at PCH side(P17)

NC7SZ08P5X_NL_SC70-5
3

AR8152 VDDCT_REG * CLKREQn * Close to

Pin40
A
1 2 AR8151 CLKREQn * LED[2] A
R558 0_0402_5%

Reserve for 8151A/B PERST# leakage issue

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 35 of 57
5 4 3 2 1
 5 4 3 2 1

D D

BH GS5009-E
<SP050006B10>

TAIMAG IH-160
<SP050006F00>

T63
JRJ45
35 LAN_ACT 1 2 11 Yellow LED+
35 LAN_MIDI0- LAN_MIDI0- 12 13 RJ45_MIDI0- R559 300_0402_5%
LAN_MIDI0+ TD4- MX4- RJ45_MIDI0+
35 LAN_MIDI0+ 11 TD4+ MX4+ 14 1 12 Yellow LED-
10 15 C588 15
TCT4 MCT4 470P_0402_50V7K RJ45_MIDI3- SHLD1
8 PR4-
35 LAN_MIDI1- LAN_MIDI1- 9 16 RJ45_MIDI1- @ 13
LAN_MIDI1+ TD3- MX3- RJ45_MIDI1+ 2 RJ45_MIDI3+ DETECT PIN1
35 LAN_MIDI1+ 8 TD3+ MX3+ 17 7 PR4+
7 TCT3 MCT3 18
RJ45_MIDI1- 6
LAN_MIDI2- RJ45_MIDI2- PR2-
35 LAN_MIDI2- 6 TD2- MX2- 19
35 LAN_MIDI2+ LAN_MIDI2+ 5 20 RJ45_MIDI2+ RJ45_MIDI2- 5
TD2+ MX2+ PR3-
4 TCT2 MCT2 21
RJ45_MIDI2+ 4
LAN_MIDI3- RJ45_MIDI3- PR3+
35 LAN_MIDI3- 3 TD1- MX1- 22
35 LAN_MIDI3+ LAN_MIDI3+ 2 TD1+ MX1+ 23 RJ45_MIDI3+ RJ45_MIDI1+ 3 PR2+ Guide Pin
1 TCT1 MCT1 24
C RJ45_MIDI0- C
Reserved for ESD 2 PR1-
S X'FORM_ IH-160 LAN @ D40 2 1B88069X9231T203_4P5X3P2-2 RJ45_MIDI0+ 1
+1.7_VDDCT PR1+
25mil SP050006F00
@ D41 SHLD1 14
2 1B88069X9231T203_4P5X3P2-2 +3V_LAN 9 Green LED+
1 2 +1.7_VDDCT_R
1

1
75_0402_1%

75_0402_1%
@ D42 2 1B88069X9231T203_4P5X3P2-2 1 2 10
35 LAN_LINK# Green LED-
C591

C592

C593

C594
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R560 R561 1 R563 300_0402_5%

R562
0_0603_5% 1 1 1 1 @ D43 2 1B88069X9231T203_4P5X3P2-2 @ SANTA_130452-3_13P-T
1 C589 CONN@

1
75_0402_1%

75_0402_1%
470P_0402_50V7K
2

2
2
R564

R565
C590
1U_0402_6.3V6K 2 2 2 2 C595
2 1000P_1206_2KV7K
RJ45_GND 1 2 LANGND
2

2
RJ45_GND
40mil
40mil
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
C596

C597

C598

C599

LAN_ACT

1
1 1 1 1 LAN_LINK#
L31

@ @ @ @
For EMI D36
100UH_SSC0301101MCF_0.18A_20%
2 2 2 2 PJDLC05C_SOT23-3

2
1
Close CT1 Close CT3 D13 LANGND
Close CT2 Close CT4 PJDLC05C_SOT23-3
B @ B

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 36 of 57
5 4 3 2 1
 A B C D E

For Wireless LAN +3VS_WLAN +1.5VS +3VS_WLAN

1
C602 C603 C604 C605 C606 C607
+3VS R566 +3VS_WLAN 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0_1206_5% 60mil

2
2 1

1
For 3G / GPS 1
+3VS_WLAN
+1.5VS +3VS_WLAN
Mini Card Power Rating
R568

1
0_0402_5%
@ 2 1
JMINI1
2
Power Primary Power (mA) Auxiliary Power (mA) To 3G Module Connect
15,35,44 PCH_PCIE_WAKE# 1 2
(WLAN_BT_DATA) 3 4 Peak Normal Normal
(WLAN_BT_CLK) 3 4
5 5 6 6
14 MINI1_CLKREQ# 7 7 8 8 +3VS 1000 750
9 9 10 10 Peak: 2.75A +3VALW
14 CLK_PCIE_MINI1# 11 11 12 12 +3V 330 250 250 (wake enable) Normal: 1.1A
14 CLK_PCIE_MINI1 13 13 14 14
15 16 +1.5VS 500 375 5 (Not wake enable) J3G1
15 16
21 GND 1 1
2 2
17 17 18 18 3 3
19 20 WL_OFF# 4
19 20 WL_OFF# 18 4
21 22 PLT_RST_BUF# 5
21 22 PLT_RST_BUF# 17 5
14 PCIE_PRX_DTX_N2 23 24 R569 1 2 0_0603_5% +3VS 6 WWAN_OFF#
23 24 6 WWAN_OFF# 18
14 PCIE_PRX_DTX_P2 25 26 7 WWAN_LED# WWAN_LED# 39
25 26 7
27 27 28 28 8 8
29 30 MINI1_SMBCLK R570 1 @ 2 0_0402_5% PCH_SMBCLK 14 9 USB20_N9
29 30 9 USB20_N9 17
31 32 MINI1_SMBDATA R571 1 @ 2 0_0402_5% PCH_SMBDATA 14 10 USB20_P9
14 PCIE_PTX_C_DRX_N2 31 32 10 USB20_P9 17
14 PCIE_PTX_C_DRX_P2 33 33 34 34 11 11
35 36 12 USB20_N12
35 36 USB20_N8 17 12 USB20_N12 17
37 38 13 USB20_P12
37 38 USB20_P8 17 13 USB20_P12 17
39 40 14 R641 10K_0402_5%
R576 39 40 R573 1 14
41 41 42 42 2 0_0402_5% 15 15 1 2 +3VS
100K_0402_5% 43 44 MINI1_LED# 39 16 UIM_DET_EC UIM_DET_EC 39
43 44 16
2<BOM Structure>
1 R574 45 45 46 46 17 17 EC_SIM_DETECT#
EC_SIM_DETECT# 39
0_0402_5% 47 47 48 48 (9~16mA) 18 18 WWAN_DET#_EC 39

1
39 E51TXD_P80DATA 1 2 E51TXD_P80DATA1_R 49 49 50 50 19 19
1 2 51 52 R575 22 20 R577 1 2 +3VALW
2 39 E51RXD_P80CLK 51 52 GND 20 2
100K_0402_5% 100K_0402_5%
R578 ACES_87213-2000G +VSB
G1
G2
G3
G3
+VSB
0_0402_5% CONN@

2
2

ACES_88910-5204
53
54
55
56

R490 CONN@
D33 +3VS_WLAN
RB751V-40_SOD323-2
1K_0402_5% 4 mm High
@
1

1 2 BT_CTRL
39,46,52,53 SUSP#
1

D Q54
BT_ON# 2 2N7002E_SOT23-3
G
S
3

+5VALW +USB_VCCB
U22 +3VALW +3VS
1 GND VOUT 8
2 VIN VOUT 7
3 VIN VOUT 6

1
BT Conn.
EPAD

4 5 C613 BT@
EN FLG USB_OC0# 17
1

C612 0.1U_0402_16V4Z C614

4.7U_0805_10V4Z BT@ 1U_0603_10V6K

2
3
+BT_VCC
(Port 13)
3 AP2301MPG-13_MSOP8 S 3
2

BT_ON# 1 BT@ 2 2 Q32

18 BT_ON# G
R579 10K_0402_5% BT@ JBT1
D AO3413L_SOT23-3 8 6

1
SYSON# G2 6
46 SYSON# 7 G1 5 5

2
USB/B Conn.
C615 W=40mils 4
4 USB20_P13 17
0.1U_0402_16V4Z +BT_VCC 3
3 USB20_N13 17
BT@ 2

1
2

1
BT@ BT@ 1
1

1
4.7U_0805_10V4Z
C616

0.1U_0402_16V4Z
C617
JUSB1 R580
300_0603_5% ACES_87212-06G0
28 BT@ CONN@
BT Wire Cable Note:

2
GND1
(Port 0,1) 27

2
GND2
USB20_N0
26 26 Pin 3, Pin 4 NC
17 USB20_N0 25 25
USB20_P0 24
17 USB20_P0 24

1
D Q33
23 23 GND
USB20_N1 22 2 2N7002E_SOT23-3
17 USB20_N1 USB20_P1 22 G BT@
17 USB20_P1 21 21
20 S

3
20
19 19
18 18
+USB_VCCB 17 17
16 16
W=120mils 15 15
14 14
+3VALW 13 13
LID_SW# 12
39 LID_SW# 12
11 11
42 SPDIF_OUT SPDIF_OUT 10 10
+5VSPDIF 9 9
SPDIF_PLUG# 8
4 42 SPDIF_PLUG# 8 4
42 HP_LEFT HP_LEFT 7
HP_RIGHT 7
42 HP_RIGHT 6 6
MIC1_VREFO 5 5
42 MIC1_L 4 4
42 MIC1_R 3 3
42 MIC_PLUG# 2 2
1 1
ACES_88514-02601-071 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ 2010/09/28 2011/09/28 Title
Issued Date Deciphered Date
GND SCHEMATIC, MB LA-7231P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
GND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
For AUDIO GND
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 37 of 57
A B C D E
 A B C D E

+3VS +3VS_CARD Modify R02, Add 0R between

1 2 +3VS and +3VS_CARD
R833 0_0805_5%
Card Reader 40 mils 40 mils

U23 +3VS_CARD
10 mils
14 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_p3 1 48 RREF R581 2 1 6.2K_0603_1%
1 HSIP RREF 1
PCIE_PTX_C_DRX_N3 2 47
40 mils 2 1
14 PCIE_PTX_C_DRX_N3 HSIN 3V3_IN C620 0.1U_0402_10V7K
14 CLK_PCIE_CARD CLK_PCIE_CARD 3 46 CARD_CLKREQ#
REFCLKP CLK_REQ# CARD_CLKREQ# 14

14 CLK_PCIE_CARD# CLK_PCIE_CARD# 4 45 PLT_RST#

REFCLKN PERST# PLT_RST# 5,17,35,39,44
1 2
20 mils AV12 5 44
C618 4.7U_0603_6.3V6K AV12 EEDO
PCIE_PRX_DTX_P3 1 2 PCIE_PRX_C_DTX_P3 6 43
14 PCIE_PRX_DTX_P3 HSOP EECS
C619 0.1U_0402_10V7K
+ODR_PWR PCIE_PRX_DTX_N3 1 2 PCIE_PRX_C_DTX_N3 7 42
14 PCIE_PRX_DTX_N3 HSON EESK
C621 0.1U_0402_10V7K
8 41 5IN1_LED#
GND GPIO/EEDI 5IN1_LED# 41
1 2
20 mils DV12 9 40 MS_INS#
+ODR_PWR C622 0.1U_0402_10V7K DV12 MS_INS#
0.1U_0402_10V7K 40 mils
C623

10U_0603_6.3V6M
C624

0.1U_0402_10V7K
C625

0.1U_0402_10V7K
C626
10 39 SD_CD#
Card1_3V3 SD_CD#
1
100K_0402_5%
R582

1 1 1 1 40 mils 11 38 SP15_SDWP_XDD7
+3VS_CARD 3V3_IN SP15
@

10U_0603_6.3V6M
C627

0.1U_0402_10V7K
C628
1 1 12 37 SP14_MSCLK_XDD6 1 2 SP14_MSCLK_XDD6_R
2
2 2 2 2 Card2_3V3 SP14 R583 0_0402_5% @
2

5P_0402_50V8C
XD_CD# 13 36 SP13_MSD7_XDD5
XD_CD# SP13

C629
2 2 20 mils DV33_18 14 35 SP12_MSD3_XDD4 1
DV33_18 SP12

4.7U_0603_6.3V6K

0.1U_0402_10V7K
@ SP11_MSD6_XDD3
1 1 15 GND SP11 34

C631
C630
SP1_SDD7_XDRDY 16 33 SP10_MSD2_XDD2
SP1 SP10
Close to connector 2 2 SP2_SDD6_XDRE# 17 32 SP9_MSD0_XDD1
2 SP2 SP9 2
SP3_SDD5_XDCE# 18 31 SP8_MSD4_XDD0
SP3 SP8
SP4_SDD4_XDWE# 19 30 SP7_MSD1_XDWP#
SP4 SP7
1 SD_D1_R 2 SD_D1 20 29 SP6_MSD5_XDALE
R584 0_0402_5% SD_D1 SP6
1 2
SD_D0_R 1 2 SD_D0 21 28 SP5_MSBS_XDCLE C632 4.7U_0603_6.3V6K
@ R585 0_0402_5% SD_D0 SP5
1 2 SD_CLK_R 1 2 SD_CLK 22 27
20 mils 1 2
C633 5P_0402_50V8C R586 33_0402_1% SD_CLK DV12_S C634 0.1U_0402_10V7K
SD_CMD_R 1 2 SD_CMD 23 26
R587 0_0402_5% SD_CMD GND
SD_D3_R 1 2 SD_D3 24 25 SD_D2 1 2 SD_D2_R
R588 0_0402_5% SD_D3 SD_D2 R589 0_0402_5%

RTS5209-GR_LQFP48_7X7

+ODR_PWR +ODR_PWR Reserve for EMI please close to JREAD1

JREAD1
22 XD-VCC SD4-VDD 11
MS9-VCC 18
SP8_MSD4_XDD0 30
SP9_MSD0_XDD1 XD10-D0 SD_CLK_R
29 XD11-D1 SD5-CLK 9 1 2 2 1
SP10_MSD2_XDD2 28 4 SD_D0_R
SP11_MSD6_XDD3 XD12-D2 SD7-DAT0 SD_D1_R R590 C635
27 XD13-D3 SD8-DAT1 3
SP12_MSD3_XDD4 26 21 SD_D2_R 33_0402_5% 6P_0402_50V8D
3 SP13_MSD7_XDD5 XD14-D4 SD9-DAT2 SD_D3_R 3
25 XD15-D5 SD1-DAT3 19
SP14_MSCLK_XDD6 24 16 SD_CMD_R
SP15_SDWP_XDD7 XD16-D6 SD2-CMD SD_CD#
23 XD17-D7 SD-CD 1
2 SP15_SDWP_XDD7
SP4_SDD4_XDWE# SD-WP
33 XD07-WE
SP7_MSD1_XDWP# 32 6 Reserve for EMI
SP6_MSD5_XDALE XD08-WP SD6-VSS
34 XD06-ALE SD3-VSS 13 please close to JREAD1
XD_CD# 39
SP1_SDD7_XDRDY XD01-CD
38 XD02-R/B
SP2_SDD6_XDRE# 37
SP3_SDD5_XDCE# XD03-RE SP14_MSCLK_XDD6_R
36 XD04-CE MS8-SCLK 17 1 2 1 2
SP5_MSBS_XDCLE 35 10 SP9_MSD0_XDD1
XD05-CLE MS4-DATA0 SP7_MSD1_XDWP# R591 C636
MS3-DATA1 8
31 12 SP10_MSD2_XDD2 33_0402_5% 6P_0402_50V8D
XD GND MS5-DATA2 SP12_MSD3_XDD4
40 XD GND MS7-DATA3 15
14 MS_INS#
MS6-INS SP5_MSBS_XDCLE
MS2-BS 7
MS1-VSS 5
41 SD CD/WP GND MS10-VSS 20
42 SD CD/WP GND
T-SOL_144-1300002600_NR
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 38 of 57
A B C D E
 5 4 3 2 1

+3VALW_EC
+3VLP
ESD 12/03 R623
0_0805_5% LID_SW# R592 2 1 100K_0402_5%
PLT_RST# 1 @ 2
5,17,35,38,44 PLT_RST# +3VALW_EC

1
+5VS
C703 R593 L32
0.1U_0402_16V4Z +3VALW 0_0805_5% FBMA-L11-160808-800LMT_0603 TP_CLK R594 1 2 4.7K_0402_5%

2
1 2 +3VALW_EC 1 2 +EC_VCCA
TP_DATA R595 1 2 4.7K_0402_5%

0.1U_0402_16V4Z
C637

0.1U_0402_16V4Z
C638

0.1U_0402_16V4Z
C639

0.1U_0402_16V4Z
C640

1000P_0402_50V7K
C641

1000P_0402_50V7K
C642
1

1
C643 +3VS
D C644 0.1U_0402_16V4Z D

ECAGND 2
22P_0402_50V8J R597 EC_MUTE# R596 2 @ 1 10K_0402_5%
@ 33_0402_5%
2 1 2 @ 1 CLK_PCI_LPC BKOFF# R601 1 2 10K_0402_5%

111
125
22
33
96

67
U24

9
+3VALW_EC

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R602 2 1 200K_0402_5%
+3VALW_EC R603 2 1 47K_0402_5% EC_RST#
GATEA20 1 21 3G_LED# D14
18 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 3G_LED# 41
C646 2 1 0.1U_0402_16V4Z EC_KBRST# 2 23 BEEP# 2 1 ACIN 15,46,48
18 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 42
SERIRQ 3 26 FAN_PWM RB751V-40_SOD323-2
13 SERIRQ SERIRQ# FANPWM1/GPIO12 FAN_PWM 45
LPC_FRAME# 4 27 ACOFF
13 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 47
LPC_AD3 5 EC_ACIN C645 2 1 100P_0402_50V8J
13 LPC_AD3 LAD3
LPC_AD2 7 PWM Output C647 2 1 100P_0402_50V8J ECAGND
+3VALW_EC 13 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
13 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 50
10/1 ENE Recommand LPC_AD0 BI_EC
13 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BI_EC 40
ADP_I/AD2/GPIO3A 65 ADP_I 48,50
R598 1 2 47K_0402_5% KSO1 CLK_PCI_LPC 12 AD Input 66 AD_BID0
17 CLK_PCI_LPC PCICLK AD3/GPIO3B
PLT_RST# 13 75 AD_PID0
R599 KSO2 EC_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 47K_0402_5% 37 ECRST# SELIO2#/AD5/GPIO43 76 @ T69
EC_SCI# 20
18 EC_SCI# SCI#/GPIO0E +3VS
PWR_SUSP_LED 38
41 PWR_SUSP_LED CLKRUN#/GPIO1D
R600 1 2 10K_0402_5% EC_SMI# 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 31
70 EC_SIM_DETECT#
EN_DFAN1/DA1/GPIO3D EC_SIM_DETECT# 37
R605 1 2 2.2K_0402_5% EC_SMB_DA1 DA Output 71 @ T67 1 2
IREF/DA2/GPIO3E

5
KSI0 55 72 @ T68 U25 C648 0.1U_0402_16V4Z
KSI1 KSI0/GPIO30 DA3/GPIO3F
56

P
R606 EC_SMB_CK1 KSI2 KSI1/GPIO31 H_PROCHOT#_EC
1 2 2.2K_0402_5% 57 KSI2/GPIO32 2 A Y 4

1
KSI3 EC_MUTE#

NC
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# 42

G
C C649 KSI4 GFX_CORE_PWRGD R607 C
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 GFX_CORE_PWRGD 54
22P_0402_50V8J R608 KSI5 60 85 WWAN_LED# WWAN_LED# 37 100K_0402_5% SN74LVC1G06DCKR_SC70-5

1
@ 33_0402_5% KSI6 KSI5/GPIO35 PSCLK2/GPIO4C H_PROCHOT#_EC
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
2 1 1 @ 2 KSI7 62 87 TP_CLK
TP_CLK 40

2
KSI[0..7] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA R609
40,41 KSI[0..7] 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 40
KSO1 40 0_0402_5%
Reserve for EMI please close to U24 KSO[0..17] KSO2 KSO1/GPIO21 VR_HOT#
40,41 KSO[0..17] 41 KSO2/GPIO22 54 VR_HOT# 2 1 H_PROCHOT# 5,50
KSO3 42 97 GPU_VID1
KSO3/GPIO23 SDICS#/GPXOA00 GPU_VID1 22,55
KSO4 43 98
+3VS KSO5 KSO4/GPIO24 SDICLK/GPXOA01 HDA_SDO
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
HDA_SDO 13
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 37
R610 1 2 2.2K_0402_5% EC_SMB_CK2 KSO7
KSO8
46 KSO7/GPIO27 SPI Device Interface Latest design guide suggest change UE4 to 74LVC1G06.
47 KSO8/GPIO28
R611 1 2 2.2K_0402_5% EC_SMB_DA2 KSO9 48 KSO9/GPIO29 SPIDI/RD# 119 FRD#_R R612 1 2 0_0402_5% FRD#
KSO10 49 120 FWR#_R R613 1 2 33_0402_5% FWR#
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK_R R614 33_0402_5% SPI_CLK
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 1 2
R615 1 2 10K_0402_5% EC_SCI# KSO12 51 128 FSEL#_R R616 1 2 33_0402_5% FSEL#
KSO13 KSO12/GPIO2C SPICS#
52 KSO13/GPIO2D
KSO14 53
KSO15 KSO14/GPIO2E UIM_DET_EC
54 KSO15/GPIO2F CIR_RX/GPIO40 73 UIM_DET_EC 37
KSO16 81 74 EC_PECI R617 1 2 43_0402_1%
KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI 5,18
KSO17 82 89 USB_CHARGE_CB
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 USB_CHARGE_CB 45
90 BATT_AMB_LED#
BATT_CHGI_LED#/GPIO52 BATT_AMB_LED# 41
SPI ROM 128KB
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 41
EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_BLUE_LED#
48,50 EC_SMB_CK1 SCL1/GPIO44 BATT_BLUE_LED# 41 +3VALW_EC
EC_SMB_DA1 78 93 PWR_LED PWR_LED 41
48,50 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
EC_SMB_CK2 79 SM Bus 95 SYSON U26
14,22 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 44,46,51 20mils
EC_SMB_DA2 80 121 VR_ON 8 4
14,22 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 54 VCC VSS
127 EC_ACIN
AC_IN/GPIO59

1
C650 3
0.1U_0402_16V4Z W
PM_SLP_S3# 6 100 PCH_RSMRST# 7
15 PM_SLP_S3# PCH_RSMRST# 15

2
B PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 LID_SW_OUT# HOLD B
15 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 LID_SW_OUT# 14
EC_SMI# 15 102 EC_ON FSEL# 1
18 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 40 S
EC_XCLK1 EC_XCLK0 WWAN_DET#_EC 16 103 EC_PME#
37 WWAN_DET#_EC LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_PME# 35
MINI1_LED# 17 104 PCH_PWROK SPI_CLK 6
37 MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 PCH_PWROK 15 C
USB_CHARGE_2A# 18 GPO 105 BKOFF#
45 USB_CHARGE_2A# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 31
1

C651 C652 GPU_VID0 19 GPIO 106 PWR_SAVE_LED# FWR# 5 2 FRD#

22,55 GPU_VID0 EC_PME#/GPIO0D WL_OFF#/GPXO09 PWR_SAVE_LED# 41 D Q
1

15P_0402_50V8J 15P_0402_50V8J USB_CHARGE_100mA 25 107 WLAN_LED#

45 USB_CHARGE_100mA EC_THERM#/GPIO11 GPXO10 WLAN_LED# 41
FAN_SPEED1 28 108 BATT_RED_LED# MX25L1005AMC-12G
OSC

OSC

BATT_RED_LED# 41
2

45 FAN_SPEED1 PCH_PWR_EN FAN_SPEED1/FANFB1/GPIO14 GPXO11

46 PCH_PWR_EN 29 FANFB2/GPIO15
E51TXD_P80DATA 30 SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P 3.3V)
37 E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 PM_SLP_S4#
37 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# 15
ON/OFF ENBKL
NC

NC

40 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL 16

T91@ TP_LED_ON/OFF 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD 42
NUM_LED# 36 GPI 115 SA_PGOOD SA_PGOOD 52 C653
41 NUM_LED#
2

NUMLED#/GPIO1A GPXID4 SUSP# R618 100P_0402_50V8J

GPXID5 116 SUSP# 37,46,52,53
X1 117 PBTN_OUT# 22_0402_5% @
GPXID6 PBTN_OUT# 15
32.768KHZ_12.5PF_Q13MC14610002 118 NV_PERFORMANCE SPI_CLK 2 @ 1 1 2
GPXID7 NV_PERFORMANCE 22
EC_XCLK1 122
@ EC_XCLK0 XCLK1 +V18R
15 SUSCLK 1 2 123 XCLK0 V18R 124
R619 0_0402_5% Reserve for EMI please close to U26

1
AGND

R655 1 @ 2 C654
GND
GND
GND
GND
GND

100K_0402_5% 4.7U_0805_10V4Z

2
KB930QF_A1
11
24
35
94
113

69

20mil
L33
Board ID Project ID ECAGND 2 1
FBMA-L11-160808-800LMT_0603
+3VALW_EC +3VALW_EC
Analog Board ID definition, Analog Project ID definition,
Please see page 3.
2

A R620 R769 A

Ra 100K_0402_5% Ra 100K_0402_5%
1

AD_BID0 AD_PID0
1

1
1

R621 C655 R770 C843

Rb 33K_0402_5% 0.1U_0402_16V4Z Rb 8.2K_0402_5% 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
2

SCHEMATIC, MB LA-7231P
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 39 of 57
5 4 3 2 1
 1 2 3 4 5 6 7 8

INT_KBD Conn.

KSI[0..7] Reset Button D-Door Battery Power

KSI[0..7] 39,41
JM
(Left) KSO[0..17]
KSO[0..17] 39,41
Down Button
JKB1
R691

10

9
A +RTCVCC 510K_0402_5% SW8 A
1 KSO0 KSO0 C677 1 2 100P_0402_50V8J R648 2 1 R653 MSS6-Q-T-R_6P

G
1 39 BI_EC
2 KSO1 KSO1 C675 1 2 100P_0402_50V8J 1K_0402_5% 0_0402_5% @
2 KSO2 KSO2 C673 100P_0402_50V8J BI BI @
3 3 1 2 1 2 50 BI 1 2 BI_R 3 3 6 6
4 KSO3 KSO3 C669 1 2 100P_0402_50V8J
4 KSO4 KSO4 C667 100P_0402_50V8J
5 5 1 2 2 2 5 5
6 KSO5 KSO5 C665 1 2 100P_0402_50V8J D18 R656 SW7 R654
6

3
7 KSO6 KSO6 C663 1 2 100P_0402_50V8J 3 0_0402_5% S Q35 0_0402_5%
7 49,50 MAINPWON
8 KSO7 KSO7 C659 1 2 100P_0402_50V8J 1 1 @ 2 1 2 BI_GATE 2 AO3413L_SOT23-3 BI_RESET 1 2 1 4
8 KSO8 KSO8 C684 100P_0402_50V8J G 1 4
9 9 1 2 49 3V5V EN 2

G
10 KSO9 KSO9 C680 1 2 100P_0402_50V8J D

1
10

1
11 KSO10 KSO10 C674 1 2 100P_0402_50V8J SKPMAME010_2P

7
11 KSO11 KSO11 C672 100P_0402_50V8J BAV70W_SOT323-3
12 12 1 2
13 KSO12 KSO12 C668 1 2 100P_0402_50V8J R646 Test Only
13

1
KSO13 KSO13 C666 100P_0402_50V8J D 10K_0402_5% BI_RESET
14 14 1 2
15 KSO14 KSO14 C664 1 2 100P_0402_50V8J BI_GATE 2 Q38

2
15 KSO15 KSO15 C662 100P_0402_50V8J G
16 16 1 2 2N7002E_SOT23-3
17 KSO16 KSO16 C657 1 2 100P_0402_50V8J S

3
17 KSO17 KSO17 C658 100P_0402_50V8J Need Check Gate Threshold Voltage
18 18 1 2
19 KSI0 KSI0 C670 1 2 100P_0402_50V8J Battery BI Low voltage is 0.8V
19 KSI1 KSI1 C676 100P_0402_50V8J
20 20 1 2
21 KSI2 KSI2 C678 1 2 100P_0402_50V8J
21 KSI3 KSI3 C682 100P_0402_50V8J JDOOR1
22 22 1 2
23 KSI4 KSI4 C671 1 2 100P_0402_50V8J BI_R 1 3
23 KSI5 KSI5 C679 100P_0402_50V8J 1 GND
24 24 1 2 2 2 GND 4
27 25 KSI6 KSI6 C681 1 2 100P_0402_50V8J
G1 25 KSI7 KSI7 C683 100P_0402_50V8J ACES_85205-0200N
28 G2 26 26 1 2
CONN@

ACES_85201-26051
CONN@
B B
(Right)

To TP/B Conn. +5VS

Power Button
1

C656
0.1U_0402_16V4Z
+3VALW_EC
JM ON/OFF switch
2

+5VS
JTP1

2
8 G2 6 6
7 5 TP_CLK R622
G1 5 TP_CLK 39
4 TP_DATA 100K_0402_5%
4 TP_DATA 39
3 LEFT_BTN#
3
C660
100P_0402_50V8J

C661
100P_0402_50V8J

2 RIGHT_BTN#

1
2
3

1 D17
1
2 ON/OFF 39
@ @ ON/OFFBTN# 1
41 ON/OFFBTN#
2

C E-T_6916-Q06N-00R D15 51ON# C

3 51ON# 47
CONN@ PJDLC05C_SOT23-3
BAV70W_SOT323-3
TOP Side

1
R644 @ D
1 2 0_0402_5% Q34
1

EC_ON 2 2N7002E_SOT23-3
39 EC_ON
Bottom Side G

2
S

3
R645 1 @ 2 0_0402_5% R624
10K_0402_5%

1
Test Only

SW2 SW3
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# LEFT_BTN# 3 1 RIGHT_BTN# 3 1

RIGHT_BTN# 4 2 4 2
3

5
6

5
6

D16
PJDLC05C_SOT23-3

D
100g for Press 100g for Press D
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 40 of 57
1 2 3 4 5 6 7 8
 A B C D E

1
Battery LED Battery Indicator BTN 1
Side View LED with Blue/Amber/Red Color
+3VALW
LED1 R626 SW6

4
300_0402_5% MPTCFG-T-Q-T-R_2P
2 1 2 BATT_AMB_LED# BATT_AMB_LED# 39
1 A KSO0 1 2 KSI2 KSI2 39,40
3 1 2 BATT_BLUE_LED# BATT_BLUE_LED# 39
B R625 100_0402_5%

6
HT-210UD5-NB5_AMBER-BLUE

R739 LED2
100_0402_5%
PWR_SUSP_LED# 1 2 2 1 BATT_RED_LED# BATT_RED_LED# 39
R
HT-110USD5_RED

3
6

D
39 PWR_SUSP_LED 2
G
PWR/B
Q36A
2

DMN66D0LDW-7_SOT363-6 JPWR1
R628 S Power LED 1 +3VALW
1

100K_0402_5% 1 PWR_LED#
2 2
+3VALW 3 ON/OFFBTN#
3 ON/OFFBTN# 40
4
1

R627 LED3 4
100_0402_5% 5
2 PWR_LED# GND 2
1 2 2 B 1 GND 6
R629
560_0402_5% ACES_88514-0401
PWR_LED# 1 2 4 3 PWR_SUSP_LED# CONN@
A
3

D HT-297UD5-CB5_AMBER-BLUE
39 PWR_LED 5
G Q36B +3VS
2

DMN66D0LDW-7_SOT363-6
R630 S
HDD LED FUN Board
4

2
100K_0402_5% +3VS
@
R632
1

10K_0402_5% JLED1

5
+3VS R740 LED4 U39 1 +3VS

1
150_0402_1% 1 PWR_SAVE_LED#
2 2

P
B 5IN1_LED# 38 2 PWR_SAVE_LED# 39
1 2 2 1 MEDIA_LED# 4 3 NUM_LED# NUM_LED# 39
B Y 3 CAPS_LED#
A 1 PCH_SATALED# 13 4 4 CAPS_LED# 39

G
5 KSO0 KSO0 39,40
HT-191NB5_BLUE MC74VHC1G08DFT2G_SC70-5 5 KSI1
6 KSI1 39,40

3
6
7 7
8 8
GND 9
GND 10
3G/Wireless LED ACES_50504-0080N-001
CONN@
+3VS
R741 LED5
100_0402_5%
1 2 2 1 3G_LED#
3 B 3G_LED# 39 3
R742
560_0402_5%
1 2 4 3 WLAN_LED#
A WLAN_LED# 39

HT-297UD5-CB5_AMBER-BLUE
KSO0
KSI1 PWR SAVE BTN#
KSI2 Battery ID BTN#

Power/SUS Battery 3G/WLAN BlueTooth ACIN

4 LED Status 4
ON SUS Full Charge 3G WLAN

Blue Amber Blue Amber Blue Amber

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 41 of 57
A B C D E
 5 4 3 2 1

+5VAMP

SM010014520 3000ma 220ohm@100mhz DCR 0.04 1 2 +5VAMP

R633 0_0805_5% HP_PLUG#

3
R789
+5VAMP 100K_0402_5% Q66B
U28

2
DMN66D0LDW-7_SOT363-6
+5VS L34 1 2
60mil 1
40mil R790 5

6 1
FBMA-L11-201209-221LMA30T_0805 IN
OUT 5 +VDDA 4.75V +3VS_CODEC 100K_0402_5%
2

4
GND

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
L35 1 2 C685 C686

1
3
FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V4Z 3 S Q66A
SHDN BYP 4 1 2 1 1 1

C688

C689

C690
@ 0.1U_0402_16V4Z C687 Q67 2 SPDIF_PLUG# 2 DMN66D0LDW-7_SOT363-6

2
D G9191-475T1U_SOT23-5 0.01U_0402_16V7K G D
AO3413L_SOT23-3
@ @ D

1
2 2 2

(output = 300 mA) +5VSPDIF

SPDIF_PLUG# 37

+3VS_CODEC

1U_0603_10V6K

0.1U_0402_16V4Z
Modify R02 +VDDA
1
Add R834 between +3VS and +3VS_Codec.

1
C693

C694

10U_0805_10V4Z

0.1U_0402_16V4Z
change power from +3VS to +3VS_CODEC. 1 1

C692

C691
2

2
2
R635 Layout Note:Path from +5VS to LPWR_5.0
0_1206_5% 2 2
RPWR_5.0 must be very low
+3VS +3VS_CODEC resistance (<0.01 ohms)

1
+3VS_CODEC
40mils 40mils

10U_0805_10V4Z

0.1U_0402_16V4Z
1 2
R834 0_0805_5% 1 1 +VDDA_R

C700

C701

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 1 1 1 1 1

C695

C696

C697

C698

C699
2 2 2 2 2

C C

21

29

31

15

18

20
4

9
U29

AVDD_HP

AVDD_5V
VDD_IO
VAUX_3.3

DVDD_3.3

LPWR5.0

RPWR5.0

CLASSDREF
37 HP_LEFT HP_LEFT 25 Please bypass caps very close to device.
PORTA_L
37 HP_RIGHT HP_RIGHT 26 PORTA_R
27 PORTD_L
14 SPKL+ L41 1 2
40mils
SPK_OUT_L+ SPKL+_L 43
28 FBMA-L11-201209-221LMA30T_0805 1 2 C796
PORTD_R SPKL- L42 1 1000P_0402_50V7K
SPK_OUT_L- 16 2 SPKL-_L 43
33 PORTE_L
FBMA-L11-201209-221LMA30T_0805
SPKR+ L43 1
1 2 C797
1000P_0402_50V7K
Internal SPEAKER
SPK_OUT_R+ 19 2 SPKR+_L 43
34 FBMA-L11-201209-221LMA30T_0805 1 2 C798
PORTE_R SPKR- L44 1 1000P_0402_50V7K
SPK_OUT_R- 17 2 SPKR-_L 43
41 FBMA-L11-201209-221LMA30T_0805 1 2 C799
PORTF_L 1000P_0402_50V7K
PORTB_L 39
42 PORTF_R
PORTB_R 40
22 FLY_P
B_BIAS 38

D34 1 2 23 8 HDA_SDIN0_AUDIO 1 R730 2 33_0402_5% HDA_SDIN0 13

C801 C702 1U_0603_10V6K FLY_N SDATA_IN
39 BEEP# 2 1
0.1U_0402_16V4Z 6 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 13
RB751V-40_SOD323-2 MIC1_L SDATA_OUT
37 MIC1_L 1 2 35 PORTC_L 1 2 22P_0402_50V8J
1 2 MONO_IN C704 4.7U_0603_6.3V6K 10 @ C800 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 13
MIC1_R SYNC
37 MIC1_R 1 2 36 PORTC_R
D35 C705 4.7U_0603_6.3V6K 11 HDA_RST_AUDIO# HDA_RST_AUDIO# 13
RESET#
1

13 HDA_SPKR 2 1 MIC1_VREFO 37 C_BIAS 1 2 22P_0402_50V8J

R731 7 @ C802 HDA_BITCLK_AUDIO_R R642 2 1 0_0402_5% HDA_BITCLK_AUDIO 13
RB751V-40_SOD323-2 10K_0402_5% BIT_CLK
1 2 22P_0402_50V8J
B @ C803 For EMI B
2

DMIC_3/4 1
MONO_IN 13 PCBEEP
DMIC_CLK0 2 1 2 DMIC_CLK 43
EC_MUTE# R732 2 1 12 90.9_0402_1% R647
39 EC_MUTE# EXT_MUTE#
0_0402_5% 3 DMIC_DATA DMIC_DATA 43
+3VS DMIC_1/2

R472 1 2 5.1K_0402_1%
HP_PLUG# R650 2 1 39.2K_0402_1% R733 FILT_1.8V FILT_1.65V
R649 2 1 10K_0402_1% SENSE_A 44 46 1 @ 2 EC_MUTE#
37 MIC_PLUG# SENSE A GPIO1/SPK_MUTE#

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS R488 1 2 5.1K_0402_1% SENSE_B 43 45 2
SENSE B GPIO2/SPDIF2

1
10K_0402_5%
0_0402_5% 1 1 C712

C709

C710

C711
39 EAPD 0_0402_5% 1 2 R651 47 GPIO0/EAPD# R652

2
FILT_1.8V @ 1
37 SPDIF_OUT 48 SPDIFO FILT_1.8 5
2 2 1U_0402_6.3V6K

2
AVEE 24 32 FILT_1.65V
AVEE FILT_1.65
EAPD active low
10U_0805_10V4Z

0.1U_0402_16V4Z

49 30 LDO_OUT_3.3V
0=power down ex AMP EP_GND AVDD_3.3
1

1
C713

C714

1=power up ex AMP CX20584-21Z_QFN48_7X7

LDO_OUT_3.3V
2

C804

10U_0805_10V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z AVDD_3.3 pin is output of
@ 1 2 internal LDO. Do NOT connect

1
C715

C716
C806 to external supply.
0.1U_0402_16V4Z

2
@ 1 2
A A
C808
0.1U_0402_16V4Z
@ 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 42 of 57
5 4 3 2 1
 A B C D E

1 1

2 2

Int. Speaker Conn.

3 3

Digital MIC CONN

JSPK1
42 SPKL+_L SPKL+_LR665 1 2 0_0603_5% SPK_L+ 1 3
SPKL-_L R667 1 1 GND
42 SPKL-_L 2 0_0603_5% SPK_L- 2 2 GND 4
+3VS
JDMIC1 ACES_85205-0200N
L36 1 2 BLM18AG121SN1D_2P +3VS_DMIC 1 1
CONN@

3
42 DMIC_CLK R666 1 2 FBMA-L10-160808-301LMT_2P DMIC_CLK_R 2
R668 1 2
42 DMIC_DATA 2 FBMA-L10-160808-301LMT_2P DMIC_DATA_R 3 3 G1 5
4 4 G2 6
For EMI D25
@ ACES_88266-04001 PJDLC05C_SOT23-3
2 1 2 @ 1 CONN@
2

C719 R671
1000P_0402_50V7K10K_0402_5%

1
D24
PJDLC05C_SOT23-3
@
JSPK2
42 SPKR+_L SPKR+_L R669 1 2 0_0603_5% SPK_R+ 1 3
SPKR-_L R670 1 SPK_R- 1 GND
42 SPKR-_L 2 0_0603_5% 2 4
1

2 GND

3
ACES_85205-0200N
CONN@

D26
PJDLC05C_SOT23-3

4 4

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 43 of 57
A B C D E
 5 4 3 2 1

+3V_USB3 +1.05VR
+1.5V to +1.05V Transfer Close to U3.D7 Close to U3.P13
+5VALW +1.5V +5VALW +1.05V_USB3

C775

C759

C773

C776

C764

C765

C766

C762

C767

C768

C769

C777

C770

C771

C772
U33
+3VA +3VA
1U_0603_10V6K

10U_0603_6.3V6M
+1.5V
C757

C758
6 VCNTL
1

1 5 VIN VOUT 3

1
9 VIN VOUT 4
+5VALW

0.1U_0402_16V7K
C774

0.01U_0402_16V7K
C760

8P_0402_50V8D

0.1U_0402_16V7K
C779

0.01U_0402_16V7K
C761

8P_0402_50V8D
@ @
2

1
C778

C763
SYSON 8 R705

2
EN

10U_0603_6.3V6M
2 1 7 2 1 2

GND
POK FB

C782

0.1U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
R704 5.1K_0402_1% 10K_0402_1%

2
1

1
Vout=0.8(1+10K/32.4K) APL5930KAI-TRG_SO8 R706

1
D 32.4K_0402_1% D
1.042 ~ 1.0469 ~ 1.0519V

2
Spec: 0.9975 ~ 1.05 ~ 1.1025

2
7K for customer request, can use other kind
R707 of capacitor, like Y5V.
0_0805_5%
+3VALW to +3V Transfer +3V_USB3
+1.05V_USB3 1 2 +1.05VR +3VA
+3V_USB3 +3VA
L40
+3VALW U34 +3V_USB3 BLM18AG601SN1D_2P
U35 1 2
3 1 <BOM Structure>

D10

H11
E11
E12

K11
K12

P13
F13
F14
VIN VOUT

L10

L13
L14

1
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
SYSON C783

P3

E3
E4
F3

L9

L5

L8
39,46,51 SYSON 4 VIN/CE VOUT 5
10U_0805_6.3V6M
2

U3AVDO33
VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U2AVDD10

2
GND
RT9701-PB_SOT23-5

14 CLK_PCIE_USB30 B2 PECLKP
14 CLK_PCIE_USB30# B1 PECLKN
U3TXDP2 B6
C787 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P4 D2
14 PCIE_PRX_DTX_P4 C784 1 0.1U_0402_16V7K PCIE_PRX_C_DTX_N4 D1 PETXP
2 PETXN U3TXDN2 A6
14 PCIE_PRX_DTX_N4
U2DM2 N8
14 PCIE_PTX_C_DRX_P4 F2 PERXP
14 PCIE_PTX_C_DRX_N4 F1 PERXN U2DP2 P8
U3RXDP2 B8

U3RXDN2 A8
+3V_USB3
C R708 1 C
5,17,35,38,39 PLT_RST# 2 0_0402_5% H2 PERSTB
R710 1 2 0_0402_5% K1 G14 OCI2B R711 1 2 10K_0402_5%
15,35,37 PCH_PCIE_WAKE# PEWAKEB OCI2B
CLKREQ_USB3 K2 Can be attach to EC, either. H13 OCI1B R712 1 2 10K_0402_5%
R713 1 PECREQB OCI1B
+3V_USB3 2 10K_0402_1%
R709 1 @ 2 100_0402_1% J2 AUXDET OCI1B 45
+3V_USB3 R714 1 2 10K_0402_5% J1 H14
SMI R797 1 PSEL PPON2
2 0_0402_5% SMI_R H1 SMI PCI Express/ExpressCard select signal PPON1 J14
SMI# R798 1 @ 2 0_0402_5% SMIB_R P4 SMIB 1:others C786
+3V_USB3 R715 1 2 10K_0402_5% P5 PONRSTB
0:Express Card or Mini card 0.1U_0402_16V7K
B10 U3TX_C_DP1 1 2 U3TXDP1_L
U3TXDP1 U3TXDP1_L 45
1 2
D32 1 2 SPI_CLK_USB M2 A10 U3TX_C_DN1 1 2 U3TXDN1_L
SPISCK U3TXDN1 U3TXDN1_L 45
1U_0603_10V6K

1SS355_SOD323-2 SPI_CS_USB# N2 N10 U2DN1_L C785 0.1U_0402_16V7K

+3V_USB3 SPISCB U2DM1 U2DN1_L 45
C788

USB_SO_SPI_SI N1 SPISI
1

USB_SI_SPI_SO M1 P10 U2DP1_L

SPISO U2DP1 U2DP1_L 45
B12 U3RXDP1_L
U3RXDP1 U3RXDP1_L 45
2

+3VS R717 A12 U3RXDN1_L

U3RXDN1 U3RXDN1_L 45
10K_0402_5%
Q63 K13 GND
2
G

2N7002E_SOT23-3 K14
1

GND
J13 GND
3 1 CLKREQ_USB3 As short as possible P12
14 USB30_CLKREQ# RREF
S

GND N12
C14 GND

1.6K_0402_1%
GND N11

R718
GND D6
USB3_XT1 N14
USB3_XT2 XT1
M14

1
XT2
B +3V_USB3 B
+3V_USB3 +3V_USB3
P6 CSEL
2

2
2

1
10K_0402_5%
R721

C790
0.1U_0402_16V7K R719 R720 P14
GND SMIB 18
10K_0402_5% 47K_0402_5% @ A1 P11
2

GND GND
2

3
A2 P9
1

GND GND
0_0402_5%
R723

0_0402_5%
R725

U38 A3 P7 Q69B
1

SPI_CS_USB# GND GND

8 VCC CS# 1 A4 GND GND P2 DMN66D0LDW-7_SOT363-6
7 2 USB_SI_SPI_SO A5 P1 SMI 5
SPI_CLK_USB NC SO GND GND
6 3 A7 N13
1

USB_SO_SPI_SI 5 SCLK WP# GND GND

4 A9 N9

4
SI GND GND GND
A11 GND GND N7
MX25L5121EMC-20G_SO8 A13 N3
GND GND
A14 GND GND M13
USB3_XT1 B3 M12
USB3_XT2 +3V_USB3 GND GND
B4 GND GND M11
B5 M10 R734 +3V_USB3
GND GND
1

B7 M9 10K_0402_5%
R727 GND GND @
B9 GND GND M8 1 2
100_0402_5% B11 M7
GND GND

2
B13 GND GND M6
B14 M5
2

Y5 GND GND SMI#

Place as close as C1 GND GND M4 1 6
1 2 possibile to C2 GND GND M3
C3 GND GND L12 Q69A
24MHZ_12PF_X5H024000DC1H U3.N14 and U3.M14 C10 GND GND L11
C11 L7 DMN66D0LDW-7_SOT363-6
GND GND
1

C792 C793 L6
12P_0402_50V8J 12P_0402_50V8J GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2

A A
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

Pin compare table for support USB remote wakeup or not UPD720200AF1-DAP-A_FBGA176
<BOM Structure>

AUXDET(Pin J2) CSEL(Pin P6) CLK

Security Classification Compal Secret Data Compal Electronics, Inc.
P/N: SA000048H10
Support USB pull high Tied to GND Must use 24MHz crystal: mount (S IC UPD720200AF1-DAP-A FBGA Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
remote
wakeup
10k to VDD33 Y1,R19,C40,C41
176P USB3.0 ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Not support USB pull high Can use either 48MHz or 24MHz When Custom B
remote wakeup Tied to GND to VDD33 use 48MHz clock: mount R22,R25
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 44 of 57
5 4 3 2 1
 +USB3_VCCA
SW_U2DP1_L R736 1 @ 2 0_0402_5% U2DP1
SW_U2DN1_L R737 1 @ 2 0_0402_5% U2DN1

USB Host Charger

150U_B2_6.3VM_R35M

10U_0805_6.3V6M
1
L39

C781
SW_U2DP1_L 3 4 U2DP1 +
3 4

C780
R726
10K_0402_5% U36

1
39 USB_CHARGE_CB 1 2 8 1 SW_U2DN1_L 2 1 U2DN1
U2DN1_L CB CEN SW_U2DN1_L 2 1
44 U2DN1_L 7 TDM DM 2
U2DP1_L 6 3 SW_U2DP1_L Oper Drain, Low Active, need PU WCM2012F2S-900T04_0805
44 U2DP1_L TDP DP
5 VCC GND 4
+USB3_VCCA R716 1 2 0_0402_5% 9
GND D31 Modify R02

1
R735 1 @ 2 0_0402_5% C789 MAX14566EETA+_TDFN-EP8_2X2 U2DP1 U2DN1
VL 6 I/O4 I/O1 1

USB3.0 Connector
0.1U_0402_16V4Z
+USB3_VCCA 5 2

2
REF2 REF1 +USB3_VCCA
4 I/O3 I/O2 3

PJUSB208H_SOT23-6
CB=0 Auto detection charger identification active JUSB2
CB=1 Connect DP/DM to TDP/TDM U2DN1
1 VBUS
2 D-
U2DP1 3 For customer request
D+
4 GND
U3RXDN1 5 GND_Frame 1 2
U3RXDP1 SSRX- R728 0_0603_5%
6 SSRX+ GND 10
7 GND GND 11 1 2
L37 U3TXDN1 8 12 R729 0_0603_5%
U3TXDP1_L 2 U3TXDP1 U3TXDP1 SSTX- GND
44 U3TXDP1_L 1 9 SSTX+ GND 13 1 2
C794
OCTEK_USB-09EAEB 0.1U_0402_16V7K
U3TXDN1_L 3 4 U3TXDN1 CONN@
+USB3_VCCA 44 U3TXDN1_L
+5VALW OCE2012120YZF_4P

C791 U37 W=60mils L38

0.1U_0402_16V7K 1 8 U3RXDP1_L 2 1 U3RXDP1
GND VOUT 44 U3RXDP1_L
1 2 2 7 R724
VIN VOUT 10K_0402_5%
3 VIN VOUT 6
EPAD
39 USB_CHARGE_2A# R722 1 2 4 EN FLG 5 1 2 OCI1B OCI1B 44 44 U3RXDN1_L
U3RXDN1_L 3 4 U3RXDN1
10K_0402_5%
OCE2012120YZF_4P
AP2301MPG-13_MSOP8
9

D30
U3RXDN1 1 1 109 U3RXDN1

U3RXDP1 2 2 98 U3RXDP1
+USB3_VCCA
U3TXDN1 4 4 77 U3TXDN1
C204 VL
1U_0603_10V6K U40 U3TXDP1 5 5 66 U3TXDP1
@ 1
VOUT
2 1 5 VIN 3 3
GND 2
8
39 USB_CHARGE_100MA R754 1 @ 2 4 3
10K_0402_5% ON OC YSCLAMP0524P_SLP2510P8-10-9
TPS22945DCKR_SC70-5 @
@

FAN1 Conn H1 H2 H3 H4 H10 H11 H24 H25 H13 H12

H_2P5 H_3P0 H_3P0 H_3P0 H_2P5 H_3P0 H_2P5 H_3P0 H_3P0 H_3P0 H18 H19
H_3P9 H_4P0
+5VS
1 @ @ @ @ @ @ @ @ @ @

1
1

D27 @ @

1
1SS355_SOD323-2
+5VS @
D28
2 1 +VCC_FAN1 BAS16_SOT23-3
2

R672 0_0603_5% @ H14 H15 H16 H17 H5

1 2 H_4P2 H_4P2 H_4P2 H_4P2 H_3P2 H21 H22
2

H_3P5x4p5N H_3P5N
C721
10U_0805_10V4Z C723 @ @ @ @ @
1

1
10U_0805_10V4Z @ @

1
1 2

C724
+3VS 1000P_0402_50V7K
1 2
FD1 FD2 FD3 FD4
1

R673 JFAN1
10K_0402_5% 6 @ @ @ @
1

1
GND2
40mil 5 GND1 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2

+VCC_FAN1 4 4
39 FAN_SPEED1 3 3
2 2
39 FAN_PWM 1 1
1

C725
1000P_0402_50V7K ACES_88231-04001
CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 45 of 57
 A B C D E

+5VALW

+5VALW TO +5VS +3VALW TO +3VALW(PCH AUX Power)

Short J5 for PCH VCCSUS3.3

2
+5VALW Q41 R675
SI4178DY-T1-GE3_SO8 +5VS +3VALW J1 @ 100K_0402_5%
1 2 +3VALW_PCH
1 2
8 1

1
7 2 JUMP_43X79 SYSON#
37 SYSON#

2
6 3 Q42 40mil

6
10U_0805_10V4Z
C730

1U_0603_10V6K
C731
5 R676 SI4178DY-T1-GE3_SO8
1

1
10U_0805_10V4Z
C728

10U_0805_10V4Z
C729
470_0603_5%
8 1 Q45A

2
1 SYSON DMN66D0LDW-7_SOT363-6 1
7 2 39,44,51 SYSON 2
2

2
6 3

1
10U_0805_10V4Z
C733

1U_0603_10V6K
C734
5

1
3

1
C732 R677 R678
470_0603_5% 100K_0402_5%

2
10mil 10U_0805_10V4Z

6 1
+VSB 2 1 5VS_GATE 5 SUSP

2
R679
20mil 100K_0402_5% Q43B

4
6

1
C735 DMN66D0LDW-7_SOT363-6 20mil 10mil
0.1U_0603_25V7K 2 PCH_PWR_EN# +5VALW
Q43A +VSB R680 2 1 200K_0402_5% 3V_GATE

2
SUSP 2 DMN66D0LDW-7_SOT363-6 Q44A

1
3

2
DMN66D0LDW-7_SOT363-6

1
R681
1

C736 100K_0402_5%
PCH_PWR_EN# 5 0.1U_0603_25V7K

1
Q44B SUSP
5,53 SUSP

4
DMN66D0LDW-7_SOT363-6

3
+3VALW Q46 +3VS Q45B
SI4178DY-T1-GE3_SO8 +1.05VS_VCCP to +1.05VSDGPU for GPU 37,39,52,53 SUSP# 5 DMN66D0LDW-7_SOT363-6

1
8 1

4
7 2 +1.05VS_VCCP R682

2
+1.05VSDGPU
10U_0805_10V4Z
C737

10U_0805_10V4Z
C738

6 3 10K_0402_5%
1

1
10U_0805_10V4Z
C739

1U_0603_10V6K
C740
5 R683 Q47
470_0603_5% AO4430L_SO8 4A

2
8 1
2

2
2 2
7 2

6 1

2
6 3 OPT@

1
C741 5 OPT@ R684 +5VALW

10U_0805_10V4Z
C742

1U_0603_10V6K
C743
R685 10mil 10U_0805_10V4Z 470_0603_5%

2
200K_0402_5% OPT@ OPT@ OPT@

2
+VSB 2 1 3VS_GATE 2 SUSP

6 1
R686
20mil Q48A 100K_0402_5%
1
3

C744 DMN66D0LDW-7_SOT363-6
0.1U_0603_25V7K 20mil R687 10mil

1
510K_0402_5% 2 VGA_ON#
2

SUSP 5 +VSB 2 OPT@ 1 1.05VSDGPU_GATE PCH_PWR_EN#

20,35 PCH_PWR_EN#
Q49A

1
Q48B @ DMN66D0LDW-7_SOT363-6
4

1
D

510K_0402_5%
DMN66D0LDW-7_SOT363-6 C745 OPT@ Q50

R688
0.1U_0603_25V7K 39 PCH_PWR_EN 2 2N7002E_SOT23-3
OPT@ G

1
VGA_ON# 5 S

3
Q49B

2
DMN66D0LDW-7_SOT363-6 R689
+1.5V to +1.5VS

4
OPT@ 100K_0402_5%

1
D Q51

2
+1.5V +1.5VS ACIN 2 2N7002E_SOT23-3
Q52 G @
AO4430L_SO8 S

3
8 1
7 2
1

2
10U_0805_10V4Z
C748

10U_0805_10V4Z
C749

0.1U_0402_16V4Z
C750

0.1U_0402_16V4Z
C751

10U_0805_10V4Z
C746

1U_0603_10V6K
C747

6 3
5 R690
1

470_0603_5%
2

+1.5V to +1.5VSDGPU for GPU

4
2

3 3
+1.5V +1.5VSDGPU
6

U32
AO4430L_SO8
10mil Q53A 8 1
+VSB 2 1 1.5VS_GATE DMN66D0LDW-7_SOT363-6 2 SUSP 7 2 OPT@

2
R692 6 3 OPT@

10U_0805_10V4Z
C754

1U_0603_10V6K
C752
20mil 750K_0402_5% 5 R693
1
1

@ C753 470_0603_5%

2
3

510K_0402_5%
R694

0.1U_0603_25V7K C755 OPT@ OPT@

4

10U_0805_10V4Z
2

1
OPT@
SUSP 5
2

6
Q53B 20mil 10mil
4

DMN66D0LDW-7_SOT363-6 +5VALW
+VSB 2 1 1.5VSDGPU_GATE 2 VGA_ON#
1

D Q56 R696 Q55A

2
15,39,48 ACIN ACIN 2 2N7002E_SOT23-3 510K_0402_5% DMN66D0LDW-7_SOT363-6

1
3

1
510K_0402_5%

G @ OPT@ C756 OPT@ R698

R697

S 0.1U_0603_25V7K 100K_0402_5%
3

@ OPT@ OPT@
2

VGA_ON# 5

1
VGA_ON#
2

+0.75VS Q55B
4

+1.05VS_VCCP +1.8VS +1.5V DMN66D0LDW-7_SOT363-6

1

OPT@ D Q57
1

1
ACIN 2N7002E_SOT23-3 D Q58
2
2

R699 G @ 2 2N7002E_SOT23-3
14,17,25,55 VGA_ON
22_0603_5% R700 R701 R702 S G OPT@
3

1
470_0603_5% 470_0603_5% 470_0603_5% S

3
@ R703
2

4 100K_0402_5% 4
1 1

1 1

1 1

OPT@
1

D D D D

2
2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G
S Q59 S Q60 S Q61 S Q62
3

2N7002E_SOT23-3 2N7002E_SOT23-3 2N7002E_SOT23-3 2N7002E_SOT23-3

@
Security Classification Compal Secret Data Compal Electronics, Inc.
2009/08/14 Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
CP_S3PowerReduction
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
WhitePaper_Rev0.9 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
0.75VS speed up discharge DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 46 of 57
A B C D E
 5 4 3 2 1

ACES_50305-00441-001 PL1
SMB3025500YA_2P
VIN @ PJ1 @ PJ2
1 1 1 2 +3VALWP 2 2 1 1 +3VALW +0.75VSP 2 2 1 1 +0.75VS
2 2
3 JUMP_43X118 JUMP_43X118
3

1
4 4
5 @ PC120 @ PC169
GND

1
6 PC3 1000P_0402_50V7K 1000P_0402_50V7K

2
GND PC1 PC2 100P_0402_50V8J PC4
PJP1 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K

2
@ PJ3 @ PJ4
+5VALWP 2 1 +5VALW +VCCSAP 2 1 +VCCSA
D 2 1 2 1 D
PJ25 JUMP_43X118 JUMP_43X118

1
@JUMP_43X39
1 1 @ PC168
2 2 1000P_0402_50V7K

2
2

PD9 @ VIN
PJSOT24CH_SOT23-3 @ PJ5 @ PJ6 +VGA_CORE
+1.8VSP 2 1 +1.8VS +VGA_COREP 2 1
2 1 2 1

2
@ PD1 JUMP_43X118 JUMP_43X118
1

1
LL4148_LL34-2 @ PJ7
@ PC128 @ PC167 2 2
PD2 @ PJ26 1000P_0402_50V7K 1000P_0402_50V7K 1 1

2
LL4148_LL34-2 JUMP_43X39 @ PJ8 JUMP_43X118
BATT+ 2 1 1 1 2 2 2 2 1 1

1
JUMP_43X118

1
@ PR2 @ PJ10
@ PR1 68_1206_5% @ PJ9 +1.5V JUMP_43X39
PQ1 68_1206_5% VS +1.5VP 2 1 1
TP0610K-T1-E3_SOT23-3 2 1 +VSBP 1 2 2 +VSB

2
JUMP_43X118
0.22U_0603_25V7K

1
N1 3 1
@PC144
@ PC144 @ PC166
1000P_0402_50V7K 1000P_0402_50V7K

2
1

PR3 1 @ PJ11
PC5

C 100K_0402_5% @ PC6 C
2 2 1 1
0.1U_0603_25V7K @ PJ12
2

PR4 JUMP_43X118 2 1
2

22K_0402_5% +1.05VS_VCCPP @ PJ13 +1.05VS_VCCP 2 1

+GFX_COREP +VGFX_CORE
1 2 2 2 JUMP_43X118
40 51ON# 1 1 @ PJ14
JUMP_43X118 2 2 1 1

1
@PC156
@ PC156 @ PC165 JUMP_43X118
1000P_0402_50V7K 1000P_0402_50V7K

2
PR5
0_0402_5%
+CHGRTC 1 2 +3VLP PQ2
VIN PR6 LL4148_LL34-2 Pre_chg TP0610K-T1-E3_SOT23-3
1K_1206_5% PD3 B+
1 2 2 1 3 1

100K_0402_5%

100K_0402_5%
PR7

1
1K_1206_5%
PR8

PR9
1

1 2
- PBJ1 @ + PR11
560_0603_5%
PR12
560_0603_5% PR10
2 1 1 2 1 2 +RTCBATT 1K_1206_5%
2

2
1 2
2

B PR13 B

1
ML1220T13RE 1K_1206_5%
1 2 PR14
12 100K_0402_5%
1

0_0402_5% PQ4
PR15 PD20 PDTC115EU_SOT323-3
39 ACOFF 2 1 2
1 2 2
+5VALW 3

BAS40CW_SOT323-3
PQ3
3

PDTC115EU_SOT323-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 47 of 57
5 4 3 2 1
 A B C D

for reverse input protection

1
D
2 PQ5
G SI1304BDL-T1-E3_SC70-3
S

3
1 2 1 2
PJ16 @
1 PR16 PR17 1 2 1

1M_0402_5% 3M_0402_5% 1 2
JUMP_43X118

VIN P1 P2 PR18 B+
PQ6 PQ7 PL16 0.02_2512_1% PQ8
AO4466L_SO8 AO4466L_SO8 1UH_FDV0630-1R0M-P3_10.3A_20% AO4466L_SO8
8 1 1 8 1 2 1 4 8 1

2200P_0402_50V7K
7 2 2 7 7 2

10U_0805_25V6K

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
6 3 3 6 2 3 6 3

0.1U_0402_25V6
2200P_0402_50V7K

5 5 5

0.01U_0402_50V7K
PC119
1

1
0_0402_5%

PC51

PC10

PC11

PC12

PC13
PC109

PC173
PR19

1
VIN

0_0402_5%
PC7

PR20
4

4
PC9

PC14
2

1
@ 2 0.1U_0402_25V6 @ @ @
1
PC8

1 2 @
2

2
0.1U_0402_25V6
PD5
2

BAS40CW_SOT323-3

1
BQ24725_BATDRV 1 2

PC15
0.047U_0402_25V7K PR21

1
4.12K_0603_1%

4.12K_0603_1%
4.12K_0603_1%
PC16
1

1 2
PR22

PR23

5
10_1206_1%

10_0603_5%
1
VIN

PR24
0.1U_0603_25V7K

PR25
2

2
1

PR70 PQ9

BQ24725_ACN
2 2

1
@ PR26 1_0603_5% SIS412DN-T1-GE3_POWERPAK8-5

PC17

BQ24725_ACP

BQ24725_BST 2
3.3_1210_5% DH_CHG 1 2 DH_CHG-1
4

2
PC18 PD6

BQ24725_LX
2
1 2 RB751V-40_SOD323-2 BATT+
1 2

DH_CHG
1U_0603_25V6K PC19 PL2 PR28

3
2
1
1 2 10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1%
@ PR27 BQ24725_LX 1 2 CHG 1 4
3.3_1210_5% 1U_0603_25V6K

5
20

19

18

17

16

SIS412DN-T1-GE3_POWERPAK8-5
2 3
2

CSOP1
4.7_1206_5%
PU1

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
1
PHASE

HIDRV

BTST
VCC

REGN

PR29

10U_0805_25V6K

10U_0805_25V6K
1

21

0.1U_0402_25V6

0.1U_0402_25V6
PAD

1
@ PC20

PC24

PC26
PC21

PC22
1

1
SX34 SMA
PQ10

PD10
2.2U_0805_25V6K 1 15 DL_CHG 4 @
2

ACN LODRV

PC23

PC25
2

2
2 14 @

680P_0402_50V7K

2
ACP GND PR66

3
2
1

2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_5%

PC27
BQ24725_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP

2
0.1U_0603_16V7K
BQ24725_ACDRV 4 12 SRN 1 2 CSON1 @

2
ACDRV SRN

PC28
PR67
6.8_0603_5%
+3VALW 1 2 5 11 BQ24725_BATDRV
PR30 ACOK ACDET BATDRV
10K_0402_1%
IOUT
3 3

SDA

SCL

ILIM
Pre_chg +3VALW
6

10
1 2
15,39,46 ACIN PR31
1

10K_0402_1% 1 2

0.01U_0402_25V7K
PD7 PR32

100K_0402_1%
RB751V-40_SOD323-2 316K_0402_1%

1
VIN PR33

PC29
PR34

1
255K_0402_1%
2

1 2

2
154K_0402_1%

2
1

PR35

Vin Dectector
Min. Typ Max.
2

H-->L 17.23V
0.1U_0402_25V6

66.5K_0402_1%

L--> H 17.63V EC_SMB_CK1 39,50

1

PC30

PR36

ILIM and external DPM

2

EC_SMB_DA1 39,50
PR72
3.97A 0_0402_5%
2

4 2 1 1 2 ADP_I 39,50
4

to EC
1

PC31 @ PC177
100P_0402_50V8J 0.1U_0402_25V6
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 48 of 57
A B C D
 5 4 3 2 1

2VREF_8205

1U_0603_10V6K
D D

1
PC32

2
PR37 PR38
13K_0402_1% 30K_0402_1%
1 2 1 2

PR39 PR40
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PL3
HCB4532KF-800T90_1812
B+ 1 2 Typ: 175mA +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0603_25V7K
PR41 PR42
110K_0402_1% 154K_0402_1%
PC33

PC40
4.7U_0805_10V6K
1 2 1 2
1

1
PC34

PC35

PC36

PC37

PC38

PC39
5

5
PU2
2

2
PC41

ENTRIP2

REF
FB2

FB1

ENTRIP1
TONSEL
1
C C
25 P PAD

2
4 4
7 24
VO2 VO1 SPOK 50
PQ11 8 23 PR44 PC43 PQ12
SIS412DN-T1-GE3_POWERPAK8-5 PR43 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3_POWERPAK8-5
1
2
3

3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL4 PC42 UG_3V 10
VFB=2.0V 21 UG_5V PL5
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
+3VALWP 1 2 LX_3V 11 PHASE2 PHASE1 20 LX_5V 1 2 +5VALWP
1

1
4.7_1206_5%

4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1

5
PR45

PR46
PQ13

SKIPSEL
SI7716ADN-T1-GE3_POWERPAK8-5 @ PR47

VREG5
40 3V5V EN 0_0402_5%

GND

VIN
RT8205EGQW_WQFN24_4X4

NC
EN
1 2 1 1
2

2
4
PC44 + 4 +

13

14

15

16

17

18
1

1
680P_0402_50V7K

680P_0402_50V7K
330U_D2E_6.3VM_R25M PR48 PC46
PD8
PC45

PC47
499K_0402_1% PQ14 150U_D2E_6.3VM_R18
2 2
1 2 1 2
2

1
2
3

2
SI7716ADN-T1-GE3_POWERPAK8-5
B+

3
2
1
RLZ5.1B_LL34
1
150K_0402_1%

1U_0603_10V6K
VL

1
PC48

1
PR49

PC49
4.7U_0805_10V6K
B Typ: 175mA B

2
2

2
ENTRIP1 ENTRIP2 RT8205_B+

1
6

D D

0.1U_0603_25V7K
PQ15A 2 5
DMN66D0LDW-7_SOT363-6 G G PQ15B 2VREF_8205

2
PC50
DMN66D0LDW-7_SOT363-6
S S TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
1

(2)SMPS2=375KHZ(+3VALWP)

PR51
100K_0402_1%
VL 2 1
40,50 MAINPWON PR50 +3.3VALWP +5VALWP
0_0402_5%
2 1 Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=375KHz, L=4.7UH f=300KHz, L=4.7UH,Rentrip=154k ohm
1

PQ16 Rdson=15~18m ohm Rdson=15~18m ohm

PD4 PR53 PDTC115EU_SOT323-3 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
LL4148_LL34-2 1M_0402_1%
2 1 1 2 2
Vlimit=10*10^-6*110Kohm/10=0.11V Vlimit=10*10^-6*154Kohm/10=0.15V
VIN Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
4.7U_0603_6.3V6K
402K_0402_1%

A Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT- Iocp=8.44~11.57A (8.44>8.4 -> OK) A

1

PC114

PR52
PR54

316K_0402_1%
3

2 1
VS
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 49 of 57
5 4 3 2 1
 5 4 3 2 1

D ACES_50299-01001-001 D

10 10
9 9
8 8 EC_SMDA
7 7 EC_SMCA
6 6 TH
5 5 BI+
4 4

2
3 3 PR55
2 2 100_0402_1%
PH1 under CPU botten side :
1 1

2
PJP2 PR56
CPU thermal protection at 92 degree C

1
100_0402_1%
<40,41> EC_SMB_DA1 39,48
+3VLP
Recovery at 56 degree C
VMB

1
1
PL6
<40,41> EC_SMB_CK1 39,48 ADP_I 39,48
SMB3025500YA_2P +3VLP
1 2 BATT+ PR57 +3VLP 65W@ PR74

1
1K_0402_5% 5.62K_0402_1%

2
PR60 PC52 PR59
1

6.49K_0402_1% 0.1U_0603_25V7K 21K_0402_1%

2
1

1
PC53 PC54 2 1 +3VALW

1
1000P_0402_50V7K 0.01U_0402_25V7K
2

2
PR76 PU3
100K_0402_1% @ PR61 1 8 90W@ PR74
VCC TMSNS1

1
100K_0402_1% 8.87K_0402_1%

2
PR62 2 7 2 PR63 1

2
GND RHYST1
1K_0402_1% 5,39 H_PROCHOT# 9.53K_0402_1%
MAINPWON 3 6
~OT1 TMSNS2

1
C D C

2
PQ22 2 4 5 1 2
2N7002W-T/R7_SOT323-3 G ~OT2 RHYST2
S G718TM1U_SOT23-8 90W@ PR77

3
16.2K_0402_1%
BATT_TEMP 39

1
BI 40 65W@ PR77

1
28.7K_0402_1%
PR78
For 65W adapter==>action 70W , Recovery 54W
10K_0402_1%
PH1

2
100K_0402_1%_NCP15WF104F03RC

2
PQ19 For 90W adapter==>action 97W , Recovery 75W
TP0610K-T1-E3_SOT23-3

3 1
0.22U_0603_25V7K

B+ +VSBP
100K_0402_1%
1
PR65

PC55
1

PC56
0.1U_0603_25V7K
2

2
2

PR68
VL 22K_0402_1%
1 2
2

+3VLP
PR69
100K_0402_1%
B B
PR71
1

1K_0402_5% D
1 2 2 PQ20
49 SPOK
1U_0402_6.3V6K

1
G 2N7002W-T/R7_SOT323-3
S @ PC57
PC58

3
1

1
0.1U_0603_25V7K

2
+3VLP @ PR73 @ PR58
2

10K_0402_1% 10K_0402_1%

2
2
@ PU4
@ PR79 1 8
100K_0402_1% VCC TMSNS1
2 GND RHYST1 7 2 1

1
MAINPWON 3 6 @ PR64
OT1 TMSNS2
40,49 MAINPWON 47K_0402_1%
4 5 @ PH2
OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
G718TM1U_SOT23-8

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 50 of 57
5 4 3 2 1
 A B C D

PL17
FBMA-L11-322513-151LMA50T_1210
1.5_8209_B+ 1 2
B+

5
6
7
8

2200P_0402_50V7K

0.1U_0402_25V6
0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0402_25V6
PQ23

1
PC59

PC60

PC61

PC62

PC81

PC121
AO4406AL_SO8
PR81
267K_0402_1% 4

2
PR82 1 2 @ @
0_0402_5%
1 2
39,44,46 SYSON

3
2
1
1 1

2
PR83 PC63 PL7
2.2_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%

15

14
+1.5VP

1
@PR84
@ PR84 PU5 BST_1.5V 2 1BST_1.5V-1 1 2 1 2
47K_0402_5% @PC64
@ PC64

EN_PSV

TP

VBST
.1U_0402_16V7K

2
2 13 DH_1.5V
TON DRVH

1
3 12 LX_1.5V 1
VOUT LL

5
6
7
8
PR85
4 V5FILT VFB=0.75V TRIP 11 +5VALW PQ24
AO4456_SO8
4.7_1206_5% + PC65
330U_D2E_2.5VM
5 10

2
VFB V5DRV 2
6 9 DL_1.5V 4
PGOOD DRVL

PGND
PR86

GND

1
15K_0402_1%
100_0603_5% PC67

1
PR87
1 2 680P_0402_50V7K
+5VALW RT8209MGQW_WQFN14_3P5X3P5 PC66

3
2
1

2
4.7U_0805_10V6K

2
1

2
PC68
4.7U_0603_6.3V6K

2
<Vo=1.5V> VFB=0.75V PR88
10K_0402_1%
V=0.75*(1+10K/10K)=1.5V 1 2
Fsw=298KHz

1
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
2 Ipeak=19.53A, Imax=23.44A, Iocp=13.67A PR89 2

Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.63A 10K_0402_1%

=>1/2Delta I=2.315A
choose Rcs=15K 2
Iocpmax=((15K*11uA)/0.0045)+2.315A=35.65A
Iocpmin=((15K*9uA)/(0.0056*1.3))+2.315A=23.06A
Iocp=23.06A~35.65A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
SCHEMATIC, MB LA-7231P

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BL B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 04, 2011 Sheet 51 of 57
A B C D
 5 4 3 2 1

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V

PU6 PL8

4
@ PJ17 SY8033BDBC_DFN10_3X3 2.2UH 20% FDSD0630-H-2R2M=P3 8.3A
LX_1.8V
+5VALW 2 1 10 PVIN 2 1 2
+1.8VSP

PG
2 1 LX

68P_0402_50V8J
JUMP_43X118 9 3
PVIN LX

1
4.7_1206_5%
1

1
PC70
PC69 8 SVIN

PR90
22U_0805_6.3VAM PR91
6 FB_1.8V 20K_0402_1%

2
D
EN_1.8V FB FB=0.6Volt D

22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

1
NC

NC
TP

PC71

PC72
11

2
1 2
37,39,46,53 SUSP#

1
1

680P_0603_50V7K
PR92

0.1U_0402_10V7K
2

PC73

PC74
510K_0402_5% PR93

1
@ PR94 10K_0402_1%

2
1M_0402_5%

2
2
1

C C

+3VS

2
PR103
10K_0402_5%

1 PR105
0_0402_5%
2 1 SA_PGOOD 39

PL19 PU7 PL9

4

FBMA-L11-322513-151LMA50T_1210 SY8033BDBC_DFN10_3X3 2.2UH 20% FDSD0630-H-2R2M=P3 8.3A

LX_VCCSAP
+5VALW 1 2 10 PVIN 2 1 2
PG

LX +VCCSAP

2
68P_0402_50V8J

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
9 PVIN LX 3

1
4.7_1206_5%
PR101
1

1
PC75

PC78

PC82

PC83

PC84
PC76 8 0_0402_5%
SVIN

PR97
22U_0805_6.3VAM

2
6 FB_VCCSAP
2

1
EN_VCCSAP FB PR100 @ @
5

2
EN FB=0.6Volt
NC

NC

3.4K_0402_1%
TP

2 1 PR102
0_0402_5%
11

1 2 1 2 VSSSA_SENSE 9
53 VCCPPWRGOOD
1

PR99
0.1U_0402_10V7K
2

PC79

100K_0402_5% PC77 1 2 VCCSA_SENSE 9

1

B B
PR104 @ PC80 680P_0603_50V7K
2

1M_0402_5% 0.1U_0402_10V7K PR107

10_0402_5%
2

2
1

+3VS

1
PR108
1

20K_0402_1% PR109
10K_0402_5%

2
PR95
10K_0402_1% PR111

2
1
D 10K_0402_5%
2

2 2 1
G

1
S PQ28
3

1
PQ27 PMBT2222A_SOT23-3

1
2N7002W-T/R7_SOT323-3 @ PC85 @ PR112
4700P_0402_25V7K 100K_0402_5% 2 2 1

1
VCCSA_VID1 9

2
PR113 @ PR114

3
100K_0402_5% 10K_0402_5%

2
VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required
0 0 0.9 V Yes/Yes
0 1 0.8 V Yes/Yes
1 1 0.75V No/Yes
1 1 0.65V No/Yes
A A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
SCHEMATIC, MB LA-7231P

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 52 of 57
5 4 3 2 1
 5 4 3 2 1

PU8

+1.5V 1 VIN VCNTL 6 +3VALW

2 GND NC 5

1
PC87

1
PC86 3 7 1U_0603_10V6K
4.7U_0805_6.3V6K PR115 VREF NC

2
1K_0402_1% 4 8
VOUT NC
D 9 D

2
TP
G2992F1U_SO8

.1U_0402_16V7K
PR116
+0.75VSP

1
100K_0402_1% D PQ30
5,46 SUSP

PC88
1 2 2 2N7002W-T/R7_SOT323-3

1
G D PR117 PC90

2
1
S 2 SUSP 1K_0402_1% 10U_0603_6.3V6M

3
PC89 G

2
1U_0402_6.3V6K PQ29 S

3
2N7002W-T/R7_SOT323-3

@ PJ19
1.05VS_51117_B+ 2 1 B+
2 1

2200P_0402_50V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118

5
6
7
8
C C

1
PC91

PC92

PC93

PC94
PR118 PQ31
267K_0402_1% AO4406AL_SO8
1 2

2
PR119
680K_0402_5% 4
1 2
37,39,46,52 SUSP#
1

@ PR120 PR121 PC96

15

14
1

1
PQ45 47K_0402_5% PU9 0_0603_5% 0.1U_0603_25V7K PL10

3
2
1
2N7002W-T/R7_SOT323-3 PC95 BST_1.05VS_VCCP 1 2 1 2 1UH_FDUE1040D-1R0M-P3_21.3A_20%

EN_PSV

TP

VBST
+1.05VS_VCCPP
1

D 0.1U_0603_25V7K 2 1
2

SUSP 2 2 13 DH_1.05VS_VCCP
G TON DRVH

1
S 3 12 LX_1.05VS_VCCP
3

VOUT LL

5
6
7
8
+5VALW PQ32
@ PR122
4.7_1206_5%
4 V5FILT TRIP 11 1
AO4456_SO8
5 VFB=0.75V V5DRV 10 + PC97

1 2
VFB

2
330U_2.5V_M
PR124 6 9 DL_1.05VS_VCCP 4
PGOOD DRVL

PGND
100_0603_5% @ PC98 PR123 2 PR145
GND

1 2 680P_0402_50V7K 0_0402_5% 0_0402_5%

+5VALW

2
2 1 VSSIO_SENSE 8

1
1

1
15K_0402_1%
RT8209MGQW_WQFN14_3P5X3P5
7

3
2
1
1

PR125
PC99
PC100 4.7U_0805_10V6K

2
4.7U_0603_6.3V6K
2

2
B B

PR126
4.02K_0402_1%
1 2
PR128
1

PR129 10_0402_5%
52 VCCPPWRGOOD 10K_0402_1% 2 1 VCCIO_SENSE 8
PR127 1 2 +3VALW
10K_0402_1%
2

@ PR130
10K_0402_1%

<Vo=1.05V> VFB=0.75V
1

V=0.75*(1+4.02K/10K)=1.052V
Fsw=298KHz
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=12.866A, Imax=9A, Iocp=15.439A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.33A
A =>1/2Delta I=1.665A A

choose Rcs=15K
Iocpmax=((15K*11uA)/0.0045)+1.665A=37.62A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=23.02A
Iocp=23.02A~37.62A Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 53 of 57
5 4 3 2 1
 5 4 3 2 1

CPU_B+

@ PC174

GFX@ PC101

GFX@ PC102

GFX@ PC103

0.1U_0402_25V6

0.1U_0402_25V6
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
1

1
1K_0402_1%

CSD17308Q3_SON8-5

1
@ PR153

PC171

PC172
GFX@ PC105 GFX@ PR140 2 1 +GFX_COREP

GFX@ PQ33
39P_0402_50V7K 2.55K_0402_1% @ PC107

2
2 1 2 1 330P_0402_50V7K GFX@ PR134

2
1 2 10_0402_1% UGATEG 1 2 4 @ @
VCC_AXG_SENSE 9

2
GFX@ PR135

330P_0402_50V7K
422_0402_1% GFX@ PR221
2 1 2 1 2 1 2 1 2 1 0_0603_5%
VSS_AXG_SENSE 9
GFX@ PL12
+GFX_COREP

3
2
1
2

1
@ PC116

GFX@ PC112 GFX@ PR139 GFX@ PC104 GFX@ PC110 0.36UH_PCMC104T-R36MN1R17_30A_20%

294K_0402_1%
150P_0402_50V8J 475K_0402_1% 330P_0402_50V7K 0.01U_0402_50V7K 2 1 PHASEG 4 1

GFX@ PR136
GFX@ PC108 1
1

680P_0603_50V7K 4.7_1206_5%
D GFX@ PR143 0.22U_0603_10V7K 3 2 D

5
+

PR138
10_0402_1% BOOTG 2 1 2 1 GFX@ PC111
2

1
TPCA8057-H_PPAK56-8-5
2 1 330U_2.5V_M
GFX@ PR137 GFX@ PR141 GFX@ PR142
GFX@ PC106 2.2_0603_5% 3.65K_0402_1% 1_0402_5% 2

2
GFX@ PQ34
UGATEG

PHASEG
1000P_0402_50V7K

LGATEG
BOOTG
LGATEG

NTCG
2 1 4

ISNG
ISPG

2
PC113
GFX@ PR144 GFX@ PH4

1
GFX@ PR132 7.5K_0402_1% 10K_0402_1%_ERTJ0EG103FA
8.06K_0402_1% +1.05VS_VCCP +3VS +5VS 1 2 1 2
GFX@ PC115

41

40

39

38

37

36

35

34

33

32

31

3
2
1

2
.1U_0402_16V7K

2
PU10 1 2 1 2

COMPG

FBG

RTNG

ISUMPG

ISUMNG

NTCG

BOOTG

UGATEG

PHASEG

LGATEG
PAD

1
GFX@ PR217 GFX@ PR147
1.91K_0402_1% PR218 11K_0402_1%

2
@ PC170 0_0603_5% 1 2

2
.1U_0402_16V7K PR148 30 BOOT2

1
BOOT2
2

PR149 130_0402_1% 1 GFX@ PC117

2
54.9_0402_1% VWG UGATE2 .1U_0402_16V7K
UGATE2 29
2 1 2
1

1
PGOODG PHASE2
28
1

PHASE2

1
+3VS 39 GFX_CORE_PWRGD 3 GFX@ PC118

ISPG
8 VR_SVID_DAT SDA
2

1.91K_0402_1%

27 LGATE2 PC164 0.047U_0402_16V4Z GFX@ PR151

@ PR159 SVID_ALERT# LGATE2 1U_0603_10V6K 1.02K_0402_1%
4

2
8 VR_SVID_ALRT# ALERT#
2

499_0402_1% 26
VCCP
PR156

SVID_SCLK 5

2
8 VR_SVID_CLK SCLK ISNG
25 2 1 +5VS 2 1
1

PR155 ISL95835HRTZ-T_TQFN40_5X5 PWM3

39 VR_ON 1 2 6 VR_ON
24 LGATE1 PR160 @ PR152 Connect to +5V can disable
1

0_0402_5% LGATE1 0_0402_5% 0_0402_5%

15 VGATE 7 PGOOD
23 PHASE1 GFX portion
PHASE1
39 VR_HOT# 8 VR_HOT#
22 UGATE1
UGATE1
1
47P_0402_50V8J

NTC 9 NTC
PC122

21 BOOT1
BOOT1

ISEN3/ FB2
C C
10
CPU_B+
2

VW

ISUMN

ISUMP
COMP

ISEN2

ISEN1

VDD
RTN

1
VIN
470KB_0402_5%_ERTJ0EV474J

FB
2

27.4K_0402_1%

PR162
1

PR133

2.2_0603_5%

11

12

13

14

15

16

17

18

19

20
PH3

2
ISEN2

ISEN1
1

NTCG

1comp

FB
2

10P_0402_50V8J
+5VS

1
PC130
1000P_0402_50V7K
3.83K_0402_1%

PC123

ISEN3
470KB_0402_5%_ERTJ0EV474J

1
27.4K_0402_1%

0.22U_0603_25V7K

2
2

2
GFX@ PR161

PR131

PL11

2
1
GFX@ PH5

PR164 HCB4532KF-800T90_1812
1

PC129

PR163 CPU_B+
1_0603_5% 1 2 B+

1
8.06K_0402_1%
2

68U_25V_M_R0.44
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1
1

PC175

PC124

PC125

PC126
CSD17308Q3_SON8-5
2

0.22U_0402_6.3V6K2

0.22U_0402_6.3V6K2
+

PC127
comp

1
PQ35
PC133

PC136
680P_0402_50V7K

PC131
2

1
3.83K_0402_1%

20.5K_0402_1%

1U_0603_10V6K @
2

2
GFX@ PR158

PC137

47P_0402_50V8J

UGATE21 2 4

2
1
PR172

1 2
267K_0402_1%

PR226
PR175

0_0603_5%
1

2
PC134

PL13
1

3
2
1
0.36UH_PCMC104T-R36MN1R17_30A_20%
PHASE2
+CPU_CORE
2
-
p
:h
h
PP
RR
1
27
7
=
2
.6
0
5
KK
VV
b
o
o
t
=
0=
V.
,
I
c
cI
mc
a
xm
=
5
4=
A5

4 1
PR165
2

680P_0603_50V7K 4.7_1206_5%
2.2_0603_5%
2
-
p
:
1
2
=
1
9

b
o
o
t
1
1
V
,
c
a
x
4
A

3 2
PC135

PR166
TPCA8057-H_PPAK56-8-5
PR173 BOOT2 2 1 2 1
VSUM-

PR177 1000P_0402_50V7K 887_0402_1% VSUM+

330P_0402_50V7K

B 2K_0402_1% PC132 B

PQ36
1 2 1 2 1 2 1 2 0.22U_0603_10V7K

2
1
LGATE2 4
FB

PC145

1.47K_0402_1%

PC141 PR167 PR169

0.033U_0402_16V7K
1

11K_0402_1%
470P_0402_50V8J 2.61K_0402_1% 3.65K_0402_1%
0.22U_0402_10V6K
1 2
1

1
PC139

PC140
VSUM+ 1 2
1

1
PR178

PC138

PR174
PR176 @ PR168
2

3
2
1
3.4K_0402_1% 10K_0402_1%

2
ISEN2 1 2
2

2
1

1
100_0402_1%

PR170 PR171
2

2
PR180

PH6 1_0402_5% 10K_0402_1%

10K_0402_1%_ERTJ0EG103FA VSUM- 1 2 2 1 ISEN1

@ @ PJ15
2

2 VSUM- JUMP_43X39

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 CPU_B+
1 2 2
1

PC176

PC147

PC148

PC149
PC146

CSD17308Q3_SON8-5
.1U_0402_16V7K

1
PQ37
2

@
0.01U_0402_50V7K
330P_0402_50V7K

UGATE1 1 2 4

2
PC142

PC143

PR227

@
2-ph: PR178=1.47K for ~70A OCP 0_0603_5%
PL14
2

3
2
1
2

2
10_0402_1%

0.36UH_PCMC104T-R36MN1R17_30A_20%
PR179

PR181 PHASE1
10_0402_1% PR182
4 1 +CPU_CORE

680P_0603_50V7K 4.7_1206_5%
2.2_0603_5% 3 2

PR183
BOOT1 2 1 2 1
1

TPCA8057-H_PPAK56-8-5
8

8
VSSSENSE

PC150 PR185
VCCSENSE

+CPU_CORE 0.22U_0603_10V7K 3.65K_0402_1%

2
PQ38
LGATE1 4 VSUM+ 1 2

1
A A

PC151
10K_0402_1%
ISEN1 1 PR184 2
3 PR187
2
1

2
1_0402_5% 10K_0402_1%
VSUM- 1 PR186 2 2 1ISEN2

+CPU_CORE +GFX_CORE
Iocp=72A, IccMAX=53A Iocp=40A, IccMAX=24A Security Classification Compal Secret Data Compal Electronics, Inc.
Load line=1.9mohm Load line=3.9mohm Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title
SCHEMATIC, MB LA-7231P

www.vinafix.vn
DCR=1.1mohm DCR=1.1mohm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 54 of 57
5 4 3 2 1
 5 4 3 2 1

VGA@ PL18
FBMA-L11-322513-151LMA50T_1210
B+ 1 2 B+_CORE

+3VS

1
VGA@ PC152 VGA@ PC153

1
10U_1206_25V6M 10U_1206_25V6M
@ PR188

2
10K_0402_5%

5
D D

CSD17308Q3_SON8-5
2

VGA@ PQ39
4

VGA@ PR189 VGA@ PC154

PU11 VGA@ 2.2_0603_5% 0.1U_0603_25V7K
VGA@ PR190 1 10 BST_VCORE 1 2 1 2

3
2
1
75K_0402_1% PGOOD VBST
1 2 2 9 DH_VCORE VGA@ PL15
TRIP DRVH 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
+3VS 3 8 SW_VCORE 3 2
EN SW +VGA_COREP
4 VFB V5IN 7 +5VALW 4 1

1 2 5 6 DL_VCORE
RF DRVL
2

ESR=10mohm

2
@ PR192 VGA@ PR191 11
TP

1
10K_0402_5% 200K_0402_1% VGA@ PC155

TPCA8057-H_PPAK56-8-5

TPCA8057-H_PPAK56-8-5
RT8237_SON10_3X3 VGA@ PR193

DL_VCORE
1U_0603_6.3V6M

1
VGA@ PR194 VFB=0.6V 4.7_1206_5% 1
1

10K_0402_1% VGA@ PR195 VGA@ PC157

VGA@ PQ40

VGA@ PQ41
VGA_ON 1 2 0_0402_5% + 330U_D2E_2.5VM

1 2
25,46 VGA_ON Switch freq. (RF pin setting) 4 4

2
1

47K ==>450KHz VGA@ PC158 VGA@ PR196 2

VGA@ PC159 680P_0603_50V7K 10_0402_5%
100K ==>390KHz

2
C .1U_0402_16V7K 2 1 C
2

3
2
1

3
2
1
200K ==>350KHz (Currently setting)
GS@ PR198
470K ==>300KHz

2
2.26K_0402_1%
GCORE_SEN
GV@ PR198 VGAVCC_SENSE 24
2.15K_0402_1%
TPCA8057-H Rds=2.6m/3.2m ohm

1
GS@ PR201
10.7K_0402_1%
+3VSDGPU

2
1
GV@ PR201

2
8.66K_0402_1%
VGA@ PC160 VGA@ PR200 VGA@ PR202
2200P_0402_25V7K 10K_0402_1% 10K_0402_5%

1
2
VGA@ PR203

1
6
D 10K_0402_5%
2 1 2
VGA@ PQ42A G

2
DMN66D0LDW-7_SOT363-6

1
GS@ PR205 S

1
Vtrip range ==> 0.2V ~ 3V @ PR219 13.3K_0402_1% GV@ PR205 VGA@ PC161 @ PR206
37.4K_0402_1% +3VSDGPU 10K_0402_1% +3VSDGPU 4700P_0402_25V7K 10K_0402_5%

2
VFB=0.7V

1
2

2
V=0.7*(1+Rtop/Rbottom)

2
Fsw=350KHz VGA@ PR216 VGA@ PR207
B 10K_0402_5% 10K_0402_5% B

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm. VGA@ PR222 VGA@ PQ43A VGA@ PR208
6

6
D 10K_0402_5% DMN66D0LDW-7_SOT363-6 D 10K_0402_5%

1
Ipeak=41.02A, Imax=28.714A, Iocp=43A 2 1 2 2 1 2 +3VSDGPU
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A VGA@ PQ44A G G
1

1
=>1/2Delta I=3.4A DMN66D0LDW-7_SOT363-6

2
S VGA@ PC163 S VGA@ PC162
1

1
choose Rcs=75K 4700P_0402_25V7K 4700P_0402_25V7K VGA@ PR210
2

2
10K_0402_5%
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A @ PR220 +3VSDGPU @ PR209

2
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A 10K_0402_5% 10K_0402_5%

1
VGA@ PR211
Iocp=48.42A~75.52A

3
D 10K_0402_5%

2
5 2 1
GPU_VID1 22,39

1
VGA@ PR223
VGA@PR223 G
10K_0402_5%
VGA@ PR225 VGA@ PQ42B S @ PR212

3
D

4
10K_0402_5% DMN66D0LDW-7_SOT363-6 10K_0402_5%

1
5 2 1 +3VSDGPU
GPU_VID2 22

2
GPU_VID2 GPU_VID1 GPU_VID0 VGA@ PQ44B G
NVIDIA/N12P-GS NVIDIA/N12P-GV1

1
DMN66D0LDW-7_SOT363-6

2
S @ PR224
4

10K_0402_5% GV@ PR213

VGA@ PR214 10K_0402_5%
P0(Cold) 1 0 1 1.0V 1.025V

3
D 10K_0402_5%

2
5 2 1
GPU_VID0 22,39

1
VGA@ PQ43B G
P0(Hot) 1 1 0 0.975V(default) 1.0V GS@ PR215
DMN66D0LDW-7_SOT363-6
S 10K_0402_5%

4
A A
P8/P12 1 1 1 0.860V 0.85V(default)

2
SJM only ==> VPS 0 1 1 0.900V ----
AP
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 55 of 57
5 4 3 2 1

www.vinafix.vn
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

2010
1 HW/Edward request Meet Turn off sequence 53 Add PQ45 DVT
D
11/24 D

Change PR119 to 680KΩ, PC95 to 0.1uF 2010

2 HW/Edward request Meet Turn on sequence 53 DVT
11/27
2010
3 HW/Edward request Meet new VGA table 55 Change PR201, PR205, PR219 DVT
12/03
2010
4 Battery Turn on time too long Change enable 3/5V path DVT
12/04
2010
5 HW/Edward request For USB 3.0 charger function 47 Add PJ26 DVT
12/04
2010
6 HW/Edward request Don't need VGA_PW_OK net 55 Delete net DVT
C
12/04 C

Change PR92 from 100K to 510K 2010

7 HW/Edward request Tune Power sequence 52 Delete PR94 DVT
12/08
2010
8 HW/Edward request Tune Power sequence 53 Change PR116 from 24.9K to 100K DVT
12/09

2011
9 Costdown 54 Change PC97, PC111 to OS-CON cap. PVT
01/06

10 ISN test fail ISN solution

Change PL16 to 1uH 2011
49 Add PC109, PC119 PVT
01/07

11 Trigger ACOC
Prevent to trigger phase to gnd threshold Change PC28 from 2.2u to 0.1u 2011
Reserve RC for ADP_I 48 Add PR72 PVT2
B
01/24 B

12

13

14

15

16
A A

17

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title
SCHEMATIC, MB LA-7231P

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 56 of 57
5 4 3 2 1
 A B C D E

A --> B Change List B --> C Change List

1209------------------------------------ 0121A------------------------------------
1. Page 24, Change R383 to GS@ 1. Page 19, Change L1 to SHI00003Y00
Change R380 to @ 2. Page 41, Change R626 to SD034499080 (499_1%)
Add Option Component for R383 and R386 4.99K_0402_1% with BOM structure GV@ Change R739 to SD034150080 (100_5%)
2. Page 46, Change R679 to 100K_0402_5% 3. Page 17, Add R185
Change R685 to 200K_0402_5% 4. Page 46, Change R703 to 100K
Change R692 to 750K_0402_5% 0110A------------------------------------
3. Page 40, Change SW8 to SN200002800 1. Change SE107475M80 to SE107475K80
1206---------------------------------------------- 2. Change SE052105Z80 to SE080105K80
1. Page 17, U16 BOM Structure change to OPT@ 3. Change SE068221J80 to SE074221K80
1 2. Page 37, C613 BOM structure change to BT@ 4. Change SE070473Z80 to SE076473K80 1
3. Page 32, Add T70, T71 for JCRT1. 5. Page 15, UnPOP U5 and POP R223
4. Page 45, Change H10 to H2P5. 6. Page 35, Unpop Q37 and POP R557
5. Page 14, Change C183, C184 to 27P 7. Change U8 to SA000047U10(N12P-GS) and SA00004JO10(N12P-GV)
6. Page 22, Change C297, C298 to 22P 8. Page41,
7. Page 35, Change C582, C583 to 33P R625 form 390 to 100
8. Page 43, Change R666, R668 to SM010017710 (For EMI) R626 from 820 to 200
9. Page 38, Pop R590, R591 with 33 ohm, C635, C636 with 6P for EMI R739 from 820 to 100
1203---------------------------------------------- R627 from 390 to 2.49K
1. Page 39, Add C703 for ESD. R629 from 820 to 3K
1202---------------------------------------------- R740 from 390 to 3.3K
1. Update power schematics R741 from 390 to 2.2K
2. Change H24 to H2P5 R740 from 820 to 3.3K
3. Page 35, Add R557 for power source +3VALW_PCH reserved 0107A------------------------------------
1201---------------------------------------------- 1. Page 40, Unpop SW8
1. Page 40, Update Reset Button circuit 2. Page 05, Add C215.
Add R656, Q38 1. Page 11, Add C207, C212, C214 (0.1U_0402) for EMI reuqire
2. Page 17, delete VGA_ON for PD only. 2. Page 12, Delete C159 for Layout space
Change PR3.2 to PCH_GPIO2, PR3.1 to PCH_GPIO53 3. Page 36, Delete R968, C994
Delete R257 4. Page 45, Reserved R736, R739
3. Update Power Schematics 1201 5. Page 18, Delete Q75
1130b---------------------------------------------- Change Q74 to Q74A, A74B (DMN66D0LDW-7_SOT363-6)
1. Page 38, U23.11 change to +3VS_CARD Change R842 PU to +3VSDGPU
2. Q2, Q13, Q19, Q21~Q29, Q31, Q33, Q34, Q50, Q51, Q54, Q56~Q63, Q68, Q74 change to SB00000J200 0103------------------------------------
1130---------------------------------------------- 1. Page 40, Add R691 for EC_BI
1. Page 18, Add Q75,Q74,R841 (The new circuit for DGPU_PWROK after 1.5V). 2. Page 39, Connect EC_BI to U24.64
Delete R271 Change R621 to 18K_0402_5%
2. Page40, Change R646 to 10K Delete net 65W/90W#
2 2
Change R648 to 1K 3. Page 25, Unpop C345, C346, C347, C348 L13, L14, C356, C357, C358
Pop R646, R648, D18, Q35, R645 for Reset mainpower and BI Change C349, C359 to 10K_5%_0402
Change R653 BOM structure to @ Unpop R415, R416
Change SW8 to SN200002700 4. Page 18, Change Q75 to AP2302GN-HF_SOT23-3
1129---------------------------------------------- Add R842, C185 with BOM structure OPT@
1. Page 07, Correct R70 bom structure to EDP@ Change Q74, Q75, R841 with BOM structure OPT@
2. Page 15,Change R244.1 net name from PCH_RSMRST# to PCH_RSMRST#_R 5. Page 37, Delete R572
Unpop R231 6. Page 08, change C81, C82 to SGA20331E10
3. Page 17, U6, U7 change to SA00000OH00 (Same as U5/U39) 7. Page 26, Change C381,C857 to SGA20471D20
4. Page 24, Delete R390, R391, R392 for space issue.
5. Page 35, Add Q37 and Unpop R555
6. Page 38, Add R833 between +3VS and +3VS_CARD
Change U23.47 to +3VS_CARD
7. Page 39,Change R621 from 0ohm to 8.2k(Board ID)
8. Page 42, Unpop R733
Pop R732, R299
Delete R637, R638, Q38, Q39, R299, R634, R636, R639, R640
Change netname of PD# to EC_MUTE#
Connect U29.4.9.21.29 to +3VS_CODEC
9. Page 45, Change C780 from SGA19151410(D size) to SGA00002N80(B2 size)
Unpop U40, C204, R754
10.Page 46, Change Q47, Q52 to AO4430L_SO8 C --> Pre-MP Change List
11.Update Power Schematics (11/25)
12.C226, C540, C549, C566, C573, C576, C580, C590, C712 change material to SE000000K80 0222A------------------------------------
13.D8, D9 change material to SCS00003600 (Need check again) 1. Page 41, Change R627, R741 to 100_0402_5%
14.D32 change to SC100001K00 (Need apply CIS Symbol) Change R740 to 150_0402_1%
1123---------------------------------------------- Change R627, R742 to 560_0402_5%
3 1. Page 22, Change R342 PU location from R762.2 to Q68.3 2. Page 45, Unpop D30 (Remove USB3.0 ESD Diode) 3
2. Page 24, Fix N12P-GV device ID 0218A------------------------------------
R489 change BOM Structure to GS@ 1.Page 31, Add L45 for USB20_P10/N10
R382, R380, R760, R756, R758, R757 change BOM Structure to GV@ Change R478/R479 to @
R380 change to 45.3K_0402_1% (SD034453280) Move C492, C493 to USB20_P10/N10
R760 change to 4.99K_0402_1% (SD034499180) Delete D5 for layout space
Delete Option compoent of R386 0215A------------------------------------
3. Page35, Modify auto boot-up issue 1. Page 44, Mount R720 for EEPROM (EON)
Unpop R552 2. Change U3 to B3 version(SA00004EEY0)
POP R553, R541 3. Page 41, change R626 to 300_0402_5%
Change R541 PU location from R552.1 to R552.2 change R739 to 100_0402_5%
4. Page36, L31 update CIS Symbol and PCB footprint 0125A------------------------------------
5. Page 40, Change R622 PU to +3VALW_EC 1. Page39 Change R621 to 33K_0402_5% (Board ID)
JTP1 pin definition upside down. 2. Update Power Schematics
Update D-Door Circuit
Delete SW1, R631
Add JDOOR1, SW
6. Page 41, SW6 change to SN100001D10
7. Page 42, Modify PD# circuit for 3V tolerance.
Add R299
Change R637, R638 PU to +3VS
Fix Headphone/MIC detect issue
Change R649 to 10K_0402_1%
Change R650 to 39.2K_0402_1%
8. Page 44, Modify SMI circuit for leakage issue.
Delete R830
Add Q69, R734
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 57 of 57
A B C D E