Colour Television Chassis

Q548.1E
LA

18560_000_090401.eps
090401

Contents Page Contents Page

1. Revision List 2 SSB: PNX8543 Audio (B03D) 98 128
2. Technical Specifications and Connections 2 SSB: PNX8543 Analog AV (B03E) 99 128
3. Precautions, Notes, and Abbreviation List 5 SSB: PNX8543 SDRAM (B03F) 100 128
4. Mechanical Instructions 9 SSB: PNX8543 MIPS/Flash/PCI (Pt.no.1)(B03G)101 128
5. Service Modes, Error Codes, and Fault Finding 16 SSB: PNX8543 MIPS/Flash/PCI (Pt.no.3)(B03G)102 129
6. Alignments 34 SSB: PNX8543 Standby Control/Debug (B03H) 103 128
7. Circuit Descriptions 40 SSB: Bolt-on (Pt. no. 1) (B04A) 104 128
8. IC Data Sheets 50 SSB: Bolt-on (Pt. no. 3) (B04A) 105 129
9. Block Diagrams SSB: Analog IO - Scart 1 & 2 (Pt. no. 1) (B04B) 106 128
Wiring Diagram 32" (Frame) 59 SSB: Analog IO - Scart 1 & 2 (Pt. no. 3) (B04B) 107 129
Wiring Diagram 37" (Roadrunner) 60 SSB: YPbPr / Side I/O / S-video (B04C) 108 128
Wiring Diagram 42" (Frame/Roadrunner) 61 SSB: HDMI (B05A) 109 128
Wiring Diagram 47" (Frame / Roadrunner) 62 SSB: Ethernet (Pt. no. 1) (B05B) 110 128
Wiring Diagram 52" (Frame) 63 SSB: Ethernet (Pt. no. 3) (B05B) 111 129
Block Diagram Video 64 SSB: PCMCIA (B05C) 112 128
Block Diagram Audio 65 SSB: Class-D (B06A) 113 128
Block Diagram Control & Clock Signals 66 SSB: Display Interface (Common) (B07A) 114 128
Block Diagram I2C 67 SSB: Display Supply (Pt. no. 1) (B07B) 115 128
Supply Lines Overview 68 SSB: Display Supply (Pt. no. 3) (B07B) 116 129
10. Circuit Diagrams and PWB Layouts Drawing PWB SSB: PNX5100 - Power (B08A) 117 128
Interface Ambilight + Single DC-DC (AB1) 69 72 SSB: PNX5100 - SDRAM (B08B) 118 128
Interface Ambilight Dual DC-DC (AB2) 70 72 SSB: PNX5100-Ctrl/PCI/Debug (Pt. no. 1)(B08C)119 128
Interface Ambilight Microcontrollerblock (AB3) 71 72 SSB: PNX5100-Ctrl/PCI/Debug (Pt. no. 3)(B08C)120 129
6 LED Ambilight Microcontroller 73 76 SSB: PNX5100 - LVDS In/Out (B08D) 121 128
8 LED Ambilight Microcontroller 77 81 SSB: PNX5100 - AmbiLight (B08E) 122 128
10 LED Ambilight Microcontroller 82 86 SSB: SRP List Explanation 123
12 LED Ambilight Microcontroller 87 91 SSB: SRP List Part 1 (Pt. no. 1) 124
SSB: DC/DC +3V3 +1V2 (B01A) 92 128 SSB: SRP List Part 2 (Pt. no. 1) 125
SSB: DC/DC +3V3 +1V2 Standby (B01B) 93 128 SSB: SRP List Part 1 (Pt. no. 3) 126
SSB: Front End (B02A) 94 128 SSB: SRP List Part 2 (Pt. no. 3) 127
SSB: PNX8543 - Power (B03A) 95 128
SSB: PNX8543 - Video/LVDS Out
(B03B) 96 128
SSB: PNX8543 Audio Amplifier (B03C) 97 128

©
Copyright 2010 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1061 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18563
2010-Jun-29
 EN 2 1. Q548.1E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0
• First release.
Manual xxxx xxx xxxx.1
• All Chapters: added CTNs to the manual, see Table 2-1
• Chapter 2: added AV output characteristics to section
2.3.2 Rear Connections
• Chapter 6: changed option codes of all sets,
see Table 6-6
• Chapter 6: introduced “option 9” for dedicated sets, see
Table 6-7
• Chapter 10: introduction of an alternative Ethernet
Controller, see diagram 8.7 Diagram SSB: Ethernet (Pt. no.
3) B05B, LAN9420 (IC7N04)
• Chapter 10: introduction of SSB Pt. 3, see diagrams
SSB: Bolt-on (Pt. no. 3), SSB: Analog IO - Scart 1 & 2 (Pt.
no. 3), SSB: Ethernet (Pt. no. 3), SSB: Display Supply (Pt.
no. 3) and SSB: PNX5100-Ctrl/PCI/Debug (Pt. no. 3).
Manual xxxx xxx xxxx.2
• All Chapters: added 47PFL8404H/60 to the manual, see
Table 2-1
• Chapter 5: removed SSB replacement flowchart
• Chapter 6: added section 6.6 Service SSB delivered
without main software loaded.
Manual xxxx xxx xxxx.3
• Chapter 2: added ethernet connector; see figure 2-1
• Chapter 5: added figure 5-12 SSB replacement flowchart
[2/2]
• Chapter 6: added white tone settings 52", see Table 6-3
White tone default settings 47" & 52" Frame sets (7000
series)
• Chapter 10: added diagram B03G Pt. 3, see diagram
SSB: PNX8543 Control MIPS/Flash/PCI (Pt. no. 3).

2. Technical Specifications and Connections

Index of this chapter: CTN Styling Published in:
2.1 Technical Specifications
42PFL7404H/12 Frame 3122 785 18560
2.2 Directions for Use
2.3 Connections 42PFL7404H/60 Frame 3122 785 18561
2.4 Chassis Overview 42PFL7674H/12 Frame 3122 785 18561
42PFL7674H/60 Frame 3122 785 18561
Notes: 42PFL7864H/12 Roadrunner 3122 785 18561
• Figures can deviate due to the different set executions. 42PFL7864H/60 Roadrunner 3122 785 18561
• Specifications are indicative (subject to change).
42PFL8404H/12 Roadrunner 3122 785 18560
42PFL8404H/60 Roadrunner 3122 785 18561
2.1 Technical Specifications 42PFL8654H/12 Roadrunner 3122 785 18561
42PFL8684H/12 Roadrunner 3122 785 18561
For on-line product support please use the links in Table 2-1.
42PFL8684H/60 Roadrunner 3122 785 18561
Here is product information available, as well as getting started,
42PFL8694H/12 Roadrunner 3122 785 18561
user manuals, frequently asked questions and software &
drivers. 42PFL8694H/60 Roadrunner 3122 785 18561
47PFL7404H/12 Frame 3122 785 18560
Table 2-1 Described Model numbers 47PFL7404H/60 Frame 3122 785 18561
47PFL7864H/12 Roadrunner 3122 785 18561
CTN Styling Published in: 47PFL8404H/12 Roadrunner 3122 785 18560
32PFL7404H/12 Frame 3122 785 18560 47PFL8404H/60 Roadrunner 3122 785 18561
32PFL7404H/60 Frame 3122 785 18561 52PFL7404H/12 Frame 3122 785 18560
32PFL7674H/12 Frame 3122 785 18561 52PFL7404H/60 Frame 3122 785 18561
32PFL7674H/60 Frame 3122 785 18561
32PFL7684H/12 Frame 3122 785 18561 2.2 Directions for Use
32PFL7684H/60 Frame 3122 785 18561
32PFL7694H/12 Frame 3122 785 18561 You can download this information from the following websites:
32PFL7694H/60 Frame 3122 785 18561 http://www.philips.com/support
32PFL7864H/12 Roadrunner 3122 785 18561 http://www.p4c.philips.com
32PFL7864H/60 Roadrunner 3122 785 18561
32PFL8404H/12 Roadrunner 3122 785 18560
32PFL8404H/60 Roadrunner 3122 785 18561
37PFL8404H/12 Roadrunner 3122 785 18560
37PFL8404H/60 Roadrunner 3122 785 18561
37PFL8684H/12 Roadrunner 3122 785 18561
37PFL8694H/12 Roadrunner 3122 785 18561

2010-Jun-29
 Technical Specifications and Connections Q548.1E LA 2. EN 3

2.3 Connections

Side connectors Back connectors

26-52"

1 11 10 9
19-22" AUDIO SPDIF EXT 2 EXT 1

2 OUT OUT (RGB/CVBS) (RGB/CVBS)

3
12
4
VGA

5
NETWORK

17

6
AUDIO IN :
LEFT / RIGHT
HDMI 1 / DVI HDMI 3
HDMI 2 / DVI
7 HDMI 3 / DVI
VGA

13
8 EXT 3 HDMI 2 HDMI 1

TV ANTENNA

14 15 16

18563_001_091218.eps
091218

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 4 - Head phone (Output)
(according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Bk - Head phone 32 - 600 Ω / 10 mW ot
Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.
5 - Common Interface
2.3.1 Side Connections 68p - See diagram B05C SSB: PCMCIA jk

1 - Cinch: Audio - In 6 - USB2.0

Rd - Audio R 0.5 VRMS / 10 kΩ jq
Wh - Audio L 0.5 VRMS / 10 kΩ jq
1 2 3 4
2 - Cinch: Video CVBS - In 10000_022_090121.eps
Ye - Video CVBS 1 VPP / 75 Ω jq 090121

3 - S-Video (Hosiden): Video Y/C - In Figure 2-2 USB (type A)

1 - Ground Y Gnd H
2 - Ground C Gnd H 1 - +5V k
3 - Video Y 1 VPP / 75 Ω j 2 - Data (-) jk
4 - Video C 0.3 VPP / 75 Ω j 3 - Data (+) jk
4 - Ground Gnd H

2010-Jun-29
 EN 4 2. Q548.1E LA Technical Specifications and Connections

7 - HDMI: Digital Video, Digital Audio - In 9 - +5VDC +5 V j

(see connector 15) 10 - Ground Sync Gnd H
11 - n.c.
8 - Service Connector (UART) 12 - DDC_SDA DDC data j
1 - Ground Gnd H 13 - H-sync 0-5V j
2 - UART_TX Transmit k 14 - V-sync 0-5V j
3 - UART_RX Receive j 15 - DDC_SCL DDC clock j

2.3.2 Rear Connections 13 - Mini Jack: Audio - In

Wh - Audio L 0.5 VRMS / 10 kΩ jo
Rd - Audio R 0.5 VRMS / 10 kΩ jo
9 - EXT1/2: Video RGB - In, CVBS - In/Out, Audio - In/Out (*)
20 2
14 - EXT3: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y 1 VPP / 75 Ω jq
21 1
Bu - Video Pb 0.7 VPP / 75 Ω jq
10000_001_090121.eps
090121
Rd - Video Pr 0.7 VPP / 75 Ω jq
Rd - Audio - R 0.5 VRMS / 10 kΩ jq
Figure 2-3 SCART connector Wh - Audio - L 0.5 VRMS / 10 kΩ jq

1 - Audio R 0.5 VRMS / 1 kΩ k 15 - HDMI 1, 2 & 3: Digital Video, Digital Audio - In

2 - Audio R 0.5 VRMS / 10 kΩ j
19 1
3 - Audio L 0.5 VRMS / 1 kΩ k 18 2
4 - Ground Audio Gnd H 10000_017_090121.eps
5 - Ground Blue Gnd H 090428
6 - Audio L 0.5 VRMS / 10 kΩ j
7 - Video Blue 0.7 VPP / 75 Ω jk Figure 2-5 HDMI (type A) connector
8 - Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9 1 - D2+ Data channel j
9.5 - 12 V: EXT 4:3 j 2 - Shield Gnd H
9 - Ground Green Gnd H 3 - D2- Data channel j
10 - n.c. 4 - D1+ Data channel j
11 - Video Green 0.7 VPP / 75 Ω j 5 - Shield Gnd H
12 - n.c. 6 - D1- Data channel j
13 - Ground Red Gnd H 7 - D0+ Data channel j
14 - Ground P50 Gnd H 8 - Shield Gnd H
15 - Video Red 0.7 VPP / 75 Ω j 9 - D0- Data channel j
16 - Status/FBL 0 - 0.4 V: INT 10 - CLK+ Data channel j
1 - 3 V: EXT / 75 Ω j 11 - Shield Gnd H
17 - Ground Video Gnd H 12 - CLK- Data channel j
18 - Ground FBL Gnd H 13 - Easylink Control channel jk
19 - Video CVBS/Y 1 VPP / 75 Ω k 14 - n.c.
20 - Video CVBS 1 VPP / 75 Ω j 15 - DDC_SCL DDC clock j
21 - Shield Gnd H 16 - DDC_SDA DDC data jk
17 - Ground Gnd H
(*) Note: The AV output on SCART 1 or 2 will be enabled (SW 18 - +5V j
controlled) for analogue RF channels only, if the decoder is 19 - HPD Hot Plug Detect j
turned “on” in the Menu: select Setup -> Installation -> Decoder 20 - Ground Gnd H
-> Status: select SCART 1 or 2 -> Channel: select any
analogue channel. 16 - Aerial - In
- - IEC-type (EU) Coax, 75 Ω D
10 - Cinch: S/PDIF - Out
Bk - Coaxial 0.4 - 0.6VPP / 75 Ω kq 17 - RJ45: Ethernet (if present)

12345678
11 - Cinch: Audio - Out
Rd - Audio - R 0.5 VRMS / 10 kΩ kq
Wh - Audio - L 0.5 VRMS / 10 kΩ kq
E_06532_025.eps
210905

12 - VGA: Video RGB - In

1
Figure 2-6 Ethernet connector
5
10
6

k
11 15
1 - TD+ Transmit signal
10000_002_090121.eps
090127 2 - TD- Transmit signal k
3 - RD+ Receive signal j
Figure 2-4 VGA Connector 4 - CT Centre Tap: DC level fixation
5 - CT Centre Tap: DC level fixation
1 - Video Red 0.7 VPP / 75 Ω j 6 - RD- Receive signal j
2 - Video Green 0.7 VPP / 75 Ω j 7 - GND Gnd H
3 - Video Blue 0.7 VPP / 75 Ω j 8 - GND Gnd H
4 - n.c.
5 - Ground Gnd H 2.4 Chassis Overview
6 - Ground Red Gnd H
7 - Ground Green Gnd H
8 - Ground Blue Gnd H Refer to chapter Block Diagrams for PWB/CBA locations.

2010-Jun-29
 Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for
proper function.
• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
• All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
• Be careful during measurements in the high voltage
section.
• Never replace modules or other components while the unit
is switched “on”.
• When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3 Notes
3.3.1 General
• Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Q548.1E LA 3. EN 5
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
3.3.2 Schematic Notes
• All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 kΩ).
• Resistor values with no multiplier may be indicated with
either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
• All capacitor values are given in micro-farads (μ = × 10-6),
nano-farads (n = × 10-9), or pico-farads (p = × 10-12).
• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
• The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
3.3.6 Alternative BOM identification
It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
2010-Jun-29
 EN 6 3. Q548.1E LA Precautions, Notes, and Abbreviation List

The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g. AP Asia Pacific
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers AR Aspect Ratio: 4 by 3 or 16 by 9
to the Service version change code, digits 5 and 6 refer to the ASF Auto Screen Fit: algorithm that adapts
production year, and digits 7 and 8 refer to production week (in aspect ratio to remove horizontal black
example below it is 2006 week 17). The 6 last digits contain the bars without discarding video
serial number. information
ATSC Advanced Television Systems
MODEL : 32PF9968/10 MADE IN BELGIUM Committee, the digital TV standard in
220-240V ~ 50/60Hz the USA
128W
ATV See Auto TV
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF
Auto TV A hardware and software control
S BJ3.0E LA system that measures picture content,
and adapts image parameters in a
10000_024_090121.eps dynamic way
100105
AV External Audio Video
AVC Audio Video Controller
Figure 3-1 Serial number (example)
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
3.3.7 Board Level Repair (BLR) or Component Level Repair carrier distance is 5.5 MHz
(CLR) BDS Business Display Solutions (iTV)
BLR Board-Level Repair
If a board is defective, consult your repair procedure to decide BTSC Broadcast Television Standard
if the board has to be exchanged or if it should be repaired on Committee. Multiplex FM stereo sound
component level. system, originating from the USA and
If your repair procedure says the board should be exchanged used e.g. in LATAM and AP-NTSC
completely, do not solder on the defective board. Otherwise, it countries
cannot be returned to the O.E.M. supplier for back charging! B-TXT Blue TeleteXT
C Centre channel (audio)
3.3.8 Practical Service Precautions CEC Consumer Electronics Control bus:
remote control bus on HDMI
• It makes sense to avoid exposure to electrical shock. connections
While some sources are expected to have a possible CL Constant Level: audio output to
dangerous impact, others of quite high potential are of connect with an external amplifier
limited current and are sometimes held in less regard. CLR Component Level Repair
• Always respect voltages. While some may not be ComPair Computer aided rePair
dangerous in themselves, they can cause unexpected CP Connected Planet / Copy Protection
reactions that are best avoided. Before reaching into a CSM Customer Service Mode
powered TV set, it is best to test the high voltage insulation. CTI Color Transient Improvement:
It is easy to do, and is a good service precaution. manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion

2010-Jun-29
 Precautions, Notes, and Abbreviation List Q548.1E LA 3. EN 7

DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote ITV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (color
Telecommunication Union relating to carrier= 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (color carrier PAL M=

2010-Jun-29
 EN 8 3. Q548.1E LA Precautions, Notes, and Abbreviation List

3.575612 MHz and PAL N= 3.582056 SVHS Super Video Home System
MHz) SW Software
PCB Printed Circuit Board (same as “PWB”) SWAN Spatial temporal Weighted Averaging
PCM Pulse Code Modulation Noise reduction
PDP Plasma Display Panel SXGA 1280 × 1024
PFC Power Factor Corrector (or Pre- TFT Thin Film Transistor
conditioner) THD Total Harmonic Distortion
PIP Picture In Picture TMDS Transmission Minimized Differential
PLL Phase Locked Loop. Used for e.g. Signalling
FST tuning systems. The customer TS Transport Stream
can give directly the desired frequency TXT TeleteXT
POD Point Of Deployment: a removable TXT-DW Dual Window with TeleteXT
CAM module, implementing the CA UI User Interface
system for a host (e.g. a TV-set) uP Microprocessor
POR Power On Reset, signal to reset the uP UXGA 1600 × 1200 (4:3)
PSDL Power Supply for Direct view LED V V-sync to the module
backlight with 2D-dimming VESA Video Electronics Standards
PSL Power Supply with integrated LED Association
drivers VGA 640 × 480 (4:3)
PSLS Power Supply with integrated LED VL Variable Level out: processed audio
drivers with added Scanning output toward external amplifier
functionality VSB Vestigial Side Band; modulation
PTC Positive Temperature Coefficient, method
non-linear resistor WYSIWYR What You See Is What You Record:
PWB Printed Wiring Board (same as “PCB”) record selection that follows main
PWM Pulse Width Modulation picture and sound
QRC Quasi Resonant Converter WXGA 1280 × 768 (15:9)
QTNR Quality Temporal Noise Reduction XTAL Quartz crystal
QVCP Quality Video Composition Processor XGA 1024 × 768 (4:3)
RAM Random Access Memory Y Luminance signal
RGB Red, Green, and Blue. The primary Y/C Luminance (Y) and Chrominance (C)
color signals for TV. By mixing levels signal
of R, G, and B, all colors (Y/C) are YPbPr Component video. Luminance and
reproduced. scaled color difference signals (B-Y
RC Remote Control and R-Y)
RC5 / RC6 Signal protocol from the remote YUV Component video
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)

2010-Jun-29
 Mechanical Instructions Q548.1E LA 4. EN 9

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal
4.4 Set Re-assembly

4.1 Cable Dressing

18560_104_090401.eps
090402

Figure 4-1 Cable dressing 32PFL7xxx/xx

18560_102_090401.eps
090402

Figure 4-2 Cable dressing 42PFL7xxx/xx

2010-Jun-29
 EN 10 4. Q548.1E LA Mechanical Instructions

18560_101_090401.eps
090402

Figure 4-3 Cable dressing 47PFL7xxx/xx

18560_100_090401.eps
090401

Figure 4-4 Cable dressing 52PFL7xxx/xx

2010-Jun-29
 Mechanical Instructions Q548.1E LA 4. EN 11

18560_103_090401.eps
090402

Figure 4-5 Cable dressing 32PFL8xxx/xx

18560_105_090401.eps
090402

Figure 4-6 Cable dressing 37PFL8xxx/xx

2010-Jun-29
 EN 12 4. Q548.1E LA Mechanical Instructions

18560_106_090401.eps
090402

Figure 4-7 Cable dressing 42PFL8xxx/xx

18560_107_090401.eps
090402

Figure 4-8 Cable dressing 47PFL8xxx/xx

2010-Jun-29
 Mechanical Instructions Q548.1E LA 4. EN 13

4.2 Service Positions 4.3.2 Speakers

For easy servicing of this set, there are a few possibilities Each speaker unit is mounted with two screws.
created: When defective, replace the whole unit.
• The buffers from the packaging.
• Foam bars (created for Service). 4.3.3 Ambi Light

4.2.1 Foam Bars Each Ambi Light unit is mounted on a subframe. Refer to
Figure 4-10 for details.

1
1

2 1 2

3
Required for sets
1 42"

2
1

18560_408_090401.eps
090402

Figure 4-10 Ambi Light unit

10000_018_090121.eps 1. Remove the Ambi Light cover [1].

090121 2. Unplug the connector(s) [2].
3. Remove the subframe [3].
Figure 4-9 Foam bars
4. The PWB can now be taken from the subframe.
When defective, replace the whole unit.
The foam bars (order code 3122 785 90580 for two pieces) can
be used for all types and sizes of Flat TVs.
4.3.4 Main Supply Panel
See figure Figure 4-9 for details. Sets with a display of 42" and
larger, require four foam bars [1]. Ensure that the foam bars
are always supporting the cabinet and never only the display. 1. Unplug all connectors.
Caution: Failure to follow these guidelines can seriously 2. Remove the fixation screws.
damage the display! 3. Take the board out.
By laying the TV face down on the (ESD protective) foam bars, When defective, replace the whole unit.
a stable situation is created to perform measurements and
alignments. By placing a mirror under the TV, you can monitor 4.3.5 IR & LED Board / Stand Support
the screen.
Refer to Figure 4-11 for details.
4.3 Assy/Panel Removal

The instructions apply to the 8000 series (Roadrunner - with

AmbiLight).

4.3.1 Rear Cover

Warning: Disconnect the mains power cord before you remove

the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.
1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.

2010-Jun-29
 EN 14 4. Q548.1E LA Mechanical Instructions

1 1

1
18560_110_090401.eps
18560_109_090401.eps 090402
090402
Figure 4-12 LCD Panel - top support
Figure 4-11 IR & LED Board / Stand Support

1. Remove the stand.

2. Remove the IR/LED cover [1]. 4 4
3. Remove the connectors on the IR/LED board.
4. Remove the fixation screws from the IR/LED board.
When defective, replace the whole unit.

Stand Support Removal for LCD panel removal

1. Remove the Main Supply Panel as earlier described. 2
2. Remove the screws [2] and take the support out.

4.3.6 Small Signal Board (SSB)

3
Caution: It is mandatory to remount screws at their original
position during re-assembly. Failure to do so may result in
damaging the SSB.
1. Unplug all connectors.
2. Remove the screws that secure the board.
3. The SSB can now be taken out of the set.

4.3.7 Keyboard Control Panel

1. Remove the right AmbiLight unit.

2. Follow instructions for removing the IR/LED board until 3.
3. Remove the connector on the IR/LED board.
4. Release the cable.
5. Release the clip on top of the unit and take the unit out. 4 4
When defective, replace the whole unit.
18560_111_090401.eps
090402
4.3.8 LCD Panel
Figure 4-13 LCD Panel - SSB subframe
Refer to Figure 4-12 to Figure 4-15 for details.
1. Remove the AmbiLight units as earlier described.
2. Remove the subwoofer as earlier described.
3. Remove the Top Support [1].
4. Release the LVDS [2] - and other connectors [3] from the
SSB.
5. Remove the subframe of the SSB [4] with the SSB still
mounted on it.
6. Release all connectors [5] from the PSU.
7. Remove the subframe of the PSU [6] with the PSU still
mounted on it.
8. Remove the stand support as earlier described.
9. Release the connectors [7] on the IR/LED Panel as earlier
described.
10. Remove the clips that secure the flare [8].
11. Remove the flare.
12. Now the LCD Panel can be lifted from the front cabinet.

2010-Jun-29
 Mechanical Instructions Q548.1E LA 4. EN 15

5
6 5 6

6 6

18560_112_090401.eps
090402

Figure 4-14 LCD Panel - PSU subframe

8 8
8
8

8 8 8 8
7

18560_113_090401.eps
090720

Figure 4-15 LCD Panel - panel removal

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse

order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
See Figure 4-1 to Figure 4-8
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

2010-Jun-29
 EN 16 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: • All service-unfriendly modes (if present) are disabled, like:
5.1 Test Points – (Sleep) timer.
5.2 Service Modes – Child/parental lock.
5.3 Step by step Start-up – Picture mute (blue mute or black mute).
5.4 Service Tools – Automatic volume levelling (AVL).
5.5 Error Codes – Skip/blank of non-favourite pre-sets.
5.6 The Blinking LED Procedure
5.7 Protections How to Activate SDM
5.8 Fault Finding and Repair Tips For this chassis there are two kinds of SDM: an analog SDM
5.9 Software Upgrading and a digital SDM. Tuning will happen according to Table 5-1.
• Analog SDM: use the standard RC-transmitter and key in
the code “062596”, directly followed by the “MENU” (or
5.1 Test Points
HOME) button.
Note: It is possible that, together with the SDM, the main
As most signals are digital, it will be difficult to measure menu will appear. To switch it “off”, push the “MENU” (or
waveforms with a standard oscilloscope. However, several key HOME) button again.
ICs are capable of generating test patterns, which can be • Digital SDM: use the standard RC-transmitter and key in
controlled via ComPair. In this way it is possible to determine the code “062593”, directly followed by the “MENU” (or
which part is defective. HOME) button.
Note: It is possible that, together with the SDM, the main
Perform measurements under the following conditions: menu will appear. To switch it “off”, push the “MENU” (or
• Service Default Mode. HOME) button again.
• Video: Colour bar signal. • Analog SDM can also be activated by, on the SSB,
• Audio: 3 kHz left, 1 kHz right. shorting for a moment the solder pads SDM [1] (see
Figure 5-1).
5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode

(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication 1
SDM
between the call centre and the customer.

This chassis also offers the option of using ComPair, a

hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section 5.4.1 ComPair).

Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
18440_200_090225.eps
5.2.1 Service Default Mode (SDM) 091118

Figure 5-1 Service mode pads

Purpose
• To create a pre-defined setting, to get the same
After activating this mode, “SDM” will appear in the upper right
measurement results as given in this manual.
corner of the screen (when a picture is available).
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic step by step start up). See How to Navigate
section 5.3 Step by step Start-up. When the “MENU” (or HOME) button is pressed on the RC
• To start the blinking LED procedure where only layer 2 transmitter, the set will toggle between the SDM and the normal
errors are displayed (see also section 5.5 Error Codes). user menu (with the SDM mode still active in the background).

Specifications How to Exit SDM

Use one of the following methods:
• Switch the set to STAND-BY via the RC-transmitter.
Table 5-1 SDM default settings
• Via a standard customer RC-transmitter: key in “00”-
sequence.
Default
Region Freq. (MHz) system
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID DVB-T
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07

• All picture settings at 50% (brightness, colour, contrast).

• All sound settings at 50%, except volume at 25%.

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding
5.2.2 Service Alignment Mode (SAM)
Purpose
• To perform (software) alignments.
• To change option settings.
• To easily identify the used software version.
• To view operation hours.
• To display (or clear) the error code buffer.
How to Activate SAM
Via a standard RC transmitter: key in the code “062596”
directly followed by the “INFO” or “I+” button. After activating
SAM with this method a service warning will appear on the
screen, continue by pressing the red button on the RC.
Contents of SAM (see also Table 6-8):
• Hardware Information
– A. SW version. Displays the software version of the
main software (example: Q5431-0.26.2.0=
AAAaB_X.Y.W.Z).
• AAAA= the chassis name, where “a” indicates the
chip version: e.g. TV543/32= Q543, TV543/82=
Q548, Q543/92= Q549.
• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
the software is now multi-region).
• X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
– B. SBY PROC version. Displays the software version
of the stand-by processor.
– C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
• Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched “on/off”, 0.5 hours is added to this number.
• Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
• Reset Error Buffer. When “cursor right” (or the “OK
button) is pressed and then the “OK” button is pressed, the
error buffer is reset.
• Alignments. This will activate the “ALIGNMENTS” sub-
menu. See chapter 6. Alignments.
• Dealer Options. Extra features for the dealers. See Table
6-8.
• Options. Extra features for Service. For more information
regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the “OK” button before
the options are stored. Otherwise changes will be lost.
• Initialize NVM. The moment the processor recognizes a
corrupted NVM, the “initialize NVM” line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
– Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
– Initialize the NVM.
• Note: When the NVM is corrupted, or replaced, there is a
high possibility that no picture appears because the display
code is not correct. So, before initializing the NVM via the
SAM, a picture is necessary and therefore the correct
display option has to be entered.
Refer to chapter 6. Alignments for details. To adapt this
option, it’s advised to use ComPair (the correct HEX values
Q548.1E LA 5. EN 17
for the options can be found in chapter 8 “Alignments”) or
a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code “062598” directly followed by the “MENU” (or HOME)
button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned in Table 6-6. Make sure to key in all three
digits, also the leading zero’s. If the above action is successful,
the front LED will go out as an indication that the RC sequence
was correct. After the display option is changed in the NVM, the
TV will go to the Stand-by mode. If the NVM was corrupted or
empty before this action, it will be initialized first (loaded with
default values). This initializing can take up to 20 seconds.
Display Option
Code
39mm
PHILIPS 040
27mm
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
(CTN Sticker)
10000_038_090121.eps
090819
Figure 5-2 Location of Display Option Code sticker
• Store - go right. All options and alignments are stored
when pressing “cursor right” (or the “OK” button) and then
the “OK”-button.
• SW Maintenance.
– SW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this information.
– HW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this information.
• Test settings. For development purposes only.
• Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
• Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
“Channel list”, “Personal settings”, “Option codes”,
“Display-related alignments” and “History list”. First a
directory “repair\” has to be created in the root of the
USB stick. To upload the settings select each item
separately, press “cursor right” (or the “OK button), confirm
with “OK” and wait until “Done” appears. In case the
download to the USB stick was not successful “Failure” will
appear. In this case, check if the USB stick is connected
properly and if the directory “repair” is present in the root of
the USB stick. Now the settings are stored onto the USB
stick and can be used to download onto another TV or
other SSB. Uploading is of course only possible if the
software is running and if a picture is available. This
method is created to be able to save the customer’s TV
settings and to store them into another SSB.
• Download from USB. To download several settings from
the USB stick to the TV. Same way of working as with
uploading. To make sure that the download of the channel
list from USB to the TV is executed properly, it is necessary
to restart the TV and tune to a valid preset if necessary.
Note: The “History list item” can not be downloaded from
USB to the TV. This is a “read-only” item. In case of
specific problems, the development department can ask
for this information.
How to Navigate
• In SAM, the menu items can be selected with the
“CURSOR UP/DOWN” key (or the scroll wheel) on the RC-
transmitter. The selected item will be highlighted. When not
2010-Jun-29
 EN 18 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding
all menu items fit on the screen, move the “CURSOR UP/
DOWN” key to display the next/previous menu items.
• With the “CURSOR LEFT/RIGHT” keys (or the scroll
wheel), it is possible to:
– (De) activate the selected menu item.
– (De) activate the selected sub menu.
• With the “OK” key, it is possible to activate the selected
action.
How to Exit SAM
Use one of the following methods:
• Switch the set to STAND-BY via the RC-transmitter.
• Via a standard RC-transmitter, key in “00” sequence, or
select the “BACK” key.
5.2.3 Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When CSM is activated, the layer 1 error is displayed via
blinking LED. Only the latest error is displayed. (see also
section 5.5 Error Codes).
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. This information can be handy if no information is
displayed.
Only for Q548.1:
When in the Q548.1 chassis CSM is activated, a test pattern
will be displayed during 5 s.: 1 s. blue, 1 s. green, and 1 s. red,
then again 1 s. blue and 1 s. green. This test pattern is
generated by the PNX5120.
So if this test pattern is shown, it could be determined that the
back end video chain (PNX5120, LVDS, and display) of the
SSB is working.
For LED backlight TV sets, the test pattern is build as follows:
1 s. blue, 1 s. green, 1 s. red (generated by the PNX5120) and
further on with 3 seconds RGB pattern from the LED Dimming
Panel.
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
How to Navigate
By means of the “CURSOR-DOWN/UP” knob (or the scroll
wheel) on the RC-transmitter, can be navigated through the
menus.
Contents of CSM
The contents are displayed on three pages: General, Software
versions, and Quality items. However, these group names itself
are not shown anywhere in the CSM menu.
General
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this.
2010-Jun-29
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee a in possibility to
do this.
• Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
• 12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
Remark: the content here can also be a part of the 12NC of
the SSB in combination with the serial number.
• 12NC display. Shows the 12NC of the display
• 12NC supply. Shows the 12NC of the supply.
• 12NC “fan board”. Shows the 12NC of the “fan board”-
module (for sets with LED backlight).
• 12NC “LED Dimming Panel”. Shows the 12NC of the
LED dimming Panel (for sets with LED backlight).
Software versions
• Current main SW. Displays the built-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q5431E_1.2.3.4.
• Stand-by SW. Displays the built-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section Software Upgrading).
Example: STDBY_1.2.3.4.
• MOP ambient light SW. Displays the MOP ambient light
EPLD SW.
• MPEG4 software. Displays the MPEG4 software (for sets
with MPEG4).
• PNX5120 boot NVM. Displays the SW-version that is used
in the PNX5120 boot NVM (for sets with PNX5120).
• LED Dimming SW. Displays the LED dimming EPLD SW
(for sets with LED backlight).
Quality items
• Signal quality. Poor/average/good
• Child lock. Not active/active. This is a combined item for
locks. If any lock (Preset lock, child lock, lock after or
parental lock) is active, the item shall show “active”.
• HDMI HDCP key. Indicates of the HDMI keys (or HDCP
keys) are valid or not. In case these keys are not valid and
the consumer wants to make use of the HDMI functionality,
the SSB has to be replaced.
• Ethernet MAC address. Not applicable.
• Wireless MAC address. Not applicable.
• BDS key. Indicates if the “BDS level 1” key is valid or not.
• CI slot present. If the common interface module is
detected the result will be “YES”, else “NO”.
• HDMI input format. The detected input format of the
HDMI.
• HDMI audio input stream. The HDMI audio input stream
is displayed: present / not present.
• HDMI video input stream. The HDMI video input stream
is displayed: present / not present.
How to Exit CSM
Press the “MENU” (or HOME) button twice on the RC-
transmitter.
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 19

5.3 Step by step Start-up

When the TV is in a protection state due to an error detected by

stand-by software (error blinking is displayed) and SDM is
activated via short cutting the pins on the SSB, the TV starts up
until it reaches the situation just before protection. So, this is a
kind of automatic step by step start-up. In combination with the
start-up diagrams below, it is shown which supplies are present
at a certain moment. Important to know is, that if e.g. the 3V3
detection fails and thus layer 2 error = 18 is blinking while the
TV is restarted via SDM, the Stand-by Processor will enable
the 3V3, but the TV set will not go to protection now. The TV
will stay in this situation until it is reset (Mains/AC Power supply
interrupted).
Caution: in case the start-up in this mode with a faulty FET
7101-1 is done, all ICs supplied by the +3V3 could be
destroyed, due to over voltage (12V on 3V3-line). It is
recommended to measure first the FET 7101-1 or others FETs
on short-circuit before activating SDM via the service pads.

The abbreviations “SP” and “MP” in the figures stand for:

• SP: protection or error detected by the Stand-by
Processor.
• MP: protection or error detected by the MIPS Main
Processor.

Mains
off Mains
on

- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed

St by Semi
- stby requested and Active
no data Acquisition St by - St by requested
required - tact SW pushed

Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection

Protection

18440_215_090227.eps
091118

Figure 5-3 Transition diagram

2010-Jun-29
 EN 20 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

Off
Hálózatot alkalmaznak
Stand by or
Protection
A Készenléti ellátás futni kezd.
Minden készenléti tápfeszültség elérhetővé válik.

st-by µP resets

Ha a védelmi állapotot az SDM csapok rövidzárlata

Inicializálja az st-byµP I / O'Pins-jét:
hagyta el, akkor a védelmi állapot észlelése az
- Kapcsoló reset-AVC LOW (reset állapot)
indításkor leállítja az indítást. A játékkészlet védelmi
- Kapcsoló WP-NandFlash LOW (védett)
feltételeit figyelmen kívül hagyják. A védelmi mód
- Kapcsolja az alaphelyzetbe állítási rendszert
nem lép be.
- Switch reset-5100 LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
-keepreset-NVM high, Audio-reset and Audio-Mute-Up HIGH

- Kapcsolja magasra az Audio-Reset gombot.

Alacsony a készenléti állapot, a készenléti
start keyboard scanning, RC detection. Wake up r e asons a re off.
üzemmód 10 másodpercnél tovább tartott.

Az NXP-től kapott megerősítés arról, hogy nincs szükség

Reset detect2_delay_flag késésre a + 1V2 és a + 3V3 emelkedése között. Csak az a
követelmény, hogy a + 1V2-t ugyanazon időpont előtt vagy
előtt kell törölni, mivel a + 3V3.150ms késleltetés törlődik.

Switch ON Platform and display supply by switching

LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power

is switched on, followed by the +1V2 DCDC converter

Detect2 should be polled on the standard 40ms

interval and startup should be continued when Delay 1.5 second before checking detect2 line Carefull we don’t hit this error
detect2 becomes high. if the detect2_delay_flag is set directly if the delay flag is set.

Power-OK error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes

No
Enter protection
Wait fixed time of 15ms

If the supply is hicking, the first detect2 could

be positive (12V still present), followed by
negative Supply-fault (already low). Adding a
Detect2 high? fixed delay brings us behind this delay gap.

Yes

This enables the +3V3 and +5V converter. As a Reset detect2_delay_flag

result, also +5V-tuner, +2V5, +1V8-PNX8541 and
+1V8-PNX5100 (if present) become available.

Enable the DCDC converter for +3V3 and

+5V. (ENABLE-3V3)

Delay of 50ms needed because of the latency of

the detect-1 circuit. This delay is also needed for Set detect2_delay_flag
the PNX5100. The reset of the PNX5100 should Wait 50ms
only be released 10ms after powering the IC.

Detect-1 I/O line Detect-2 I/O line Disable 3V3, switch standby
No No
High? High? line high and wait 4 seconds

Yes

These checks prevent the set from going in to

Yes Wait 50ms standby on the false error condition where the
first 3V3 is negative because of a hickup,
although the 12V was about to reappear.
Because of this reappearance, the 12V check
is OK which would cause protection. If we wait
Yes Detect-1 I/O line
50ms, the 3V3 should be back as well.
High?

No
No

Detect-2 I/O line

High?

Yes

Enable the supply detection algorithm Voltage output error:

Layer1: 2
Layer2: 18
Enter protection
Set I²C slave address
of Standby µP to (A0h)

This will allow access to NVM and

Switch LOW the RESET-NVM line to allow access to NVM. (Add a NAND FLASH and can not be done
2ms delay before trying to address the NVM to allow correct NVM earlier because the FLASH needs to
initialization, this is no issue in this setup, the delay is automatically be in Write Protect as long as the
No covered by the architectural setup) supplies are not available.

Switch HIGH the WP-NandFlash to

allow access to NAND Flash

Only usefull in case of PNX5100 present. To avoid

Release Reset-PNX5100.
diversity in standby µP, the reset-PNX5100 will still be
PNX5100 will start booting.
switched by the standby µP.

This 10ms delay is still present to give some relaxation

Wait 10 ms to the supplies. (The PCI arbiter on the PNX5100 is
never used and is not the reason anymore)

Detect EJTAG debug probe

(pulling pin of the probe interface to An EJTAG probe (e.g. WindPower ICE probe) can be
ground by inserting EJTAG probe) connected for Linux Kernel debugging purposes.

EJTAG probe
Yes
connected ?

No

No Cold boot?

Yes

Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism

To: 18440_216b_090227.eps To: 18440_216b_090227.eps

18440_216a_090227.eps
091118

Figure 5-4 “Off/Stand-by” to “Semi Stand-by” flowchart (part 1)

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 21

From: 18440_216a_090227.eps From: 18440_216a_090227.eps

Reset-system is switched HIGH by the Reset-system is switched HIGH by the

AVC at the end of the bootscript AVC at the end of the bootscript
Reset-system is connected to the
Micronas MultiStandard decoder.

AVC releases Reset-Ethernet when the AVC releases Reset-Ethernet when the
end of the AVC boot-script is detected end of the AVC boot-script is detected
This cannot be done through the bootscript,
the I/O is on the standby µP

Reset-Audio and Audio-Mute-Up are Reset-Audio and Audio-Mute-Up are

switched by MIPS code later on in the switched by MIPS code later on in the
Timing need to be updated if startup process startup process
more mature info is available.

Bootscript ready
No
in 1250 ms?

Yes

Set I²C slave address

of Standby µP to (60h)

RPC start (comm. protocol)

Timing needs to
be updated if more
Flash to Ram mature info is
No image transfer succeeded available.
within 30s?
Code =
Layer1: 2
Layer2: 15 Yes
Timing needs to be
updated if more
Code = mature info is
Switch AVC PNX8543 SW initialization
Layer1: 2 No available.
in reset (active low) succeeded
Layer2: 53
within 20s?

Wait 10ms Yes

Enable Alive check mechanism

Switch the NVM reset
line HIGH.

MIPS reads the wake up reason Wait until AVC starts to

from standby µP. communicate
Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.

5100 SW start
Wait 5ms
Startup screen shall only be visible when there is a coldboot
Wake up reason to an active state end situation. The startup screen shall not
coldboot & not semi- be visible when waking up for reboot reasons or waking up to
switch off the remaining DC/DC
standby? semi-standby conditions.
converters

yes
Switch Standby I/O line high
3-th try?
and wait 4 seconds
The first time after the option turn on of the startup screen or
Startup screen cfg file when the set is virgin, the cfg file is not present and hence
present? the startup screen will not be shown.
Yes

yes
Blink Code as
error code
MIPS sends display parameters and
Bitmap to 5100

No To keep this flowchart readable, the exact display turn on

description is not copied here. Please see the Semi-standby
MIPS triggers 5100 to display the
Enter protection startup screen
to On description for the detailed display startup sequence.
During the complete display time of the Startup screen, the
No preheat condition of 100% PWM is valid.

Startup screen visible

Initialize audio

In case of a LED backlight display, a LED DIM panel is present

Switch on the display in case of a LED backlight
display by sending the TurnOnDisplay(1) (I²C)
command to the PNX5100
which is fed by the Vdisplay. To power the LED DIM Panel, the
Vdisplay switch driven by the PNX5100 must be closed. The
display startup sequence is taken care of by the LED DIM
panel. Secondly, this cmd will also enable the LVDS output of
the 5100 towards the LED DIM panel.

Enable the PWM output towards the display LVDS In case of a LED backlight display, the PWM-dimming signal
cable in case of a LED Backlight set. needs to be routed to the LVDS cable. This routing is not
(CTRL4-PNX5100) allowed in non-LED sets (see also display configuration)

Initialize tuner and Multi Standard decoder

Initialize source selection

Initialize video processing IC's :

- local contrast FPGA

- PNX5100 (if present)

Initialize AutoTV

Initialize Ambilight with Lights off.

Semi-Standby

18440_216b_090227.eps
090702

Figure 5-5 “Off/Stand-by” to “Semi Stand-by” flowchart (part 2)

2010-Jun-29
 EN 22 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

Constraints taken into account:

- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the backlight, the backlight should be driven with a PWM duty cycle of 100%
during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output level
(Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts, the
picture should only be unblanked after these first seconds.

Semi Standby
The assumption here is that a fast toggle (<2s) can
only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
Wait until previous on-state is left more than 2
made in less than 2s, because the standby state will
seconds ago. (to prevent LCD display problems)
be maintained for at least 4s.

Assert RGB video blanking

CPipe already generates a valid output and audio mute
clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?

(splash screen)

No

No PNX5100 present?

Switch on the display power by

Yes Yes
The exact timings to switching LCD-PWR-ON low
switch on the Switch on the display by sending the
display (LVDS Initialize audio and video
TurnOnDisplay(1) (I²C) cmd to the PNX5100
delay, lamp delay) Wait x ms processing IC's and functions
are defined in the according needed use case.
display file. Delay Lamp-on with the sum of the LVDS delay and
Switch on LVDS output in 8543
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set

The sum of the LVDS delay and the Lamp delay needs the BOOST control to nominal and make sure
to be used because the Lamp delay is specified with PWM output is set to 100%
the appearance of the LVDS on the display as
reference. This moment is not known by ceplf, only the
switch on of the LCD power is known. The delta
between both is the LVDS delay. Switch on LCD backlight (Lamp-ON)

The complete algorithm description is

removed here.
Only the start of the algorithm
is mentioned here as reminder.
Start POK line detection
algorithm
Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return

Switch Audio-Reset low and wait 5ms

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

Restore dimming backlight feature, PWM and BOOST output

The higher level requirement is that audio and video
and unblank the video.
should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Switch on the Ambilight functionality according the last status
settings.
The higher level requirement is that the
ambilight functionality may not be switched on
before the backlight is turned on in case the
set contains a CE IPB inverter supply. Startup screen Option
and Installation setting
Photoscreen ON?

Yes

Display cfg file present

and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active

18440_217_090227.eps
091112

Figure 5-6 “Semi Stand-by” to “Active” flowchart

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 23

Active

Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground

(I/O: audio reset) a nd wait 5ms

Switch off Ambilight

The higher level requirement is that the

Wait until Ambilight has faded out: Output power backlight may not be switched off before the
Observer on PNX5100 should be zero ambilight functionality is turned off in case the
set contains a CE IPB inverter supply.

Switch off POK line detection

algorithm

Switch off LCD backlight

Mute all video outputs

Wait x ms (display file)

No PNX5100 present?
The exact timings to
switch off the
Yes display (LVDS
delay, lamp delay)
are defined in the
Switch off LVDS output in 8543
Switch off the display by sending: display file.
- TurnOnDisplay(0) (I²C) command to the PNX5100
Wait x ms - or sending OUTPUT-ENABLE(0) to the LED DIM
panel in case of a LED BL set.

Switch off the display power by

switching LCD-PWR-ON high

Semi Standby

18440_219_090227.eps
091112

Figure 5-7 “Active” to “Semi Stand-by” flowchart

2010-Jun-29
 EN 24 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

Semi Stand by

If ambientlight functionality was used in semi-standby

(lampadaire mode), switch off ambient light

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

Transfer Wake up reasons to the Stand by µP.

Switch Memories to self-refresh (this creates a more

stable condition when switching off the power).

Switch AVC system in reset state (reset-system and

reset-AVC lines)
Switch reset-PNX5100 LOW
Switch Reset-Ethernet LOW

Wait 10ms

Switch the NVM reset line HIGH

Switch WP-Nandflash LOW

Disable all supply related protections and switch off

the DC/DC converters (ENABLE-3V3)

Wait 5ms

Switch OFF all supplies by switching HIGH the

Standby I/O line

Important remarks:

release reset audio 10 sec after entering

standby to save power

Also here, the standby state has to be

maintained for at least 4s before starting
another state transition.
Stand by

18440_220_090227.eps
091112

Figure 5-8 “Semi Stand-by” to “Stand-by” flowchart

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 25

5.4 Service Tools 5.5 Error Codes

5.4.1 ComPair 5.5.1 Introduction

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the uP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.
How to Connect
This is described in the chassis fault finding database in
ComPair.
TO TV
TO TO
UART SERVICE
CONNECTOR
I2C SERVICE
CONNECTOR
ComPair II
Multi
function
RC in RC out
Optional Power Link/ Mode
Switch Activity I2C
PC
ComPair II Developed by Philips Brugge
Optional power
HDMI
I2C only
Figure 5-9 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
• Software is available via the Philips Service web portal.
• ComPair serial interface cable for Q52x.x.
(using 3.5 mm Mini Jack connectors): 3138 188 75051.
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
New in this chassis is the way errors can be displayed:
There is a simple blinking LED procedure for board level repair
(home repair) so called LAYER 1 errors next to the existing
errors which are LAYER 2 errors (see Table 5-3).
– LAYER 1 errors are one digit errors
– LAYER 2 errors are two digit errors.
• In protection mode.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
• Fatal errors, if I2C bus is blocked and the set re-boots, CSM
and SAM are not selectable.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
Important remark:
For all errors detected by MIPS which are fatal =>
rebooting of the TV set (reboot starts after LAYER 1
error blinking), one should short the solder paths at
TO
UART SERVICE
CONNECTOR
start-up from the power OFF state by mains
interruption and not via the power button to trigger the
SDM via the hardware pins.
• In CSM mode
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
RS232 /UART • In SDM mode
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
• In the ON state
– In “Display error mode”, set with the RC commands
“mute_06250X _OK” LAYER 2 errors are displayed via
blinking LED.
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
5V DC
Basically there are three kinds of errors:
10000_036_090121.eps
• Errors detected by the Stand-by software which lead to
091118 protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
• Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section Extra Information. Note
that it can take up several minutes before the TV starts
blinking the error (e.g. LAYER 1 error = 2, LAYER 2
error = 15 or 53).
• Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.

Note: When having problems, please contact your local

support desk.

2010-Jun-29
 EN 26 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

5.5.2 How to Read the Error Buffer content, as this history can give significant information). This to
ensure that old error codes are no longer present.
Use one of the following methods: If possible, check the entire contents of the error buffer. In
• On screen via the SAM (only when a picture is visible). some situations, an error code is only the result of another error
E.g.: code and not the actual cause (e.g. a fault in the protection
– 00 00 00 00 00: No errors detected detection circuitry can also lead to a protection).
– 23 00 00 00 00: Error code 23 is the last and only
detected error.
– 37 23 00 00 00: Error code 23 was first detected and There are several mechanisms of error detection:
error code 37 is the last detected error. • Via error bits in the status registers of ICs.
– Note that no protection errors can be logged in the • Via polling on I/O pins going to the stand-by processor.
error buffer. • Via sensing of analogue values on the stand-by processor
• Via the blinking LED procedure. See section 5.5.3 How to or the PNX8543.
Clear the Error Buffer. • Via a “not acknowledge” of an I2C communication.
• Via ComPair.
Take notice that some errors need several minutes before they
5.5.3 How to Clear the Error Buffer start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
Use one of the following methods: check if the front LED is blinking or if an error is logged.
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu. Table 5-2 Layer 1 code overview (multi chassis overview)
• With a normal RC, key in sequence “MUTE” followed by
“062599” and “OK”. LAYER 1 codes
• If the content of the error buffer has not changed for 50+ SSB 2
hours, it resets automatically. Display supply 3
Platform supply 4 Only for display option 196 and 197
Fan 7
5.5.4 Error Buffer
AmbiLight or DC/DC or 3D LED dim panel 8

In case of non-intermittent faults, clear the error buffer before

starting to repair (before clearing the buffer, write down the

Table 5-3 Error code overview (multi chassis overview)

EB: in Error Buffer
BL: Blinking LED

Special Remarks
Defective board
LAYER 1 error
LAYER 2 error
Description

Error/Prot.
Monitored

Medium

Device

Main NVM 2 0 MIPS I2C1 E x STM24C128 SSB TV shut down with red LED blinking 2.
Temp. protection 3 12 MIPS I2C4 P BL/EB Supply
I2C3 2 13 MIPS I2C3 E BL/EB SSB SSB TV is rebooting endlessly with red LED blinking “2”.
I2C2 2 14 MIPS I2C2 E BL/EB SSB SSB
PNX does not boot (HW cause) 2 15 St-by µP I2C1 P BL SSB SSB TV is rebooting endlessly with red LED blinking “2”
PNX 5100 does not boot
12V 3 16 St-by µP I/O P BL Supply TV shut down with red LED blinking “3”.
12V 3 16 St-by µP I/O P BL Platform Supply
Inverter or display supply 3 17 Mips I/O E EB Supply TV still in normal operation mode, but without backlights.
Enter CSM Layer 1 red LED blinking “3”.
Only for display option 196 and 197 4 17 Mips I/O E EB Display Supply
1V2, 1V2, 3V3, 5V to low 2 18 St-by µP I/O P BL SSB TV shut down with red LED blinking “2”.
PNX 5100 2 21 MIPS I2C3 E EB PNX 5100 SSB TV is rebooting endlessly, with red LED blinking “2” (shown
every 20 second).
HDMI MUX 2 23 MIPS I2C3 E EB TDA9996 SSB Activate CSM red LED blinking “2”.
I2C switch 2 24 Mips I2C2 E EB PCA9540 SSB
Boot-NVM PNX5120 2 25 MIPS I2C3 E EB STM24C08 SSB TV is rebooting endlessly, with red LED blinking “2” (shown
every minute).
Multi Standard demodulator (Micronas IF) 2 27 MIPS 2
I C3 E EB DRX3616K SSB TV is in normal operation but without video displayed (RF).
DRX3626K
2
ARM (AL) 8 28 MIPS I C3 E EB NXP LPC2103 AL mod. or DC/DC TV is in normal operation but without AMBILIGHT “on”.
FPGA (Local contrast) 2 29 MIPS I2C3 E EB Altera SSB
Tuner1 2 34 MIPS I2C3 E EB UV1783S SSB TV is in normal operation but without video displayed (RF).
HD1816
FAN I2C expander 7 41 MIPS I2C2 E EB PCA 9533 FAN mod.
T× sensor 7 42 MIPS I2C2 E EB LM 75 T×sensor
FAN 1 7 43 MIPS I2C2 E EB FAN
FAN 2 7 44 MIPS I2C2 E EB FAN
MIPS does not boot (SW cause) 2 53 St-by µP I2C1 P BL PNX8543 SSB TV is rebooting endlessly with white LED blinking.
Display 5 64 MIPS I2C2 E BL/EB Altera Display
FPGA LED dim 2D 2 65 MIPS I2C3 E EB Xilinx SSB
FPGA LED dim 3D 8 65 MIPS I2C2 E EB Altera SSB

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding
Extra Information
• Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8.6 UART Logging). It’s shown that the
loggings which are generated by the main software keep
continuing. In this case diagnose has to be done via
ComPair. 5.6
• Main NVM. When there is no I2C communication towards
the main NVM, LAYER 1 error = “2” will be displayed via 5.6.1
the blinking LED procedure. In SDM, LAYER 2 error can be
“19”. Check the logging for keywords like “I2C bus blocked”.
• Error 13 (I2C bus 3 blocked). When this error occurs, the
TV will constantly reboot due to the blocked bus. The best
way for further diagnosis here, is to use ComPair.
• Error 15 (PNX8543 doesn’t boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8543
(supplies not OK, PNX 8541 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C2 bus is
blocked (NVM). I2C2 can be indicated in the schematics as
follows: SCL-UP-MIPS, SDA-UP-MIPS, SCL-2 or SDA-2.
Other root causes for this error can be due to hardware
problems with: NVM PNX5120, PNX5120 itself, or DDRs.
• Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = “3”). When SDM
is activated we see blinking LED LAYER 2 error = “16”.
• Error 17 (POK). The display is switched “on” with the
signal “Lamp On”. If the inverter starts (or 24V display is
OK) the POK line becomes “high”. If the POK line is not
“high”, the set backlight will be switched “off” and “on” again
for 3 times (start-up). If the set POK line becomes “high”
after the retries, no error is logged; if the POK stays “low”,
error is logged: LAYER 1 error = “3”, LAYER 2 error = “17”.
No protection is required, the start-up goes on.
• Error 18 (1V2-3V3-5V too low). All these supplies are
generated by the DC/DC supply on the SSB. If one of these
supplies is too low, protection occurs and blinking LED
LAYER 1 error = “2” will be displayed automatically. In
SDM this gives LAYER 2 error = “18”.
• Error 21 (PNX5120). When there is no I2C communication
towards the PNX5120 after start-up (power “off” by
disconnection of the mains cord), LAYER 2 error will blink
continuously via the blinking LED procedure in SDM. (start-
up the TV with the solder paths short to activate SDM).
• Error 23 (HDMI). When there is no I2C communication
towards the HDMI multiplexer after start up, LAYER 2
error = “23” will be logged and displayed via the blinking
LED procedure if SDM is switched “on”.
• Error 25 (Boot-NVM PNX5120). When there is no I2C
communication towards the PNX5120 NVM after start-up,
TV is rebooting endlessly with blinking LAYER 1 error = 2
(shown every minute). When SDM is activated we see
blinking LED LAYER 2 error = “25”.
• Error 27 (Multi Standard demodulator). When there is no
I2C communication towards the Multi Standard
demodulator after start up, LAYER 2 error = “27” will be
logged and displayed via the blinking LED procedure when 5.6.2
SDM is switched “on”.
• Error 28 (FPGA ambilight). When there is no I2C
communication towards the FPGA ambilight after start up,
LAYER 2 error = “28” will be logged and displayed via the
blinking LED procedure if SDM is switched “on”. Note that
it can take up several minutes before the TV starts blinking
LAYER 1 error = “2” in CSM or in SDM, LAYER 2
error = “28”.
• Error 34 (Tuner). When there is no I2C communication
towards the tuner after start up, LAYER 2 error = “34” will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
• Error 53. This error will indicate that the PNX8543 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
Q548.1E LA 5. EN 27
of hardware problems (NAND flash,...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take up to 2 minutes
before the TV starts blinking LAYER 1 error = “2” or in
SDM, LAYER 2 error = “53”.
The Blinking LED Procedure
Introduction
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-3 Error code
overview (multi chassis overview)) which causes the failure
of the TV. This approach will especially be used for home
repair and call centres. The aim here is to have service
diagnosis from a distance.
• Blinking LED procedure LAYER 2 error. Via this procedure,
the contents of the error buffer can be made visible via the
front LED. In this case the error contains 2 digits (see table
5-3 Error code overview (multi chassis overview)) and will
be displayed when SDM (hardware pins) is activated. This
is especially useful for fault finding and gives more details
regarding the failure of the defective board.
Important remark:
For all errors detected by MIPS which are fatal (rebooting
of the TV set, with reboot starts after LAYER 1 error
blinking), one should short the SDM solder paths at start-
up from the power OFF state by mains interruption and not
via the power button, to trigger the SDM via the hardware
pins.
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error-buffer. Error
codes greater then 10 are shown as follows:
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence
6. The sequence starts again.
How to Activate
Use one of the following methods:
• Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in “normal operation”
mode or automatically when the error/protection is
monitored by the stand-by processor. At the time of this
release, this layer 1 error blinking was not working as
expected.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether “error devices” are
mentioned. (see section 5.8.6 UART Logging).
• Activate the SDM. The blinking front LED will show the
entire contents of the layer 2 error buffer, this works in
“normal operation” mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
2010-Jun-29
 EN 28 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding
Important remark:
For all errors detected by MIPS which are fatal =>
rebooting of the TV set (reboot starts after LAYER 1 error
blinking), one should short the solder paths at start-up from
the power OFF state by mains interruption and not via the
power button to trigger the SDM via the hardware pins.
• Transmit the commands “MUTE” - “062500” - “OK”
with a normal RC. The complete error buffer is shown.
Take notice that it takes some seconds before the blinking
LED starts.
• Transmit the commands “MUTE” - “06250x” - “OK”
with a normal RC (where “x” is a number between 1
and 5). When x = 1 the last detected error is shown, x = 2
the second last error, etc.... Take notice that it takes some
seconds before the blinking LED starts.
5.7 Protections
5.7.1 Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
• Protections related to supplies: check of the 12V, +5V,
+3V3 and 1V2.
• Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Step by step Start-
up).
5.7.2 Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. The
audio protection circuit pulls the “supply-fault” low and the tv set
will blink LAYER 1 error = 2 or in SDM, LAYER 2 error = 19.
Be very careful to overrule this protection via SDM (not to
cause damage to the Class D audio amplifier). Check audio
part first before activating via SDM. In case one of the
speakers is not connected, the protection can also be
triggered.
Repair Tips
• It is also possible that the set has an audio DC protection
because of an interruption in one or both speakers (the DC
voltage that is still on the circuit cannot disappear through
the speakers).
Caution: (Dis)connecting the speakers during the ON
state of the TV can damage the audio amplifier.
2010-Jun-29
5.7.3 Important remark regarding the blinking LED indication
As for the blinking LED indication, the blinking LED of layer 1
error displaying can be switched “off” by pushing the power
button on the keyboard.
This condition is not valid after the set was unpowered (via
mains interruption). The blinking LED starts again and can only
be switched “off” by unplugging the mains connection.
This can be explained by the fact that the MIPS can not load
the keyboard functionality from software during the start-up and
does not recognise the keyboard commands at this time.
5.8 Fault Finding and Repair Tips
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
Information”.
5.8.1 Ambilight
Due to degeneration process of the AmbiLights, there can be a
difference in the colour and/or light output of the spare
ambilight module in comparison with the originals ones
contained in the TV set. Via ComPair, the light output can be
adjusted.
5.8.2 CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.3 Exit “Factory Mode”
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode).
Then push the “SOURCE” button on the TV’s local keyboard
for 10 seconds until the “F” disappears from the screen.
5.8.4 DC/DC Converter
Introduction
• The best way to find a failure in the DC-DC converters is to
check their starting-up sequence at “power-on via the
mains cord”, presuming that the stand-by microprocessor
is operational.
• If the input voltage of DC-DC converters is around 12.7 V
(measured on decoupling capacitors 2107 and 2123 and
the enable signals are “low” (active), then the output
voltages should have their normal values. The +12V and
+5VPOD supplies start-up first (enabled by PODMODE
signal from the stand-by microprocessor). There is a
supplementary condition for 12V to start-up: if the +5V-
POD does not start up due to a local defect, then +12V will
not be available as well. The +5V-ON supply is enabled by
the ONMODE signal (coming also from the stand-by
microprocessor). The +1V2 supply starts up when the
+12V appears, then at least 100 ms later, the +3V3 will be
activated via the ENABLE-3V3 signal from the stand-by
microprocessor. If the +12V value is less than 10 V, the last
enumerated voltages will not show up due to the under-
voltage detection circuit 7105-1 + 6101 and surrounding
components. Furthermore, if the +12V is less than 8 V,
then also the +1V2 will not be available. The +5V5-TUN
generator 7202 (present only for the analogue version of
China platforms) will start to operate as soon as the 12V
(PSU) is present.
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 29

• The consumption of controller IC 7103 is around 19 mA 5.8.5 Fan self test (only for sets with LED backlight)
(that means almost 200 mV drop voltage across resistor
3108). In case fans are present, a softest can be done by pushing the
• The current capability of DC-DC converters is quite high red coloured button on the remote control while the TV set is in
(short-circuit current is 7 to 10 A). CSM. Exit CSM and check the status of the fans in the error
• The DETECT1 signal (active “low”) is an internal protection buffer by entering SAM (062596 + info button on the RC). In
(error 18) of the DC-DC convertor and will occur if the case of failure (fully red screen) more detailed information is
output voltage of any DC-DC convertor is out of limits (10% available in the error buffer (error 41, 42, 43, 44).
of the normal value).
5.8.6 UART Logging
Fault Finding
• Symptom: +1V2 not present (even for a short while ~10
When something is wrong with the TV set (f.i.the set is
ms) rebooting) checking the UART logging using hyperterminal can
– Check 12 V availability (resistor 3108, MOS-FETs
be done to find more information. Hyperterminal is a standard
7101 and 7102), value of +12 V, and surrounding
Windows application. It can be found via Programs,
components) Accessories, Communications, Hyperterminal. Connect a
– Check the voltage on pin 9 (1.5 V),
“ComPair UART”-cable (3138 188 75051) from the Service
– Check for +1V2 output voltage short-circuit to GND that
connector in the TV set, via the ComPair interface (this is
can generate pulsed over-currents 7...10 A through coil compulsory, otherwise ICs are blown in the PC), to the
5103.
“COMx”-port of the PC. After start-up of Hyperterminal, fill in a
– Check the over-current detection circuit (2106 or 3131
name (f.i. “logging”) in the “Connection Description” box, then
interrupted). apply the following settings:
• Symptom: +1V2 present for about 100ms, +3V3 not rising.
1. COMx
– Check the ENABLE-3V3 signal (active “low”),
2. Bits per second = 115200
– Check the voltage on pin 8 (1.5 V), 3. Data bits = 8
– Check the under-voltage detection circuit (the voltage
4. Parity = none
on collector of transistor 7105-1 should be less than
5. Stop bits = 1
0.8 V), 6. Flow control = none
– Check for output voltages short-circuits to GND (+3V3)
During the start-up of the TV set, the logging will be displayed.
that can generate pulsed over currents 7...10 A
This is also the case during rebooting of the TV set (the same
through coil 5101, logging appears time after time). Also available in the logging
– Check the over-current detection circuit (2105 or 3127
is the “Display Option Code” (useful when there is no picture),
interrupted).
look for item “DisplayRawNumber” in the beginning of the
• Symptom: +1V2 OK, +3V3 present for about 100 ms. logging.
Possible cause: SUPPLY-FAULT line stays “low” even
Tip: When there is no picture available during reboot, it is
though the +3V3 and +1V2 is available - the stand-by
possible to check for “error devices” in the logging (LAYER 2
microprocessor is detecting that and switching “off” all
error). This can be very helpful to determine the failure cause
supply voltages. of the reboot. For protection state, there is no logging.
– Check the drop voltage across resistor 3108 (they
could be too high, meaning a defective controller IC or
5.8.7 Loudspeakers
MOS-FETs),
– Check if the boost voltage on pin 4 of controller IC 7103
is less than 14 V (should be 19 V), Make sure that the volume is set to minimum during
– Check if +1V2 or +3V3 are higher than their normal disconnecting the speakers in the “on” state of the TV. The
values - that can be due to defective DC feedback of audio amplifier can be damaged by disconnecting the speakers
the respective DC-DC convertor (ex. 3152, 3144). during “on” state of the set! Sometimes the set can go into
• Symptom: +1V2 and +3V3 show a high level of ripple protection, but that is not always the case.
voltage (audible noise can come from the filtering coils
5101, 5103). Possible cause: instability of the frequency 5.8.8 Tuner
and/or duty cycle of a DC-DC converter or stabiliser.
– Check the resistor 3164, capacitors 2102 and 2103, Attention: In case the tuner is replaced, always check the tuner
input and output decoupling capacitors. options!
– Check AC feedback circuits (2120, 2129, 3141, 3153,
2110, 2114 and 3135).
5.8.9 Display option code
• Symptom: +1V2, +3V3 ok, no +5V5-TUN (analogue sets
only). Possible cause: the “+5V5-TUN GENERATOR”
circuit (7202 and surroundings components) is defective: Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
check transistor 7202 (it has to have gate voltage pulses of
Performance with the incorrect display option code can lead to
about 10 V amplitude and drain voltage pulses of about 35
V amplitude) and surrounding components. A high unwanted side-effects for certain conditions.
See also Table 6-6 for the code.
consumption (more than 6 mA) from +5V5-TUN voltage
can cause also +5V5-TUN voltage to be too low or zero.
5.8.10 Upgrade HDMI EDID NVM
Note: when a pair of power MOSFETs (7101 or 7102)
becomes defective, the controller IC 7103 should be replaced To upgrade the HDMI EDID, see ComPair for further
as well. instructions.

2010-Jun-29
 EN 30 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

5.8.11 Upgrade VGA EDID NVM

To upgrade the VGA EDID NVM, pin 7 of the EDID NVM [2] has
to be short circuited to ground. See ComPair for further
instructions.

1
2
SDM
EDID

18440_201_090225.eps
090306

Figure 5-10 VGA EDID NVM

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 31

5.8.12 SSB Replacement

In st ru ct io n n o t e SSB rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,

go to SAM and save the current TV settings via “Upload to USB”

1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.

Start-up the set

Due to a possible wrong display option code in the received Service
SSB (NVM), it’s possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,

and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select

3) Plug the prepared USB stick into the TV set. Follow the the “autorun .upg” file in the displayed browser.
instructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press “Ok”.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and “Ok” to start flashing the main
TV software. Printouts like: “L: 1-100%, V: 1-100% and
P: 1-100%” should be visible now in the UART logging.

3) Wait until the message “Operation successful !” is displayed

5) Wait until the message “Operation successful !” is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the “Display Option” code, the set is going to

Standby
(= validation of code)

Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings
on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Yes

Open ComPair browser Q54x
In case of settings reloaded from USB, the set type,
Go to SAM and reload settings serial number, display 12 NC, are automatically stored
via “Download from USB” function. when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.

If not already done:

Check latest software on Service website. - Check if correct “display option” code is programmed.
Update main and Stand-by software via USB. - Verify “option codes” according to sticker inside the set.
- Default settings for “white drive” > see Service Manual.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.

Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End Q54x.E SSB Board swap – VDS

Updated 22-03-2010

H_16771_007a.eps
100402

Figure 5-11 SSB replacement flowchart [1/2]

2010-Jun-29
 EN 32 5. Q548.1E LA Service Modes, Error Codes, and Fault Finding

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An “F” is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).

- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds

- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”

The noise on the screen is replaced

with the blue mute or the “F” is disappeared!

Unplug the mains cord to verify the correct

disabling of the Factory mode.

Program display option code

via “062598 MENU”, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering “display option” code, the set is

going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-12 SSB replacement flowchart [2/2]

An in-depth clarification is given in section 6.5 Reset of

Repaired SSB and 6.6 Service SSB delivered without main
software loaded.

2010-Jun-29
 Service Modes, Error Codes, and Fault Finding Q548.1E LA 5. EN 33

5.9 Software Upgrading 5. The renamed “upg” file will be visible and selectable in the
upgrade application.
5.9.1 Introduction
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
The set software and security keys are stored in a NAND-
be due to a corrupted boot 2 sector) via the above described
Flash, which is connected to the PNX8543 via the PCI bus.
method, try activating the “back-up software upgrade
application”.
It is possible for the user to upgrade the main software via the
How to start the “back-up software upgrade application”
USB port. This allows replacement of a software image in a
manually:
stand alone set, without the need of an E-JTAG debugger. A 1. Disconnect the TV from the Mains/AC Power.
description on how to upgrade the main software can be found
2. Press the “INFO”-button on a Philips remote control or
in the DFU.
“CURSOR DOWN” button on a Philips DVD RC-6 remote
control (it is also possible to use a TV remote in “DVD”
Important: When the NAND-Flash must be replaced, a new mode). Keep the “INFO”-button (or “cursor down” button)
SSB must be ordered, due to the presence of the security keys! pressed while reconnecting the TV to the Mains/AC Power.
(copy protection keys, MAC address, ...). It is not possible 3. The software upgrade application will start.
anymore to replace the NAND-Flash with another one from a
scrap-board.
5.9.3 Stand-by Software Upgrade via USB
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software (see the DFU for instructions). In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
3. Perform the alignments as described in section Reset of
software via USB.
Repaired SSB.
4. Check in CSM if the HDMI keys are valid. Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
For the correct order number of a new SSB, always refer to the
2. Copy the Stand-by software (part of the one-zip file, e.g.
Spare Parts list, available on the Philips Spare Part web portal.
StandbySW_CFT69_84.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
5.9.2 Main Software Upgrade
4. Start the download application manually (see
section Manual Software Upgrade.
• The “UpgradeAll.upg” file is only used in the factory. 5. Select the appropriate file and press the “red” button to
• The “FlashUtils.upg” file is only used by Service centres upgrade.
that are allowed to do component level repair on the SSB.
5.9.4 Content and Usage of the One-Zip Software File
Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with
Below the content of the One-Zip file is explained, and
the TV, the main software and the default software upgrade instructions on how and when to use it.
application can be upgraded with the “AUTORUN.UPG”
(FUS part of the one-zip file: e.g. FUS _Q5431E_
1.25.5.0_commercial.zip). This can also be done by the File name Description
consumers themselves, but they will have to get their software EDID_Q5481_x.x.x.x.zip Contains the EDID content of the
from the commercial Philips website or via the Software Update different VGA NVM. See ComPair for
further instructions.
Assistant in the user menu (see DFU). The “autorun.upg” file
EJTAGDownload_Q5481_x.x.x.x.zip Only used by service centra which are
must be placed in the root of the USB stick. allowed to do Component Level
How to upgrade: Repair.
1. Copy “AUTORUN.UPG” to the root of the USB stick. FUS_Q5481_vx.x.x.x.zip Contains the “autorun.upg” which is
2. Insert USB stick in the set while the set is in ON MODE. needed to upgrade the TV main
The set will restart and the upgrading will start software and the software download
application.
automatically. As soon as the programming is finished, a
VGA_HD_EDID_TV543_x.x.x.x.zip Contains the EDID content of the
message is shown to remove the USB stick and restart the different (HD) VGA NVM. See ComPair
set. for further instructions.
processNVM_Q5481_x.x.x.x.zip Default NVM content. Must be
Manual Software Upgrade programmed via ComPair.

In case that the software upgrade application does not start Software_history_vx.x.x.x.pdf Contains a history overview of the
software.
automatically, it can also be started manually.
StandbySW_CFT73_x.x.x.x.zip Contains the Stand-by software in
How to start the software upgrade application manually: “upg” and “hex” format.
1. Disconnect the TV from the Mains/AC Power. - The “StandbySW_xxxxx_prod.upg”
2. Press the “OK” button on a Philips TV remote control or a file can be used to upgrade the Stand-
Philips DVD RC-6 remote control (it is also possible to use by software via USB.
a TV remote in “DVD” mode). Keep the “OK” button - The “StandbySW_xxxxx.hex” file can
pressed while reconnecting the TV to the Mains/AC Power. be used to upgrade the Stand-by
software via ComPair.
3. The software upgrade application will start.
- The files
“StandbySW_xxxxx_exhex.hex” and
Attention! “StandbySW_xxxxx_dev.upg” may not
In case the download application has been started manually, be used by Service technicians (only
for development purposes).
the “autorun.upg” will maybe not be recognized.
VGA_FHD_EDID_TV543_x.x.x.x.zip Contains the EDID content of the
What to do in this case: different (FHD) VGA NVM. See
1. Create a directory “UPGRADES” on the USB stick. ComPair for further instructions.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.

2010-Jun-29
 EN 34 6. Q548.1E LA Alignments

6. Alignments
Index of this chapter: • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 475.25 MHz
6.2 Hardware Alignments • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.3 Software Alignments signal strength of at least 1 mV and a frequency of 61.25
6.4 Option Settings MHz (channel 3).
6.5 Reset of Repaired SSB • LATAM models: an NTSC M TV-signal with a signal
6.7 Total Overview SAM modes strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).

6.1 General Alignment Conditions

6.3.1 Tuner AGC (RF AGC Take Over Point Adjustment)

Perform all electrical adjustments under the following

Purpose: To keep the tuner output signal constant as the input
conditions:
signal amplitude varies.
• Power supply voltage (depends on region):
No alignment is necessary, as the AGC alignment is done
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%).
automatically (standard value: “64”).
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%).
Store settings and exit SAM.
– EU: 230 VAC / 50 Hz (± 10%).
– LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%).
– US: 120 VAC / 60 Hz (± 10%). 6.3.2 White Point
• Connect the set to the mains via an isolation transformer
with low internal resistance. • Set “Active control” to “Off”.
• Allow the set to warm up for approximately 15 minutes. • Choose “TV menu”, “TV Settings” and then “Picture” and
• Measure voltages and waveforms in relation to correct set picture settings as follows:
ground (e.g. measure audio signals in relation to Picture Setting
AUDIO_GND). Dynamic backlight Off
Caution: It is not allowed to use heat sinks as ground. Dynamic Contrast Off
• Test probe: Ri > 10 MΩ, Ci < 20 pF. Colour Enhancement Off
• Use an isolated trimmer/screwdriver to perform Picture Format Un scaled
alignments. Light Sensor Off
Brightness 50
6.1.1 Alignment Sequence Colour 0
Contrast 100

• First, set the correct options:

– In SAM, select “Options”, and then “Option numbers”. • Go to the SAM and select “Alignments”-> “White point”.
– Fill in the option settings for “Group 1” and “Group 2”
according to the set sticker (see also section Option White point alignment LCD screens:
Settings). • Use a 100% white screen as input signal and set the
– Press OK on the remote control before the cursor is following values:
moved to the left. – “Colour temperature”: “Normal”.
– In submenu “Option numbers” select “Store” and press – All “White point” values to: “127”.
OK on the RC. – “Red BL offset” values to “7”.
• OR: – “Green BL offset” values to “7”.
– In main menu, select “Store” again and press OK on
the RC. In case you have a colour analyser:
– Switch the set to Stand-by. • Measure with a calibrated contactless colour analyser in
• Warming up (>15 minutes). the centre of the screen. Consequently, the measurement
needs to be done in a dark environment.
• Adjust the correct x, y coordinates (while holding one of the
6.2 Hardware Alignments White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
Not applicable. correct x, y coordinates (see Table 6-1). Tolerance: dx: ±
0.004, dy: ± 0.004.
• Repeat this step for the other colour temperatures that
6.3 Software Alignments need to be aligned.
• When finished press OK on the RC and then press STORE
Put the set in SAM mode (see chapter 5. Service Modes, Error (in the SAM root menu) to store the aligned values to the
Codes, and Fault Finding). The SAM menu will now appear on NVM.
the screen. Select ALIGNMENTS and go to one of the sub • Restore the initial picture settings after the alignments.
menus. The alignments are explained below.
The following items can be aligned: Table 6-1 White D alignment values
• Tuner AGC.
• White point. Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.278 0.289 0.314
To store the data: y 0.278 0.291 0.319
• Press OK on the RC before the cursor is moved to the
left.
• In main menu select “Store” and press OK on the RC.
• Press MENU on the RC to switch back to the main menu. If you do not have a colour analyser, you can use the default
• Switch the set to stand-by mode. values. This is the next best solution. The default values are
average values coming from production.
For the next alignments, supply the following test signals via a • Select a COLOUR TEMPERATURE (e.g. COOL,
video generator to the RF input: NORMAL, or WARM).

2010-Jun-29
 Alignments Q548.1E LA 6. EN 35

• Set the RED, GREEN and BLUE default values according
to the values in Table 6-1.
• When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
select STORE in the SAM root menu and press OK on the
RC.
• The new option setting is only active after the TV is
switched “off” / “stand-by” and “on” again with the mains
switch (the NVM is then read again).

Table 6-2 White tone default settings 32" & 42" Frame sets 6.4.2 Dealer Options
(7000 series)
For dealer options, in SAM select “Dealer options”.
White Tone 32" 42" Black level See Table 6-8.
offset
Colour Temp R G B R G B R G
6.4.3 (Service) Options
Normal 127 93 100 127 116 112 8 8
Cool 127 98 122 125 114 124 8 8
Warm 127 83 61 127 108 73 8 8
Select the sub menu's to set the initialisation codes (options) of
the model number via text menus. See Table 6-8.

Table 6-3 White tone default settings 47" & 52" Frame sets 6.4.4 Opt. No. (Option numbers)
(7000 series)
Select this sub menu to set all options at once (expressed in
White Tone 47" 52" Black level two long strings of numbers).
offset
An option number (or “option byte”) represents a number of
Colour Temp R G B R G B R G
different options. When you change these numbers directly,
Normal 127 120 105 127 127 106 8 8
you can set all options very quickly. All options are controlled
Cool 126 125 125 124 127 121 8 8
via eight option numbers.
Warm 127 110 68 127 118 70 8 8
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
Table 6-4 White tone default settings 32" & 37" Roadrunner must set both option number lines. You can find the correct
sets (8000 series) option numbers on a sticker inside the TV set and in Table 6-6.
Example: The options sticker gives the following option
White Tone 32" 37" Black level numbers:
offset • 08192 00133 01387 45160
Colour Temp R G B R G B R G • 12232 04256 00164 00000
Normal 127 93 97 125 127 102 8 8 The first line (group 1) indicates hardware options 1 to 4, the
Cool 127 100 120 122 127 117 8 8 second line (group 2) indicate software options 5 to 8.
Warm 127 83 59 127 118 62 8 8 Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
Table 6-5 White tone default settings 42" & 47" Roadrunner
values of each Option Byte (OB) will give the option number.
sets (8000 series) See Table 6-6 for the options.

White Tone 42" 47" Black level

offset Diversity
Colour Temp R G B R G B R G Not all sets with the same Commercial Type Number (CTN)
Normal 127 103 99 127 119 107 8 8 necessarily have the same option code!
Cool 127 109 118 127 124 125 8 8 Use of Alternative BOM An alternative BOM number usually
Warm 127 94 61 127 111 68 8 8 indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code. For
the power supply there is no difference.
6.3.3 LCD Panel Flicker Alignment Refer to Chapter 3. Precautions, Notes, and Abbreviation List.

Note: This is only necessary for Forward Integration models 6.4.5 Option Code Overview
(sets that have the LCD Timing Controller (TCON) located on
the SSB) - not applicable to sets in this chassis.
Table 6-6 Option and display code overview

See ComPair for further instructions.
6.4 Option Settings
6.4.1 Introduction
The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX5120 ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.
Notes:
• After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
CTN Options Group 1 Options Group 2 Disp.
(Alt. BOM#) code
32PFL7404H/xx 08193 00649 01391 45288 10165 28832 00162 00000 181
32PFL7674H/xx 08209 00656 02031 45288 10165 28832 00160 00000 181
32PFL7684H/xx 08209 00656 02031 45288 10165 28832 00160 00000 181
32PFL7694H/xx 08193 00650 01391 45288 10165 28832 00162 00000 181
32PFL7864H/xx 08193 00650 01391 45288 10165 28832 00162 00000 181
32PFL8404H/xx 08209 00656 02031 45288 26549 28834 00162 00000 181
37PFL8404H/xx 08209 00656 02031 45288 26549 28834 00170 00000 161
37PFL8684H/xx 08209 00658 02031 45288 26529 28834 00168 00000 161
37PFL8694H/xx 08209 00658 02031 45288 26529 28834 00168 00000 161
42PFL7404H/xx 08193 00651 01391 45288 10167 28832 00178 00000 183
42PFL7674H/xx 08193 00652 01391 45288 10167 28832 00176 00000 183
42PFL7864H/xx 08193 00652 01391 45288 10167 28832 00177 00000 183
42PFL8404H/xx 08209 00657 02031 45288 26551 28834 00178 00000 183
42PFL8654H/xx 08209 00659 02031 45288 26551 28834 00176 00000 183
42PFL8684H/xx 08209 00659 02031 45288 26551 28834 00176 00000 183
42PFL8694H/xx 08209 00659 02031 45288 26551 28834 00176 00000 183
47PFL7404H/xx 08193 00651 01391 45288 10170 28832 00162 00000 186
47PFL7864H/xx 08193 00652 01391 45288 10170 28832 00161 00000 186

2010-Jun-29
 EN 36 6. Q548.1E LA Alignments

CTN Options Group 1 Options Group 2 Disp. 6.6 Service SSB delivered without main software
(Alt. BOM#) code
loaded
47PFL8404H/xx 08209 00657 02031 45288 26554 28834 00162 00000 186
52PFL7404H/xx 08193 00651 01391 45288 10192 28832 00186 00000 208
Due to a changed manufacturing process, new Service SSB’s
Important: after having edited the option numbers as can be delivered to the warehouse without main TV
described above, you must press OK on the remote control software loaded. Below you find the steps to follow when such
before the cursor is moved to the left! an SSB is received.

BBE & WMA Functionality 6.6.1 When a picture is available

Some sets have the possibility to swith “on” the “BBE” and/or
“WMA” functionality for an enhanced audio experience. This 1. Mount the Service SSB into the TV set. After start-up,
has to be executed via ComPair via “option 9”. normally the download application will appear on the
screen.
Table 6-7 “Option 9” overview 2. Download the latest main software (FUS) from the
www.p4c.philips.com website.
CTN Option 9
3. Create a folder "upgrades" in the root of a USB stick (size
(Alt. BOM#) > 50 MB) and save the "autorun.upg" file in this "upgrades"
32PFL7674H/xx 00010 folder. Note: it is possible to rename this file, e.g.
42PFL7674H/xx 00010 "Q549_SW_version.upg", this in case there are more than
32PFL7684H/xx 00010 one "autorun.upg" files on your USB stick
32PFL7694H/xx 00010 4. Plug the prepared USB stick into the TV set, and select the
32PFL7864H/xx 00010 "autorun" file in the displayed browser on the screen
42PFL7864H/xx 00010 5. Now the main TV software will be loaded automatically,
47PFL7864H/xx 00010 supported by a progress bar
42PFL8654H/xx 00014 6. Set the correct "display code" via "062598-HOME-xxx",
37PFL8684H/xx 00014 where "xxx" is the 3-digit display panel code (see sticker on
42PFL8684H/xx 00014 the side/bottom of the cabinet).
37PFL8694H/xx 00014
42PFL8694H/xx 00014 6.6.2 When no picture is available

Due to a possible wrong display option code in the received

6.5 Reset of Repaired SSB
A very important issue towards a repaired SSB from a service
repair shop implies the reset of the NVM on the SSB.
A repaired SSB in service should get the service Set type
“00PF0000000000” and Production code “00000000000000”.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool.
In case of a display replacement, reset the “Operation hours” to
“0”, or to the operation hours of the replacement display.
6.5.1 SSB identification
Whenever ordering a new SSB, it should ne noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a “Service” SSB is the same as the ordering
number of an initial “factory” SSB.
Service SSB (NVM), no picture can be available at start-up and
thus no download application will be visible. Here you can
proceed and finalize step by step to load the main TV software
via the UART logging on the PC (for visual feedback).
1. Start-up the TV set, equipped with the Service SSB, and
enable the UART logging on the PC (see for settings 5.8
Fault Finding and Repair Tips 5.8.6 UART Logging)
2. The TV set will start-up automatically in the download
application if main TV software is not loaded
3. Plug the prepared USB stick into the TV set, press cursor
"Right" to enter the list, and navigate to the "autorun" file in
the UART logging printout via the cursor keys on the
remote control. When the correct file is selected, press
"OK"
4. Press cursor "Down" and "OK" to start the flashing of the
main TV software. Printouts like: "L: 1-100% , V: 1-100%
and P: 1-100%" should be visible now in the UART logging
5. Wait until the message "Operation successful!” is
displayed and remove all inserted media. Restart the TV
set
6. Set the correct "display code" via "062598-HOME-xxx",
where "xxx" is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).

6.6.3 Use of repaired SSBs instead of new

Repaired SSBs on stock will obviously already contain main TV

software. This implies that only a main software upgrade is
required if you use a “repaired” SSB for board swap instead of
a “new” SSB.

18310_221_090318.eps
090319

Figure 6-1 SSB identification

2010-Jun-29
 Alignments Q548.1E LA 6. EN 37

6.7 Total Overview SAM modes

Table 6-8 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Information A. SW version e.g. “Q5431_0.26.10.0” Display TV & Stand-by SW version and CTN serial
number.
B. Stand-by processor version e.g. “STDBY_84.69.0.0”
C. Production code e.g. “See type plate”
Operation hours Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Error Displayed the most recent error.
Reset error buffer Clears all content in the error buffer.
Alignment Tuner AGC RF-AGC Take over point adjustment (AGC default
value is 64)
White point Colour temperature Normal 3 difference modes of colour temperature can be se-
lected
Warn
Cool
White point red LCD White Point Alignment. For values,
see Table 6-1.
White point green
White point blue
Red black level offset
Green black level offset
Dealer options Picture mute Off/On Select Picture mute On/Off. Picture is muted / not
muted in case no input signal is detected at input con-
nectors.
Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
E-sticker Off/On Select E-sticker On/Off (USP’s on-screen)
Auto store mode None Autostore mode disabled (not in installation menu)
PDC/VPS Autostore mode via ATS (PDC/VPS) enabled
TXT page Autostore mode via ACI enabled
PDC/VPS/TXT Autostore mode via ACI or ATS enabled
Options Digital broadcast DVB Off/On Select DVB On/Off
DVB - T installation Off/On or Country dependent Select DVB T installation On/Off or by country
DVB - T light Off/On Select DVB T light On/Off
DVB - C Off/On Select DVB C On/Off
DVB - C installation Off/On or Country dependent Select DVB C installation On/Off or by country
Over the air download Off/On or Country dependent Select Over the air download On/Off or by country
8 days EPG Off/On Select 8 day EPG On/Off
Digital features USB Off/On Select USB On/Off
Ethernet Off/On Select Ethernet On/Off
Wi-Fi Off/On Select Wi-Fi On/Off
DLNA Off/On Select DLNA On/Off
On-line service Off On-line service is Off
PTP (Picture Transfer Protocol) Off/On Select PTP On/Off
Update assistant Off/On Select Update assistant On/Off
Internet software update Off Internet software update is Off
Display Screen 201 / LCD LGD WUE SBA1 37" Displayed the panel code & type model.
LightGuide Off/On Select LightGuide On/Off
Display fans Not present/Present Select Display fans Present/Not present.
Temperature sensor No sensor N.A
Temperature LUT 0 N.A
E-box & monitor Off/On Select E-box & monitor On/Off
Video reproduction Picture processing None/PNX5120 Select Picture processing None/PNX5120 (Q543.xE
chassis).
MOP local contrast Off/On Select MOP local contrast On/Off
Light sensor Off/On Select Light sensor On/Off
Light sensor type 0/1/2/3 Select Light sensor type form 0 to 3 (for difference
styling).
Pixel Plus type Pixel Plus HD Select type of picture improvement.
Perfect Pixel HD
Pixel Precise HD
Pixel Plus HD (used in Q543.xE)
Pixel Precise HD (used in Q548.1E)
Ambilight None, Select type of Ambilight modules use.
2 sided 2/2 For 8400 series only
2 sided 4/4
3 sided 2/3/2
3 sided 4/3/4
3 sided 4/5/4
4 sided 4/3/4/3
Ambilight technology LED/Future use Ambilight technology LED is in use.
MOP ambilight Off/On Select MOP ambilight On/Off

2010-Jun-29
 EN 38 6. Q548.1E LA Alignments

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Audio reproduction Acoustic system Cabinet design used for setting dynamic audio pa-
rameters.
Source selection EXT1/AV1 type SCART CBVS RGB LR Select input source when connected with external
equipment.
CVBS Y/C YPbPr LR
CVBS Y/C YPbPr HV LR
(CVBS) YPbPr LR
EXT2/AV2 type SCART CBVS RGB LR Select input source when connected with external
equipment.
CVBS Y/C LR
(CVBS) YPbPr LR
CVBS Y/C LR
EXT3/AV3 type None Select input source when connected with external
equipment.
CVBS
CVBS LR
YPbPr
YPbPr LR
YPbPr HV LR
VGA Off/On Select VGA On/Off
SIDE I/O Off/On Select SIDE I/O On/Off
HDMI 1 Off/On Select HDMI 1 On/Off
HDMI 2 Off/On Select HDMI 2 On/Off
HDMI 3 Off/On Select HDMI 3 On/Off
HDMI 4 Off/On Select HDMI 4 On/Off
HDMI side Off/On Select HDMI side On/Off
HDMI CEC Off/On Select HDMI CEC On/Off
HDMI CEC RC pass through Off/On Select HDMI CEC RC pass through On/Off
HDMI CEC Pixel Plus link Off/On Select Pixel Plus link On/Off
Miscellaneous Region Europe/AP-PAL-MULTI/Australia Select Region/country.
Tuner type HD1816-MK1/TD1716-MK4/ Select type of Tuner used.
TD1716-MK3/HD1816-MK2
System RC support Off/On Select System RC support On/Off.
Embedded user manual Off/On Select Embedded user manual On/Off.
Start-up screen Off/On Select Start-up screen On/Off.
Wallpaper Off/On Select Wallpaper On/Off.
Hotel mode Off Hotel mode is Off.
Option number Group 1 e.g. “08192.02181.01387.45160” The first line (group 1) indicates hardware options 1
to 4.
Group 2 e.g. “10185.12448.00164.00000” The second line (group 2) indicates software options
5 to 8.
Store Store after changing.
Initialise NVM N.A
Store Select Store in the SAM root menu after making any
changes.
Software maintenance Software events Display Display information is for development purposes.
Clear
Test reboot
Test reboot is to restart the TV.
Hardware events Display Display information is for development purposes.
Clear
Operation hours display 0003 In case the display must be swapped for repair, you
can reset the “Display operation hours” to “0”. So, this
one does keeps up the lifetime of the display itself
(mainly to compensate the degeneration behaviour).
Test setting Digital information QAM modulation: 64-QAM Display information is for development purposes.
Symbol rate: 23:29
Original network ID: 12817
Network ID:12817
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: -1
Install start frequency 000 Install start frequency from 0 MHz
Install end frequency 999 Install end frequency as 999 MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before instal-
lation.
Digital + Analogue

2010-Jun-29
 Alignments Q548.1E LA 6. EN 39

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Development file ver- Development 1 file version Display parameters DISPT 4.0.8.11 Display information is for development purposes.
sions Acoustics parameters ACSTS 3.0.6.1
PQF - Fixed settings 1
“4.54.34.32.34”
PQS - Profile set 1 “4.57.34.32.34”
PQU - User styles 1 “4.56.34.32.34”
Development 2 file version 12NC one zip software Display information is for development purposes.
Initial main software
NVM version Q5431_0.4.3.0
Flash units SW Q5431_0.16.48.24
Upload to USB Channel list To upload several settings from the TV to an USB
stick
Personal settings
Option codes
Display-related alignment
History list
Download from USB Channel list To download several settings from the USB stick to
the TV.
Personal settings
Option codes
Display-related alignment

2010-Jun-29
 EN 40 7. Q548.1E LA Circuit Descriptions

7. Circuit Descriptions
Index of this chapter: Main difference with the previous chassis is the addition of the
7.1 Introduction PNX5120 Video Back-End Processor.
7.2 Power Supply
7.3 DC-DC Converter Roadrunner sets (8000 series) are equipped with AmbiLight.
7.4 Front-End
7.5 HDMI
7.1.1 Implementation
7.6 Video and Audio Processing - PNX8543
7.7 Common Interface CI+
Key components of this chassis are:
• PNX8543 Digital Colour Decoder
Notes:
• HD1816AF Hybrid Tuner
• Only new circuits (circuits that are not published recently)
• DRX3926K Demodulator
are described. • TDA9996 HDMI Switch
• Figures can deviate slightly from the actual situation, due
• TPA3123D2PWP Class D Power Amplifier
to different set executions.
• PNX5120 Video Back-End Processor.
• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter 9.
7.1.2 TV543 Architecture Overview
Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification. • For details about the chassis block diagrams refer to
chapter 9. Block Diagrams. An overview of the TV543
architecture can be found in Figure 7-1.
7.1 Introduction

The Q548.1E LA chassis (platform name TV543/82) is a

derivative from the Q543.1E LA chassis.

Optional for
Q548 chassis

18540_200_090327.eps
091112

Figure 7-1 Architecture of TV543/82 platform

2010-Jun-29
 Circuit Descriptions Q548.1E LA 7. EN 41

7.1.3 SSB Cell Layout

18540_201_090327.eps
091112

Figure 7-2 SSB layout cells (top view)

2010-Jun-29
 EN 42 7. Q548.1E LA Circuit Descriptions

7.2 Power Supply

Min 20 msec
All power supplies described below are a black box for Service. Max 1.0sec Max 0.5 sec Max 5.0 sec

When defective, a new board must be ordered and the

defective one must be returned, unless the main fuse of the Vin AC
board is broken. Always replace a defective fuse with one with
the correct specifications! This part is available in the regular STANDBY
market.
Consult the Service Spare Parts website for the order codes of +3V3-STANDBY

the boards.
+12V, +Vsnd, +24V

7.2.1 Specifications
18440_209_090226.eps
090227
Most sets in the TV543 platform use the Integrated Power
Board (IPB) - incl. inverter. The 52" sets in this chassis have a
conventional PSU - with separate inverter. Figure 7-4 PSU Timing Diagram

In this Service Manual, no detailed information is available for 7.2.5 Power Supply Protection
design protection reasons.
Power supply protection is implemented via the stand-by
7.2.2 Diversity controller of the PNX8543 via the following signals:
• POWER-OK: signal from PSU to indicate if the supply
Below find an overview of the different PSUs that are used: output from the IPB is normal
• DETECT1: signal to indicate if the +5V, +3V3 and +1V2
voltages on the chassis are present
Table 7-1 Supply diversity
• DETECT2: signal to indicate if the +12V voltage on the
chassis is present.
Supplier PSU Model Input Voltage Range
LGIT PLHL-T826B 32" High Mains (198 to 265 VAC)
Delta DPS-298CP A 37" High Mains (198 to 265 VAC) 7.3 DC-DC Converter
Delta DPS-298CP-4 A 42" High Mains (198 to 265 VAC)
Delta DPS-298CP-2 A 47" High Mains (198 to 265 VAC) Input power is obtained from the IPB module via the following
Delta DPS-411AP-3A 52" High Mains (198 to 265 VAC) voltages:
• +3V3-STANDBY (stand-by-mode only)
7.2.3 Application • +12V (on-mode)
• +Vsnd (audio power) (on-mode)
• +24V (bolt-on power) (on-mode).
An application diagram can be found below:
Control is achieved by the PNX8543 controller via the
STANDBY signal.

Inverter
Audio power is specifically for audio supply usage only and
To Lamps does not go through any DC conversion.

+12V
AC Input
RELAY
Vo=400V Below find a block diagram of the on-board DC-DC converters.
PFC Audio Supply (+12V)

+24V
NCP5422 + 2x
STANDBY Si4936 +1V2-PNX8543
Flyback (HIIGH=OFF, LOW=ON) (Sync Dual
+12V Controller +3V3
+ Dual FETs)

+3V3_STANDBY LD1117 +1V8-PNX8543

(Linear Regulator)

LD1117
(Linear Regulator) +1V8-PNX5100
Non- Isolated/Hot Isolated/Cold

18440_208_090226.eps ENABLE-3V3
090327
ST1S10
(Sync Power IC) +5V_+5V5-TUN
Figure 7-3 Application Integrated Power Board
ST1S10 +1V2-PNX5100
(Sync Power IC)
7.2.4 Power Supply Timing
LD3985M
+3V3-STANDBY +1V2-STANDBY
(Linear Regulator)
The STANDBY signal controls the on-mode voltages +12V,
+Vsnd and +24V. During chassis cold start from AC mains, 18440_210_090227.eps
+12V can be expected to be stable within 1.0 seconds, while for 090227
a warm start, i.e. wake up from stand-by power state, this
timing becomes 0.5 seconds maximum. During AC switch off, Figure 7-5 DC-DC converters
stand-by power +3V3-STANDBY decay is at least 20 ms but
not more than 5.0 seconds compared to +12V. Refer to
Figure 7-4:

2010-Jun-29
 Circuit Descriptions Q548.1E LA 7. EN 43

7.4 Front-End
P la tfo rm w ith e m b e d d e d E D ID
The Front-End consist of the following key components:

• Tuner HD1816AF
• IF demodulator DRX3926K
E D ID: 2 5 3 B I 2C CPU
• AGC amplifier UPC3221GV TDA9996
• SAW filter 36M125. 3B 3B 3B 3B

2 5 3 co m m o n B yte s
Below find a block diagram of the front-end application. + 1B su b a d d re s o f
S o u rce P h ysica l A d d re ss
+3B fo r inp u t A
I2C-SSB
+3B fo r inp u t B
NXP Hybrid SAW IF Amplifier DRX3926K
CVBS
PNX8543
4 × HDMI +3B fo r inp u t C
Filter 2nd SIF
Tuner
TS inputs +3B fo r inp u t D

IF-AGC 18440_214_090227.eps
I2C-TUNER 090720

18440_211_090227.eps
090227 Figure 7-8 EDID control (embedded EDID)

Some delta’s w.r.t. TDA9996 compared to earlier chassis/

Figure 7-6 Front-End block diagram platforms are:
• +5V detection mechanism
The DRX3926K is a multi-standard demodulator supporting • stable clock detection mechanism
DVB-C, DVB-T and analogue standards. The demodulated • integrated EDID
digital stream is fed into the parallel transport stream data ports • RT control
of the PNX8543. The demodulated analogue signal in the form • HPD control
of CVBS is connected to the analogue video CVBS/Y input • TMDS output control
channel, while the SIF is connected via the SSIF2 positive input • CEC control
port. • new hot-plug control for PNX8543 for 5th HDMI input
• new EDID structure: EDID stored in TDA9996, therefore
7.5 HDMI there are no EDID pins on the SSB. Only in the event of a
5th HDMI input, an additional EEPROM is foreseen, as
was implemented in previous platforms.
In this platform, the TDA9996 HDMI multiplexer is
implemented. The EDID contents are no longer stored in a
separate EEPROM, but directly in the multiplexer. Each input Some delta’s with respect to PNX8543 compared to earlier
has its own physical sub address: the first 253 bytes are chassis/platforms are:
common, where the last 3 bytes define the specific input. The • 2 HDMI inputs (A & B)
EDID contents are, at +5V power-up, downloaded to RAM. The • HDMI deep colour RGB/YCbCr 4:4:1 10/12 bit detection.
following figures show the HDMI input configuration and EDID
control. After replacement of the TDA9996 HDMI multiplexer, the
default I2C address should be reprogrammed from C0 to CE,
and the HDMI EDIDs should be reprogrammed as well. Both
actions should be executed via ComPair.

PNX8543

A B

H D M IB-R X
1P 05

DRX
H D M IA-R X D
Out

H D M I Side
C

TDA9996 (optional)

CRX
A

AR X
E d id B

BR X

HDMI 4
1P06

1P04

1P03

1P02

(optional)

HDMI 3
HDMI 2 HDMI 1
1M 96 (optional)

18440_213_090227.eps
090720

Figure 7-7 HDMI input configuration

2010-Jun-29
 EN 44 7. Q548.1E LA Circuit Descriptions

7.6 Video and Audio Processing - PNX8543
The PNX8543 is the main audio and video processor (or
System-on-Chip) for this platform. It is a member of the
PNX85xx SoC family (described in earlier chassis) with the
addition of the MPEG4 functionality; the separate STi710x
MPEG4 decoder is no longer implemented in this platform.
The PNX8543 handles the digital and analogue audio- and
video decoding and processing. The processor is a MIPS32
general purpose CPU and a 8051-based TV controller for
power management and user event handling.
• For a functional diagram of the PNX8543, refer
to Figure 7-9.

PNX8543x
MEMORY
CONTROLLER

TS in from
channel decoder MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single or dual
OUTPUT channel)
DV-ITU-656 DV INPUT

AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT

Low-IF DIGITAL IF MPEG/H.264

VIDEO SCALER,
DECODER DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
SSIF, LR
AND DECODE AUDIO DACS analog audio

AUDIO DSP
Dual SPDIF I2 S
AUDIO IN AUDIO OUT
I2S SPDIF
300 MHz
AV-DSP
HDMI
Dual HDMI
RECEIVER DRAWING
ENGINE

SYSTEM 300 MHz

CONTROLLER MIPS32 4KEc
(8051) CPU DMA BLOCK

I2C PWM GPIO IR ADC SPI UART I2C GPIO Flash USB 2.0 CA PCI 2.2
x 22 x 10

18440_202_090226.eps
090819

Figure 7-9 PNX8543 functional diagram

2010-Jun-29
 Circuit Descriptions Q548.1E LA 7. EN 45

7.6.1 Video Subsystem

Refer to Figure 7-10 for the main video interfaces for the
PNX8543 and the video signal flow between blocks and
memory.

DDR2-SDRAM

PNX8543x
MCU-DDR

VCP/PC 2D_DE
VCP_
UIP
LOW IF VCP_RX GFX1
CVBS VCP_ LCD panel
WIFD GFX2
RGB AFE CPIPE_ LVDS_BUF FPD-LVDS1
(ADC) PIP L2QTV LVDS_TX
YPbPr LCD panel
PC_
VGA PC_RX FPD-LVDS2
UIP
DMA BUS

main

HDMI
MBVP_
L2QTV
Dual HDMI HDMI_ HDMI_UIP
RX
MBVP_
L2VO1

monitor
CVBS/Y DAC
CPIPE_ CVBS1/Y
MBVP_ DENC
L2VO C
DV (including L2VO2
VIP
ITU-656) (ITU-656)

monitor
MUX DAC CVBS2/C
A
TS
TSI
PCMCIA
CAI MSVD
TSDO
TSDI VMSP
CMD

18440_203_090226.eps
090819

Figure 7-10 PNX8543 video flow diagram

The Video Subsystem consist of the following blocks:

• Analogue Front-End (AFE) block
• Video and PC Capture (VPC/PC) pipe
• HDMI Receiver interface
• Memory-Based Video Processor MBVP)
• Video Composition Pipe (CPIPE)
• Memory Based Video Processor (MBVP) VO-1
• Memory Based Video Processor (MBVP) VO-2
• Video Composition Pipe (CPIPE)
• Dual Flat Panel Display-LVDS (FPD-LVDS)
• Digital Encoder (DENC)
• Digital Video VIP
• 2D graphics block.

2010-Jun-29
 EN 46 7. Q548.1E LA Circuit Descriptions

7.6.2 Audio Subsystem

Refer to Figure 7-11 for the main audio interfaces for the
PNX8543 and the audio signal flow between blocks and
memory.

DDR2-SDRAM

PNX8543x
MCU

TM2270
TS-IN CAI VMSP (MPEG, AC-3, MP3
DECODER)
XB4
XB1

SPDIF-IN1 SPDIF-IN SPDIF-OUT SPDIF-Out

SPDIF-IN2
DMA BUS

fast SPDIF
I2S-IN-SD1
I2S-IN-SD2
XB2
I2S-IN-SD3
I2S-IN-SD4
AI AO
I2S-IN-WS
I2S-IN-SCK
I2S-IN-OSC
4 × I2S

SPDIF
4 × I2S
HDMI HDMI_RX XB3
4
I2S
4 × I2S

I2S-OUT-SD1
4 I2S-OUT-SD2
IF ADC I2S-OUT-SD3
SSIF ASDEC APP - AUDIO DSP I2S-OUT-SD4
DigIF (DEMODULATION (POST PROCESSING)
from AND DECODING)
SPDIF I2S-OUT-WS
XB4 I2S-OUT-SCK
I2S-OUT-OSC

L, R ADC
2 Main L, R
DAC
2
HP L, R
DAC
2
SCART2 L, R
DAC

2
SCART1 L, R
DAC

18440_204_090226.eps
090819

Figure 7-11 PNX8543 audio flow diagram

The Audio Subsystem consist of the following blocks:

• Analogue Audio Front End (AAFE) used to capture
Baseband Audio Inputs and to sample Secondary Sound
IF (SSIF) directly or via Low-IF input
• HDMI Receiver interface block
• SPDIF input block
• Audio Input (AI) block
• Audio Output (AO) block
• Demodulation & Decoding (ASDEC) DSP for decoding all
analogue terrestrial TV sound standards
• Audio Post-Processing (APP) block
• Digital Audio decoder.

2010-Jun-29
 Circuit Descriptions Q548.1E LA 7. EN 47

7.6.3 Connectivity and Compute Subsystem

Refer to Figure 7-12 for the connectivity and compute

subsystem.

DDR2-SDRAM

PNX8543x

MCU_DDR

I2C-1 IIC4_DMA

I2C-2 IIC2_DMA MIPS

4KEc
EJTAG
DCS-NETWORK

I2C-3 IIC3_DMA
AVDSP
DMA BUS

UART-1 UART1
PCI_XIO

PCI/XIO
UART-2 UART2
CAI
CI/CA

USB USB2.0
I2C-MC
SYSTEM UART-3
CONTROLLER
JTAG_MMIO 80C51 PWMs
EJTAG
GPIOs

18440_205_090226.eps
090819

Figure 7-12 PNX8543 connectivity and compute subsystem

The Connectivity Subsystem consists of: 7.6.4 Service Notice - FLASH RAM / PNX8543 exchange
• PCI/XIO interface
• USB2.0 interface The FLASH RAM (item 7M00) and/or PNX8543 (item 7600)
• Three 2-wire UARTs can only be exchanged by an authorised central workshop with
• Four Master/Slave I2C interfaces dedicated programming tools. Due to the presence of (CI+)
• Common Interface/Conditional Access Interface. keys in the components, unauthorised exchange of these
components will always result in a defective board.
The Computing Subsystem consists of:
• 32-bit MIPS RISC core
• Enhanced JTAG (EJTAG) block inside the MIPS 7.7 Common Interface CI+
• JTAG_MMIO blocks
• TV controller Together with this platform, an extension to the Common
• Audio/Video DSP (AV_DSP) Interface (CI) Conditional Access system is added, called CI+.
• Memory Control Unit (MCU).
CI+ or Common Interface Plus is a specification that extends
the Common Interface (DVB-CI) as described in the digital
broadcasting standard DVB.

2010-Jun-29
 EN 48 7. Q548.1E LA Circuit Descriptions

The weakness of the conventional CI module used in a

Conditional Access system was the absence of a Copy
Protection mechanism, as decrypted content could be sent channel TS -IN P U T D E S /AE S d eco d er MMatrix
atrix
tuner d em u x
d escram b ler
decoder
over the PCMCIA interface unscrambled. With the CI+
extension, a form of copy protection is established between the M H E G CI+

Conditional Access Module (CAM) and the Integrated Digital P N X 8543

Television (IDTV). The security mechanisms in CI+ are T ransport stream C om m and

C A -C T R L
C A -M D I

C A -M D O

P C I/X IO
derived/copied from POD (with the exception of Out Of Band interface interface
(OOB) used in US CA systems). For more information about

MHEG MMI
a p p lic a tio n
s c ra m b le r
C A c lie n t

D E S /AE S
conventional CA systems using a CI module, refer to the Tran sp o rt S tream s

BJ3.0E L/PA or BL2.xU Service Manual. C A-C o n tro l

CAM P ro p rietary C A
scram b ling

The CI+ standard is downwards compatible with the existing CI (S C ) C I + S tan d ard ised C C S
scram b ling
standard.
18440_221_090227.eps
090819

The following figure shows the implementation of the CI+

Conditional Access system in the TV543 platform. Figure 7-13 CI+ Conditional Access implementation

7.8 Ambi Light

The Ambi Light architecture in this platform has been entirely The use of the DC/DC board is optional. In case no DC/DC
renewed. The characteristics are: board is implemented, the ARM processor is located on one of
• Additional DC/DC board generating 12/16/24 V (optional) the AL boards.
• ARM processor (on DC/DC panel or AL board)
• Low-power LEDs Refer to Figure 7-14 for the Ambi Light architecture.
• SPI interface from ARM to LED drivers
• I2C upgradeable via USB
• Each AL module has a temperature sensor.

18310_203_090317.eps
090918

Figure 7-14 Interface between Ambi Light and SSB

7.8.1 ARM controller

Refer to Figure 7-15 below for signal interfacing to and from the
SD A SPI C LO C K
ARM controller. The ARM controller is located on the DC/DC Sda1 Sck
SC L
board (item no. 7302) or AL panel (item no. 7102). S c l1
P0.7
SPI LATC H
SEL1 SPI LATC H 2
tbd (only on dc/dc for aurea)
P0.8
SEL2
tbd
SPI D ATA O U T
M OSI

PW M C LO C K
M A T0 .0

AR M M ISO
SPI D ATA R ETU R N

BLAN K
M A T1 .0

PR O G
tbd
Tx D
Tx d 0 C S EEPR O M
tbd
RxD
R x d0 TEM P
P0.10

18310_204_090318.eps
090318

Figure 7-15 ARM controller interface

2010-Jun-29
 Circuit Descriptions Q548.1E LA 7. EN 49

Data transfer between ARM processor and LED drivers is
executed by a Serial Peripheral Interface (SPI) bus interface.
The SPI bus is a synchronous serial data link standard that
operates in full duplex mode.
For debugging purposes, the working principle is given below:
• At startup the controller will read-out matrix data from the
EEPROM devices (via SPI DATA RETURN)
• Before operation, the driver current is set via SPI, with
driver in DC mode
• During normal operation the controller receives RGB-,
configuration-, operation mode- and topology data via I2C
• The controller converts the I2C RGB data via the matrixes
to SPI LED data
• Via data return the controller receives error data (if
applicable).
Also PWM clock and BLANK signals are generated by the
controller. The controller can be reprogrammed via I2C (via
USB). The controller can receive matrix values via I2C, which
will be stored in the EEPROM of each AL module via the SPI
bus. The temperature sensor in each AL module controls the
TEMP line; in case of a too high temperature the controller will
reduce the overall brightness.
7.8.2 LED driver communication (via SPI bus)
Refer to Figure 7-16 below for signal interfacing between the
ARM controller and the LED drivers on the AL boards, and the
LED drivers and the EEPROMs on the AL boards.

A m b ilig h t m o d u le 1 Am b ilig h t m o d u le 2 A m b ilig h t m o d u le N

o ut16

o ut16

o ut16
S o ut S in S o ut S in S o ut
LED LED LED
D R IV E R D R IV E R D R IV E R
1 2 N
S P I d ata in

SPI d ata return

SPI c lo c k (SC LK)

SPI latc h (XLAT )
PR O G (VPR G )
ARM BLAN K
PW M C LO C K ( G SC LK)

18310_205_090318.eps
090318

Figure 7-16 SPI communication between ARM controller and LED drivers

The ARM controller communicates with the LED drivers (on

each AL module) via an SPI bus. For debugging purposes, the
working principle is given below: Am bilight m odule 1 Am bilight m odule 2 Am bilight m odule N
Vcc Vcc Vcc
• Data from the ARM controller is linked through the drivers,
which are connected in cascade TEMP
Pull-up
TEMP
Pull-up
TEMP
Pull-up

• SPI CLK, SPI LATCH, PROG, BLANK and PWM CLOCK SENSOR SENSOR SENSOR
are going directly from the controller to each driver
• SPI DATA RETURN is linked from the last driver to the
controller: controller decides which driver returns data.

7.8.3 Temperature Control ARM

Refer to Figure 7-17 for signal interfacing between the ARM

controller and the temperature sensor on the AL boards. 18310_206_090318.eps
090318

Figure 7-17 Communication between ARM controller and

temperature sensor

Each AL board is equipped with a temperature sensor. If one of

the sensors detects a temperature over the threshold, the
TEMP line is pulled LOW which results in brightness reduction.

2010-Jun-29
 EN 50 8. Q548.1E LA IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).

8.1 Diagram SSB: DC/DC +3V3 +1V2 B01A, NCP5422AD (IC 7103)

Block Diagram VCC ROSC

BIAS CURRENT
+ SOURCE
GEN RAMP1 RAMP2
−
+ VCC
8.6 V BST
−
7.8 V
IS+1
CLK1
+ BST
OSC GATE(H)1
IS−1
− + − CLK2 S
Reset non−overlap
IS+2 70 mV Dominant VCC
PWM FAULT GATE(L)1
+ Comparator 1 R
IS−2
− + − FAULT

70 mV S Q FAULT
Set RAMP1
Dominant
− 0.425 V BST
R GATE(H)2
+ − S
+ + non−overlap
− 0.25 V Reset
FAULT Dominant VCC
PWM GATE(L)2
Comparator 2 R
RAMP2 FAULT
E/A OFF
GND
+ E/A OFF
− 0.425 V 1.2 mA FAULT
5.0 A + E/A1 −
1.0 V −
− +
+

E/A2
1.0 V

VFB1 COMP1 VFB2 COMP2

Pin Configuration

SO−16
1 16
GATE(H)1 GATE(H)2
GATE(L)1 GATE(L)2
NCP5422A

GND VCC
AWLYWW

BST ROSC
IS+1 IS+2
IS−1 IS−2
VFB1 VFB2
COMP1 COMP2

A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
F_15400_129.eps
240505

Figure 8-1 Internal block diagram and pin configuration

2010-Jun-29
 IC Data Sheets Q548.1E LA 8. EN 51

8.2 Diagram SSB: DC/DC +3V3 +1V2 Standby B01B, ST1S10PH (IC 7202/7222)

Block diagram

Pinning information

DFN8 (4 × 4) PowerSO-8

I_18010_083.eps
100402

Figure 8-2 Internal block diagram and pin configuration

2010-Jun-29
 EN 52 8. Q548.1E LA IC Data Sheets

8.3 Diagram SSB: DC/DC +3V3 +1V2 Standby B01B, LD3985M (IC 7201)

Block Diagram

Pin Configuration

TSOT23-5L/SOT23-5L Flip-Chip

G_16290_084.eps
020206

Figure 8-3 Internal block diagram and pin configuration

2010-Jun-29
 IC Data Sheets Q548.1E LA 8. EN 53

8.4 Diagram SSB: Front End B02A, DRX3926K (IC 7303)

Block Diagram

RF AGC MPEG-2
DVB-T/QAM TS
IF AGC FEC
SAW
Main
IF AMP ADC CVBS
Tuner
DVB-T/QAM/ATV DAC
Demodulator

Stereo Decoder
Integrated Tuner SIF
DAC
I2S Audio

Presaw
Sense

I2C
I2 C
System Controller
GPIO

Pin Configuration
VSSAH_CVBS INP
VDDAH_CVBS INN
CVBS VSSAH_AFE1
SIF VDDAH_AFE1
VSSAL_AFE2 VDDAL_AFE1
VDDAL_AFE2 VSSAL_AFE1
PDP IF_AGC
PDN RF_AGC

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XI 49 32 RSTN
XO 50 31 SAW_SW
VSSAH_OSC 51 30 GPIO2
VDDAH_OSC 52 29 VSYNC
VDDH 53 28 VSSL
VSSH 54 27 VDDL
VSSL 55 26 VDDH
VDDL 56 25 VSSH
TDO 57
DRXK 24 I2C_SDA1
TMS 58 23 I2C_SCL1
TCK 59 22 MD7
TDI 60 21 MD6
I2C_SDA2 61 20 MD5
I2C_SCL2 62 19 MD4
I2S_CL 63 18 VDDH
I2S_DA 64 17 VSSH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I2S_WS VDDL
VDDL VSSL
VSSL MD3
GPIO1 MD2
MSTRT MD1
MERR MD0
VSSH MVAL
18440_300_090303.eps
VDDH MCLK 090303

Figure 8-4 Pin configuration

2010-Jun-29
 EN 54 8. Q548.1E LA IC Data Sheets

8.5 Diagram SSB: PNX8543 - Power B03A-B03H, PNX8543 (IC7600)

Block Diagram
PNX8543x
MEMORY
CONTROLLER

TS in from
channel decoder MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single or dual
OUTPUT channel)

DV-ITU-656 DV INPUT

AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT

Low-IF DIGITAL IF MPEG/H.264

VIDEO SCALER,
DECODER DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DEMOD
SSIF, LR
AND DECODE AUDIO DACS analog audio

AUDIO DSP
Dual SPDIF I2S
AUDIO IN AUDIO OUT
I2S SPDIF
300 MHz
AV-DSP
HDMI
Dual HDMI
RECEIVER DRAWING
ENGINE

SYSTEM 300 MHz

CONTROLLER MIPS32 4KEc
(8051) CPU DMA BLOCK

I2C PWM GPIO IR ADC SPI UART I2C GPIO Flash USB 2.0 CA PCI 2.2
x 22 x 10

Pin Configuration
ball A1
index area 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

A
B
C
D
E
F
G
H
J
K PNX8543xEH
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
Transparent top view
18440_301_090303.eps
090303

Figure 8-5 Internal block diagram and pin configuration

2010-Jun-29
 IC Data Sheets Q548.1E LA 8. EN 55

8.6 Diagram SSB: Ethernet (Pt. no. 1) B05B, DP83816 (IC7N04)

Block Diagram

TPRDP/M TPTDP/M
3V DSP Physical Layer

Test data out

MII Mgt
MII RX
MII TX

Test data in
25 MHz Clk

SRAM
RX-2 KB
RAM MII RX
SRAM MII TX
RXFilter BIST Interface MII Mgt
.5 KB Logic Logic BIOS ROM Cntl
SRAM BIOS ROM Data
TX-2 KB EEPROM/LEDs
Rx rd data
Tx rd data

BROM/EE
Rx wr data
Tx wr data

MII Mgt
R x A ddr

M I I RX
Tx Addr

MII TX
PCI CLK

PCI CNTL
MAC/BIU
PCI AD

DP83816

Pin Configuration
RXDV/MA11
RXER/MA10

MA4/EECLK
TXD3/MA15
TXD2/MA14
TXD1/MA13
TXD0/MA12

RXD3/MA9
RXD2/MA8
RXD1/MA7

RXD0/MA6
COL/MA16

MA3/EEDI
AUXVDD

AUXVDD

AUXVDD

AUXVDD

RXCLK
TXCLK

RXOE
TXEN

MDIO
M DC
C RS

M A5
VSS

VSS

VSS

VSS

VSS

VSS
NC

NC

C1
X2
X1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

NC 37 144 MA2/LED100N
38 143 MA1/LED10N
VSS
39 142 MA0/LEDACTN
IAUXVDD
VREF 40 141 MD7
RESERVED 41 Pin1 140 MD6
NC 42 Identification 139 MD5
NC 43 138 MD4/EEDO
VSS 44 137 AUXVDD
TPRDM 45 136 VSS
TPRDP 46 135 MD3
IAUXVDD 47 134 MD2
REGEN 48 133 MD1/CFGDISN
VSS 49 132 MD0
RESERVED 50 131 MWRN
VSS 51 130 MRDN
VSS 52 129 MCSN
TPTDM 53 128 EESEL
TPTDP
VSS
AUXVDD
VSS
AUXVDD
54
55
56
57
58
DP83816 127
126
125
124
123
RESERVED
NC
NC
NC
PWRGOOD
PMEN/CLKRUNN 59 122 3VAUX
PCICLK 60 121 AD0
INTAN 61 120 AD1
RSTN 62 119 AD2
GNTN 63 118 AD3
REQN 64 117 PCIVDD
VSS 116 AD4
65
AD31 115 AD5
66
AD30 114 VSS
67
AD29 113 AD6
68 AD7
PCIVDD 69 112
AD28 111 CBEN0
70 AD8
AD27 71 110
AD26 109 AD9
72
100
101
102
103
104
105
106
107
108
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

PCIVDD
VSS
VSS

PCIVDD
AD25
AD24
CBEN3
IDSEL

AD23
AD22

AD21
AD20
AD19

AD18
AD17
AD16
CBEN2

CBEN1
IRDYN

AD15
AD14

AD13
AD12
AD11

AD10
DEVSELN
FRAMEN

TRDYN

STOPN
PERRN
SERRN
PAR
PCIVDD

VSS
NC
NC

F_15710_167.eps
230905

Figure 8-6 Internal block diagram and pin configuration

2010-Jun-29
 EN 56 8. Q548.1E LA IC Data Sheets

8.7 Diagram SSB: Ethernet (Pt. no. 3) B05B, LAN9420 (IC7N04)

Block Diagram

EEPROM
(optional)
PCI Host

To Ethernet
LAN9420/LAN9420i Magnetics

GPIOs/LEDs
PCI Bus
(optional)

PCI Device External

25MHz Crystal

PCI Device

Pin Configuration

18561_300_090717.eps
090717

Figure 8-7 Internal block diagram and pin configuration

2010-Jun-29
 IC Data Sheets Q548.1E LA 8. EN 57

8.8 Diagram SSB: Class-D B06A, TPA3123D (IC 7L10)

Block diagram 1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR

PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
SD 1 F
Control

MUTE
GAIN0

GAIN1
} Control

Pinning information
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR

TERMINAL
24-PIN I/O/P DESCRIPTION
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Thermal pad Die pad P
secure device to printed wiring board.

18440_302_090303.eps
090318

Figure 8-8 Internal block diagram and pin configuration

2010-Jun-29
 EN 58 8. Q548.1E LA IC Data Sheets

8.9 Diagram SSB: Ethernet (Pt. no. 1) B08D, PNX51xx (IC7C00)

Block Diagram
PNX51xx
MEMORY
CONTROLLER

TM327x 1
LVDS RX 1 GIC 1
Video
UIP L3K7
TM327x 2
GIC 2
LVDS RX 2

TM327x 3
GIC 3
PCI/XIO

LVDS TX 1
I2C Video
LVDS TX 2
I2C-DMA
CPIPE L3K7
I2C
GFX LVDS TX 3

LVDS TX 4

UART UART

16 X GPIO

EJTAG

CLOCK CAB
AUDIO IN
AUDIO OUT

Pin Configuration

ball A1
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H PNX51xx
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

Transparent top view

18560_300_090403.eps
090403

Figure 8-9 Internal block diagram and pin configuration

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 59

9. Block Diagrams
Wiring Diagram 32" (Frame)
WIRING DIAGRAM 32" (FRAME / ROADRUNNER)

*8M85
1M83 (AL1) 1M85 (AL4)
1. SCL 14. GND
2. SPI-DATA-IN 13. VLED2
3. SDA 12. GND
4. CONTROL-1 11. VLED1
5. CONTROL-2 10. PROG
6. +3V3 9. TEMP-SENSOR
7. BLANK 8319 8. EEPROM-CS
8. EEPROM-CS 7. BLANK-BUF
9. TEMP-SENSOR 6. +3V3
TO
10. PROG
11. VLED1
LCD DISPLAY (1004) BACKLIGHT
5. PWM-CLOCK-BUF
4. SPI-LATCH
12. GND 3. SPI-DATA-RETURN
13. VLED2 2. SPI-DATA-OUT
14. GND *8M83 1. SPI-CLOCK-BUF

1G50 (B07B) 1M59 (B08E)

1. N.C 1. SCL-AMBI-3V3
TO 2. N.C 2. GND
... 3. SDA-AMBI-3V3
BACKLIGHT 8G50 ... 4. GND
... 5. GND
+ - SUBWOOFER (5214) 39. N.C 6. +3V3
40. N.C 7. GND
41. N.C

1G51 (B07B)
1. +VDISP-OUT
SSB
8G51
2. +VDISP-OUT
3. +VDISP-OUT
4. +VDISP-OUT
...
B (1150)

8316 *8M83 ...

...
51. GND

1M20 (B03G)
8. +5V
7. KEYBOARD
6. LED1
DANGEROUS DANGEROUS 8M20 5. +3V3-STANDBY

5. +24V

3. +24V

1. +24V
6. GND

4. GND

2. GND
HIGH VOLTAGE HIGH VOLTAGE

CN7
4. LED2
3. RC
2. N.C.
1. HV1

3. HV1

2. N.C.
1. HV2

3. HV2

2. GND
CN2

CN3

1. LIGHT-SENSOR

CN4 1M95 (B01B)

11. FAN_PWM 11. N.C
10. GND_SND 10. GNDSND
9. +VSND 9. +AUDIO-POWER
KEYBOARD CONTROL

8. +12V 8. +12V
7. +12V 8M95 7. +12V
6. +12V 6. +12V
5. GND1 5. GND
4. GND1 4. GND
MAIN POWER SUPPLY 3. GND1 3. GND
2. STANDBY 2. STANDBY
IPB PLHL-T826B 1. 3V3_ST 1. +3V3-STANDBY
(1005)

*AMBI-LIGHT MODULE
1M99 (B01B)
CN5 12. GND
12. GND1 11. SDA-SET
(1114)

11. I2C_DATA 10. SCL-SET

10. I2C_SCL 9. POWER-OK
9. INV_OK 8. GND
8. A/P_DIM 8M99 7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT

10 LED (1175)
7. BOOST
6. DIM 5. LAMP-ON-OUT
5. BL_ON_OFF 4. GND
4. GND1 3. GND
3. GND1 2. +12VD
2. +12V 1. +12VD
1. +12V
1735 (B06A)
4. RIGHT-SPEAKER
3. GNDSND

AL
2. GNDSND
T3.15A 1. LEFT-SPEAKER
CN1
1. N
2. L

1736 (B06A)
*AMBI-LIGHT MODULE

3. RIGHT-SPEAKER
2. GNDSND
1. LEFT-SPEAKER

1M83 (AL1)
10 LED (1176)

14. GND
8763 13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
Board Level Repair 5. CONTROL-2
INLET
AL

4. CONTROL-1
8308 3. SDA
2. GND
1. SCL
Component Level Repair
Only For Authorized Workshop
IR LED PANEL
RIGHT SPEAKER
(1112) P2 P1 LEFT SPEAKER
(5213) (5213)
3P 8P
* Only For 32PFL8404H/xx
18560_400_090326.eps
090714

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 60

Wiring Diagram 37" (Roadrunner)

WIRING DIAGRAM 37" (ROADRUNNER)

8M85
1M83 (AL1) 1M85 (AL4)
1. SCL 14. GND
2. SPI-DATA-IN 13. VLED2
3. SDA 12. GND
4. CONTROL-1 11. VLED1
5. CONTROL-2 10. PROG
6. +3V3 9. TEMP-SENSOR
7. BLANK 8319 8. EEPROM-CS
8. EEPROM-CS 7. BLANK-BUF
9. TEMP-SENSOR 6. +3V3
TO
10. PROG
11. VLED1
LCD DISPLAY (1004) BACKLIGHT
5. PWM-CLOCK-BUF
4. SPI-LATCH
12. GND 3. SPI-DATA-RETURN
13. VLED2 2. SPI-DATA-OUT
14. GND 8M83 1. SPI-CLOCK-BUF

1G50 (B07B) 1M59 (B08E)

1. N.C 1. SCL-AMBI-3V3
TO 2. N.C 2. GND
... 3. SDA-AMBI-3V3
BACKLIGHT ... 4. GND
8G50
... 5. GND
39. N.C 6. +3V3
40. N.C 7. GND
41. N.C

1G51 (B07B)
1. +VDISP-OUT
2. +VDISP-OUT
3. +VDISP-OUT
B SSB
(1150)
8G51 4. +VDISP-OUT
...
8316 8M83 ...
...
51. GND

1M20 (B03G)
8. +5V
7. KEYBOARD
6. LED1
8M20 5. +3V3-STANDBY
2. N.C.
1. HV1

3. HV1

2. N.C.
1. HV2

3. HV2

5. +24V

3. +24V

1. +24V
6. GND

4. GND

2. GND
CN2

CN3

CN7
4. LED2
3. RC
2. GND
1. LIGHT-SENSOR

CN4 1M95 (B01B)

11. FAN_PWM 11. N.C
10. GND_SND 10. GNDSND
9. +VSND 9. +AUDIO-POWER
KEYBOARD CONTROL

8. +12V 8. +12V
7. +12V 8M95 7. +12V
6. +12V 6. +12V
5. GND1 5. GND
4. GND1 4. GND
MAIN POWER SUPPLY 3. GND1 3. GND
2. STANDBY 2. STANDBY
IPB DPS-298CPA B 1. 3V3_ST 1. +3V3-STANDBY
(1005)
1M99 (B01B)

AMBI-LIGHT MODULE
CN5 12. GND
12. GND1 11. SDA-SET
(1114)

11. I2C_DATA 10. SCL-SET

10. I2C_SCL 9. POWER-OK
9. INV_OK 8. GND
8. A/P_DIM 8M99 7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT

10 LED (1175)
7. BOOST
6. DIM 5. LAMP-ON-OUT
5. BL_ON_OFF 4. GND
4. GND1 3. GND
3. GND1 2. +12VD
2. +12V 1. +12VD
1. +12V
1735 (B06A)
FUSE 4. RIGHT-SPEAKER
3. GNDSND

AL
2. GNDSND
1. LEFT-SPEAKER
CN1
1. N
2. L

1736 (B06A)
AMBI-LIGHT MODULE

3. RIGHT-SPEAKER
2. GNDSND
1. LEFT-SPEAKER

1M83 (AL1)
10 LED (1176)

14. GND
13. VLED2
12. GND

8736
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
5. CONTROL-2
AL

Board Level Repair 4. CONTROL-1

3. SDA
INLET

2. GND
8308 1. SCL

Component Level Repair

IR LED PANEL SUBWOOFER (5214)
RIGHT SPEAKER
(5213)
Only For Authorized Workshop (1112) P2 P1
+ -
LEFT SPEAKER
(5213)
3P 8P

18560_410_090331.eps
090714

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 61

Wiring Diagram 42" (Frame/Roadrunner)

WIRING DIAGRAM 42" (FRAME / ROADRUNNER)

*8M85
1M83 (AL1) 8319 1M85 (AL4)
1. SCL 14. GND
2. SPI-DATA-IN 13. VLED2
3. SDA 12. GND
4. CONTROL-1
5. CONTROL-2
LCD DISPLAY (1004) 11. VLED1
10. PROG
6. +3V3 9. TEMP-SENSOR
7. BLANK 8. EEPROM-CS
8. EEPROM-CS TO 7. BLANK-BUF
9. TEMP-SENSOR 6. +3V3
10. PROG BACKLIGHT 5. PWM-CLOCK-BUF
11. VLED1 4. SPI-LATCH
12. GND TO 3. SPI-DATA-RETURN
13. VLED2 BACKLIGHT 2. SPI-DATA-OUT
14. GND *8M83 1. SPI-CLOCK-BUF

1G50 (B07B) 1M59 (B08E)

1. N.C 1. SCL-AMBI-3V3
2. N.C 2. GND
... 3. SDA-AMBI-3V3
8G50 ... 4. GND
... 5. GND
39. N.C 6. +3V3
40. N.C 7. GND
41. N.C

1G51 (B07B)
1. +VDISP-OUT
2. +VDISP-OUT
3. +VDISP-OUT
8G51 4. +VDISP-OUT
...
8316 ...
...
*8M83 51. GND

1M20 (B03G)
8. +5V
CN4
7. KEYBOARD
11. FAN_PWM
6. LED1
10. GND_SND
9. +VSND
8M20 5. +3V3-STANDBY
2. N.C.
1. HV1

3. HV1

2. N.C.
1. HV2

3. HV2

5. +24V

3. +24V

1. +24V
4. LED2

6. GND

4. GND

2. GND
CN2

8. +12V
CN3

CN7
3. RC SSB
7. +12V
6. +12V
5. GND1
2.
1.
GND
LIGHT-SENSOR
B (1150)
4. GND1
3. GND1 1M95 (B01B)
2. STANDBY 11. N.C
1. 3V3_ST 10. GNDSND
9. +AUDIO-POWER
KEYBOARD CONTROL

8. +12V
8M95 7. +12V
CN5 6. +12V
12. GND1 5. GND
11. I2C_DATA 4. GND
MAIN POWER SUPPLY 10. I2C_SCL 3. GND
9. INV_OK 2. STANDBY
IPB DPS-298CP-4A 8. A/P_DIM 1. +3V3-STANDBY
7. BOOST

*AMBI-LIGHT MODULE
(1005)
6. DIM 1M99 (B01B)
5. BL_ON_OFF 12. GND
4. GND1 11. SDA-SET
3. GND1
(1114)

10. SCL-SET
2. +12V 9. POWER-OK
1. +12V 8. GND
8M99 7. BACKLIGHT-BOOST

12 LED (1175)
6. BACKLIGHT-OUT
5. LAMP-ON-OUT
4. GND
3. GND
2. +12VD
1. +12VD

1735 (B06A)
4. RIGHT-SPEAKER
3. GNDSND

AL
2. GNDSND
1. LEFT-SPEAKER
CN1

8308
1. N

FUSE
2. L
*AMBI-LIGHT MODULE

1736 (B06A)

8735
3. RIGHT-SPEAKER
INLET 2. GNDSND
1. LEFT-SPEAKER

1M83 (AL1)
12 LED (1176)

14. GND
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
Board Level Repair 6. +3V3
5. CONTROL-2
AL

4. CONTROL-1
3. SDA
Component Level Repair 2. GND
1. SCL
Only For Authorized Workshop
+ -

+ -
* Only For AmbiLight-sets IR LED PANEL
(1112) P2 P1
SPEAKER RIGHT (5212) 3P 8P SPEAKER LEFT (5211)

18560_412_090331.eps
090714

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 62

Wiring Diagram 47" (Frame / Roadrunner)

WIRING DIAGRAM 47" (FRAME / ROADRUNNER)

1M83 (AL1) 1M85 (AL4)

1. SCL 14. GND
2. SPI-DATA-IN *8M85 13. VLED2
3. SDA 12. GND
4. CONTROL-1 11. VLED1
5. CONTROL-2 10. PROG
6. +3V3 8319 9. TEMP-SENSOR
7. BLANK 8. EEPROM-CS
8. EEPROM-CS 7. BLANK-BUF
9. TEMP-SENSOR 6. +3V3
10. PROG
11. VLED1
LCD DISPLAY (1004) 5. PWM-CLOCK-BUF
4. SPI-LATCH
12. GND TO 3. SPI-DATA-RETURN
13. VLED2 2. SPI-DATA-OUT
14. GND BACKLIGHT 1. SPI-CLOCK-BUF
TO
BACKLIGHT
*AMBI-LIGHT MODULE

*AMBI-LIGHT MODULE
8 LED (1178)

8 LED (1178)
*8M59

1G50 (B07B) 1M59 (B08E)

1. N.C 1. SCL-AMBI-3V3
2. N.C 2. GND
... 3. SDA-AMBI-3V3
AL

AL
8G50 ... 4. GND
... 5. GND
39. N.C 6. +3V3
40. N.C 7. GND
41. N.C
8316
1G51 (B07B)
1. +VDISP-OUT
2. +VDISP-OUT
1M85 (AL4) 3. +VDISP-OUT
8G51 4. +VDISP-OUT
1M83 (AL1)
1. SPI-CLOCK-BUF 14. GND
2. SPI-DATA-OUT ...
13. VLED2
3. SPI-DATA-RETURN ...
12. GND
4. SPI-LATCH ...
*8M90 11. VLED1
5. PWM-CLOCK-BUF 51. GND
10. PROG
6. +3V3 9. TEMP-SENSOR
1M20 (B03G)
KEYBOARD CONTROL

7. BLANK-BU 8. EEPROM-CS
8. EEPROM-CS 8. +5V 7. BLANK
9. TEMP-SENSOR 7. KEYBOARD 6. +3V3
10. PROG 6. LED1 5. CONTROL-2
11. VLED1 5. +3V3-STANDBY 4. CONTROL-1
CN4

5. +24V

3. +24V

1. +24V
6. GND

4. GND

2. GND
2. N.C.
1. HV2

3. HV2

4. LED2
2. N.C.
1. HV1

3. HV1

12. GND
CN7
3. SDA
CN3
CN2

11. FAN_PWM 3. RC
13. VLED2
14. GND
10. GND_SND 2. GND B SSB 2. SPI-DATA-IN
1. SCL
9. +VSND 1. LIGHT-SENSOR (1150)
8. +12V
7. +12V
*8M82

8M95 1M95 (B01B)

*8M81
6. +12V
11. N.C
5. GND1
10. GNDSND
4. GND1
(1114)

9. +AUDIO-POWER
3. GND1
8. +12V
2. STANDBY
1M83 (AL1) 1. 3V3_ST
7. +12V
1M84 (AL1)
1. SCL 6. +12V
5. GND 14. GND
2. SPI-DATA-IN
4. GND 13. VLED2
3. SDA

5. CONTROL2
4. CONTROL1
12. GND

1M90 (AB1)

1M59 (AB1)
4. CONTROL-1 CN5 3. GND
12. GND1 2. STANDBY 11. VLED1
5. CONTROL-2
10. PROG

7. GND
11. I2C_DATA 1. +3V3-STANDBY

5. +24V

3. +24V

1. +24V

6. +3V3
6. +3V3

6. GND

4. GND

2. GND

2. GND
3. SDA

1. SCL
7. BLANK MAIN POWER SUPPLY 10. I2C_SCL 9. TEMP-SENSOR
8. EEPROM-CS
8. EEPROM-CS 9. INV_OK 1M99 (B01B)
9. TEMP-SENSOR IPB DPS-298CP-2A 8. A/P_DIM
8M99 12. GND
7. BLANK-BUF
6. +3V3
10. PROG (1005) 7. BOOST 11. SDA-SET
*DC-DC 5. PWM-CLOCK-BUF
11. VLED1
12. GND
13. VLED2
6. DIM
5. BL_ON_OFF
4. GND1
AB INTERFACE (1179)
10. SCL-SET
9. POWER-OK
8. GND
4. SPI-LATCH
3. SPI-DATA-RETURN
3. GND1 2. SPI-DATA-OUT
14. GND 7. BACKLIGHT-BOOST
2. +12V 1. SPI-CLOCK-BUF
6. BACKLIGHT-OUT
1. +12V 5. LAMP-ON-OUT
1M84 (AB1)
14. GND 4. GND
*AMBI-LIGHT MODULE

13. VLED2 3. GND

12. GND 2. +12VD

*AMBI-LIGHT MODULE
11. VLED1 1. +12VD
10. PROG
9. TEMP-SENSOR 1735 (B06A)
8. EEPROM-CS 4. RIGHT-SPEAKER
7. BLANK-BUF 3. GNDSND
6. +3V3 2. GNDSND
6 LED (1177)

5. PWM-CLOCK-BUF 1. LEFT-SPEAKER
8308 4. SPI-LATCH1CONN

6 LED (1177)
3. SPI-DATA-RETURN
2. SPI-CLOCK-BUF 1736 (B06A)
3. RIGHT-SPEAKER
INLET
CN1

1. SPI-LATCH2CONN
1. N

FUSE 2. GNDSND
2. L

8735
1. LEFT-SPEAKER
AL

*8M84

AL
1M84 (AL1) 1M83 (AL1)
1. SPI-CLOCK-BUF
14. GND
2. SPI-DATA-OUT
13. VLED2
3. SPI-DATA-RETURN
4. SPI-LATCH
8M20 12. GND
11. VLED1
5. PWM-CLOCK-BUF
10. PROG
6. +3V3
9. TEMP-SENSOR
7. BLANK-BUF
8. EEPROM-CS
8. EEPROM-CS
9. TEMP-SENSOR Component Level Repair 7. BLANK
6. +3V3
10. PROG
11. VLED1 Only For Authorized Workshop 5. CONTROL-2
4. CONTROL-1
+ -

+ -
12. GND
3. SDA
13. VLED2
14. GND * Only For 47PFL8404H/12 IR LED PANEL
2. SPI-DATA-IN
1. SCL
(1112) P2 P1
SPEAKER RIGHT (5212) 3P 8P SPEAKER LEFT (5211)

18560_411_090331.eps
090714

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 63

Wiring Diagram 52" (Frame)

WIRING DIAGRAM 52" (FRAME)

Board Level Repair

Component Level Repair

Only For Authorized Workshop LCD DISPLAY (1004)
CONNECTOR

1G50 (B07B)
INVERTER

1. N.C
2. N.C
...
CN2/1319 ...
14. PDIM_Select 8G50
CN6/1M95 ...
8316

13. PWM
11. FAN_PWM 39. N.C
12. On/Off
10. GND_SND 40. N.C
11. Vbri
9. +VSND 41. N.C
10. GND3
9. GND3 8. +12V
8. GND3 7. +12V 1G51 (B07B)
7. GND3 6. +12V 1. +VDISP-OUT
5. GND1 2. +VDISP-OUT
INVERTER 6. GND3
5. 24Vinv 4. GND1
8G51
3. +VDISP-OUT
4. 24Vinv 3. GND1 4. +VDISP-OUT
3. 24Vinv 2. STANDBY ...
2. 24Vinv 1. 3V3_ST ...
1. 24Vinv ...
51. GND

CN3/1316 CN7/1M99
12. N.C. 12. GND1 1M20 (B03G)
11. I2C_DATA 8. +5V
11. N.C.
10. GND3 MAIN POWER SUPPLY 10. I2C_SCL 7.
6.
KEYBOARD
LED1
9. GND3 9. INV_OK
8M20
8. GND3 PSU DPS-411AP3A B 8. A/P_DIM 5.
4.
+3V3-STANDBY
LED2
7. GND3 (1005) 7. BOOST
3. RC
6. GND3 6. DIM
5. BL_ON_OFF 2. GND B SSB
5. 24Vinv (1150)
4. GND1 1. LIGHT-SENSOR
4. 24Vinv
3. 24Vinv 3. GND1
8319

2. 24Vinv 2. +12V 1M95 (B01B)

1. 24Vinv 1. +12V 11. N.C
10. GNDSND
9. +AUDIO-POWER
KEYBOARD CONTROL

8. +12V
8M95 7. +12V
6. +12V
5. GND
4. GND
3. GND
2. STANDBY
1. +3V3-STANDBY

1M99 (B01B)
12. GND
11. SDA-SET
CONNECTOR
(1114)

10. SCL-SET
INVERTER

9. POWER-OK
8. GND
8M99 7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT
5. LAMP-ON-OUT
4. GND
3. GND
2. +12VD
1. +12VD
FUSE

1735 (B06A)
4. RIGHT-SPEAKER
CN1/1308

3. GNDSND
2. GNDSND
1. LEFT-SPEAKER
8308
1. N
2. L

1736 (B06A)
3. RIGHT-SPEAKER
INLET 2. GNDSND
1. LEFT-SPEAKER
+ -

+ -
IR LED PANEL
(1112) P2 P1
SPEAKER RIGHT (5212) 3P 8P SPEAKER LEFT (5211)

18560_402_090326.eps
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2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 64

Block Diagram Video

VIDEO
B02A FRONT END B05C PCMCIA 7K04-7K05 B03 PNX8543 B08D PNX5100 - LVDS IN/OUT B07B DISPLAY INTERFACE
74LVC245APW 1G50
1K00 7600
20 1
+3V3 PNX85433EH/M2A 7C00 I2C 2
B03B TUN_CA B03B LVDS PNX5100EH/M2
B08D LVDS TX1 3
B08D LVDS
MDO(0-7) BUFFER CA-MDO(0-7) CA_MD0 AP18 RX51001A+ AE20 RX TX
A_P
AN18 RX51001A- AF20

68P
A_N TO DISPLAY
PCMCIA AL18 RX51001B+ AC20
B_P TX2 1080p 50/60Hz
CA-MDI(0-7) CA_MDI AK18 RX51001B- AD20
17 B_N 37
AP19 RX51001C+ AC19
PCMCIA-VCC-VPP C_P
CONDITIONAL 18 AN19 RX51001C- AD19 38
C_N
ACCESS 33 AP20 RX51001D+ AE19
D_P 39
RX51001D-
51
52
D_N
E_P
AN20
AM20
AL20
RX51001E+
RX51001E-
AF19
AE18
AF18
PNX5100 N.C.
40
41
E_N
7303 AM19 RX51001CLK+ AC18 E17
1301 CLK_P +3V3
DRX3926K AL19 RX51001CLK- AD18 QUAD LVDS
HD1816AF/BHXP
4302 3306 2364 33AA 2365
CLK_N
HD-NM E14
+3V3
1920x1080
1G51
51
10 PDP 47 AP22 RX51002A+ AE17
FE-DATA(0-7) TNR_TSDI
IF-OUT1 PD_P LOUT2_A_P
RX51002A- FHD 100Hz 100/120HZ 50

5311
AN22 AF17
4303 2367 33AC 2368 LOUT2_A_N I2C 49
11 PDN 48 AL22 RX51002B+ AC17
IF-OUT2 PD_N LOUT2_B_P TX3
B03E ANALOG VIDEO AK22 RX51002B- AD17 40
7302 3311 LOUT2_B_N
44 SIF F2 AP23 RX51002C+ AC16
UPC3221GV SIF AI51 LOUT2_C_P
+5V-TUNER AN23 RX5100C- AD16
DEMODULATOR 7345 LOUT2_C_N
1 AGC AMPLIFIER 43 3348 4314 CVBS H3 AP24 RX51002D+ AE16 TX4
CVBS AI44 LOUT2_D_P TO DISPLAY
MAIN HYBRID VCC AN24 RX51002D- AF16 11
LOUT2_D_N 1080p 100/120Hz
TUNER 1
1303
5 2306 2 7 3303 IF-N 39 4315 CVBS-TER-OUT LOUT2_E_P
AM24 RX51002E+ AE15
AL24 RX51002E- AF15 5
LOUT2_E_N 4
2307 3304 8,18,26,53 AM23 RX51002CLK+ AC15
2 4 3 6 IF-P 40 VDDH +3V3B LOUT2_CLK_P
2,16,27,56 AL23 RX51002CLK- AD15 3
IN OUT VDDL +1V2 LOUT2_CLK_N
SAW 36M125 37 2
4 49 VDDAH_AFE1 +3V3A
AGC CONTROL XI 42 B08A 1
VDDAH_CVBS +3V3E AK19 +VDISP-OUT
1304 52 IREF_LVDS VDDA-LVDS SUPPLY
VDDAH_OSC +3V3D AB20
+3V3A 27M +3V3
36,46 AA5
50 VDDAL_AFE +1V2A +1V2-PNX5100
XO L16
3305
+5V-TUNER +1V8-PNX5100
P22
IF-AGC 34 +1V2-PNX5100-DDR-PLL1
IF_AGC AB18
3301

+3V3-PNX5100-LVDS-IN
3 33 J5
RF-AGC +1V2-PNX-TRI-PLL1

PNX8543
RF-AGC RF_AGC L5
+1V2-PNX-TRI-PLL2
T5
+1V2-PNX-TRI-PLL3
M22
+1V2-PNX5100-DLL
B05A HDMI 1H03
B04B ANALOG IO - SCART 1&2 AE25
7F02 +3V3-PNX5100-DDR-PLL0
1 74HC4053PW E15
DRX2+ +1V2-PNX5100-LVDS-PLL
16 B15
3 DRX2- MDX +5V +3V3-PNX5100-LVDS-PLL

H264 AE14
1

4
2

DRX1+ +1V2-PNX5100-CLOCK
5 CVBS-TER-OUT AD14
6 DRX1- 14 +3V3-PNX5100-CLOCK
7F07-7F08
7
9
DRX0+
DRX0-
1F01
7F03
1 Y_CVBS-MON-OUT-SC Y-CVBS-MON-OUT A3
CVBS1Y_P USB 2.0
18

B08B DDR2 B08B PNX5100 - SDRAM

19

10 19
DRXC+ 9,10,11 7F01
HDMI SIDE 12 DRXC- REGIMBEAU_CVBS-SWITCH P24
1 B03H VREF PNX5100-DDR2-VREF-CTRL
CONNECTOR
CONTROL 7C01
1H01 8 AV1_STATUS
EXT 1 B03H B03A VDD EDE5116AJBG
7 7F06
1 CRX2+ CONTROL
16 AV1_BLK AJ6
3 CRX2- 11 B03H VDDA_3V3_AADC VDDA-DAC DDR2
(0-12)
SDRAM
1

4 CRX1+ 15 SC1-R J2 AK12

2

15
16 AI32 VDDA_3V3_ADAC VDDA-ADC
6 CRX1-
7 SC1-B L2 AK20 J1
7 CRX0+ 20
21 AI22 VDD_3V3_LVDS VDDA-LVDS D PNX5100-DDR2-D(0-15) VDDL +1V8-PNX5100
J2
9 CRX0- SCART1 11 SC1-G N2 F16 VREF PNX5100-DDR2-VREF-DDR
RREF-PNX85XX
18

AI12 VDDA_HDMI_3V3_BIAS
19

10 CRXC+
20 CVBS1 G4 AC6 7C02
HDMI 1 12 CRXC- AI41 VDD_3V3_SBPER +3V3-STANDBY
EDE5116AJBG
CONNECTOR 1F02 AJ12
7F04 VDD_1V2_CORE +1V2-PNX85XX
1H00 19 DDR2
AF5 PNX5100-DDR2-A(0-12)
1 VDD_1V2_SBCORE 1V2-STANDBY A
BRX2+ SDRAM
7 AV2-PB_SC2-B L3 AI23 AJ21
3 BRX2- 1
VDD_3V3_PER +3V3-PER
1

J1
2

4 BRX1+ 15 AV2-PR_SC2-R J3 (16-31)

AI33 AG30 VDDL +1V8-PNX5100
6 BRX1- 7 VDD_1V8_DDR 1V8-PMNX85XX J2
11 AV2-Y_SC2-G N3 VREF PNX5100-DDR2-VREF-DDR
7 BRX0+ EXT 2 AI13
11
9 BRX0- 20 CVBS2 H1
18

AI42
19

10 BRXC+ 16
15
7F05 B03G PNX8543 - CONTROL MIPS/FLASH/PCI
HDMI 2 12 BRXC- 16 AV2-BLK_LCD-SDA B03G CONROL +5V
20
21
B03H
CONNECTOR
SCART2 CONTROL
8 AV2-STATUS
1H02 B03H

3M31
1 ARX2+ CONTROL 1M09

+T
3 ARX2- AL16 USB-OC 1
USB_FAULT USB 2.0
B04C YPBR / SIDE IO / S-VIDEO

1
AN16 USB20-DM 2
1

4 ARX1+ CONNECTOR SIDE

2

3 2
USB_DM
6 ARX1- AP16 USB20-DP 3 SW UPLOAD
1G30 USB_DP JPEG
4

4
7 ARX0+ 1 R-VGA K4 PC3_AI3 AM17 3M21 MP3
9 ARX0- USB_RPU +3V3-PER
2 G-VGA P4
18

10
19

15

10 ARXC+ PC1_AI3 AN17 3M23

5

3 B-VGA M4 USB_VBUS +3V3-PER

12 ARXC- PC2_AI3
HDMI 3 13 H-SYNC-VGA T1
HSYNCIN
1

CONNECTOR
11

14 V-SYNC-VGA T2
VSYNCIN 7M00
B03G PCI NAND01GW3B2BN6F
7H11 VGA
TDA9996 CONNECTOR NAND
CRX2+ 72 90 DRX2+ 1G22 FLASH
PCI PCI-AD<->NAND-AD
CRX2- 71 89 DRX2- 7 AV3-PR K1 1G
DRX1+ PR PC3_AI1
CRX1+ 69 87
12,37
68 86 DRX1- 12 AV3-Y P1 VCC +3V3-NAND
CRX1- EXT 3
RXC RXD 84 DRX0+ Y PC1_AI1
CRX0+ 66
65 83 DRX0- 9 AV3-PB M1
CRX0-
81 DRXC+ PB PC2_AI1
63 B03F MEMORY
CRXC+
HDMI 80 DRXC-
B03F PNX8543 - SDRAM
CRXC- 62

BRX2+ 42
SWITCH 1G20
AA31 3B03
M_IREF +1V8-PNX85XX
BRX2- 41 8,45,91,24, AB32
2 FRONT-Y_CVBS H2 M_VREF DDR2-VREF-CTRL
BRX1+ 39 75,95 CVBS AI43
VDDx_1V8 VDD_1V8
BRX1- 39 4 SIDE 7B01
RXB VDDO_3V3 VDDO_3V3 FRONT-C G1
36 46,55 I/O 1G37 AI54 EDE1116AEBG
BRX0+ VDDx_3V3 VDDS_3V3 1
BRX0- 35 3
15,21,34,40,
BRXC+ 33 64,70,85,88 SVHS IN 5 SDRAM
VDDH_3V3 VDDH_3V3 4 (0-12)
BRXC- 32 2

ARX2+ 23 B05A HDMI_DV J1

M_DQ DDR2-D(0-15) VDDL +1V8-PNX85XX
ARX2- 22 2 RXC+ A14 J2
C_+ HDMI_RXC_B_N VREF DDR2-VREF-DDR
ARX1+ 20 3 RXC- A15
C_- HDMI_RXC_B_P
ARX1- 19 RXA 99 RX0+ B13 7B00
D0_+ HDMI_RX0_B_N
RX0- B14 EDE1116AEBG
ARX0+ 17 100 HDMI_RX0_B_P
D0_-
ARX0- 16 96 RX1+ A12
D1_+ HDMI_RX1_B_N SDRAM
ARXC+ 14 97 RX1- A13 M_A DDR2-A(0-12)
D1_- HDMI_RX1_B_P
ARXC- 13 93 RX2+ B11
D2_+ HDMI_RX2_B_N
94 RX2- B12 J1
D2_- HDMI_RX2_B_P (16-31) VDDL +1V8-PNX85XX
3H64 C16 J2
HDMI_RREF VREF DDR2-VREF-DDR
RREF-PNX85XX

18560_403_090326.eps
090326

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 65

Block Diagram Audio

AUDIO
B02A FRONT END B05C PCMCIA 7K04-7K05 B03 PNX8543 B06A CLASS-D
74LVC245APW
1K00
20 7H00
+3V3
PNX85439EH/M2

B03B TUNER_CA B03D AUDIO AN8 5902

AADC VDDA-AUDIO 7L10
MDO(0-7) BUFFER CA-MDO(0-7) CA_MD0 AM9 5900 TPA3123D2PWP
VREF_POS
AK9 1,3 5L07

68P
PCMCIA VDDA_3V3_DAC VDDA-DAC PVCC_L +AUDIO-POWER
CA-MDI(0-7) 10,12 5L08
CA_MDI PVCC_R
17 1735
PCMCIA-VCC-VPP
CONDITIONAL 18 ADAC(1) 5 22 LEFT-SPEAKER 1
AN14 OUT-L
ACCESS ADAC1 IN-L
33
51
CLASS D 5L09 2
POWER
52 SPEAKER L
AMPLIFIER
3
AP13 ADAC(2) 6
7303 ADAC2 IN-R
1301 DRX3926K
HD1816AF/BHXP 15 RIGHT-SPEAKER 4
OUT-R
10 4302 3306 2364 33AA 2365 PDP 47 A-STBY 2 SPEAKER R
FE-DATA(0-7) TNR_TSDI B03H STANDBY SD
IF-OUT1 PD_P

5311
1736
11 4303 2367 33AC 2368 PDN AC5 3L17
48 AUDIO-MUTE MUTE 4 1
IF-OUT2 PD_N PO_7 MUTE
B03E ANALOG VIDEO 5L10
7302 3311 2
44 SIF F2
UPC3221GV SIF AI51 7L03
+5V-TUN 3
DEMODULATOR 7345 A-STBY STANDBY &
1 AGC AMPLIFIER 43 3348 4314 CVBS H3 PROTECTION SUBWOOFER
MAIN HYBRID VCC CVBS AI44
(OPTIONAL)
TUNER 1
1303
5 2306 2 7 3303 IF-N 39
B03C PNX8543 - AUDIO AMPLIFIER B04C YPBR / SIDE IO / S-VIDEO
2307 3304 8,18,26,53
2 4 3 6 IF-P 40 VDDH +3V3B
2,16,27,56 7807-1 7807-2
SAW 36M125 IN OUT VDDL +1V2
37 AD1 AUDIO-RESET A-PLOP B04B
4 49 VDDAH_AFE1 +3V3A PO_6
AGC CONTROL XI 42 B04C
VDDAH_CVBS +3V3E
1304 52
+3V3A 27M VDDAH_OSC +3V3D
36,46

PNX8543
50 VDDAL_AFE +1V2A
XO 7830

3305
+3V3A
TPA6111A2DGN
IF-AGC 34
IF_AGC
3305

HEADPHONE
3 RF-AGC 33
RF-AGC RF_AGC AMPLIFIER
AUDIO-RESET 5
SHUTDOWN 1G21

B05A HDMI 1H03 B04B ANALOG - SCART 1&2 B03C PNX8543 - AUDIO B03D AUDIO H264 AM12 ADAC(3) 2
VO_1
1 HP_LOUT 2

ADAC3 IN-1 7 HP_ROUT 3

1
3
DRX2+
DRX2- 1
1F01
3 AP-SCART-OUT-L 3F00 AUDIO-CL-L 1
AMPLIFIER
7803-1/2
3 ADAC(7) AL9
ADAC7
USB 2.0 AM11 ADAC(4) 6
VO_2

8
1 HEADPHONE
OUT 3.5mm
ADAC4 IN-2 VDD +3V3
1

4
2

DRX1+ 3F02
6 1 AP-SCART-OUT-R AUDIO-CL-R 7 5 ADAC(8) AL8 ADAC8
DRX1- 7

7 DRX0+ EXT 1
11
6 AUDIO-IN1-L AN7 AIN_1_L
9 DRX0-
18
19

10 DRXC+ 16
15
B03G PNX8543 - CONTROL MIPS/FLASH/PCI
12 2 AUDIO-IN1-R AP7
HDMI SIDE DRXC- 20
AIN_1_R B03G CONROL +5V
21
CONNECTOR
1H01 SCART1
1F02

3M31
1 CRX2+ 1M09
1 3 AP-SCART-OUT-L 7F00

+T
3 CRX2- A-PLOP AL16 USB-OC 1
A-PLOP B03C USB_FAULT USB 2.0

1
1

4 CRX1+ 2
2

AN16 USB20-DM CONNECTOR ON SSB

1 AP-SCART-OUT-R

3 2
7 USB_DM
6 CRX1- AP16 USB20-DP 3 SW UPLOAD
EXT 2 USB_DP
7 CRX0+ 11
4 JPEG

4
6 AUDIO-IN2-L AK6
9 CRX0- 15 AIN_2_L AM17 3M21 MP3
18

16 USB_RPU +3V3-PER
19

10 CRXC+
2 AUDIO-IN2-R AL6 AN17 3M23
HDMI 1 12 CRXC- 20
21 AIN_2_R USB_VBUS +3V3-PER
CONNECTOR SCART2
1H00
1 BRX2+
3 BRX2- B04C YPBR / SIDE IO / S-VIDEO
1
2

4 BRX1+
6 BRX1-
7 BRX0+ 1G25 7M00
9 BRX0- 7G01 B03G PCI
18

DIGITAL EF NAND01GW3B2BN6F
19

2 SPDIF-OUT-1 V1
10 BRXC+ SPDIF_OUT
AUDIO
HDMI 2 12 BRXC- OUT NAND
CONNECTOR 4 AUDIO-OUT-L 8 7803-3/4 10 ADAC(5) AN11 FLASH
ADAC5 PCI PCI-AD24<->NAND-AD
1H02 AUDIO OUT 1G
L+R 6 AUDIO-OUT-R 14 12 ADAC(6) AP10
1 ARX2+ ADAC6
3 ARX2- 12,37
1

7G00 +3V3-NAND
2

4 ARX1+ A-PLOP
1G22 A-PLOP B03C
6 ARX1-
5 AUDIO-IN3-L AM6
7 ARX0+ AIN_3_L
9
18

ARX0- EXT 3 AUDIO IN

19

10 L+R 3 AUDIO-IN3-R AN6

ARXC+ AIN_3_R B03F MEMORY
HDMI 3 12 ARXC-
B03F PNX8543 - SDRAM
CONNECTOR
1G20 AA31 3B03
RES FOR /32 +1V8-PNX85XX
M_IREF
5 AUDIO-IN5-L AN5 AB32
AIN_5_L M_VREF DDR2-VREF-CTRL
7H11 AUDIO IN
SIDE
TDA9996 L+R 8 AUDIO-IN5-R AP5 7B01
I/O AIN_5_R
90 DRX2+ EDE1116AEBG
CRX2+ 72
71 89 DRX2-
CRX2-
87 DRX1+ SDRAM
CRX1+ 69 1G18 (0-12)
68 86 DRX1-
CRX1- 2 AUDIO-IN4-L AP6
RXC RXD 84 DRX0+ AIN_4_L J1
CRX0+ 66 AUDIO IN +1V8-PNX85XX
DRX0- AUDIO-IN4-R M_DQ DDR2-D(0-15) J2
CRX0- 65 83 DVI -> HDMI 3 AM5
AIN_4_R DDR2-VREF-DDR
63 81 DRXC+
CRXC+ 1
CRXC- 62
HDMI 80 DRXC- 7B00

BRX2+ 42
SWITCH EDE1116AEBG

BRX2- 41 8,45,91,24, SDRAM

75,95 M_A DDR2-A(0-12)
BRX1+ 39 VDDx_1V8 VDD_1V8
BRX1- 39 4
RXB VDDO_3V3 VDDO_3V3
BRX0+ 36 46,55 (16-31) J1
VDDx_3V3 VDDS_3V3 +1V8-PNX85XX
BRX0- 35 15,21,34,40, J2
B04H DIGITAL VIDEO IN DDR2-VREF-DDR
BRXC+ 33 64,70,85,88
VDDH_3V3 VDDH_3V3
BRXC- 32
2 HDMIB-RXC+ A14
C_+ HDMI_RXC_B_N
ARX2+ 23 3 HDMIB-RXC- A15
C_- HDMI_RXC_B_P
ARX2- 22 99 HDMIB-RX0+ B13
D0_+ HDMI_RX0_B_N
ARX1+ 20 100 HDMIB-RX0- B14
D0_- HDMI_RX0_B_P
ARX1- 19 RXA 96 HDMIB-RX1+ A12
D1_+ HDMI_RX1_B_N
ARX0+ 17 97 HDMIB-RX1- A13
D1_- HDMI_RX1_B_P
ARX0- 16 93 HDMIB-RX2+ B11
D2_+ HDMI_RX2_B_N
ARXC+ 14 94 HDMIB-RX2- B12
D2_- HDMI_RX2_B_P
ARXC- 13 3H64 C16
RREF-PNX85XX HDMI_RREF
18540_404_090311.eps
100119

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 66

Block Diagram Control & Clock Signals

CONTROL + CLOCK SIGNALS
B05B ETHERNET B02A FRONT END B03 PNX8543 B8D PNX5100 - LVDS IN/OUT B07B DISPLAY INTERFACE
7N04
1N00 DP83816AVNGNOPB 7303
DRX3926K-XK-A3 7600
17 PNX85433EH/M2A/ 7C00
PNX5100EH/M2 1G50
49 B03B TUN_CA

1N02
25

25M
ETHERNET B08B DDR2 E18 TX1CLK-
FE-DATA(0-7) TNR_TSDI

1304

27M
DEMODULATOR
CONTROLLER E19 TX1CLK+ 24
ETHERNET 18 50 TO
CONNECTOR 9 FE-CLK B10 9
TNR_MICLK E20 TX2CLK- DISPLAY
PCI-AD(0-31) 10 FE-VALID C10
TNR_MIVAL AL23 RX51002CLK- AE16
PNX5100
PCI-CLK-ETHERNET 60 5 FE-SOP B9 TNR_MISTRT LOUT2_CLK_N E21 TX2CLK+ 8
B03G 61 IRQ-PCI RESET-SYSTEM 32
RESET-ETHERNET 62 B03G AM23 RX51002CLK+ AD16
B03H LOUT2_CLK_P
SSB_31391236443.1 AL19 RX51001CLK- AD19
CLK_N 1G51
7N04 B05C PCMCIA 1K00
1N00 LAN9420 AM19 RX51001CLK+ AC19 E10 TX3CLK- 33
120
1 CA-MICLK H32
CA_MICLK PNX8543 CLK_P
E11 TX3CLK+ 32
TO
CA-MDI(0-7) CA_MDI

1N02

25M
ETHERNET E12 TX4CLK- 17 DISPLAY
7K04-7K05
CONTROLLER A34

COMMON INTERFACE
CA_VSN_0 16
ETHERNET 119 MOCLKA CA-MOCLK_VS2 H31 E13 TX4CLK+
CONNECTOR CA_MOCLK
PCI-AD(0-31) MDO(0-7) CA-MDO(0-7) CA_MDO
PCI-CLK-ETHERNET 16
B03G 14 IRQ-PCI 7K03 CA-DATADIR D31
RESET-ETHERNET 15 CA_DATA_DIR B03F MEMORY
B03H SSB_31391236443.3 PCMCIA CA-DATAEN A31
B03F PNX8543 - SDRAM
CA_DATA_EN 7B00
OPTIONAL EDE1116AEBG
PCMCIA-D(0-7) PCI-AD(24-31)
B08 PNX5100 M_DQ DDR2-D(0-31)(0-15) 7B01
CONDITIONAL
7K00 EDE1116AEBG
7C00 ACCESS
7K01
PNX5100EH/M2 CA-ADDEN B31
CA_ADD_EN
B08C CONTROL M_A DDR2-A(0-12)
AF24 RESET-PNX5100 PCMCIA-A(0-14) PCI-AD(0-14)
B03H
DDR2-CLK_P
SDRAM
AB34 J8
AE13 IRQ-CA J34 CA_RDY M_CLK_P

PNX5100 68
IRQ-PCI
M_CLK_N
AB33 DDR2-CLK_N K8
1CD0

27M

B03G PNX8543 - CONTROL MIPS/FLASH/PCI B03G PCI

AF13

B08C PCI_XIO B03G PNX8543 - CONTROL MIPS/FLASH/PCI

PCI-AD(0-31) PCI-AD(0-31) PCI-AD(0-31) PCI_AD

7M00
L3 PCI-CLK-PNX5100 NAND01GW3B2BN6F
B03G PCI-CLK-OUT 3M30 PCI-CLK-PNX5100
AP28
PLL_OUT B08C

3M46
NAND-AD(0-7) <-- PCI-AD(24-31)
NAND A30 PCI-CLK-PNX8543
TRDY_CLK
FLASH 7 XIO-ACK A20
XIO_ACK
WP-NANDFLASH 19
(1G) 9 XIO-SEL-NAND B20
XIO_SEL_0

B03G CONTROL
B08B DDR2 B08B PNX5100 - SDRAM AN28 RESET-SYSTEM
IRQ-CA L34 RESET_SYS B02A B03H
GPIO_3
IRQ-PC1 U4 U3 WC-EEPROM-PNX5100_SPI-DI
7C01 GPIO_2 GPIO_2 B04C
1M09
EDE5116AJBG V2 PNX8543-LCD-PWR-ON_SPI-DI
1 USB-OC AL16 GPIO_6 B07B 1M04
PNX5100-DDR2-D(0-31) 7C02 USB_FAULT
1

EDE5116AJBG USB 2.0 2 USB20-DM AN16 L32 RXD-MIPS 2

USB_DM GPIO_4
3 2

CONNECTOR 3 USB20-DP AP16 UART

USB_DP TXD-MIPS
ON SSB 4 GPIO_5 L31 3 SERVICE
4

TO 1M10 FOR USB 2.0

DDR2-A(0-12) 1 CONNECTOR
CONNECTOR SIDE STANDBY
AD2 B03H
SDRAM P0_5
P26 PNX5100-DDR2-CLK_P J8 1M20 B03H PNX8543 - STANDBY-CONTROL / DEBUG
1 LIGHT-SENSOR AN2
P25 PNX5100-DDR2-CLK_N K8 CADC_1
2 B03H
3 RC 4D00 RC_uP AF2 P1_0 1M01
AG1 RXD-UP 3
UA_RX_0
TO IR/LED PANEL 4 LED2 AJ2
PWM_1 TXD-UP 1
AND KEYBOARD CONTROL AH5
5 UA_TX_1 FOR
B08C GPIO +3V3-STANDBY 7M81 2 FACTORY USE
6 LED1 AJ3 PWM_0 2D08 ONLY
B23 PNX5100-BL-CTRL AG2 SDM
P1_7 4
7 KEYBOARD AN3 SDM
CADC_0
RES
8 2D07
+5V P6_4 AK2 SPI-PROG
SPI-PROG

B07B DISPLAY INTERFACE B07A DISPLAY INTERFACE (COMMON) B03H PNX8543 - STANDBY-CONTROL / DEBUG
DETECT-12V 4D09 DETECT2 AD3 7D06
B01B P2_5 M24C64-WDW6P
7D07
DETECT1 AD4
B01A P2_4 RESET-NVM
P0_1 AC1 8
EEPROM
RESET-SYSTEM AH3 P3_3
B03G
W1
(8Kx8)
AV1-BLK AH1 XTAL_I
B04B P3_5

1D00
AV2-BLK_LCD-SDA AH2

27M
B04B P3_4
AV1-STATUS AP2 7D09
B04B CADC_2 W2
XTAL_O M25P05-AVMN6P
3P24 BACKLIGHT-IN BACKLIGHT-OUT AV2-STATUS AP1
B04B CADC_3
CONTROL B01B
AJ1 SPI-CLK 6
+3V3-STANDBY 7D05 SPI_CLK 512K
NCP303LSN30G AK4 SPI-WP 3
P6_5 FLASH
AK3 SPI-CSB 1 B01B DC / DC +3V3-STANDBY_+1V2-STANDBY
SPI_CSB
SPI-SDO 5
OUTP 1 RESET-STBY AF3
RESET_IN SPI_SDO
AJ4
2 AK1 SPI-SDI 2
INP SPI_SDI
1M99
3 LAMP-ON-OUT 5
GND P2_2 AE1
ENABLE-3V3 6 TO
AE4 BACKLIGHT-OUT
P2_7 B01A B01B B07A POWER
B05A HDMI 7H09 AF1 REGIMBEAU_CVBS-SWITCH BACKLIGHT-BOOST 7 SUPPLY
CEC-HDMI AG4 P1_1 B04B N.C.
CONTROL P1_2
POWER-OK 9
7H11 P2_6 AE5
TO PIN:
TDA9996 AD1 AUDIO-RESET
1H02-13 B05A HDMI_DV P0_6 B03C
1H00-13 CEC 57
1H01-13 AC5 AUDIO-MUTE
1
2

1H03-13 HDMI P0_7 B06A 1M95

TO
SWITCH P2_3
AD5 STANDBY 2 POWER
ARX-DDC-CLK 12 RX HDMI_RX SUPPLY
1H02-15
18

BRX-DDC-CLK 31
19

1H00-15
CRX-DDC-CLK 61
4x HDMI 1H01-15
DRX-DDC-CLK 79
CONNECTOR 1H03-15 18560_405_090326.eps
091014

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 67

Block Diagram I2C

I²C
B03G PNX8543 - CONTROL MIPS/FLASH/PCI B05A HDMI B02A FRONT END B08C PNX5100 - CONTROL / PCI / DEBUG B08E PNX5100 - AMBILIGHT

7600 +3V3-PER
PNX85433EH/M2A
SSB BUS
400 kHz

3M27

3M26
G32 SDA3 3M19 SDA-SSB
SDA 3
D33 SCL3 3M18 SCL-SSB
SCL 3

3H66

3H65

3CDD

3CDC
3399

3398

3CD8

3CD9
+3V3
PNX8543 ERR
ARX-5V
13 B03F PNX8543 - SDRAM 49 50 24 23 5 6 K1 K2
AMBILIGHT BUS
B03F +3V3B 30 kHz

3388

3365
3H08

3H07
7B01 1H02 1M59
EDE1116AEBG 7H11 7303 TUNER BUS 7CD0 7C00 3CDA
11 ARX-DDC-DAT 16 400 kHz L1 SDA-AMBI-3V3 3
MEMORY TDA9996 DRX3926K-XK M24C08 PNX5100EH

3388

3365
7B00 HDMI
M_DQ DDR2-D L2 3CD9 1
EDE1116AEBG 12 ARX-DDC-CLK 15 CONNECTOR 3 SCL-AMBI-3V3
HDMI DEMODULATOR 61 SDA-TUNER EEPROM PNX5100
MUX BRX-5V MICRONAS 2
M_A DDR2-A SDRAM 62 SCL-TUNER
4 TO AMBILIGHT
ERR ERR ERR ERR ERR

3H10

3H09
5 (OPTIONAL)

3317

3316
23 1H00 27 25 15 21
B05A +5V
30 BRX-DDC-DAT 16 7
7 6
HDMI 5CE5 1CE2 6
HDMI_DV

3H01

3H02
31 BRX-DDC-CLK 15 CONNECTOR 2 +3V3
1301 T1.0A
D15 DDC-SDA 6 CRX-5V HD1816AF
DDC_SDA_B

DDC_SCL_B
C15 DDC-SCL 5 MAIN B08B PNX5100 - SDRAM

3H14

3H13
1H01 TUNER
B03G PNX8543 - CONTROL 60 CRX-DDC-DAT 16 7C01
MIPS/FLASH/PCI EDE5116AJBG
HDMI ERR
B03G CRX-DDC-CLK 15 34
7M00 61 CONNECTOR 1 7C02
PNX5100-DDR2-D(0-31)
NAND01GW3B2 DRX-5V EDE5116AJBG
PCI
FLASH PNX5100-DDR2-A(0-12) SDRAM
1G

3H12

3H11
PCI_AD PCI-AD 1H03
78 DRX-DDC-DAT 16 HDMI
CONNECTOR
79 DRX-DDC-CLK 15
SIDE

B01B DC / DC +3V3-STANDBY_+1V2-STANDBY B04B ANALOG IO - SCART 1&2 B04C YPBR / SIDE IO / S-VIDEO

+3V3-PER +3V3
+5V
SET BUS
100 kHz
3M93

3M92

3F55

3F54

3G60

3G56
1M71 1G30
B33 SDA2 3M91 SDA-SET 3F56 1

10

15
12 DATA-SDA

5
SDA 2 TO
D32 SCL2 3M90 SCL-SET 3F57 3 TEMPERATURE
SCL 2 SENSOR 15 CLK-SCL

6
11
RES

3G61

3G58
ERR +3V3-PER
14 VGA
STANDBY BUS CONNECTOR 5 6
400 kHz
3M25

3M24

1M99 7G31
H33 SDA1 3M15 SDA-UP-MIPS 4202 11 WC-EEPROM-PNX5100_SPI-DI 7G32 7 M24C02
SDA 1 TO B03G
F33 SCL1 3M14 SCL-UP-MIPS 4201 10 POWER
SCL 1 EEPROM
SUPPLY
RES 256x8

3G63
B03H PNX8543 - STANDBY - CONTROL / DEBUG
+3V3
+3V3-STANDBY

B03H
3D39

3D38

AK5 3D46 SDA-UP-MIPS

MC_SDA B03G PNX8543 - CONTROL MIPS/FLASH/PCI
AL5 3D45 SCL-UP-MIPS
MC_SCL
+3V3-PER RES
STANDBY
3D56-2

5 6
7D07
AC1 RESET-NVM 3D56-1 8 7D06
PO_1 M24C64

7D09 EEPROM
ERR M25P05 (NVM)
53

512K
FLASH
+3V3-STANDBY
3D21

3D22

1M01
AG1 RXD-UP 3M74 3
UA_RX_0
AH5 TXD-UP 3M73 1
UA_TX_1 FOR
2 FACTORY USE
ONLY
B04A BOLT-ON 4
+3V3-PER
RES
3M09

3M10

1M04
L32 RXD-MIPS 4E18 RXD 3M76
3
GPIO_4
4E19 3M75 UART
L31 TXD-MIPS TXD 2
GPIO_5 SERVICE
1 CONNECTOR

18560_406_090326.eps
091014

2010-Jun-29
 Block Diagrams Q548.1E LA 9. EN 68

Supply Lines Overview

SUPPLY LINES OVERVIEW
B01B DC / DC +3V3-STANDBY_+1V2-STANDBY

B02A FRONT END B03G PNX8543 - CONTROL MIPS/FLASH/PCI

B06A CLASS-D
CN5 1M99
+12VD +3V3 +3V3 +3V3 +3V3
1 1 B01a
+12V B07a B01a
7308 5M00 +3V3-NAND
2 2 +1V2
+12V IN OUT +3V3-PER +3V3-PER
COM
3 3 5304 +1V2A B03a +AUDIO-POWER +AUDIO-POWER
GND1 +3V3-STANDBY +3V3-STANDBY B01b
B01b
4 4
GND1 +5V +5V +5V +5V
B01b B01b
5 5 LAMP-ON-OUT 7309 1M20
BL-ON_OFF B03H
3V3B 5M84 5
6 6 BACKLIGHT-OUT
CONTROL IN OUT
COM TO B07A DISPLAY INTERFACING (COMMOM)
DIM B07A 5307 3V3A 5M88 8 IR/LED
CONTROL PANEL +3V3 +3V3
7 7 BACKLIGHT-BOOST 5306 3V3D
BOOST N.C. B01a
5305 3V3E +5V +5V
8 8 B01b
B03H PNX8543 - STANDBY-CONTROL/DEBUG

4P26

4P28

4P39
A/P_DIM +5V5-TUN +5V5-TUN
9 9 POWER-OK B01b RES +VDISP-IN
B03H 7307 B07b
INV_OK
MAIN +5V-TUNER

4P29

4P30

4P31
CONTROL IN OUT +1V2-PNX85XX +1V2-PNX8541
COM B01a +12VD +12VD
POWER SUPPLY 7315 3389 ANTENNA-SUPPLY
B01b
+1V2-PNX5100 +1V2-PNX5100
B01b
+3V3-STANDBY +3V3-STANDBY
+12V +12V B01b
B01b +3V3 +3V3
CN4 1M95 RES B01a B07B DISPLAY SUPPLY
1 1 +3V3-STANDBY +3V3-PER +3V3-PER
3V3_ST B03a,g,h,
+3V3 +3V3
7201 B04a,B05a, B03a
+1V2-STANDBY +5V +5V B01a
B01b +VDISP-IN +VDISP-IN
IN OUT
COM
B03a B03A PNX8543 - POWER B07a
7P02 +VDISP-OUT
+1V2-PNX85XX +1V2-PNX85XX
2 2 STANDBY
STANDBY B03H B01a
SENSE+1V2-PNX85XX
B04A BOLT-ON
3 3 CONTROL B01A 7P03
GND1
PNX8543-LCD-PWR-ON_SPI-DI
+3V3-STANDBY +3V3-STANDBY
4 4 +1V2-STANDBY +1V2-STANDBY B01b
GND1 B01b +5V +5V
5 5 +3V3F +3V3F B01b
GND1
B01a +12V +12V
6 6 +12V 7601
+12V B01a,B02a, +1V8-PNX85XX B01b
5203
7202
5204 6217 +5V B04a,b IN OUT B03f,B05a
RES B08A PNX5100 - POWER
7 7 VOLT. COM
+12V B02a,
REG.
8 8 B03d,g,h, +1V2-PNX5100 +1V2-PNX5100
+12V B01b
B04a,b,c,
B05a,c, +3V3-STANDBY +3V3-STANDBY B04B ANALOG IO - SCART 1&2 5C60 +1V2-PNX5100-CLOCK
B07a B01b +5V +5V
+5V5-TUN +3V3 +3V3 B01b 5C61 +1V2-PNX5100-TRI-PLL1
7222 B02a B01a +3V3 +3V3
5221 +1V2-PNX5100 5612 +3V3-PER B01a 5C62 +1V2-PNX5100-TRI-PLL2
VOLT.
B03h,B08a B03b,g,h +12V +12V
REG. B01b
5600 RREF-PNX85xx 5C63 +1V2-PNX5100-TRI-PLL3
9 9 +AUDIO-POWER B05a
+VSND B03c,B06a 5615 VDDA-LVDS 5C64 +1V2-PNX5100-DDR-PLL1
B03b
GND_SND
10 10 B04C YPBR / SIDE IO / S-VIDEO 5C65 +1V2-PNX5100-LVDS-PLL
VDDA-AUDIO VDDA-AUDIO
B03d
+3V3 +3V3 5C66 +1V2-PNX5100-DLL
11 11 5621 VDDA-DAC B01a
N.C. N.C. B03d
+5V +5V CC60 SENSE+1V2-PNX5100
5622 VDDA-ADC B01b B01b

+3V3 +3V3
B01a
5C67 +3V3-PNX5100-LVDS-IN
B05A HDMI
5C68 +3V3-PNX5100-CLOCK
+3V3 +3V3
B03B PNX8543 - VIDEO STREAMS/LVDS OUTPUT B01a
5C69 +3V3-PNX5100-DDR-PLL0
5H01 VDDO_3V3
SENCE+1V2-PNX5100 SENCE+1V2-PNX5100 5C70 +3V3-PNX5100-LVDS-PLL
B08a 5H06 VDDS_3V3
VDDA-LVDS VDDA-LVDS
B03a
5H03 VDDH_3V3 +3V3F +3V3F
+3V3-PER +3V3-PER B01a 7C60
B03a +1V8-PNX85XX +1V8-PNX85XX
B03a IN OUT
+1V8-PNX5100
B08b
5H00 VDD_1V8 COM
B01A DC / DC +3V3_+1V2
B03C PNX8543 - AUDIO AMPLIFIER
B01b
+3V3-STANDBY +3V3-STANDBY

+5V +5V
SENSE+1V2-PNX85XX SENSE+1V2-PNX85XX B01b
B03a +AUDIO-POWER +AUDIO-POWER
RREF-PMX85XX RREF-PMX85XX
B08B PNX5100 - SDRAM
B01b B03a
+12V +12V 4801 +1V8-PNX5100 +1V8-PNX5100
B01b B08a
RES 1H02 3C20 PNX5100-DDR2-VREF-CTRL
5104 +12VF HDMI 3
3819 7801 AUDIO-VDD 18 ARX-5V
CONNECTOR
3C22 PNX5100-DDR2-VREF-DDR
1H00
3108

7103 7802 HDMI 2

18 BRX-5V
NCP5422ADG CONTROL CONNECTOR
CN2
14
1 +3V3 +3V3
HV1 Dual 7101-1 12V/3V3 B03a 1H03
N.C.
2
TO DISPLAY Synchronous COVERSION
HDMI SIDE
CONNECTOR
18 DRX-5V B08C PNX5100 - CONTROL / PCI / DEBUG
3 Step-Down 1 B02a,
HV1 5101 +3V3 B03a,c,d,g,h, +3V3 +3V3
Controller 1H01 B01a
7U01-2 B04b,c,B05a,b,c, HDMI 1 CRX-5V
18
B07a,b, CONNECTOR
CN3 2 B08a,c,d,e B03D PNX8543 - AUDIO
1 5105 +3V3F
HV2 B03a,B08a
2 +3V3 +3V3 B08D PNX5100 - LVDS IN / OUT
N.C. TO DISPLAY B01a
7102-1 12V/1V2
HV2
3
COVERSION +5V +5V
B05B ETHERNET
B01a
+3V3 +3V3
16 B01b +3V3 +3V3
7900 B01a
5103 +1V2-PNX85XX VDDA-AUDIO
7102-2 B03a,h IN OUT B03a 5N06 +3V3-ET-DIG
COM
15 5N07 +3V3-ET-ANA
VDDA-DAC VDDA-DAC
B03a
B08E PNX5100 - AMBILIGHT

B05C PCMCIA
B03F PNX8543 - SDRAM
B01a
+3V3 +3V3
+3V3 +3V3
B01a
+1V8-PNX85XX +1V8-PNX85XX
B03a 5K00 +3V3_BUF 1M59
3B47 DDR2-VREF-CTRL 6 TO AMBI-LIGHT
+5V +5V (OPTIONAL)
3B48 DDR2-VREF-DDR B01b
3K00 PCMCIA-VCC-VPP
+T
18560_407_090326.eps
090326

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 69

10. Circuit Diagrams and PWB Layouts

Interface Ambilight + Single DC-DC
1 2 3 4 5 6 7 8 9 10 11 12 13

A 1 2 3 4 5 6 7 8 9 1100 A6 F123 E2 A
1101 A7 F124 E2
1M59 C2 F125 B3
1M84 A2 F126 A2
1M85 A2 I100 A6
1M90 D2 I101 C6
INTERFACE + SINGLE DC-DC 5107 RES
2100 A6
2101 B5
I102 C6
I103 C6
30R 2102 C6 I104 D9
B 5108 RES
+24VF +16V
2103 D6 I105 D5 B
2104 D5 I106 D7
A A

5100 RES

5101 RES
30R 2105 D9 I108 D6
2106 D9 I109 A8

30R

30R
1100 I100 5102
F126 +24V 2107 E9 c001 E2
SPI-LATCH2CONN T 3.0A 32V 10u
F107
1101 * I109 2108 D3 c002 E2
* 2109 E3

2100

220n
1M85 1M84
2.0A T 63V 3100 B5
1 1
F101 SPI-CLOCK-BUF
* * 3101 C5

5103

5104
30R

30R
F102 SPI-DATA-OUT
C 2
3
2
3
F103
F104
SPI-DATA-RETURN
SPI-LATCH1CONN
3102 D6 C
4 4 3103 D9
F105 PWM-CLOCK-BUF +12V
5 5 3104 D6
is prohibited without the written consent of the copyright

6 6 F106 +3V3
All rights reserved. Reproduction in whole or in parts

3100 3105 D5
B 7 7
F108 BLANK-BUF
* * B 3106 D5

5105

5106
F109

30R

30R
8 8 EEPROM-CS 0R1
F110 TEMP-SENSOR RES 3107 D5
9 9
10 10 F111 PROG 3108 E9
F112 VLED1 +16V
11 11 3109 D2

100R
2101

3112
10n
12 12 7100
F113 F114 NCP3163BMNR2G 3110 D3

3
D 13
14
13
14
F125
VLED2
VCC
Φ
3111 E8 D
15 16 15 16 3112 B6
4 15 5100 A8
LPK_SENSE LVI_OUT
502382-1470 502382-1470 5101 A8
5 10 VSW
3101 I101 DRV_COL 5102 A7
11
SPI-LATCH1 47R
6 SWI_EMIT 12 5103 B8
9101 SPI-LATCH1CONN 7 13 5104 B8
C 9102 (RES) 8 SWI_COL
C 5105 B8
owner.

9 20
5106 B8

SS24
6100
9103(RES)
E 9104 SPI-LATCH2CONN
2102 I103
14
BOOT_IN
21
22 5107 A6 E
SPI-LATCH2 23 5108 A6
2n2
1M59 17 24 6100 C8
1
F115 SCL I102 16 VFB 25 7100 B7
1 2
+16V I108 VIA 26
2
1 27
9101 C3
3 F116 SDA TIM_CAP 9102 C3

3103
3109 RES 28

3K3
4 F117 CONTROL1
F118 100R 3110 RES CONTROL2 2 29 9103 C3
5 NC

2104

100n

2103

220p
3102
100R 30 9104 C3

15K
6 F119 +3V3

330R
3104
F120 31 F101 B3
7 I104
F D D F102 B3 F
2108

100p
RES

1735446-7 GND GND_HS

I105 F103 B3

2105

100n
2106

100n
18

19
1%
F104 B3

3105

3106

3107
1M0
F105 B3

33K

12K
F106 B3
1M90 I106 F107 A7
F121 F108 B3
1 +24V
F109 B3

1%
F122
2
3
F123 +24V F110 B3
G G

100K
2109

100p

3111

3108

2107

100n
3K3
RES

F124 F111 B3
4
5 +24V F112 B3
6 F113 B3
1735446-6 F114 B5
E E F115 C2
F116 D2
F117 D2
c001 F118 D2
+12V VLED1
F119 D2
H c002
F120 D2 H
+16V VLED2 F121 E2
F122 E2

1 2 3 4 5 6 7 8 9

I STUFFING DIVERSITIES FOR DC/DC INTERFACE AMBI 2K9 I

See the stuffing diversities table in the case of components marked with one star (*)
DC/DC INTERFACE 1101 1M85 5103/5104 5105/5106 VLED1 VLED2
CHN SETNAME

CLASS_NO 1 08-06-19
3104 328 58341 in in in out 24V 16V DC-DC INTERFACE 2 08-08-06

J 3104 328 58351 out out out in 12V 12V 08-06-19 1 3 08-09-18 J
3104 313 6325
3104 328 58361 out out out in 16V 16V 08-08-06 2 AMBI 2K9 4 08-10-23

3104 328 58371 out out out out 12V 16V 08-10-23 3 5 08-12-06

NAME Peter Van Hove SUPERS. 3 ** 130 1 *** A3

CT MGr CHECK ******** DATE 08-06-06 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13
18310_600_090305.eps
090305

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 70

Interface Ambilight Dual DC-DC

1 2 3 4 5 6 7 8 9 10 11 12 13

A A
2200 A4 I213 D5
1 2 3 4 5 6 7 8 2201 A4 I214 D4
2202 A5 I215 D3
2203 A5 I216 B5
2204 B3 I217 B4
DUAL DC-DC 2205 B6
+24VF 2206 B1
B 2207 B2
2208 B7
B
A A 2209 B7
2210 B8

100u 35V

100u 35V
2211 C3

2200

2201

220n

2202

220n
2203
2212 C4
RES RES
2213 C6
3200 I200 I201 3201 2214 C3
VSW 2215 C6
C 6R8
** 2204 7200 2205
6R8
2216 C2 C
3202
** * 3203
*

14
TPS54283PWP 2217 C7

1
PVDD1 PVDD2
**5200 6R8 47n F204 Φ F203 47n 6R8 (VLED1) 2218 D1
is prohibited without the written consent of the copyright

(VLED2) I204 2 13 I205

F200 BOOT1 BOOT2 5201
* 2219 D2
All rights reserved. Reproduction in whole or in parts

3 12 +12V
+16V SW1 SW2 2220 D7
B **
10u
5
EN1 EN2
6
10u B 2221 D3
7 8
* * RES RES
*

100u 35V

220u 25V
** ** ** FB1 FB2

SS24

SS24
2206

2207

6200

3204

3205

6201

2208

2209

2210
2222 D5

10R

10R
I206

4u7

22u

22u
I217 9 16 I216 2223 D8
ILIM2
10 17
I208 SEQ
* 2224 D8

9201
11 18
D BP
19
I209 3200 A3
3201 A6
D
**
20
*

2211

2213
21 3202 B3
**

1n0

1n0
9202
VIA2 22 3203 B6
23
24
3204 B3
I211 I210 3205 B6
F207 25
3206 D3
C ** 26
* C

2214

2215
GND GND_HS 3207 D2

1n0

1n0
owner.

2212

15
4u7
3208 D7
E 3209 D5
3210 D3
E
3211 D3
RES
2216 RES I212 2217 F201 3212 D6
+16V +12V 3213 D6

RES
22n 22n 5200 B2

RES 3206
3207
** 3208
* 5201 B7

3K3

3K3
3209
2218 RES

6200 B2
2219 RES

68K 47K
** ** *

*
*
1% 1% 1% 6201 B7
F F
3210

3211

3212

3213

2220
3K9

33K

3K3

33K
4u7

4u7

10u
I214 I213 7200 B4
D D

1%
9201 B5

2222 RES
RES 2221
9202 C4

22n

22n
VLED1
F200 B2
I215

F201 C7
* *

2223

2224
10u

10u
F202 D3
F202 F203 B5
F204 B4
F207 C4
7200 : TPS54383 in case of 16V or dual dc-dc converter
G I200 A3
I201 A6
G
The components marked with one star (*) belong to the 12V versions (3104 328 58351, 3104 328 58371). I204 B2
I205 B6
E The components marked with two stars (**) belong to the 16V versions E I206 B6
I208 B3
(3104 328 58331, 3104 328 58341, 3104 328 58361, 3104 328 58371). I209 B6
I210 C6
I211 C3
H I212 C3 H
1 2 3 4 5 6 7 8

I I

CHN SETNAME

CLASS_NO 1 08-06-19

DC-DC INTERFACE 2 08-08-06

J 08-06-19 1
3104 313 6325 3 08-09-18 J
08-08-06 2 AMBI 2K9 4 08-10-23

08-10-23 3 5 08-12-06

NAME Peter Van Hove SUPERS. 3 130 2 A3

CHECK DATE 08-06-09 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13
18310_601_090305.eps
090305

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 71

Interface Ambilight Microcontrollerblock

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A A

1300 E2 9303 F3
1 2 3 4 5 6 7 8 9 10 11 1301 H5 9305 G1
1302 C4 9307 H4
B 2300 A3
2301 A4
C300 B8
F300 A5
B
2302 A5 F301 A8
MICROCONTROLLER 3310 2303 A4 F302 A10
2304 B8 F303 B11
7301
LD2985BM18R
RES +3V3 +3V3
100K RES 2305 B10 F304 C4
2306 B9 F305 C4
A F300
+3V3
A 2307 B10 F306 D4

1%

1%
1 5 +1V8
+3V3 IN OUT 2308 D4 F307 F3

3311
C C

3312
I303 7300-2

1K5

1K5
3
INH BP
4 LM393PT 2309 D5 F308 F3

2300

2301

100n

2302

4u7
1u0
F301 2310 F6 F309 G6

8
COM 5
2311 F7 F310 G6

2303
7

10n
F302 2312 F7 F311 G8
6

2
2313 F7 F312 G8

RES

4
2304

3314
2314 F7 F313 G8

-T 10K

10n
3313
2315 F7 F314 G5

10K
+3V3
F303 2316 F8 F315 H4
D 2305 2318 G2 F316 C9 D
B B 2319 G6 F317 F1

C300
10n RES
2320 H5 F320 E9

1K5 1%
3315

2306

100n

2307
+3V3

3316
10n
2321 H4 I300 E9
47K RES 2322 H4 I302 F9
7300-1
2323 H4 I303 A4

1K5 1%
LM393PT
2324 H4 I304 C10

RES
3317

8
3 3300-2 D5 I305 E6
E F316
2
1
I304 3318
3300-3 D7 I306 E7 E
+3V3 +3V3 10K RES 3300-4 D7 I307 G6

4
3301-1 D6 I308 G2

1K8 1%
3319
+3V3 3301-2 E5 I309 G5

RES
3301-3 E6 I310 D5
C C

3320
10K

10K
3321
3301-4 D7 I311 E7
3302-1 D7 I312 E7
RES
1302
F304 3302-2 D6 I313 E7

10K

10K

10K
3302-3 E6 I314 F7

10K

10K
F F

10K

10K

10K
10K

10K
1

5
2 F305 3302-4 D6 I315 F7
3 3303-1 E6 I316 F8
4 5 3303-2 D6 I317 F6

3302-2

3302-4

3301-1
3303-2

3304-1

3301-4
F306

3300-3

3304-2

3304-4
2

4
3303-3 E6 I318 F7

10K

10K
B3B-PH-SM4-TBT(LF)

RES
3304-1 D6 I319 F5

7
100R

100R
3322

3323

3324
3304-2 D7 I320 F8
3304-3 D7 I321 F6

7 3300-2

10K 3325
3304-4 D7 I322 G5

2
G D D 3305-1 E7 G
3305-2 G8

RES
10K
10K
10K

10K

10K

10K

10K

10K

10K

10K

10K
I310

8
2308

100p

2309

100p
3305-3 G9
3305-4 G8
3306-1 E8

3302-1

3300-4

3304-3

3305-1
3326

3327
3302-3
3301-2 2

1
3301-3
3306-2 E8

3303-1

3303-3
3306-3 E8

3328
7302

19
43

31

3329
LPC2103FBD48 3306-4 E8

7
H VSS Φ VSSA 3307-1 E8
H

I305
11 13

10K
X1 P0.0|TXD0|MAT3.1 3307-2 F8
MICRO- P0.1|RXD0|MAT3.2
14
I306 3307-4 F8
16M9

I300
12 CTRL 18 3306-3 3 6 CONTROL1
X2 P0.2|SCL0|CAP0.0
E E 3308-1 F8
1300

21 RES 3330 100R PWM-CLOCK-BUF

P0.3|SDA0|MAT0.0 I311
P0.4|SCK0|CAP0.1
22 3331 100R SPI-CLOCK-BUF 3308-2 F8
20 23 I312 3306-2 2 7 100R SPI-DATA-RETURN 3308-4 F8
RTXC1 P0.5|MISO0|MAT0.1
RES 9300 25 24 3306-1 1 8 100R SPI-DATA-OUT
RTXC2 P0.6|MOSI0|CAP0.2 3309-1 F8
28 3306-4 4 5 100R SPI-LATCH1
3332 P0.7|SSEL0|MAT2.0 F320 3309-4 F8
26 29 3307-1 1 8 100R SPI-LATCH2
RTCK P0.8|TXD1|MAT2.1 I313 3310 A10
I +3V3 10K
9301
RES
4
VBAT
P0.9|RXD1|MAT2.2
P0.10|RTS1|CAP1.0|AD0.3
30
35
3338
3307-4 4 5
100R
100R
PWM-CLOCK-BUF
TEMP-SENSOR TEMP-SENSOR 3311 A8 I
36 I314 3307-2 2 7 100R EEPROM-CS 3312 A10
F307 P0.11|CTS1|CAP1.1|AD0.4
RES 9302 37 3308-4 4 5 100R BLANK-BUF
P0.12|DSR1|MAT1.0|AD0.5 I315 100R
3313 B8
RES 9303 27 41 3308-2 2 7 PROG
DBGSEL P0.13|DTR1|MAT1.1 100R 3314 B8
44
+3V3 P0.14|DCD1|SCK1|EINT1 I316 3315 B10
45 3308-1 1 8 CONTROL2
+3V3 F308 P0.15|RI1|EINT2
3316 B10
is prohibited without the written consent of the copyright

6 46 100R
RST P0.16|EINT0|MAT0.2 I317 I318 I302
F 47 I319 3309-4 5 4
F
All rights reserved. Reproduction in whole or in parts

P0.17|CAP1.2|SCL1 SCL 3317 B8

48 3309-1 8 1 100R SDA
P0.18|CAP1.3|SDA1 3318 C10
3339

2314 RES
J 1 100R
J
1K0

P0.19|MAT1.2|MISO1 I320 3319 C8

3333

2
10K

7303 P0.20|MAT1.3|MOSI1 I321 3320 C5

2310

100p
2311

100n
2312

100p
2313

100p

100p
2315

100p
2316

100p
NCP303LSN10T1 3
P0.21|SSEL1|MAT3.0
2
IN P0.22|AD0.0
32 3321 C5
1 33 3322 D5
F317 RST P0.23|AD0.1
3 34
GND P0.24|AD0.2 3323 D5
9305 RES

38
I308 P0.25|AD0.6 I307 3324 D7
5 4 39 UD-MD
CD NC P0.26|AD0.7 I322 3325 D6
8 F309
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
9 3326 D6
F310
2318

100n

K P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
10
15
F311
F312
4
3305-4
5
10K 3 6
3327 D6
3328 E5
K
G P0.31|TDO
16
22R
3334 F313 2
3305-2
7
10K
3305-3 10K +3V3 G 3329 E5
VDD_1V8 VDD_3V3 VDDA 3330 E8
owner.

3331 E8
5

17
40

42

3335 F314
I309 3332 E3
100R 3333 F2
1
2

2319

100p

3336
10K

10K
3337
3334 G5
2320

100n

SKHUBHE010

3335 G5
L 9307
L
1301

3336 G6
RES

+3V3 F315 3337 G6

+1V8 3338 E8
3339 F1
3
4

H H 7300-1 B9
2321

100n
2322

100n
2323

100n

2324

100n

7300-2 A10
7301 A4
7302 E3
M 7303 F2 M
9300 E3
9301 F3
9302 F3

1 2 3 4 5 6 7 8 9 10 11
N N

O O
CHN SETNAME

CLASS_NO 1 08-06-19

DC-DC INTERFACE 2 08-08-06

08-06-19 1 3 08-09-18
P 3104 313 6325
08-08-06 2 AMBI 2K9 4 08-10-23

08-10-23 3 5 08-12-06 P
NAME Peter Van Hove SUPERS. 3 130 3 A2

CHECK DATE 08-06-09 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_602_090305.eps
090410

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 72

Layout DC/DC Interface Ambilight

Personal Notes:

1M59
1302 5201 2208 1M85
2209
3338

6201

2220

2300
9104

2203 2210

3331
2310
7301

2322
2315
9103

7200
2301

9102
3307 9101
2202 2302 3306

2303
2321

2316
3308

2311
2201

2218 2323

3309
2319
3324

2200 2206
9201 3326
1101

2312

1301
9202

2219
1M90

6200

2223

2224
5102
1100

5200 2207

1M84

F115

F102 F108 2108 F119

F103
F106 F109
c001
I302 F116
F101 F113

F105
F110 F111
I300

F122
3109 F117
F307
F126

3110
5106 5103
9302
3332
9300

F118
F112 F304
9303

c002
3330

5105 5104
3321

3320

F306 I210 I205 F120

I311
3305

3300 3322 3323 2215 2213

3334

3205
3304 F312
I305 2308 2309 2212 I209
I306

F313
I312
3209

F305 I213
2318
F311

F207

3201
3203

I317
2222
1300

F201 F203 I201

3213
7303 I308

6100
I313

I303 2205
3212
I206

I217

F310 3208
F308

7302
I310

3337 2217
F309

3336

3204
3207
F300

3333
3339
9305

F317
9301 F200 2216
3303

I105
3210
I216

I321

2106
2104

3105 3200
I314

I204
3211
I315

3106 3202
I102

I104

I318
I320 2313 2105 3206 F123
I212

3107 2204 F107

I322

2102
3104
3103

3325 2221
F320

I307
3329
2107 I103
5107
F202

I319 F204 I200

I214
3302 3108
2314 3327
3301 2324 9307
F315
I106
3111

I316 3328 I211 5108

2320
3313

I208
C300
2304
3314
3311

2214 2211
F301

I309 3335 F314

2100
F125

5100
2307 3312

F302
F303

7100 I109
3310
3318
3316
3315
2305

7300 5101 2109

F114

I304
3102
2103

F124
2306

I100
I108
3317 3112

3100
F316
I101

F104
F121
3319 I215 2101
3101

10000_012_090121.eps
090121

3104 313 6325.5 18310_550_090309.eps

090729

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 73

6 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER BLOCK LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101

1%

1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT

3135

3136
F121 9111 SPI-DATA-IN SPI-DATA-RETURN 9108 SDA +1V8
2 7116-2 2111 G4 C140 B10

1K5

1K5
2101

2102

100n

2103
C RES 3 4
C

4u7
F122

1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116

8
2113 H7 F102 F5

2104
F124 9110 COM 5

10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5

2
7

RES
F127 RES EEPROM-CS

4
8 2116 F9 F105 D7

2105

3137
-T 10K
F128

10n
TEMP-SENSOR

3111
9 2117 F9 F106 B12
F129 PROG
10

10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D

C140
9112
9114

2125

33p
14 1105 10n RES 2121 H6 F112 G8

1K5 1%
10u 35V

10u 35V
15 16 VLED1 VLED1-F 3138 2122 F9 F116 A10
2127

2128

2129

2107

100n

2108
+3V3

3139
1u0

10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11

1K5 1%
LM393PT 2125 B3 F120 A1

RES
3140
2126 F10 F121 A1

8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E

4
2

1K8 1%
3 SDA 2130 F2 F125 B1

3123
+3V3
C C

RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1

3107
10K

10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1

10K
10K

10K

10K

10K

10K

10K
10K

10K
PROG
10 3102-2 D9 F131 B1

5
F 11 VLED1 F105
3102-3 E9 F132 B1 F

10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1

3105-2 2

3106-2 2

3104-1 1

3102-1 1

3104-4 4

3101-3 3

4
14

10K
RES
10K
15 16 3103-2 G10 F135 E1

3102-2

3102-4
7
100R

100R
3109

3110

3105-4

3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1

10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G

10K
3104-3 E8 I110 G8

10K
RES

10K
10K
10K

10K

10K

10K

10K

10K

10K
3104-4 D9 I111 G8

8
5
2109

100p

2110

100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10

1
3114

3115
3104-2 2

3104-3 3

3
4
3116

3103-1
3105-4 D8 I124 E11

3102-3
3101-4
3105-1
3105-3

3106-1

3106-3
7102 3106-1 E8 I125 E11

19
43

31

3117
LPC2103FBD48

7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H

10K
X1 P0.0|TXD0|MAT3.1
E 16M9 12
X2
MICRO-
CTRL
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
14
18 3124-4 4 5 I124 CONTROL-1
E 3107 C7
3108 C7
1101

21 3128 100R PWM-CLOCK-BUF

OUT P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
22 3129 100R SPI-CLOCK-BUF
3109 D7
1M84 20 23 3124-1 1 8 100R SPI-DATA-RETURN 3110 D7
RTXC1 P0.5|MISO0|MAT0.1
F133 SPI-CLOCK-BUF 9101 25 24 3124-2 2 7 100R SPI-DATA-IN 3111 B10
1 RTXC2 P0.6|MOSI0|CAP0.2
F135 SPI-DATA-OUT 28 3124-3 3 6 100R SPI-LATCH 3112 D9
2 3118 P0.7|SSEL0|MAT2.0
F136 SPI-DATA-RETURN 26 29 3125-1 1 8 100R I125 SPI-LATCH-2 3113 D8
3 RTCK P0.8|TXD1|MAT2.1
F139 SPI-LATCH +3V3 10K RES 30 3142 100R
4 P0.9|RXD1|MAT2.2 3114 E8
I 5
6
F137
+3V3
PWM-CLOCK-BUF 9102
F102
4
VBAT P0.10|RTS1|CAP1.0|AD0.3
P0.11|CTS1|CAP1.1|AD0.4
35
36
3125-2
3125-4
2
4
7
5
100R
100R
TEMP-SENSOR
EEPROM-CS
TEMP-SENSOR
3115 E8 I
F138 BLANK-BUF RES 9103 37 3126-2 2 7 100R BLANK-BUF 3116 E8
7 P0.12|DSR1|MAT1.0|AD0.5
F134 EEPROM-CS 9104 27 41 3126-4 4 5 100R PROG 3117 E7
8 DBGSEL P0.13|DTR1|MAT1.1
TEMP-SENSOR RES 44 100R 3118 E5
9 +3V3 P0.14|DCD1|SCK1|EINT1
F 10
11 VLED1
PROG
+3V3 F104
6
RST
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
45
46
3126-1 1 8
100R
I126 CONTROL-2
F 3119 F4
3120 F5
is prohibited without the written consent of the copyright

47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts

13 VLED2 P0.18|CAP1.3|SDA1 SDA

2130

3119

2122 RES

2124 RES
1 100R 3124-1 E11

2114 RES
10K
1u0

14 P0.19|MAT1.2|MISO1
3120

J 2
J
10K

15 16 7110 P0.20|MAT1.3|MOSI1 3124-2 E11

100p
2115

100p
2116

100p
2117

100p

100p
2123

100p

100p
2126

100p
2131

100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES

38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G G
2111

100n

SPI-DATA-OUT 10 I110 I113 3103-4 5

2 P0.29|TCK|CAP2.2
3126-4 F11
K 3
4
SPI-DATA-RETURN
SPI-LATCH
P0.30|TDI|MAT3.3
P0.31|TDO
15
16 3130
I114
I115 3103-2
4
7
10K 3103-3
3
6
10K +3V3 3127-1 F11 K
PWM-CLOCK-BUF 2 10K 3127-4 F11
5 22R
+3V3 VDD_1V8 VDD_3V3 VDDA
6 3128 E11
5

17
40

42

BLANK-BUF
owner.

7 3131 F112

2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R

100p

3132
3131 G7

10K

10K
3133
10 PROG

2112

100n

9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119

100n
2120

100n
2121

100n

2113

100n

3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

1X03
REF EMC HOLE

O O
CHN SETNAME
1

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 2008-10-27
P 8204 000 8857
2008-08-08 2 2K9
2008-10-27 3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_610_090305.eps
090730

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 74

6 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER BLOCK LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B 9208 RES

+3V3
2218 C12
2219 D12
B
+3V3 +3V3
7201-1 2220 E9

14
2214

100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219

3213

3210
3 PWM-CLOCK-BUF

10K

10K
3207 F205 3204 B7
+3V3 1 100R
EN 3205 C5

2201

2217

100p
1K0 RES

33p
7212 3207 B9

7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6 (64K) 7201-4 3214 H6
C +3V3

2209

3203
74HCT125PW

10K
3215 H6

33p

14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D

2202

2218

100p
GND 1K0 RES 3219 B11

33p
7210

7
3220 C11

10K RES
PDTC144EU 4
3 9211
3221 H11

3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E

14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R

2203

2219

100p
1K0 RES 7201-4 B10

33p

7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9

14
74HCT125PW
9 9210 B10
3121 8 9211 C9
SPI-DATA-RETURN F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10

2220 RES
100R 9213 D9

7
9214 D10

100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9

F F
I +3V3
I
2216 2215

1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts

7215

28
TLC5946PWP

J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
owner.

XLAT 10
18 F215
11
H H

3224

3221
4 19

3K3
SPI-CLOCK-BUF PWM-B2

3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS

470R
2211

3222
1

29

30
31
32
33
33p

SML-310
6216

M I I M
+3V3

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 2008-10-27
P 8204 000 8857
2008-08-08 2 2K9
2008-10-27 3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_610_090305.eps
090730

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 75

6 LED Ambilight LEDs

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5

9307

9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7

5
3328 G4 9325 F10
D D

9309-2

9309-1

9309-4

9310-2

9310-4

9310-1

9312-4

9312-3

9312-1

9313-1

9313-2

9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301

9302

3332 F4 F302 G5

4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5

E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7

7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12

9320-1 8

9320-4 5

9320-2 7

6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13

9306-4

9306-1

9306-3

9319-1

9319-4

9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G

3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3346 3350 3342 3357 D13
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331

3301
I 7307 3371 F1
I
10K

10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317

9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332

3303
3385 F1
10K

10K
560R 1K5 3320 3366
is prohibited without the written consent of the copyright

3373 3389 3386 F1

All rights reserved. Reproduction in whole or in parts

1K5 560R 3387 F1

560R 1K5 3321 3367 3388 F1
J 3374 3390 PWM-B1 PWM-B2
Place jumper 9325, 9326, 9327
1K5 560R 3389 F1 J
560R 1K5 if VLED < 17V 3322 3368 3390 G1
VLED1-F VLED1-F
3391 3391 G1
1K5 560R 7000 C2
G 1K5 F302 F327
RED-2
3323 G 7001 C3
Place jumper 9314, 9316, 9317 7002 C4
3325

3304
7305
10K

10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314

9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326

3306
10K

10K
7307 F4
owner.

7315 G9

8
7316 H10
PWM-R1 PWM-R2

9311-4

9311-3

9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L

1
GREEN-2 9303-1 C10
3327

3307
7306
10K

10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316

9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330

3309
10K

10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N

1 2 3 4 5 6 7 8 9 10 11 12 13

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 2008-10-27
P 8204 000 8857
2008-08-08 2 2K9
2008-10-27 3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_612_090305.eps
090730

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 76

Layout 6 LED Ambilight

3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108

3107
9313

2129 2128

9113

9109
9112
9111
2125

3110
3120

1M83 1M84
3128

3317
3316
3315
3313
3312
3311
3310

3335
3345
3348
3351
3119
3129 9315
2101 9121
3132

6216

3314
3320
3319
3318
3323
3322
3321
3221
3224

2103
2102
2211
3216
3133

9102

3117
3114

3113
3138 3136

7101

3111
C140
3106 3127
2106 3139

7215

2105
3137
I110

2111
3222
7110 2209 2108

2104
2119
1101 2117

9110
2130
9114

7212 7210

7209
9107
2202
9302

2127
I113
3342 3103 I111 2116
2107
7000

7001

7002

7003

7004

7005
3339 3115

9106
3131

3140 3135
7116
3126

1105
I114

3306
3305
3304

3303
3302
3301

3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116

3332
7307 3334
3331
3343 3373 3356 3391 2203

9325

9327
3220 3212

9326
2120 9119 2214

7315

7317

7316
2113

3209 9210 9214

3346 3372 3350 3386 9212

7102
9308

3211

3204

3123
9317

3210
3333
3327
3330
2218
3349 3371 3347 3387

2210
7201
2123

7214

3326
3328
3325

3104
9307 2124 3134

2122
3352 3370 3344 3388

9208
3219

3102
2216 2121 3141
3355 3341 3353

9213

3142
3207

7306
3214 2215 2131

9301

3217

9311
3337

7305
9211

9316
2217 9209

9312

9303

9319

9304
3203 3205

3218

3215

9305

9309

9320

9318

9310
9103
3118
9101
2114
9314

9306
9108

2201
3336

2220

2115
3112

2118
9104
3223 2219 3101 3125 3105

F135 F132 F120

F130
F346
F215 F107 F108 F105 F127 F123
F348 F347 F349
F214

1M2A 1M1A
F139 F122
F126

I126
F345
F116

F106

F344 F209 F104 I124 F212

F101
F109
F213 F137
F128

F131

F129

F124
F121

F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205

F341
F117 F307
F204 F342
F304 F302

18310_551_090309
3104 313 6313.3 090309

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 77

8 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101

1%

1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT

3135
9111 9108

3136
F121 SPI-DATA-IN SPI-DATA-RETURN SDA +1V8
2 7116-2 2111 G4 C140 B10

1K5

1K5
2101

2102

100n

2103
C F122 RES 3 4
C

4u7
1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116

8
2113 H7 F102 F5

2104
F124 9110 COM 5

10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5

2
7

RES
F127 RES EEPROM-CS

4
8 2116 F9 F105 D7

2105

3137
-T 10K
F128

10n
TEMP-SENSOR

3111
9 2117 F9 F106 B12
F129 PROG
10

10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D

C140
9112
9114

2125

33p
14 1105 10n RES 2121 H6 F112 G8

1K5 1%
10u 35V

10u 35V
15 16 VLED1 VLED1-F 3138
+3V3 2122 F9 F116 A10
2127

2128

2129

2107

100n

2108

3139
1u0

10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11

1K5 1%
LM393PT 2125 B3 F120 A1

RES
3140
2126 F10 F121 A1

8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E

4
2

1K8 1%
3 SDA 2130 F2 F125 B1

3123
+3V3
C C

RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1

3107
10K

10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1

10K
10K

10K

10K

10K

10K

10K
10K

10K
PROG
10 3102-2 D9 F131 B1

5
F 11 VLED1 F105
3102-3 E9 F132 B1 F

10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1

3105-2 2

3106-2 2

3104-1 1

3102-1 1

3104-4 4

3101-3 3

4
14

10K
RES
10K
15 16 3103-2 G10 F135 E1

3102-2

3102-4
7
100R

100R
3109

3110

3105-4

3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1

10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G

10K
3104-3 E8 I110 G8

10K
RES

10K
10K
10K

10K

10K

10K

10K

10K

10K
3104-4 D9 I111 G8

8
5
2109

100p

2110

100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10

1
3114

3115
3104-2 2

3104-3 3

3
4
3116

3103-1
3105-4 D8 I124 E11

3102-3
3101-4
3105-1
3105-3

3106-1

3106-3
7102 3106-1 E8 I125 E11

19
43

31

3117
LPC2103FBD48

7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H

10K
X1 P0.0|TXD0|MAT3.1
E MICRO- P0.1|RXD0|MAT3.2
14
E 3107 C7

16M9
12 18 3124-4 4 5 I124
X2 CTRL P0.2|SCL0|CAP0.0 CONTROL-1 3108 C7
1101

21 3128 100R PWM-CLOCK-BUF

OUT P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
22 3129 100R SPI-CLOCK-BUF
3109 D7
1M84 20 23 3124-1 1 8 100R SPI-DATA-RETURN 3110 D7
RTXC1 P0.5|MISO0|MAT0.1
F133 SPI-CLOCK-BUF 9101 25 24 3124-2 2 7 100R SPI-DATA-IN 3111 B10
1 RTXC2 P0.6|MOSI0|CAP0.2
F135 SPI-DATA-OUT 28 3124-3 3 6 100R SPI-LATCH 3112 D9
2 3118 P0.7|SSEL0|MAT2.0
F136 SPI-DATA-RETURN 26 29 3125-1 1 8 100R I125 SPI-LATCH-2 3113 D8
3 RTCK P0.8|TXD1|MAT2.1
F139 SPI-LATCH +3V3 10K RES 30 3142 100R
4 P0.9|RXD1|MAT2.2 3114 E8
I 5
6
F137
+3V3
PWM-CLOCK-BUF 9102 4
F102
VBAT P0.10|RTS1|CAP1.0|AD0.3
P0.11|CTS1|CAP1.1|AD0.4
35
36
3125-2
3125-4
2
4
7
5
100R
100R
TEMP-SENSOR
EEPROM-CS
TEMP-SENSOR
3115 E8 I
F138 BLANK-BUF RES 9103 37 3126-2 2 7 100R BLANK-BUF 3116 E8
7 P0.12|DSR1|MAT1.0|AD0.5
F134 EEPROM-CS 9104 27 41 3126-4 4 5 100R PROG 3117 E7
8 DBGSEL P0.13|DTR1|MAT1.1
TEMP-SENSOR RES 44 100R 3118 E5
9 +3V3 P0.14|DCD1|SCK1|EINT1
F 10
11 VLED1
PROG
+3V3 F104
6
RST
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
45
46
3126-1 1 8
100R
I126 CONTROL-2
F 3119 F4
3120 F5
is prohibited without the written consent of the copyright

47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts

13 VLED2 P0.18|CAP1.3|SDA1 SDA

2130

3119

2122 RES

2124 RES
1 100R 3124-1 E11

2114 RES
10K
1u0

14 P0.19|MAT1.2|MISO1
3120

J 2
J
10K

15 16 7110 P0.20|MAT1.3|MOSI1 3124-2 E11

100p
2115

100p
2116

100p
2117

100p

100p
2123

100p

100p
2126

100p
2131

100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES

38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111

100n

SPI-DATA-OUT 10 I113 3103-4 5

2 P0.29|TCK|CAP2.2
3126-4 F11
K 3
4
SPI-DATA-RETURN
SPI-LATCH
P0.30|TDI|MAT3.3
P0.31|TDO
15
16 3130
I114
I115 3103-2
4
7
10K 3103-3
3
6
10K +3V3 3127-1 F11 K
PWM-CLOCK-BUF 2 10K 3127-4 F11
5 22R
+3V3 VDD_1V8 VDD_3V3 VDDA
6 3128 E11
5

17
40

42

BLANK-BUF
owner.

7 3131 F112

2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R

100p

3132
3131 G7

10K

10K
3133
10 PROG

2112

100n

9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119

100n
2120

100n
2121

100n

2113

100n

3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

1X03
REF EMC HOLE

O O
CHN SETNAME
1

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_500_090403.eps
090410

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 78

8 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B +3V3 +3V3
9208 RES

+3V3
2218 C12
2219 D12
B
7201-1 2220 E9

14
2214

100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219

3213

3210
3 PWM-CLOCK-BUF

10K

10K
3207 F205 3204 B7
1
+3V3 EN 100R 3205 C5

2201

2217

100p
1K0 RES

33p
7212 3207 B9

7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3

2209

3203
74HCT125PW

10K
33p
3215 H6

14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D

2202

2218

100p
GND 1K0 RES 3219 B11

33p
7210

7
3220 C11

10K RES
PDTC144EU 4
3 9211
3221 H11

3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E

14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R

2203

2219

100p
1K0 RES 7201-4 B10

33p

7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9

14
74HCT125PW
9 9210 B10
3121 9211 C9
SPI-DATA-RETURN 8 F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10

2220 RES
100R 9213 D9

7
9214 D10

100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9

F F
I +3V3
I
2216 2215

1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts

7215

28
TLC5946PWP

J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
owner.

XLAT 10
18 F215
11
H H

3224

3221
4 19

3K3
SPI-CLOCK-BUF PWM-B2

3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS

470R
2211

3222
1

29

30
31
32
33
33p

SML-310
6216

M I I M
+3V3

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_501_090403.eps
090410

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 79

8 LED Ambilight LEDs

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5

9307

9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7

5
3328 G4 9325 F10
D D

9309-2

9309-1

9309-4

9310-2

9310-4

9310-1

9312-4

9312-3

9312-1

9313-1

9313-2

9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301

9302

3332 F4 F302 G5

4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5

E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7

7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12

9320-1 8

9320-4 5

9320-2 7

6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13

9306-4

9306-1

9306-3

9319-1

9319-4

9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G

3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3342 3357 D13
3346 3350
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331

3301
I 7307 3371 F1
I
10K

10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317

9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332

3303
3385 F1
10K

10K
560R 1K5 3320 3366
is prohibited without the written consent of the copyright

3373 3389 3386 F1

All rights reserved. Reproduction in whole or in parts

1K5 560R 3387 F1

560R 1K5 3321 3367 3388 F1
J 3374 3390 PWM-B1 PWM-B2
Place jumper 9325, 9326, 9327
1K5 560R 3389 F1 J
560R 1K5 if VLED < 17V 3322 3368 3390 G1
VLED1-F VLED1-F
3391 3391 G1
1K5 560R 7000 C2
G 1K5 F302 F327
RED-2
3323 G 7001 C3
Place jumper 9314, 9316, 9317 7002 C4
3325

3304
7305
10K

10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314

9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326

3306
10K

10K
7307 F4
owner.

7315 G9

8
7316 H10
PWM-R1 PWM-R2

9311-4

9311-3

9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L

1
GREEN-2 9303-1 C10
3327

3307
7306
10K

10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316

9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330

3309
10K

10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N

1 2 3 4 5 6 7 8 9 10 11 12 13

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_502_090403.eps
090403

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 80

8 LED Ambilight LED Drive

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A A

1M3A E2
1 2 3 4 5 6 7 8 9 10 1M85 D2
3536 E9
B 3537 E9
3538 E7
B
3539 E9
3540 E7
LED DRIVE 3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
C 3547 E8 C
A A 3549 F7
3550 E8
3552 F7
3553 F8
3555 F7
7006 2 7007 3556 F8
LTW-E500T-PH1 LTW-E500T-PH1
3569 F7
D GREEN-1 4 GREEN 3 4 GREEN 3
3570 F7
3571 G7
D
RED-1 5 RED 5 RED 3572 G7
3573 G7
BLUE-1 6 BLUE 1 6 BLUE 1 3574 G7
B GND_HS GND_HS B 3584 F8
3585 F8

7
3586 F8
E 3587 G8 E
3588 G8
3589 G8
2
3590 G8
3591 G8
7006 A5
7007 A7

F C C F

1M85
1 SPI-CLOCK-BUF
2 SPI-DATA-OUT

G 3
4
SPI-DATA-RETURN
SPI-LATCH G
5 PWM-CLOCK-BUF GREEN-2
6 +3V3
D 7
8
BLANK-BUF
EEPROM-CS
RED-2
D
9 TEMP-SENSOR BLUE-2
10 PROG
11 VLED1
12
H 13
14
VLED2
H
15 16

3536
3538 3541

560R 1K5 390R

3540 3544 3537

E 1M3A 560R 1K5 390R

E
I 1
2
SPI-CLOCK-BUF
SPI-DATA-OUT
3543 3547 3539
I
3 SPI-DATA-RETURN 560R 1K5 390R
SPI-LATCH 3546 3550 3542
4
5 PWM-CLOCK-BUF
6 +3V3 560R 1K5 390R
7 BLANK-BUF 3549 3553
is prohibited without the written consent of the copyright

8 EEPROM-CS
All rights reserved. Reproduction in whole or in parts

9 TEMP-SENSOR 560R 1K5

10 PROG 3552 3556
J 11
12
VLED1
560R 1K5
J
F 13
14
VLED2 3555 3584 F
15 16 560R 1K5
3569 3585

560R 1K5
3570 3586

K 560R
3571
1K5
3587
K
560R 1K5
owner.

3572 3588

G 560R
3573
1K5
3589
G
560R 1K5
L 3574 3590
L
560R 1K5
3591

1K5

M M
1 2 3 4 5 6 7 8 9 10

1X04
REF EMC HOLE

N N

O O
CHN SETNAME

CLASS_NO 1 2008-05-23

2LED + CONNECTOR 2 2008-08-08

2008-05-23 1 3 0
P 8204 000 8874
2008-08-08 2 2K9
2008-10-31 3 P
NAME Peter Van Hove SUPERS. 1 130 1 A2

CHECK DATE 2008-04-20 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

18560_503_090403.eps
090403

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 81

Layout 8 LED Ambilight

3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108

3107
9313

2129 2128

9113

9109
9112
9111
2125

3110
1M83 1M84 1M85
3120
3128

3317
3316
3315
3313
3312
3311
3310

3335
3345
3348
3351
3119
3129 9315
2101 9121
3132

6216

3314
3320
3319
3318
3323
3322
3321
3221
3224

2103
2102
7215
2211
3216
3133

9102

3117
3114

3113
3138 3136

7101

3111
C140
3106 3127
2106 3139

2105
3137
2111
I110
3222
7110 2209 2108

2104
2119
1101 2117

9110
2130
9114

7212 7210

7209
9107
2202
9302

2127
I113
3103

7000

7001

7002

7003

7004

7005

7006

7007
3342 2116

1X03 1X04
I111

3339 3115 2107

9106
3131

3140 3135
7116
1105
I114 3126

3306
3305
3304

3303
3302
3301

3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116

3332
7307 3334
3331
3343 3373 3356 3391 2203

9325

9327
3220 3212

9326
2120 9119 2214

7315

7317

7316
3209 9210 9214
2113
3346 3372 3350 3386

7102
9212

3211

3204
9308

3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
3123
9317

3210
3333
3327
3330
2218

2210
3349 3371 3347 3387

7201
2123

7214

3326
3328
3325

3104
9307 2124 3134

2122

3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
3352 3370 3344 3388

9208
3219

3102
2216 2121 3141
3355 3341 3353

9213

3142
3207

7306
3214 2215 2131

9301

3217

9311
3337

7305
9211

9316
2217 9209

9312

9303

9319

9304

3536
3537
3539
3542
3203 3205

3218

3215

9305

9309

9320

9318

9310
9103
3118
9101
2114
9314

9306
9108

2201
3336

2220

2115
3112

2118
9104
3223 2219 3101 3125 3105

F135 F132 F120

F130
F346
F215 F107 F108 F105 F127 F123
F348 F347 F349

1M3A 1M2A 1M1A

F214
F139 F122
F126

I126
F345

F116

F106
F344 F209 F104 I124 F212

F101
F109
F213 F137
F128

F131

F129

F124
F121

F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205

F341
F117 F307
F204 F342
F304 F302

18490_550_090326.eps
3104 313 6314.3 090729

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 82

10 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER BLOCK OSRAM 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101

1%

1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT

3135

3136
F121 9111 SPI-DATA-IN SPI-DATA-RETURN 9108 SDA +1V8
2 7116-2 2111 G4 C140 B10

1K5

1K5
2101

2102

100n

2103
C RES 3 4
C

4u7
F122

1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116

8
2113 H7 F102 F5

2104
F124 9110 COM 5

10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5

2
7

RES
F127 RES EEPROM-CS

4
8 2116 F9 F105 D7

2105

3137
-T 10K
F128

10n
TEMP-SENSOR

3111
9 2117 F9 F106 B12
F129 PROG
10

10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D

C140
9112
9114

2125

33p
14 1105 10n RES 2121 H6 F112 G8

1K5 1%
10u 35V

10u 35V
15 16 VLED1 VLED1-F 3138 2122 F9 F116 A10
2127

2128

2129

2107

100n

2108
+3V3

3139
1u0

10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11

1K5 1%
LM393PT 2125 B3 F120 A1

RES
3140
2126 F10 F121 A1

8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E

4
2

1K8 1%
3 SDA 2130 F2 F125 B1

3123
+3V3
C C

RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1

3107
10K

10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1

10K
10K

10K

10K

10K

10K

10K
10K

10K
PROG
10 3102-2 D9 F131 B1

8
5

5
F 11 VLED1 F105
3102-3 E9 F132 B1 F

10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1

3105-2 2

3106-2 2

3104-1 1

3102-1 1
4

3104-4 4

3101-3 3

4
14

10K
RES
10K
15 16 3103-2 G10 F135 E1

3102-2

3102-4
7
100R

100R
3109

3110

3105-4

3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1

10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G

10K
3104-3 E8 I110 G8

10K
RES

10K
10K
10K

10K

10K

10K

10K

10K

10K
3104-4 D9 I111 G8

8
6

6
6

5
2109

100p

2110

100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10

1
3114

3115
3104-2 2

3
3104-3 3

4
3116

3103-1
3105-4 D8 I124 E11

3102-3
3101-4
3105-1
3105-3

3106-1

3106-3
7102 3106-1 E8 I125 E11

19
43

31

3117
LPC2103FBD48

7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H

10K
X1 P0.0|TXD0|MAT3.1
E MICRO- P0.1|RXD0|MAT3.2
14
E 3107 C7
16M9

12 18 3124-4 4 5 I124
X2 CTRL P0.2|SCL0|CAP0.0 3108 C7
1101

21 3128 100R PWM-CLOCK-BUF

OUT P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
22 3129 100R SPI-CLOCK-BUF
3109 D7
1M84 20 23 3124-1 1 8 100R SPI-DATA-RETURN 3110 D7
RTXC1 P0.5|MISO0|MAT0.1
F133 SPI-CLOCK-BUF 9101 25 24 3124-2 2 7 100R SPI-DATA-IN 3111 B10
1 RTXC2 P0.6|MOSI0|CAP0.2
F135 SPI-DATA-OUT 28 3124-3 3 6 100R SPI-LATCH 3112 D9
2 3118 P0.7|SSEL0|MAT2.0
F136 SPI-DATA-RETURN 26 29 3125-1 1 8 100R I125 SPI-LATCH-2 3113 D8
3 RTCK P0.8|TXD1|MAT2.1
F139 SPI-LATCH +3V3 10K RES 30 3142 100R
4 P0.9|RXD1|MAT2.2 3114 E8
I 5
6
F137
+3V3
PWM-CLOCK-BUF 9102
F102
4
VBAT P0.10|RTS1|CAP1.0|AD0.3
P0.11|CTS1|CAP1.1|AD0.4
35
36
3125-2
3125-4
2
4
7
5
100R
100R
TEMP-SENSOR
EEPROM-CS
TEMP-SENSOR
3115 E8 I
F138 BLANK-BUF RES 9103 37 3126-2 2 7 100R BLANK-BUF 3116 E8
7 P0.12|DSR1|MAT1.0|AD0.5
F134 EEPROM-CS 9104 27 41 3126-4 4 5 100R PROG 3117 E7
8 DBGSEL P0.13|DTR1|MAT1.1
TEMP-SENSOR RES 44 100R 3118 E5
9 P0.14|DCD1|SCK1|EINT1
F 10
11 VLED1
PROG +3V3
+3V3 F104
6
RST
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
45
46
3126-1 1 8
100R
I126 CONTROL-2
F 3119 F4
3120 F5
is prohibited without the written consent of the copyright

47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts

13 VLED2 P0.18|CAP1.3|SDA1
2130

3119

2122 RES

2124 RES
1 100R

2114 RES
3124-1 E11
10K
1u0

14 P0.19|MAT1.2|MISO1
3120

J 2
J
10K

15 16 7110 P0.20|MAT1.3|MOSI1 3124-2 E11

100p
2115

100p
2116

100p
2117

100p

100p
2123

100p

100p
2126

100p
2131

100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES

38 3125-2 F11
P0.25|AD0.6
5 4 39 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111

100n

SPI-DATA-OUT 10 I113 3103-4 5

2 P0.29|TCK|CAP2.2
3126-4 F11
K 3
4
SPI-DATA-RETURN
SPI-LATCH
P0.30|TDI|MAT3.3
P0.31|TDO
15
16 3130
I114
I115 3103-2
4
7
10K 3103-3
3
6
10K +3V3 3127-1 F11 K
PWM-CLOCK-BUF 2 10K 3127-4 F11
5 22R
+3V3 VDD_1V8 VDD_3V3 VDDA
6 3128 E11
5

17
40

42

BLANK-BUF
owner.

7 3131 F112

2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R

100p

3132
3131 G7

10K

10K
3133
10 PROG
2112

100n

9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119

100n
2120

100n
2121

100n

2113

100n

3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

1X03
REF EMC HOLE

O O
CHN SETNAME
1

CLASS_NO 1 2008-06-10

DRIVER 6LED OSRAM 2 2008-08-08

3 2008-10-24
P 8204 000 8884
2008-08-08 2 2K9
2008-10-24 3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 83

10 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER BLOCK LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B +3V3 +3V3
9208 RES

+3V3
2218 C12
2219 D12
B
7201-1 2220 E9

14
2214

100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219

3213

3210
3 PWM-CLOCK-BUF

10K

10K
3207 F205 3204 B7
1
+3V3 EN 100R 3205 C5

2201

2217

100p
1K0 RES

33p
7212 3207 B9

7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3

2209

3203
74HCT125PW

10K
33p
3215 H6

14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D

2202

2218

100p
GND 1K0 RES 3219 B11

33p
7210

7
3220 C11

10K RES
PDTC144EU 4
3 9211
3221 H11

3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E

14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R

2203

2219

100p
1K0 RES 7201-4 B10

33p

7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9

14
74HCT125PW
9 9210 B10
3121 9211 C9
SPI-DATA-RETURN 8 F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10

2220 RES
100R 9213 D9

7
9214 D10

100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9

F F
I +3V3
I
2216 2215

1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts

7215

28
TLC5946PWP

J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
owner.

XLAT 10
18 F215
11
H H

3224

3221
4 19

3K3
SPI-CLOCK-BUF PWM-B2

3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS

470R
2211

3222
1

29

30
31
32
33
33p

SML-310
6216

M I I M
+3V3

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_631_090306.eps
090306

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 84

10 LED Ambilight LEDs

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5

9307

9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7

5
3328 G4 9325 F10
D D

9309-2

9309-1

9309-4

9310-2

9310-4

9310-1

9312-4

9312-3

9312-1

9313-1

9313-2

9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301

9302

3332 F4 F302 G5

4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5

E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7

7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12

9320-1 8

9320-4 5

9320-2 7

6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13

9306-4

9306-1

9306-3

9319-1

9319-4

9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G

3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3342 3357 D13
3346 3350
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331

3301
I 7307 3371 F1
I
10K

10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317

9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332

3303
3385 F1
10K

10K
560R 1K5 3320 3366
is prohibited without the written consent of the copyright

3373 3389 3386 F1

All rights reserved. Reproduction in whole or in parts

1K5 560R 3387 F1

560R 1K5 3321 3367 3388 F1
J 3374 3390 PWM-B1 PWM-B2
Place jumper 9325, 9326, 9327
1K5 560R 3389 F1 J
560R 1K5 if VLED < 17V 3322 3368 3390 G1
VLED1-F VLED1-F
3391 3391 G1
1K5 560R 7000 C2
G 1K5 F302 F327
RED-2
3323 G 7001 C3
Place jumper 9314, 9316, 9317 7002 C4
3325

3304
7305
10K

10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314

9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326

3306
10K

10K
7307 F4
owner.

7315 G9

8
7316 H10
PWM-R1 PWM-R2

9311-4

9311-3

9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L

1
GREEN-2 9303-1 C10
3327

3307
7306
10K

10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316

9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330

3309
10K

10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N

1 2 3 4 5 6 7 8 9 10 11 12 13

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_632_090306.eps
090306

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 85

10 LED Ambilight LED Drive

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A A

1M3A E2
1 2 3 4 5 6 7 8 9 10 1M85 D2
3536 E9
3537 E9
B 3538 E7 B
LED DRIVE 3539 E9
3540 E7
3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
C 3547 E8
3549 F7
C
A A 3550 E8
3552 F7
3553 F8
3555 F7
3556 F8
7006 2 7007 7008 7009
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 3569 F7
3570 F7
D GREEN-1 4 GREEN 3 4 GREEN 3 4 GREEN 3 4 GREEN 3 3571 G7 D
3572 G7
RED-1 5 RED 5 RED 5 RED 5 RED
3573 G7
6 1 6 1 6 1 6 1
3574 G7
BLUE-1 BLUE BLUE BLUE BLUE
B GND_HS GND_HS GND_HS GND_HS B 3584 F8
3585 F8

7
3586 F8
3587 G8
E 3588 G8 E
3589 G8
3590 G8
2 2 2 3591 G8
7006 A2
7007 A4
7008 A5
7009 A6
F C C F

1M85
1 SPI-CLOCK-BUF
2 SPI-DATA-OUT

G 3
4
SPI-DATA-RETURN
SPI-LATCH G
5 PWM-CLOCK-BUF GREEN-2
6 +3V3
D 7 BLANK-BUF
EEPROM-CS
RED-2 D
8
9 TEMP-SENSOR BLUE-2
10 PROG
11 VLED1
12
H 13
14
VLED2
H
15 16

3536
3538 3541

560R 1K5 390R

3540 3544 3537
E 1M3A 560R 1K5 390R
E
I 1
2
SPI-CLOCK-BUF
SPI-DATA-OUT
3543 3547 3539
I
3 SPI-DATA-RETURN 560R 1K5 390R
SPI-LATCH 3546 3550 3542
4
5 PWM-CLOCK-BUF
6 +3V3 560R 1K5 390R
7 BLANK-BUF 3549 3553
is prohibited without the written consent of the copyright

8 EEPROM-CS
All rights reserved. Reproduction in whole or in parts

9 TEMP-SENSOR 560R 1K5

10 PROG 3552 3556
J 11
12
VLED1
560R 1K5
J
F 13 VLED2 3555 3584 F
14
15 16 560R 1K5
3569 3585

560R 1K5
3570 3586

K 560R
3571
1K5
3587
K
560R 1K5
owner.

3572 3588

560R 1K5

G 3573 3589
G
560R 1K5
L 3574 3590
L
560R 1K5
3591

1K5

M M
1 2 3 4 5 6 7 8 9 10

N 1X04
N
REF EMC HOLE

O O
CHN SETNAME

CLASS_NO 1 2008-08-14

4 LED + CONNECTOR 2 2008-10-24

3 2008-10-31
P 8204 000 8897
2008-08-14 2 LITEON 2K9
2008-10-31 3 P
NAME Peter Van Hove SUPERS. 1 130 1 A2

CHECK DATE 2008-07-29 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_633_090306.eps
090306

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 86

Layout 10 LED Ambilight

3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108

3107
9313

2129 2128

9113

9109
9112
9111
2125
1M83 1M84 1M85

3110
3120
3128

3317
3316
3315
3313
3312
3311
3310

3335
3345
3348
3351
3119
3129 9315
2101 9121
3132

6216

3314
3320
3319
3318
3323
3322
3321
3221
3224

2103
2102
7215
2211
3216
3133

9102

3117
3114

3113
3138 3136

7101

3111
C140
3106 3127
2106 3139

2105
3137
I110

2111
3222
7110 2209 2108

2104
2119
1101 2117

9110
2130
9114

7212 7210

7209
9107
2202
9302

2127
I113
3103
7000

7001

7002

7003

7004

7005

7006

7007

7008

7009
3342 2116

1X03 1X04
I111

3339 3115 2107

9106
3131

3140 3135
7116
3126

1105
I114

3306
3305
3304

3303
3302
3301

3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116

3332
7307 3334
3331
3343 3373 3356 3391 2203

9325

9327
3220 3212

9326
2120 9119 2214

7315

7317

7316
2113

3209 9210 9214

3346 3372 3350 3386

7102
9212

3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
9308

3211

3204

3123
9317

3210
3333
3327
3330
2218
3349 3371 3347 3387

2210
7201
2123

7214

3326
3328
3325

3104
9307 2124 3134

3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
2122
3352 3370 3344 3388

9208
3219

3102
2216 2121 3141
3355 3341 3353

9213

3142
3207

7306
3214 2215 2131
9301

3217

9311

3536
3537
3539
3542
3337

7305
9211

9316
2217 9209

9312

9303

9319

9304
3203 3205

3218

3215

9305

9309

9320

9318

9310
9103
3118
9101
2114
9314

9306
9108

2201
3336

2220

2115
3112

2118
9104
3223 2219 3101 3125 3105

F135 F132 F120

F130
F346
F215 F107 F108 F105 F127 F123
F348 F347 F349

1M3A 1M2A 1M1A

F214
F139 F122
F126

I126
F345

F116

F106
F344 F209 F104 I124 F212

F101
F109
F213 F137
F128

F131

F129

F124
F121

F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205

F341
F117 F307
F204 F342
F304 F302

18310_553_090309
3104 313 6315.2 090309

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 87

12 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101

1%

1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT

3135
9111 9108

3136
F121 SPI-DATA-IN SPI-DATA-RETURN SDA +1V8
2 7116-2 2111 G4 C140 B10

1K5

1K5
2101

2102

100n

2103
C F122 RES 3 4
C

4u7
1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116

8
2113 H7 F102 F5

2104
F124 9110 COM 5

10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5

2
7

RES
F127 RES EEPROM-CS

4
8 2116 F9 F105 D7

2105

3137
-T 10K
F128

10n
TEMP-SENSOR

3111
9 2117 F9 F106 B12
F129 PROG
10

10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D

C140
9112
9114

2125

33p
14 1105 10n RES 2121 H6 F112 G8

1K5 1%
10u 35V

10u 35V
15 16 VLED1 VLED1-F 3138
+3V3 2122 F9 F116 A10
2127

2128

2129

2107

100n

2108

3139
1u0

10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11

1K5 1%
LM393PT 2125 B3 F120 A1

RES
3140
2126 F10 F121 A1

8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E

4
2

1K8 1%
3 SDA 2130 F2 F125 B1

3123
+3V3
C C

RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1

3107
10K

10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1

10K
10K

10K

10K

10K

10K

10K
10K

10K
PROG
10 3102-2 D9 F131 B1

5
F 11 VLED1 F105
3102-3 E9 F132 B1 F

10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1

3105-2 2

3106-2 2

3104-1 1

3102-1 1

3104-4 4

3101-3 3

4
14

10K
RES
10K
15 16 3103-2 G10 F135 E1

3102-2

3102-4
7
100R

100R
3109

3110

3105-4

3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1

10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G

10K
3104-3 E8 I110 G8

10K
RES

10K
10K
10K

10K

10K

10K

10K

10K

10K
3104-4 D9 I111 G8

8
5
2109

100p

2110

100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10

1
3114

3115
3104-2 2

3104-3 3

3
4
3116

3103-1
3105-4 D8 I124 E11

3102-3
3101-4
3105-1
3105-3

3106-1

3106-3
7102 3106-1 E8 I125 E11

19
43

31

3117
LPC2103FBD48

7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H

10K
X1 P0.0|TXD0|MAT3.1
E MICRO- P0.1|RXD0|MAT3.2
14
E 3107 C7

16M9
12 18 3124-4 4 5 I124
X2 CTRL P0.2|SCL0|CAP0.0 CONTROL-1 3108 C7
1101

21 3128 100R PWM-CLOCK-BUF

OUT P0.3|SDA0|MAT0.0
P0.4|SCK0|CAP0.1
22 3129 100R SPI-CLOCK-BUF
3109 D7
1M84 20 23 3124-1 1 8 100R SPI-DATA-RETURN 3110 D7
RTXC1 P0.5|MISO0|MAT0.1
F133 SPI-CLOCK-BUF 9101 25 24 3124-2 2 7 100R SPI-DATA-IN 3111 B10
1 RTXC2 P0.6|MOSI0|CAP0.2
F135 SPI-DATA-OUT 28 3124-3 3 6 100R SPI-LATCH 3112 D9
2 3118 P0.7|SSEL0|MAT2.0
F136 SPI-DATA-RETURN 26 29 3125-1 1 8 100R I125 SPI-LATCH-2 3113 D8
3 RTCK P0.8|TXD1|MAT2.1
F139 SPI-LATCH +3V3 10K RES 30 3142 100R
4 P0.9|RXD1|MAT2.2 3114 E8
I 5
6
F137
+3V3
PWM-CLOCK-BUF 9102 4
F102
VBAT P0.10|RTS1|CAP1.0|AD0.3
P0.11|CTS1|CAP1.1|AD0.4
35
36
3125-2
3125-4
2
4
7
5
100R
100R
TEMP-SENSOR
EEPROM-CS
TEMP-SENSOR
3115 E8 I
F138 BLANK-BUF RES 9103 37 3126-2 2 7 100R BLANK-BUF 3116 E8
7 P0.12|DSR1|MAT1.0|AD0.5
F134 EEPROM-CS 9104 27 41 3126-4 4 5 100R PROG 3117 E7
8 DBGSEL P0.13|DTR1|MAT1.1
TEMP-SENSOR RES 44 100R 3118 E5
9 +3V3 P0.14|DCD1|SCK1|EINT1
F 10
11 VLED1
PROG
+3V3 F104
6
RST
P0.15|RI1|EINT2
P0.16|EINT0|MAT0.2
45
46
3126-1 1 8
100R
I126 CONTROL-2
F 3119 F4
3120 F5
is prohibited without the written consent of the copyright

47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts

13 VLED2 P0.18|CAP1.3|SDA1 SDA

2130

3119

2122 RES

2124 RES
1 100R 3124-1 E11

2114 RES
10K
1u0

14 P0.19|MAT1.2|MISO1
3120

J 2
J
10K

15 16 7110 P0.20|MAT1.3|MOSI1 3124-2 E11

100p
2115

100p
2116

100p
2117

100p

100p
2123

100p

100p
2126

100p
2131

100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES

38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111

100n

SPI-DATA-OUT 10 I113 3103-4 5

2 P0.29|TCK|CAP2.2
3126-4 F11
K 3
4
SPI-DATA-RETURN
SPI-LATCH
P0.30|TDI|MAT3.3
P0.31|TDO
15
16 3130
I114
I115 3103-2
4
7
10K 3103-3
3
6
10K +3V3 3127-1 F11 K
PWM-CLOCK-BUF 2 10K 3127-4 F11
5 22R
+3V3 VDD_1V8 VDD_3V3 VDDA
6 3128 E11
5

17
40

42

BLANK-BUF
owner.

7 3131 F112

2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R

100p

3132
3131 G7

10K

10K
3133
10 PROG

2112

100n

9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119

100n
2120

100n
2121

100n

2113

100n

3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

1X03
REF EMC HOLE

O O
CHN SETNAME
1

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

18560_510_090403.eps
090410

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 88

12 LED Ambilight Microcontroller

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B +3V3 +3V3
9208 RES

+3V3
2218 C12
2219 D12
B
7201-1 2220 E9

14
2214

100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219

3213

3210
3 PWM-CLOCK-BUF

10K

10K
3207 F205 3204 B7
1
+3V3 EN 100R 3205 C5

2201

2217

100p
1K0 RES

33p
7212 3207 B9

7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3

2209

3203
74HCT125PW

10K
33p
3215 H6

14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D

2202

2218

100p
GND 1K0 RES 3219 B11

33p
7210

7
3220 C11

10K RES
PDTC144EU 4
3 9211
3221 H11

3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E

14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R

2203

2219

100p
1K0 RES 7201-4 B10

33p

7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9

14
74HCT125PW
9 9210 B10
3121 9211 C9
SPI-DATA-RETURN 8 F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10

2220 RES
100R 9213 D9

7
9214 D10

100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9

F F
I +3V3
I
2216 2215

1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts

7215

28
TLC5946PWP

J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
owner.

XLAT 10
18 F215
11
H H

3224

3221
4 19

3K3
SPI-CLOCK-BUF PWM-B2

3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS

470R
2211

3222
1

29

30
31
32
33
33p

SML-310
6216

M I I M
+3V3

1 2 3 4 5 6 7 8 9 10 11 12 13
N N

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_511_090403.eps
090410

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 89

12 LED Ambilight LEDs

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5

9307

9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7

5
3328 G4 9325 F10
D D

9309-2

9309-1

9309-4

9310-2

9310-4

9310-1

9312-4

9312-3

9312-1

9313-1

9313-2

9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301

9302

3332 F4 F302 G5

4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5

E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7

7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12

9320-1 8

9320-4 5

9320-2 7

6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13

9306-4

9306-1

9306-3

9319-1

9319-4

9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G

3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3342 3357 D13
3346 3350
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331

3301
I 7307 3371 F1
I
10K

10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317

9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332

3303
3385 F1
10K

10K
560R 1K5 3320 3366
is prohibited without the written consent of the copyright

3373 3389 3386 F1

All rights reserved. Reproduction in whole or in parts

1K5 560R 3387 F1

560R 1K5 3321 3367 3388 F1
J 3374 3390 PWM-B1 PWM-B2
Place jumper 9325, 9326, 9327
1K5 560R 3389 F1 J
560R 1K5 if VLED < 17V 3322 3368 3390 G1
VLED1-F VLED1-F
3391 3391 G1
1K5 560R 7000 C2
G 1K5 F302 F327
RED-2
3323 G 7001 C3
Place jumper 9314, 9316, 9317 7002 C4
3325

3304
7305
10K

10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314

9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326

3306
10K

10K
7307 F4
owner.

7315 G9

8
7316 H10
PWM-R1 PWM-R2

9311-4

9311-3

9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L

1
GREEN-2 9303-1 C10
3327

3307
7306
10K

10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316

9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330

3309
10K

10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N

1 2 3 4 5 6 7 8 9 10 11 12 13

O O
CHN SETNAME

CLASS_NO 1 2008-06-10

DRIVER 6LED LITEON 2 2008-08-08

3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2

CHECK DATE 2008-06-02 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_512_090403.eps
090403

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 90

12 LED Ambilight LED Drive

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A A
1M3A F2
1 2 3 4 5 6 7 8 9 10 11 12 1M85 D2
3536 E11
3537 E11
3538 E9
3539 F11
B 3540 F9
B
LED DRIVE 3541 E10
3542 F11
A A 3543 F9
3544 F10
3546 F9
3547 F10
3549 F9
3550 F10
C 3552 F9 C
3553 F10
3555 G10
3556 F10
3569 G9
3570 G9
B 7006
LTW-E500T-PH1
2 7007
LTW-E500T-PH1
7008
LTW-E500T-PH1
7009
LTW-E500T-PH1
7010
LTW-E500T-PH1
7011
LTW-E500T-PH1
B 3571 G9
3572 G9
D GREEN-1 4 GREEN 3 4 GREEN 3 4 GREEN 3 4 GREEN 3 4 GREEN 3 4 GREEN 3
3573 H9 D
3574 H9
RED-1 5 RED 2 5 RED 2 5 RED 2 5 RED 2 5 RED 2 5 RED 2 3584 G10
3585 G10
BLUE-1 6 BLUE 1 6 BLUE 1 6 BLUE 1 6 BLUE 1 6 BLUE 1 6 BLUE 1
3586 G10
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3587 G10
3588 G10

7
3589 H10
E 3590 H10 E
3591 H10
C C 7006 B2
7007 B3
7008 B5
7009 B6
7010 B7
7011 B8

F F

D 1M85
D
1 SPI-CLOCK-BUF
2 SPI-DATA-OUT

G 3
4
SPI-DATA-RETURN
SPI-LATCH G
5 PWM-CLOCK-BUF GREEN-2
6 +3V3
7 BLANK-BUF RED-2
8 EEPROM-CS
9 TEMP-SENSOR BLUE-2
10 PROG
11 VLED1

H E 12
13 VLED2 E H
14
15 16

3536
3538 3541

560R 1K5 390R

3540 3544 3537

1M3A 560R 1K5 390R

I 1
2
SPI-CLOCK-BUF
SPI-DATA-OUT
3543 3547 3539
I
3 SPI-DATA-RETURN 560R 1K5 390R
SPI-LATCH 3546 3550 3542
F 4
5 PWM-CLOCK-BUF
560R 1K5 390R
F
6 +3V3
7 BLANK-BUF 3549 3553
is prohibited without the written consent of the copyright

8 EEPROM-CS
All rights reserved. Reproduction in whole or in parts

9 TEMP-SENSOR 560R 1K5

10 PROG 3552 3556
J 11
12
VLED1
560R 1K5
J
13 VLED2 3555 3584
14
15 16 560R 1K5
3569 3585

560R 1K5
G 3570 3586 G
K 560R
3571
1K5
3587
K
560R 1K5
owner.

3572 3588

560R 1K5
3573 3589

560R 1K5
L 3574 3590
L
H 560R 1K5 H
3591

1K5

M M
1 2 3 4 5 6 7 8 9 10 11 12
1X04
REF EMC HOLE

N N

O O
CHN SETNAME

CLASS_NO 2 2008-10-29

6 LED + CONNECTOR
P 8204 000 8898
2008-08-14 2 2K9 LITEON
2008-10-29 3 P
NAME Peter Van Hove SUPERS. 1 130 1 A2

CHECK DATE 2008-07-30 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18560_513_090403.eps
090729

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 91

Layout 12 LED Ambilight

3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108

3107
9313

2129 2128

9113

9109
9112
9111
2125
1M83 1M84 1M85

3110
3120
3128

3320 3317
3319 3316
3318 3315
3323 3313
3322 3312
3321 3311
3310

3335
3345
3348
3351
3119
3129 9315
2101 9121
3132

6216

3314
3221
3224

2103
2102
7215
2211
3216
3133

9102

3117
3114

3113
3138 3136

7101

3111
C140
3106 3127
2106 3139

2105
3137
I110

2111
3222
7110 2209 2108

2104
2119
1101 2117

9110
2130
9114

7212 7210

7209
9107
2202
9302

2127
I113
3103

7000

7001

7002

7003

7004

7005

7006

7007

7008

7009

7010

7011
3342 2116

1X03 1X04
I111

3339 3115 2107

9106
3131

3140 3135
7116
3126

1105
I114

3306
3305
3304

3303
3302
3301

3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116

3332
7307 3334
3331
3343 3373 3356 3391 2203

9325

9327
3220 3212

9326
2120 9119 2214

7315

7317

7316
2113

3209 9210 9214

3346 3372 3350 3386

7102
9212

3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
9308

3211

3204

3123
9317

3210
3333
3327
3330
2218
3349 3371 3347 3387

2210
7201
2123

7214

3326
3328
3325

3104
9307 2124 3134

3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
2122
3352 3370 3344 3388

9208
3219

3102
2216 2121 3141
3355 3341 3353

9213

3142
3207

7306
3214 2215 2131

9301

3217

9311

3536
3537
3539
3542
3337

7305
9211

9316
2217 9209

9312

9303

9319

9304
3203 3205

3218

3215

9305

9309

9320

9318

9310
9103
3118
9101
2114
9314

9306
9108

2201
3336

2220

2115
3112

2118
9104
3223 2219 3101 3125 3105

F135 F132 F120

F130
F346
F215 F107 F108 F105 F127 F123
F348 F347 F349

1M3A 1M2A 1M1A

F214
F139 F122
F126

I126
F345

F116

F106
F344 F209 F104 I124 F212

F101
F109
F213 F137
F128

F131

F129

F124
F121

F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205

F341
F117 F307
F204 F342
F304 F302

18490_551_090326.eps
3104 313 6335.2 090729

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 92

SSB: DC/DC +3V3 +1V2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A 2100 B2
2101 B4
2107 B6
2108 B5
2114 C8
2115 D7
2121 E8
2122 B11
2129 F8
2130 F7
2140 C9
2141 C9
3106 C2
3107 C3
3115 C6
3116 C5
3122 F2
3124 C6
3130 E5
3131 E6
3137 D6
3138 E9
3144 F8
3145 E11
3151 G11
3152 G11
3158 F3
3159 H1
5103 E8
5104 B11
6104 B2
7100-1 C2
7103 C4
7104 D2
F100 C4
F101 C7
F107 B7
F108 D10
F114 D4
F115 D4
I107 D3
I108 D4
I115 C5
I116 D5
I122 E5
I124 E4
I130 F7
I131 E8
I138 F11
I141 H2
A
2102 D1 2109 C6 2116 E9 2123 B11 2131 F7 3100 B2 3108 B4 3117 D1 3125 D6 3132 C7 3139 E7 3146 E10 3153 F8 3160 H1 5105 E11 7100-2 B1 7105-1 E3 F102 D6 F109 E10 I100 B3 I109 C2 I117 D5 I125 F3 I132 E8 I143 C8
2103 D4 2110 C8 2117 E9 2124 C12 2132 F5 3101 B2 3109 C5 3118 E1 3126 D6 3133 C8 3140 E8 3147 F11 3154 F8 3164 D4 6100 E6 7101-1 B5 7105-2 E4 F103 D6 F110 F10 I101 B1 I111 D5 I118 D6 I126 F5 I133 F8 I144 C8
2104 B6 2111 C8 2118 E9 2125 E12 2133 H2 3102 C2 3110 C5 3119 E4 3127 D6 3134 C8 3141 E8 3148 F10 3155 F8 5100 B8 6101 F5 7101-2 C6 7106 F7 F104 E7 F111 E12 I102 C1 I112 B5 I119 D6 I127 F2 I134 F8 I146 E5
2105 D6 2112 C9 2119 E9 2127 E12 2134 H2 3103 C1 3113 C5 3120 E4 3128 D5 3135 D8 3142 E6 3149 F11 3156 F7 5101 C8 6102 G7 7102-1 C7 7107-1 E10 F105 F4 F112 D9 I103 B4 I113 C5 I120 D6 I128 D1 I136 E9 I147 F7
2106 E5 2113 C7 2120 E8 2128 F7 2135 H2 3105 C1 3114 C5 3121 E4 3129 D5 3136 D7 3143 E6 3150 F11 3157 F7 5102 E8 6103 F7 7102-2 D6 7107-2 F10 F106 C2 F113 F7 I106 D4 I114 D8 I121 C6 I129 E6 I137 E11 I148 C8

B B
1 2 3 4 5 6 7 8 9 10 11 12 13 14

C DC / DC +3V3_+1V2 C
A A

D D
+12VF
RES 5104
+12V
F107 10u
3100

B B
2100

100n

3108

2104

2107

RES 2122

2123
RES
10R
22K

10u

22u

10u

22u
7101-1

E BC847BPN
4
3101 I103
I112
2
7 8
FDS6930B
E
7100-2 5 12V/3V3 CONVERSION

1
22K RES
I101 6104 2108 VSW 5100

2101
3

1u0
I100

3110 22R
BAS316 3n3 10u
F101 5101
3103

3109

22R
10K

I109 3102 F106 +3V3

6 DETECT1 10u
5 6
I102 0V 100R 3V3 GND-SIG I113 7101-2

RES 3132

RES 3133

3134

2110

2111

2112

2140

RES 2141
F 2 4
F

22R

22R

6K8
7100-1

3n3

22u

22u

22u

22u

220u 25V
FDS6930B

RES 2124
BC847BPN

3
C 1 7103
14 I121
7 8 7102-1
C
3105

3106

3107

NCP5422ADR2G 2 FDS6930B
10K

10K

22K

I143
Φ

3113

3114
VCC
I144

4R7

4R7

1
3115
F100 2109

RES 2113

2114

100n
4 1

1n0
BST H1

3116

22R
GATE I115 3n3
2
L1 3124

22R
7 7102-2 I148
1 I116 I114
G F114
10
2
VFB
GATE
H2
16
I117
4R7
3125
5 6 G
F115

RES 2115

3135
15 4

1K0
1n0
L2
8 I118 I119

3
1 4R7
I106 5 FDS6930B
I107 COMP +1 I120 3126 F102 3136
9 6
2 -1
D D
2102

100n

IS 1K0 6K8
I108 13 12
ROSC +2 I111

2105

100n

3127
11

2K2
-2
GND 12V/1V2 CONVERSION
2103

100n

3164

H 7104
H
39K

BC847BW 3 3128 F108

GND-SIG 3
F112
3117 I128 2K7 3129 F103 3137 +1V2-PNX85XX

2116 RES

2118 RES
1
RES

RES

330u 6.3V
33K I122 1K0 6K8 F104 5102

2125
2

2117
2119
3118

*
33K

10u

2106

100n

3131

3138

10R
2K2
GND-SIG GND-SIG GND-SIG

10u

10u

10u

10u
5103
3130
I E GND-SIG GND-SIG
I146
2K7
10u
5105 F111
+3V3F
E I

RES 3139

RES 3140

3141

2120
22R

22R

6K8

3n3
3119 BAS316 I129 3142 RES 22u
RES I124

100R
2121

3145
1u0

220u 25V
3146 F109

2127
6
330R 6100 68R I136
3120

1K0

3143 I131 10K

7105-1 1 7105-2 4 I132 7107-1 2
I137
3121 BC847BS
is prohibited without the written consent of the copyright

BC857BS BC857BS 68R 2131

I126

1% 120R
RES 2128

2129

100n

3144
2 5 F105 1
All rights reserved. Reproduction in whole or in parts

1n0
3122 1K0 +12VF I147

3147

1K0
I125 100n
J 6 3
J
PDZ9.1-B

BAS316
10K 3156
6101

6103
I127 I133
I134
100K
3158

470R 3148 F110

2132

3
1u0

3157
F F

RES 2130

3153
3V3-ST

1K0
1n0
I130 10K I138 3149
7107-2 5
470R
3 BC847BS
F113 3K3
4

3150
1

2K2
7106
BC817-25W

3154

3155
K 2
K

15K

1% 1K0
PDZ18-B
6102
BOOSTER
12V UNDER-VOLTAGE DETECTION 3151
1%
owner.

+1V2-PNX85XX
GND-SIG GND-SIG 1K0 3152
SENSE+1V2-PNX85XX
120R 1%
G ENABLE-3V3
G
L PROT-DC
L
2133

100p

2134
M 100p
I141 M
H H
1% 470R
3159

3160

2135

100n
4K7

MULTI 12NC : 3139_123_64421 / 64541 / 64561

BD 12NC : 3139_123_64431 / 64551 / 64571
GND-SIG GND-SIG GND-SIG CELL 12C : 8239_125_14871
N N
1 2 3 4 5 6 7 8 9 10 11 12 13 14

" X100 ~ X199 "

O 1X05 1X06 1X12 1X02 1X07 1X03 1X08
O
REF EMC HOLE REF EMC HOLE REF EMC HOLE REF EMC HOLE REF EMC HOLE REF EMC HOLE REF EMC HOLE CHN DC343514 SETNAME ********

CLASS_NO 1 2009-01-16
3PC332
PCB SB SSB BD 1 2008-12-16

-- -- -- 1
P 3139 123 6443
2008-10-17 2 TV543_2K9
Oval screw hole of 2009-01-16 3 P
Round screw hole of 4.02mm Round screw hole of 4.5mm 5mm x 4.02mm NAME Kailash SUPERS. **** *** ***** 25 10 130 01 A2

SV CHECK DATE 2008-10-17 C ROYAL PHILIPS ELECTRONICS N.V. 2008

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18440_500_090223.eps
090224

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 93

SSB: DC/DC +3V3 +1V2 Standby

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A A

1M95 D1 2203 C2 2208 E2 2213 B9 2218 B12 2223 F9 2228 F13 2233 B6 3201 B1 3211 C12 3221 G12 3226 C5 3231 D6 4202 C2 6217 B12 7203 B14 7223-2 C6 F203 B1 F208 D1 F213 D1 F218 B6 F223 B1 F228 B1 I203 B9 I210 F9 I216 D5
B 1M99 B1 2204 D2 2209 B5 2214 B9 2219 C10 2224 F12 2229 F13 2235 C3 3204 D2 3212 B14 3222 G12 3227 C6 3232 D4 5203 B9 6225 D4 7204 D10 7224-1 E6 F204 B1 F209 D1 F214 E1 F219 B12 F224 B1 F229 B12 I204 B10 I212 C5 I217 D6 B
2200 C1 2205 D3 2210 B6 2215 B12 2220 D2 2225 F12 2230 E2 2236 C2 3207 B10 3213 B13 3223 F13 3228 D6 3233 E4 5204 B11 7201 A6 7222-1 E10 7224-2 C7 F205 B1 F210 D1 F215 E1 F220 B14 F225 C1 F230 B15 I205 B11 I213 D5 I218 C6
2201 C1 2206 E1 2211 D4 2216 C13 2221 F9 2226 F13 2231 C1 2237 C2 3208 C11 3214 C13 3224 F12 3229 D6 3234 E5 5221 F9 7202-1 B10 7222-2 F10 F201 B1 F206 B1 F211 D1 F216 E1 F221 D14 F226 C1 F231 F12 I206 B14 I214 D4 I219 C6
2202 C2 2207 E2 2212 B9 2217 B12 2222 F9 2227 F13 2232 C2 3200 B1 3210 C12 3215 C14 3225 C5 3230 D6 4201 B2 5222 F11 7202-2 C10 7223-1 D5 F202 B1 F207 D1 F212 D1 F217 E1 F222 F12 F227 D6 I202 B6 I207 D11 I215 E5

C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C

DC / DC +3V3-STANDBY_+1V2-STANDBY

D A A D
DC / DC
7201
+3V3-STANDBY LD3985M122
E 1 5
7202-1
ST1S10PH
+5V5-TUN
E

1
6
IN OUT +1V2-STANDBY RES 6217

SW
1M99 SS36
I202 5203 I204 5204 F219
F228 +12VD 3 4 F218
+12V
I203 3207
2 7 I205 +5V
1 INH BP INH VIN SW
F201 33R
2 100K 10u

2215 10u
FROM PSU

220u 25V
5 3
B 3
F202 COM
SYNC VFB B

2217

2218
2209

2210

100n
2233

10u
GND

1u0

1u0
4

2212

2213

2214
10u

10u

10u
F203 3200 68R LAMP-ON-OUT A P HS

2
5 RES F220 3212 F230
BACKLIGHT-OUT PROT-DC

4
8
9
F204 3201 68R
6
7
F205 BACKLIGHT-BOOST 3213 I206 10K
F229
F 8
9
F206
F223 POWER-OK
RES 3K9
7203
BC847BW F

18K 1%
F224 4201 SCL-SET 7202-2
10 2216

3210

3211
RES
ST1S10PH

3215
F225 4202 SDA-SET

1K0

1K0
11
F226
12 +12V 4n7
10 VIA 11
1-1735446-2
3214
100p

100p

100p

100p

100p

100p

100p

100p

10n

100K 1%

3225
C C

10K
3208
2200

2201

2231

2232

2203

2203

2203

2202

G +3V3 G
2235

I212 4 7223-2 100K

BC847BPN(COL)
RES

2219

100n
5 I218 3227 I219 4 7224-2
BC847BPN(COL)

3226
10K
3 220K 5
3V3-ST
PDZ8.2-B 3
6225

3228

3229
6K8

10K
RES
+3V3-STANDBY
I213
6
RES 2220

H H
1n0

I214 DETECT-12V RES I207 F221

3204 68R STANDBY 2 7223-1 7204 ENABLE-3V3
BC847BPN(COL) F227
D 1M95 PDTC144EU
D
1n0

1n0

3230

3231
1

10K

3K3
F207
1
3232

2211
1K0

1u0

F208
2
F209
3 I216
2204

2205
RES
RES

F210
FROM PSU

4
F211
5
F212 +12V I217
6
I 7
8
F213
F214 +1V2-STANDBY
3233 3234 6 I
F215 +AUDIO-POWER
9 10K 22K I215
10
F216
GNDSND
2
F217
11
1-1735446-1
1 7224-1
BC847BPN(COL) DC / DC
E E
is prohibited without the written consent of the copyright

1n0
RES
2206

100n

2207

100n

2208

100n
RES
All rights reserved. Reproduction in whole or in parts

RES

J J
2230
RES

7222-1
ST1S10PH

1
6
GNDSND

SW
5221 I210 5222 F222
+12V 2 7 +1V2-PNX5100
INH VIN SW

22u
22u
22u
33R

22u
2u0

1%

220u 25V
5 3
SYNC VFB

2225

RES 3224

2227
4n7
GND

2221

2222

2223
10u

10u

10u
A P HS

100K

2224
2226

RES 2228

RES 2229
K K

4
8
9
F F
7222-2
owner.

ST1S10PH
F231 3223
SENSE+1V2-PNX5100
10 VIA 11 470R 1%

1K0 1%
3221

3222
4K7
L L

G G

M M

H H
N MULTI 12NC : 3139_123_64421 / 64541 / 64561 N
BD 12NC : 3139_123_64431 / 64551 / 64571
CELL 12C : 8239_125_14871

O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 O
CHN DC343514 SETNAME ********

CLASS_NO 1 2009-01-16
3PC332
PCB SB SSB BD 1 2008-12-16

-- -- -- 1
P 3139 123 6443
2008-10-17 2 TV543_2K9
2009-01-16 3 P
" X200 ~ X299 " NAME Kailash

SV CHECK
SUPERS.

DATE
**** *** *****

2008-10-17
25

C
10 130 02

ROYAL PHILIPS ELECTRONICS N.V. 2008

A2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18440_501_090223.eps
090224

2010-Jun-29
 Circuit Diagrams and PWB Layouts Q548.1E LA 10. EN 94

SSB: Front End

1300 E6 3398 F11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1301 D1 3399 F11
1303 G3 33AA H5
1304 E11 33AB H5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1306 F1
2300 F6
33AC H5
4302 E2
2301 C4 4303 F2

A FRONT END A
2302 E2
2304 D3
4304 F3
4306 E5
2305 D3 4307 F4
A A 2306 G4 4308 F5
2307 G4 4312 E5
2308 G7 4313 F5
2309 G8 4314 I15
2310 G8 4315 J15
2311 C12 4316 E2
2312 C12 4317 F7
2313 C12 4318 F7
B 3386 +5V
B 2314 C13 4319 F10
2315 C13 4320 H4
B 4R7 +1V2-PNX85XX
RES 5308 30R I324 +1V2 B 2316 C13 4321 H5
2317 C13 4322 I5
+3V3 7308 2318 C14 4323 G3
+5V-TUNER

5309
RES
LD1117DT12

4u7
7307
2319 C14 4324 G7

RES 5313
LK112SM50
5304 F308
3 2 2320 C14 4325 G7

30R
F306 7309 IN OUT +1V2A
5 4 LK112M33TR 2321 C13 4326 F1
+5V5-TUN IN OUT +5V-TUNER 10u

120R
3301

3318

2311

2312

2313

2314

100n
2315

100n
2316

100n
2317

100n

2318

100n
2319

100n
2320
C COM
C

RES
6K8

10u

10u

10u

2u2
+3V3B 2322 C13 4327 F1

2344

100n
1 3 5 4
SHDN BP +5V IN OUT 2323 C13 5301 D3

1
2324 C13 5302 G3
2336

2337

100n

2369
COM 1 3
1u0

2u2
SHDN BP
5305 F309
2325 D13 5303 G8

2301

2371

2372

100n

2373
COM 2326 D13 5304 B14

22n

1u0

2u2
2 +3V3E

C 30R
C 2327 D13 5305 C12

2321

100n
2322

2u2
2
2328 D13 5306 C12
2329 D14 5307 D14
2330 D14 5308 B11
D +5V-TUNER
5306 F310
+3V3D D 2331 E11 5309 B3
30R 2332 E11 5310 D4

2323

100n
2324

2u2
2334 F11 5311 H4
TUNER BOUNDARY SCAN 2335 H7 5313 B10

5301

30R
RF-AGC +3V3B 3354 F301
3350 10K
TDO 5307 F311
2336 C2 6301 H9
RES
5310 22R F302 +3V3A 2337 C2 6302 H10
3351 10K 2341 E7 7302 G5
TCK 10u

2325

100n
2326

100n
2327

2328

2329

2330

100n
2u2

2u2

2u2
47u 16V
E 30R F303
E 2342 E7 7303 E12
2304

100n
2305
3352 10K
D F304
TMS D 2344 C11 7307 B2
3353 10K 2345 H15 7308 B11
ANTENNA-SUPPLY TDI
2346 H14 7309 B9
* F305

+3V3B
1XXX

+3V3D
+3V3A

+3V3E

+1V2A
2347 G10 7312-1 G15

+1V2
I313 3316 47R +3V3B
HD1816 MK1 SCL-TUNER
I314 3317 47R
2348 G10 7312-2 G16
* I…C ADRESS C0 SDA-TUNER
2349 E5 7314-1 I15
+3V3B 2350 E5 7314-2 J16
4316
RES
RF-IN

2341

2342

10K
10K
10K
10K
10K
2351 F5 7315 H9

18p

18p
F * 2302 F 2352 F5 7316-1 I11
*TDTC-G321D
1XXX 7303
MT

MT
4n7 2353 F14 7316-2 J11

37

42

52

36
46

18
26
53

16
27
56
10K
F317 DRX3926K-XK-A3

4K7
4K7

2
DC_PWR ANT_PWR 2354 G16 7345-1 I15
LG1

VDDAH_AFE1

VDDAH_CVBS

VDDAH_OSC

VDDAL_AFE1
VDDAL_AFE2
F318 2358 4n7 2362 100n F327
* *

3393
RES 3394
RES 3395
RES 3396
RES 3397
NC1 B1 2331 VDDH VDDL
2355 H10 7345-2 H15

RES
F319
E RF_AGC
F320 RES 2363 4u7
RF_AGC Pend new 12nc
49 E

27M
NC2 SCL 12p XI 2356 H9 A310 E2
TUNER

TUNER

1304
F321 3308-4
* 2359 4n7 5 MSTRT 4 5 47R FE-SOP 2357 H8 A311 F2

3302
AS SDA MSTRT

3388
3365
F322 50 6 MERR F339 3308-3 3 6 47R
SCL B2 2332 XO MERR 2358 E2 A312 F1
F323 2349 100n F332 Φ 9 MCLK 3308-2 2 7 47R
SDA
F324 * VTU_TP MCLK
3308-1
FE-CLK
2359 E2 A322 E5

G
XTAL_OUT
F325 *2360 10n
* 2350 100n
4306
F333
F334
NC
IF-P
IF-N
12p 40
39
DEMODULATOR MVAL
10
11
MVAL
MD0 3309-4
1
4
8
5
47R
47R FE-DATA(0)
FE-VALID

G 2360 E2 A323 F5
+5V
A310 * IF_AGC 0
3309-3
IF_OUT1
A311 *4302 A328
*4312 A322
DIF2 I322 1
12 MD1
3309-2
3 6 47R FE-DATA(1) 2361 F5 A324 G7
IF_OUT2
*4303 4304
A329
*4313 A323
F335
DIF1
PDP
RES 2334 100n I323
47
48
P
PD
2
13
14
MD2
MD3 3309-1
2
1
7
8
47R
47R
FE-DATA(2)
FE-DATA(3)
2362 E5 A325 F6
MT

AIF N
MD
3
19 MD4 3310-4 4 5 47R FE-DATA(4)
2363 E2 A326 G7

100n

100n
RES PDN

100n

MT
4 2364 H4 A327 G6
RESET-SYSTEM 4319 32 20 MD5 3310-3 3 6 47R FE-DATA(5)
A312 RSTN 5 3310-2 2365 H6 A328 E4
4307

4308

21 MD6 2 7 47R FE-DATA(6)

6 3310-1 FE-DATA(0:7)
A325 31 22 MD7 1 8 47R FE-DATA(7) 2366 H6 A329 F4
2351
2361

2352
SAW_SW 7
RES 4XXX
RES 4XXX

F * * * * * SCL-SSB 3398 47R 23

SCL1 RF_AGC
33 RF-AGC F 2367 H4
2368 H6
F301 D11
F302 D11
H +5V-TUNER
SDA-SSB 3399 47R 24
SDA1
I2C
IF_AGC
34
I301
IF-AGC
H 2369 C3 F303 D11
SCL-TUNER F312 62 44 2353 100n 3355 18K +5V-TUNER 2370 G7 F304 D11
SCL2 SIF
SDA-TUNER F313 61 I2C 2371 C8 F305 D11
SDA2

470R
4317

4318

3356
43 2372 C9 F306 B3
CVBS

18p
18p
not in Arch2K8

2300

100n
1XXX
*HD1816 59
TCK I303 4
2373 C9 F308 B15
1

MK2 60 64 BC847BPN
7302
* *
RF-IN

TDI DA 7312-2 3301 C4 F309 C15

UPC3221GV-E1 57 63 5
TDO I2S CL

2347
2348
RES

RES
3302 E10 F310 C15
VCC

58 1 6
RES 3303 A324 2309 TMS WS
1303 2 INPUT1 OUTPUT1 7 IF-N 3 3303 G7 F311 D15
MT

5302 3357
I318
I DC_PWR
1
I O1
5 2306 10n
220R 100p ANTENNA-CTRL 4
GPIO1 VSYNC
29 2 7312-1
I 3304 G7 F312 F10

2308

2370

5303

680n
820n 2 4 2307 10n 30 BC847BPN

22p

2p2
NC1 IGND O2 GPIO2 10K 3305 H7 F313 F10
3 INPUT2 OUTPUT2 6 I319 1
G RF_AGC
NC2
3
GND
3304 2310
IF-P 66 84
3358 3359
G 3306 H3 F314 J16
TUNER

RESERVED 67 85 3307 H3 F315 I16

GND1

GND2

AS 220R A326 100p 3366

OFWX6966M 4 VAGC AGC CONTROL RES 68 86 3308-1 E15 F316 H8
SCL +3V3B 150R 150R
36M125 RES
4323

+5V-TUNER 4324 4K7 69 87 3308-2 E15 F317 E2

SDA
I325 SIF
is prohibited without the written consent of the copyright

4325 ANTENNA-SUPPLY 70 88 3311 100R

XTAL_OUT +3V3A
F336 71 89
3308-3 E15 F318 E2
All rights reserved. Reproduction in whole or in parts

+5V 3308-4 E15 F319 E2

2354
A327 72 90

3p3
BZX384-C6V8
IF_OUT1
3309-1 F15 F320 E2
3305

J IF_OUT2 6K8
+5V-TUNER 73 91
J

6302

2355

100n
74 92 3309-2 F15 F321 E2
F316 VIA VIA
MT

IF-AGC 75 93
+5V-TUNER
3309-3 E15 F322 E2
RES 76 94
3306 3309-4 E15 F323 E2

2356

100n
4320 I321 PDP 77 95 2346
78 96 I307 3348 3310-1 F15 F324 E2
0R05 2364 33AA 2365
510R

3310-2 F15 F325 E2

3307
RES

79 97
H 22u 18K
H

2
4

2345
80 98 3310-3 F15 F327 E5

22u
VSSAH_CVBS
560R

VSSAH_AFE1
10n 10n

VSSAL_AFE1
VSSAL_AFE2
VSSAH_OSC
RES 3XXX

RES 3XXX

470R
220K
RES 4321

RES 2366

100n

2335

3346
+5V-TUNER 81 99
22K
22n

+12V 3364 7345-2

+5V-TUNER
3310-4 F15 F332 E5
33AB

470R
5311

820n

1 7315 82 100 BC847BPN(COL)

GND_HS
BCP56 3311 G15 F333 E5
K 4K7 I326 3389
83 101
I308
4
K 3312 H7 F334 E5

100K
3387
3
VSSH VSSL 3313 H7 F335 F5

2357
6 5

22n
2367 33AC 2368 6301 2R2 3377 I327

150R
150R
38

41

51

35
45

7
17
25
54

3
15
28
55

65
PDN
3367 3345
3316 D7 F336 G10
2 7345-1 3
owner.

10n 560R 10n BAS316 100K 3317 D7 F337 I11

RES 4322

BC847BPN(COL)
2R2 +12V 10K 3318 C12 F338 J8

220R

220R
3368

3369
1
3349 3347 3391 3345 I14 F339 E14
I328 7316-1

RES 3360
RES 3361
8
3346 H15 I301 F14
* 1300 LGI
Y
RFS
N
3 LM393PT
1
3370 F337
SIF-GND
150R 150R
I306
18R
3347 I15 I303 F15
1301 N Y
I L 2302 N Y
I331
2
10K
4314
F315 3392 CVBS L I 3348 H15 I306 I15

4
3349 I14 I307 H14

10K
3371

3372
2349 Y N

27K

27K
RES BC857BS 68R 3350 D10 I308 H15
2350 Y N 3362 7314-1
1
3351 D10 I313 D7

3376
2351 Y N RES
2352 Y N 100R
2 3352 D10 I314 D7
2358 N Y 3353 D10 I318 G6
2359 N Y +12V 6
3354 D11 I319 G6
2360 N Y F338 7316-2
3355 F15 I321 H8

8
2361 Y N ANTENNA-CTRL 3373 10K 5 LM393PT 4315 F314 CVBS-TER-OUT
3356 F15 I322 F11
M 2362
4302
Y
N
N
Y +3V3
3374 2K7
I329
6
7
RES
3363
4 M 3357 G14 I323 F11
4303 N Y BC857BS 3358 G15 I324 B11

4
4304 Y N

3375
5 7314-2

4K7
100R RES 3359 G15 I325 G16
4306 Y N
J 4307 Y N 3 J 3360 I16 I326 H9
4308 Y N 3361 I16 I327 H11
4312 Y N 3362 I15 I328 I10
4313 Y N