a拉扎维模拟CMOS集成电路第二版最新答案

Design of Analog CMOS Integrated Circuits
Solution for Chapter 2 Problem 1P

Question:
For W/L = 50/0.5, plot the drain current of an NFET and a PFET as a function of |VGS| as |VGS| varies from
0 to 3 V. Assume that |VDS| = 3 V.
Step 1 Of 9
For NFET:
The schematic diagram of NFET is drawn as shown in Figure 1.
Step 2 Of 9
Refer to Figure 1, for the device is in off condition. Therefore, the drain current .
Consider the general expression for the drain current when .
…… (1)
Here,
is the drain current is, is the mobility of electrons, is the gate-source voltage, is the drain-source voltage, is the threshold
voltage, is the channel-length modulation coefficient, is the gate oxide capacitance per unit area, W is the width, and is the length,
which is .
Refer to Figure 1, .
Substitute for and for in equation (1).
…… (2)
Step 3 Of 9
Consider the expression for the gate oxide capacitance per unit area.
…… (3)
Here,
is the permittivity of the oxide, which is and is the gate oxide thickness.
Substitute for in equation (3).
…… (4)
Refer to Table 2.1 in the textbook for the term .
Refer to Table 2.1 in the textbook for the terms , , and .
Substitute for , for , for , 0.7 V for , for , 3 V for , and for
in equation (2).
…… (5)
Substitute the unit for in equation (5).
…… (6)
Step 4 Of 9
Consider if , then equation (6) becomes .
Consider .
Substitute 0.8 V for in equation (6).

Likewise, substitute the various values of in equation (6) to obtain the drain current , which are tabulated in Table 1.
Step 5 Of 9
Draw the plot between and as shown in Figure 2.
Thus, the Figure 2 shows the drain current of NFET as function of varies from 0 to 3 V.
Step 6 Of 9
For PFET:
Draw the schematic diagram of PFET as shown in Figure 3.
Step 7 Of 9
Refer to Figure 3, for the device is in off condition. Therefore, the drain current .
Consider the expression for the drain current when or .
…… (7)
Refer to Table 2.1 in the textbook for the terms , , and .
Substitute for , for , for , 0.8 V for , for , 3 V for , and for
in equation (7).
…… (8)
…… (9)
Step 8 Of 9
Consider if , then equation (9) becomes .

Consider .
Likewise, substitute the various values of in equation (9) to obtain the drain current which are tabulated in Table 2.
Step 9 Of 9
Figure 4 shows the plot drawn between and .
Thus, the Figure 4 shows the drain current of PFET as function of varies from 0 to 3 V.
Question:
For W/L = 50/0.5 and |ID| = 0.5 mA, calculate the transconductance and output impedance of both NMOS
and PMOS devices. Also, find the “intrinsic gain,” defined as gmrO.
Step 1 Of 7
For NMOS device:
Consider the general expression for the transconductance .
…… (1)
Here,
is the drain current, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width, and L is the length.
…… (2)
Here,
…… (3)
Step 2 Of 7
Substitute for , for , for and for in equation (1) to find the transconductance
.
…… (4)
Thus, the transconductance is .
Step 3 Of 7
Consider the general expression for the output resistance .
…… (5)
Here, is the channel-length modulation coefficient.
Substitute for and for in equation (5) to find the output resistance .
…… (6)
Thus, the output resistance or output impedance is .
Step 4 Of 7
Consider the expression for the intrinsic gain.
…… (7)

Thus, the intrinsic gain is .
Step 5 Of 7
For PMOS device:
Substitute for , for , for and for in equation (1) to find the transconductance
.
…… (8)
Step 6 Of 7
…… (9)

Thus, the output resistance or output impedance is .
Step 7 Of 7
Thus, the intrinsic gain is .

Question:
Derive expressions for gmrO in terms of ID and W/L. Plot gmrO as a function of ID with L as a parameter.
Note that λ ∝ 1/L.
Step 1 Of 5
Consider the expression for the transconductance .
…… (1)
Here,
is the drain current, is the mobility of electrons, is the gate oxide capacitance per unit area, is the width, and is the length.
…… (2)
Here,
is the channel-length modulation coefficient.
…… (3)
Step 2 Of 5
Consider the expression for the intrinsic gain A.
…… (4)
Substitute equations (1) and (3) in equation (4).
…… (5)
Here,
is constant, which is .
Rearrange the equation (5).
…… (6)
Step 3 Of 5
Consider for length and modify the equation (6).
…… (7)
Consider the parameter .
Substitute 1 for in equation (7).
…… (8)
Consider for length and modify equation (6).
…… (9)
Consider the parameter .
…… (10)
Consider for length and modify equation (6).
…… (11)
…… (12)
Consider the drain current is .

Step 4 Of 5
Likewise, substitute the various values of in equations (8), (10) and (12) to obtain the respective intrinsic gain A which are tabulated in Table 1.
Step 5 Of 5
Figure 1 shows the plot between and with L as a parameter.
Thus, the intrinsic gain in terms of and is derived and the Figure 1 shows the plot as function of with various values of L as
a parameter.
Question:
Plot ID versus VGS for a MOS transistor (a) with VDS as a parameter, and (b) with VBS as a parameter.
Identify the break points in the characteristics.
Step 1 Of 3
For NFET:
Step 2 Of 3
Refer to Figure 1.
Case I:
Consider that if , then the NFET device is in the off condition. Therefore, the drain current is approximately equal to zero. That is,
Case II:
Consider that if , then the NFET device operates in the saturation region.
Consider the expression for the drain current when .
Here, is the mobility of electrons, is the gate-source voltage, is the threshold voltage, is the gate oxide capacitance per unit area,
W is the channel width, and is the channel length.
Case III:
Consider that if , then the NFET device operates in the triode region.
Consider the expression for the drain current when .
Here, is the drain-source voltage.
Step 3 Of 3
(a)
Figure 2 shows the sketch for drain current versus gate-source voltage with as a parameter.
Refer to Figure 2; for various values of drain-source voltage , the characteristic curve is drawn between and .
For the constant voltage of , the drain current increases with the increase of gate-source voltage until the break point. Further
increase in results, the drain current in saturation part. The slope is drawn at a break point to determine the conductance of the device and
the threshold voltage . Likewise, for the constant values of drain-source voltage of and , the drain current increases with the
increase in , providing the respective threshold voltage at the break point, which is shown in Figure 2.
Thus, the drain current versus the gate-source voltage with as a parameter is and also the break points are identified in
the characteristics as shown in Figure 2.
(b)
Figure 3 shows the sketch for drain current versus gate-source voltage with as a parameter.
Refer to Figure 3, for various values of bulk-to-source voltage , characteristic curve is drawn between and . For , the gate-
source voltage increases with increase in drain current . Further increase of results, the drain current reaches saturation part. The
break point at which the saturation part occurs results the threshold voltage . Likewise, for , the gate-source voltage increases
with increase in drain current as shown in Figure 3. Consider if , then the characteristic curve just shift to the left side of . The
slope is drawn at a break point to determine the conductance of the device and also used to determine the threshold voltages.
Thus, the drain current versus the gate-source voltage with as a parameter is and also break points are identified in the
characteristics as shown in Figure 3.
Question:
Sketch IX and the transconductance of the transistor as a function of VX for each circuit in Fig. 2.47 as VX
varies from 0 to VDD. In part (a), assume that VX varies from 0 to 1.5 V.
Figure 2.47
Step 1 Of 22
(a)
Refer to Figure 2.42 (a) in the textbook for the circuit. Assume that the voltage varies from 0V to and the drain-drain voltage is 3 V.
Refer to Table 2.1 in the textbook for SPICE model for the NMOS device.
The body effect coefficient is , the channel-length modulation coefficient is , PHI is ,and the threshold
voltage is .
Refer to Figure 2.42 (a), consider the gate-source voltage is , the drain-source voltage is , and the bulk voltage at
source is .
Consider the expression for the drain current which is equal to in the NFET device , when it operates in the saturation region.
…… (1)
Here, is the mobility of electrons, is the gate-source voltage, is the drain-source voltage, is the threshold voltage, is the
channel-length modulation coefficient, is the gate oxide capacitance per unit area,W is the width, and is the length.
Step 2 Of 22
Write the expression for threshold voltage with body effect.
Here, is the body effect coefficient, is the threshold voltage, and is the bulk voltage at source.
Substitute 0.7 for , 0.45 for , 0.9 for , and for .
Substitute for , for , and for in equation (1).
…… (2)
Equation (2) is valid for .
Simplify the condition to find .
Simplify the condition.
Reduce the condition.
Choose the minimum value because the maximum supply voltage is 3 V. Therefore, .
Step 3 Of 22
For :
Substitute 0.1 for in equation (2).
Step 4 Of 22
Consider the expression for the trans conductance .
…… (3)
Here,
is the drain current.
Since, .
Substitute for .
For , the current is zero and hence the transconductance .
Step 5 Of 22
Draw the plot for the current and the transconductance of the transistor as a function of the voltage as shown in Figure 1.
In Figure 1, the curve shows that for as a function of . At , the current has some magnitude. At ,the current
gradually decreases until it reaches to 1.97 V.Further increase in voltage resultsin the current that is equal to zero upto the voltage
.
In Figure 1, the curve shows that for as a function of .At , the transconductance has some magnitude. At ,the
transconductance linearly decreases until it reaches to 1.97 V.Further increase in voltage resultsin the transconductance that is equal to zero
upto the voltage .
Thus, the plot drawn for the current and the transconductance of the transistor as a function of the voltage is shown in Figure 1.
Step 6 Of 22
(b)
Refer to Figure 2.42 (b) in the textbook for the circuit. Assume that the voltage varies from 0V to 1.5 V, the drain-drain voltage is 3 V, the
channel-length modulation coefficient is , and the body effect coefficient is .
In Figure 2.42 (b), for , the source and drain of the NFET device exchange their roles. Therefore, the gate-source voltage is
and the drain-source voltage is .
Consider the expression for overdrive voltage.
…… (4)
Substitute for and 0.7 for .
Consider the expression for the drain current , which is equal to in the NFET device .
Substitute for and for .
…… (5)
Step 7 Of 22
Calculate the transconductance of the NFET device .
…… (6)
Step 8 Of 22
…… (7)
Equations(5) and (7) are valid for .
Consider that the direction of current is reversed.Therefore, the gate-source voltage is and the drain-source voltage is
.
Substitute for and 0.7 for in equation (4).
For , the NFET device operates in the triode region.
Consider the expression for the drain current , which is equal to in the NFET device when it operates in the triode region.

Step 9 Of 22
For , the NFET device operates in the saturation region.
Consider the expression for the drain current , which is equal to in the NFET device when it operates in the saturation region.
Substitute 0.2 for .
Since, .
…… (8)
Step 10 Of 22
In Figure 2, the curve shows that as a function of . At , the current has some negative magnitude. At ,the current
gradually increases until it reaches to 1 V.Further increase in voltage resultsin the current that increases linearly upto the voltage 1.2 V.
When , the current becomes a constant value upto the voltage .
In Figure 2, the curve shows that as a function of . At , the transconductance has some negative magnitude. At ,the
transconductance linearly increases until it reaches to 1 V.Further increase in voltage resultsin the transconductance that increases linearly upto
the voltage 1.2 V. When , the transconductance becomes constant value upto the voltage .
Step 11 Of 22
(c)
Refer to Figure 2.42 (c) in the textbook for the circuit. Assume that the voltage varies from 0V to 1.5 V, the drain-drain voltage is 3 V, the
Refer to Figure 2.42 (c), consider that the source and drain of the NFET device exchange their roles. Therefore, the gate-source voltage is
For :
Consider the NFET device that moves into the saturation region. Therefore, consider the expression for the drain current which is equal to
in the NFET device , when it operates in the saturation region.
…… (9)
Equation (9) is valid for .
For :
Consider if the NFET device is turned off when , then the device never turns on again. Therefore, the current and the
transconductance .
Step 12 Of 22
gradually increases until it reaches to 0.3 V.Further increase in voltage resultsin the current that is equal to zero upto the voltage
.
In Figure 3, the curve shows that as a function of . At , the transconductance has some negative magnitude. At ,the
transconductance linearly increases until it reaches to 0.3 V.Further increase in voltage resultsin the transconductance that is equal to zero upto
the voltage .
Step 13 Of 22
(d)
Refer to Figure 2.42 (d) in the textbook for the circuit.Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, the
Refer to Table 2.1 in the textbook for SPICE model for PMOS device, the threshold voltage is .
Refer to Figure 2.42 (d), consider that the source and drain of the PFET device exchange their roles. Therefore, the gate-source voltage is
For :
Consider the expression for the drain current , which is equal to in the PFET device when it operates in the saturation region.
Here, is the mobility of holes.
Step 14 Of 22
…… (10)
Here,
Since, .
Substitute for .
Consider that the PFET device enters into the saturation region until the voltage . That is, . Further, the device
moves into the triode region.
Step 15 Of 22
For :
Consider the expression for the drain current , which is equal to in the PFET device when it operates in the triode region.
Substitute for , for , and for .
Calculate the transconductance of the PFET device .
…… (11)
Substitute for .
Step 16 Of 22
For :
Consider that the source and drain of the PFET device exchange their roles when . Therefore, the gate-source voltage is
Consider the expression for the drain current , which is equal to in the PFET device when it operates in the triode region.
Step 17 Of 22
remains constantat negative magnitude until it reaches to .Again when the voltage increases, then the current gradually increases and
reaches to . Further increase in voltage results in the magnitude of the current that increases graduallyupto the voltage
.
In Figure 4, the curve shows that as a function of . At , the transconductance has some magnitude. At ,the
transconductance remains constant at negative magnitude until it reaches to 1.8 V.Again, when the voltage increases, then the
transconductance increases linearly and reaches to . Further increase in voltage results in the magnitude of the transconductance
that increases linearly upto the voltage .
Step 18 Of 22
(e)
Refer to Figure 2.42 (e) in the textbook for the circuit.Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, and the
channel-length modulation coefficient is .
Refer to Table 2.1 in the textbook for the SPICE model for the NMOS device.
The body effect coefficient is , PHI is ,and the threshold voltage is .
Refer to Figure 2.42 (e), consider that the gate-source voltage is (that is, ), the drain-source voltage is
(that is, ), and the bulk voltage at source is .
Consider the expression for the drain current , which is equal to in the NFET device , when it operates in the saturation region.
…… (12)
Step 19 Of 22
Consider the expression for threshold voltage with the body effect.
Substitute 0.7 for , 0.45 for , 0.9 for , and for .
Substitute 0 for .
Substitute 0.9 for and for in equation (12).
…… (13)
Step 20 Of 22
…… (14)
Equations (13) and (14) are valid upto the edge of the triode region.
Step 21 Of 22
Square on both sides of the equation.
Step 22 Of 22
For , the NFET device moves into the triode region.
Consider the expression for the drain current , which is equal to in the NFET device when it operates in the triode region.
Substitute for , 0.9 for , and for .

In Figure 5, the curve shows that for as a function of . When the current increases gradually upto the voltage and again
increases the voltage to some extent, the curve linearly increases upto the voltage . Further when there is an increase in voltage ,
the current increases linearly upto the voltage .
In Figure 5, the curve shows that for as a function of .When the transconductance increases gradually upto the voltage
and again increases the voltage to some extent, the transconductance is constant upto the voltage . Further when there is an
increase in voltage , the transconductance remains constant throughout upto the voltage .
Question:
Sketch IX and the transconductance of the transistor as a function of VX for each circuit in Fig. 2.48 as VX
varies from 0 to VDD.
Figure 2.48
Step 1 Of 19
(a)
Refer to Figure 2.43 (a) in the textbook for the circuit. Assume that the voltage varies from0V to , the drain-drain voltage is 3 V, and the
body effect coefficient is .
Refer to Figure 2.43 (a), the source-gate voltage is and the source-drain voltage is .
For , the PFET device in the saturation region (or otherwise the PFET device in the off condition). Therefore, the condition
that exists in the saturation region is .

Step 2 Of 19
For , consider the expression for the drain current , which is equal to in the PFET device , when it operates in
the saturation region.
Here, is the mobility of holes, is the gate oxide capacitance per unit area, W is the channel width, is the channel length, and is the
threshold voltage.
Substitute for .
Step 3 Of 19
…… (1)
Here,
Since, .
Substitute for .
Step 4 Of 19
In Figure 1, the curve shows that for as a function of . At , the current has some magnitude. At ,the current
gradually decreases until it reaches to .Further increase in voltage resultsin the current that is equal to zero upto
the voltage .
In Figure 1, the curve shows that as a function of .At , the transconductance has some magnitude. At ,the
transconductance linearly decreases until it reaches to .Further increase in voltage resultsin the transconductance that
is equal to zero upto the voltage .
Step 5 Of 19
(b)
Refer to Figure 2.43 (b) in the textbook for the circuit. Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, and the
body effect coefficient is .
Refer to Figure 2.43 (b), the gate-source voltage is and the drain-source voltage is .
For , the NFET device in the saturation region (or otherwise the NFET device in the off condition). Therefore, the condition
that exists in the saturation region is .

Step 6 Of 19
For , consider the expression for the drain current , which is equal to in the NFET device , when it operates in
the saturation region.
Here, is the mobility of electrons and is the gate-source voltage.
Substitute for .
Step 7 Of 19
…… (2)
Here,
Since, .
…… (3)
Substitute for .
Step 8 Of 19
In Figure 2, the curve shows that as a function of . At , the current has some magnitude. At ,the current gradually
decreases until it reaches to .Further increase in voltage resultsin the current that is equal to zero upto the voltage
.
transconductance linearly decreases until it reaches to .Further increase in voltage resultsin the transconductance that
is equal to zero upto the voltage .
Step 9 Of 19
(c)
Refer to Figure 2.43 (c) in the textbook for the circuit. Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, and the
body effect coefficient is . Consider that the current flow through the resistor due to voltage is . Considerthat the currents
and have the same polarity,so that the range of current is .
Refer to Figure 2.43 (c), the gate-source voltage is and the drain-source voltage is .
For , the NFET device is in the triode region. Therefore, consider the expression for the drain current , which is equal to
in the NFET device , when it operates in thetriode region.
Calculate the transconductance of the transistor in the triode region.
Step 10 Of 19
Substitute for .
Now, consider the NFET device that moves into the saturation region. Therefore, consider the expression for the drain current , which is
equal to in the NFET device , when it operates in the saturation region.
Substitute for .
Now, consider the NFET device is turned off when the voltage .
Step 11 Of 19
In Figure 3, the curve shows that for as a function of . At , the current has some magnitude, which is less than . At
,the current gradually decreases until it reaches to .Further increase in voltage resultsin the current again, which decreases
upto the voltage .When , then the current equals to zero upto the voltage .
In Figure 3, the curve shows that for as a function of . At , the transconductance has some magnitude. At ,the
transconductance gradually increases until it reaches to .Further increase in voltage resultsin the transconductance that gradually
decreases upto the voltage . When , then the current equals to zero upto the voltage .
Step 12 Of 19
(d)
Refer to Figure 2.43 (d) in the textbook for the circuit. Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, and the
body effect coefficient is . Consider the current flow through the resistor due to voltage is . Assume that the drop is
greater than the threshold voltage.
Refer to Figure 2.43 (c), the gate-source voltage is and the drain-source voltage is .
For , the NFET device is in the saturation region. Therefore, consider the expression for the drain current , which is equal
to in the NFET device , when it operates in thesaturation region.
Substitute for .
Step 13 Of 19
Step 14 Of 19
For , the NFET device moves into the triode region. Therefore, consider the expression for the drain current , which is equal
to in the NFET device , when it operates in the triode region.
…… (4)
…… (5)
From equation (5), the second term represents that the current decreases with increase in voltage . Therefore, the polarity of the current
changes with an increase in voltage .
Substitute for .
Step 15 Of 19
In Figure 4, the curve shows that as a function of . At , the current has some magnitude. At ,the current remains
constant until it reaches to .Again the voltage increases, then the current gradually decreases and reaches to zero. Further
increase in voltage results in the magnitude of the current that decreases with a negative polarityupto the voltage .
transconductance remains constant until it reaches to .Again, the voltage increases, then the transconductance decreases suddenly
and reaches to zero. Further increase in voltage results in the magnitude of the transconductance that decreases with negative polarity. After
some time, the transconductance remains constant upto the voltage .
Step 16 Of 19
(e)
Refer to Figure 2.43 (e) in the textbook for the circuit. Assume that the voltage varies from 0V to , the drain-drain voltage is 3 V, and the
body effect coefficient is . Consider that the current flow through the resistor due to voltage is .
Step 17 Of 19
For , the NFET device is in the off condition. Therefore, the current and the transconductance . Now, consider
that the device is turned on (that is, saturation region).
Consider the expression for the drain current , which is equal to in the NFET device , when it operates in the saturation region.
Refer to Figure 2.43 (e), consider that the NFET device is in the saturation region until the gate-drain voltage is . Consider
that the gate-drain voltage is equal to the threshold voltage in the saturation region. Therefore, .
Rearrange the threshold equation .
Substitute for .
Reduce the expression.
Step 18 Of 19
Refer to Figure 2.43 (e), the gate-source voltage is and the drain-source voltage is . For
, the NFET device moves into the triode region.
Substitute for .
Step 19 Of 19
In Figure 5, the curve shows that as a function of . When , the current . For , the current
increases linearly with the an increase in voltage upto . Further when there is an increase in voltage , the current gradually
increases upto the voltage .
In Figure 5, the curve shows that as a function of . When , the transconductance . For ,
the transconductance increases linearly with the increase in voltage to some extent. Further increase in voltage , the transconductance
decreases gradually upto the voltage .
Question:
Sketch Vout as a function of Vin for each circuit in Fig. 2.49 as Vin varies from 0 to VDD.
Figure 2.49
Step 1 Of 17
(a)
Refer to Figure 2.44 (a) in the textbook for the circuit. Assume that the input voltage varies from 0 V to , the drain-drain voltage is 3 V, the
The modified circuit of Figure 2.44 (a) is shown in Figure 1 when the drain and source interchange their roles after a definite time.
Step 2 Of 17
Refer to Figure 1;
For , the NFET device is in off condition. Therefore, the output voltage is equal to zero.
Consider the NFET device moves into saturation region for the range of input voltage .
Consider the expression for the drain current using Ohm’s law.
Here, is the output voltage and is the resistance of the resistor.
Step 3 Of 17
Consider the expression for the drain current in the NFET device when operates in saturation region.
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, and is the channel length, is
the threshold voltage, and is the input voltage.
Refer to Figure 1, the gate-source voltage is and the drain-source voltage is .
Substitute for .
…… (1)
Equation (1) represents the input-output relationship for the device in saturation region.
Step 4 Of 17
For , the NFET device moves into triode region
Consider the expression for the drain current in the NFET device when operates in triode region.
Substitute for , for , and 0.7 for .
…… (2)
Equation (2) represents the input-output relationship for the device in triode region.
Step 5 Of 17
Draw the plot for output voltage as a function of input voltage as shown in Figure 2.
In Figure 2, the input voltage from 0 V to 0.7 V, the output voltage is zero with condition the device is in off condition. For ,
the output voltage increases linearly with increase in output voltage. When , the voltage gradually increases and the reaches the
maximum voltage of 1 V and remains constant until the input voltage equal to .
Step 6 Of 17
Thus, the plot drawn for the output voltage as a function of input voltage which varies from 0 to 3 V and it is shown in Figure 2.
Step 7 Of 17
(b)
Refer to Figure 2.44 (b) in the textbook for the circuit. Assume that the input voltage varies from 0 V to , the drain-drain voltage is 3 V, the
The modified circuit of Figure 2.44 (b) is shown in Figure 3 when the drain and source interchange their roles after a definite time.
Step 8 Of 17
Refer to Figure 3;
For , the NFET device is in triode region. In this Figure 3, the gate-source voltage is and the drain-source
voltage is .
…… (3)
…… (4)
Step 9 Of 17
Substitute for .
…… (5)
Step 10 Of 17
In Figure 4, the input voltage increases linearly with increase in output voltage until it reaches to 1.3 V. For , the output voltage remains
constant because the output voltage does not depends on input voltage from equation (5).
Step 11 Of 17
(c)
Refer to Figure 2.44 (c) in the textbook for the circuit. Assume that the input voltage varies from 0 V to , the drain-drain voltage is 3 V, the
For , the NFET device is in triode region. In Figure 2.44 (c), the gate-source voltage is and the drain-source
voltage is .
…… (6)
…… (7)
Step 12 Of 17
Substitute for .
…… (8)
Step 13 Of 17
In Figure 5, the input voltage increases linearly with increase in output voltage until it reaches to 2.3 V. For , the output voltage remains
constant because the output voltage does not depends on input voltage from equation (8).
Step 14 Of 17
(d)
Refer to Figure 2.44 (d) in the textbook for the circuit. Assume that the input voltage varies from 0 V to , the drain-drain voltage is 3 V, the
channel-length modulation coefficient is , and the body effect coefficient is . In this figure, for PFET device the magnitude of
threshold voltage is 0.8 V.
Refer to Figure 2.44 (d);
For , the NFET device is in off condition. Therefore, the output voltage is equal to zero. After sometime the PFET device
turned on and enters into saturation region. Therefore, the output voltage goes up until it reaches to . Further, the PFET device moves
into the triode region.
Step 15 Of 17
Consider the expression for the drain current in the PFET device when and .
Substitute for .
…… (9)
Consider the equation (9) is good for the range of input voltage. That is,
Step 16 Of 17
For :
In this condition, consider the expression for the drain current in the PFET device operates in triode region.
Substitute for .
…… (10)
Step 17 Of 17
In Figure 6, for , the output voltage is equal to zero. When , the output voltage increases linearly with the increase in input
voltage until the output voltage is equal to 1.8 V. Further increase in input voltage results that the output voltage start raising until the input voltage
equal to .
Question:
Sketch Vout as a function of Vin for each circuit in Fig. 2.50 as Vin varies from 0 to VDD.
Figure 2.50
Step 1 Of 13
(a)
Refer to Figure 2.45 (a) in the textbook for the circuit. Assume that the input voltage varies from 0 V to and the drain-drain voltage is 3 V.
Consider the source voltage as and the bulk voltage as .
Consider the expression for the bulk voltage at source.
Step 2 Of 13
Consider the expression for the drain current in the NFET device when it operates in the saturation region.
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, is the channel length, is the
threshold voltage, and is the output voltage.
From Figure 2.45 (a), the drain current is equal to the current . Therefore,
…… (1)
Step 3 Of 13
…… (2)
Substitute equation (2) in (1).
Substitute for .
…… (3)
Using equation (3), the output voltage is obtained for the different values of input voltage.
Step 4 Of 13
In Figure 1, if the device operates in saturation region, then the output voltage exists when the input voltage equals to zero. Further increase in input
voltage result that the output voltage starts decreasing to some voltage upto .
Thus, the plot drawn for the output voltage as a function of input voltage, which varies from 0 to is shown in Figure 1.
Step 5 Of 13
(b)
Refer to Figure 2.45 (b) in the textbook for the circuit. Assume that the input voltage varies from 0V to and the drain-drain voltage is 3 V.
Consider the bulk voltage at source as and the bulk-source voltage as .
Substitute for .
…… (4)
Step 6 Of 13
Refer to Table 2.1 in the textbook for SPICE models for NMOS device for the term PHI , GAMMA , VTO .
Substitute 0.9 for , 0.7 for , and 0.45 for in equation (4).
Assume that the input voltage varies from 0 to 1.9 V and the resistor is small enough to assure that the NFET device remains in the
saturation region.
Step 7 Of 13
Consider the expression for the drain current in the NFET device when it operates in the saturation region.
Substitute for .
Refer to Figure 2.45 (b), consider the expression for the output voltage.
Substitute for .
Step 8 Of 13
In Figure 2, if the device operates in saturation region, then the output voltage exists when the input voltage equals zero. Further increase in input
voltage result that the output voltage starts decreasing to some voltage and even extend upto with minimum output voltage.
Step 9 Of 13
(c)
Refer to Figure 2.45 (c) in the textbook for the circuit. Assume that the input voltage varies from 0V to and the drain-drain voltage is 3 V.
Consider the gate-source voltage is and the bulk voltage at source is .
The modified circuit of Figure 2.45 (c) is shown in Figure 3 when the drain and source interchange their roles after a definite time.
Step 10 Of 13
Refer to Figure 3;
Assume that the bulk voltage at source is greater than . Consider the NFET device operates in the saturation for or
.
Substitute for .
…… (5)
Refer to Table 2.1 in the textbook for SPICE models for NMOS device for the term PHI , GAMMA , VTO .
Substitute 0.9 for , 0.7 for , and 0.45 for in equation (5).
Step 11 Of 13
Refer to Figure 3, consider the expression for the drain current in the NFET device when it operates in the saturation region.
Substitute for .
…… (6)
Step 12 Of 13
Refer to Figure 3, consider the expression for the drain current using Ohm’s law.
…… (7)
Step 13 Of 13
In Figure 4, if the device operates in saturation region, then the minimum output voltage exists when the input voltage equals to zero. Further
increase in input voltage result that the output voltage gradually increases to some voltage and even extends upto with the increase in output
voltage.
Question:
Sketch VX and IX as a function of time for each circuit in Fig. 2.51. The initial voltage of C1 is equal to 3 V.
In part (e), assume that the switch turns off at t = 0.
Figure 2.51
Step 1 Of 18
(a)
Refer to Figure 2.46 (a) in the textbook for the circuit. Assume that the channel-length modulation coefficient is , the body effect coefficient
is , and the initial voltage of the capacitor is 3 V.
Refer to Figure 2.46 (a), consider the expression for the drain current, which is equal to when the device operates in the saturation region for
.
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, and is the channel length, and
is the threshold voltage.
Refer to Figure 2.46 (a), write the expression for the voltage at node X.
Here, is the capacitance of the capacitor.
Substitute for .
Step 2 Of 18
Refer to Figure 2.46 (a), consider the expression for the drain current, which is equal to when the device moves into the saturation region for
.
Write the expression for the current .
…… (1)
Substitute for .
…… (2)
Here, consider .
Step 3 Of 18
Integrate the equation.
…… (3)
Step 4 Of 18
Substitute for t and for to find k.

Substitute 0 for k in equation (3).
Step 5 Of 18
Simplify the equation.
Step 6 Of 18
Draw the plot for and as a function of time as shown in Figure 1.
In Figure 1, the curve shows the voltage at node X. In this curve, when the time increases, the voltage starts decreasing from the initial voltage of
capacitor to 3 V. When , the voltage at node X is equal to , then gradually decreases to zero. Likewise, the curve shows the
current .When the time increases from zero, the current remains constant upto ,then gradually decreases from the respective current to
zero.
Thus, the plot drawn for the voltage at node X and current at node Xas a function of time is shown in Figure 1.
Step 7 Of 18
(b)
Refer to Figure 2.46 (b) in the textbook for the circuit. Assume that the channel-length modulation coefficient is , the body effect coefficient
Refer to Figure 2.46 (b), consider the expression for the drain current, which is equal to when the device operates always in the saturation
region.
Here, is the voltage at node X.

Refer to Part (a).
Substitute for .
Step 8 Of 18
…… (4)
Substitute for t and 3 for to find k.
Step 9 Of 18
Substitute for k in equation (4).

Step 10 Of 18
In Figure 2, at time , the voltage at node X is equal to 3 V. After sometime, the voltage at node Xgradually decreases from 3 V and reaches
to 0.7 V. When there is a further increase in time, the voltage at node X remains constant at 0.7 V. Likewise, at time , the current has the
magnitude of drain current,which is equal to and gradually decreases until it reaches to zero when time increases.
Thus, the plot drawn for the voltage at node X and current at node X as a function of time is shown in Figure 2.
Step 11 Of 18
(c)
Refer to Figure 2.46 (c) in the textbook for the circuit. Assume that the channel-length modulation coefficient is , the body effect coefficient
is , the drain-drain voltage is 3 V, and the initial voltage of the capacitor is 3 V.
Refer to Figure 2.46 (c), at time , the voltage at node Xis equal to the voltage across the capacitor . That is, . The drain-drain
voltageis . Hence, the NFET device is in the off condition and the device is not turned on,so that the circuit remains in this state.
Thus, the voltage at node X is and the current .
Step 12 Of 18
In Figure 3, the voltage at node X remains constant at 3 V and the current .

Step 13 Of 18
(d)
Refer to Figure 2.46 (d) in the textbook for the circuit. Assume that the channel-length modulation coefficient is , the body effect coefficient
Refer to Figure 2.46 (d), consider the current is equal to the current .That is, . Write the expression for the current .
Substitute for .
…… (5)
Step 14 Of 18
Substitute 3 for and 0 for t.
Substitute 3 for k in equation (5).

Step 15 Of 18
In Figure 4, at ,the voltage at node X is equal to 3 V. Further increase in time results in the voltage at node X startsgradually decreasing to
zero. After sometime, the voltage at node X is a negative value and the current .
Step 16 Of 18
(e)
Refer to Figure 2.46 (e) in the textbook for the circuit. Assume that the channel-length modulation coefficient is , the body effect coefficient
Step 17 Of 18
The Figure 2.46 (e) is redrawn with current directions as shown in Figure 5.
Refer to Figure 5, the current through the NFET device is . Therefore, the gate-source voltage is developed and the voltage at node X is
equal to and the current .
At , the drain current of the NFET device flows from the capacitor . That is, since . Therefore, the current
. Consider, if the source current is ideal, then the voltage at node N jumps into . If the current is not ideal, then voltage at node N
jumps to zero and discharges the capacitor through the NFET device .
Step 18 Of 18

In Figure 1, the curve shows the voltage at node X. In this curve, at time ,the voltage at node X has some voltage and starts gradually
decreasing to zero. Likewise, the voltage at node N is shown in curve because it is actually about 0.6 V and decreases to zero when time
increases.
In Figure 1, the curve shows the current . In this curve, the current at time and raises steeply to some extent. Further increase in
time results in the current that gradually decreases to zero.
Question:
Sketch VX and IX as a function of time for each circuit in Fig. 2.52. The initial voltage of each capacitor is
shown.
Figure 2.52
Step 1 Of 18
(a)
Refer to Figure 2.47 (a) in the textbook for the circuit. Assume that the initial voltage of the capacitor is 1 V and the initial voltage of the
capacitor is 3 V.
Figure 2.47 (a) is redrawn as shown in Figure 1.
Step 2 Of 18
Refer to Figure 1, write the expression for the gate voltage .
Here, is the source current, t is time, and is the capacitance of the capacitor.
Consider the circuit settles at . In Figure 1, when the gate voltage , then the drain current is equal to negative of current through the
NFET device and the drain-source voltage is equal to zero. Because, the drain and source interchange their roles after a definite time at which
the current and after sometime the voltage at node X becomes negative. In this condition, the NFET device operate in triode region.
Step 3 Of 18
Refer to Figure 1, write the expression for the drain current in the NFET device .
Here, is the mobility of electrons, is the gate voltage, is the threshold voltage, is the gate oxide capacitance per unit area, W is the
channel width, and is the channel length, and is the node voltage at point X.
Substitute for and 0.7 V for .
Step 4 Of 18
Refer to Figure 1, write the expression for the current .
Substitute for .
Step 5 Of 18

Step 6 Of 18
In Figure 2, the curve shows the voltage at node X. In this curve, when the time increase the voltage starts decreasing from the initial voltage of
capacitor to zero and move to negative value and then start raising until it reaches to zero. Likewise, when the time increases, the current
start decreasing from the respective current to zero and reaches to zero for the negative maximum of voltage at node X and further reaches to
negative value and then start raising until it reaches to zero.
Step 7 Of 18
(b)
Refer to Figure 2.47 (b) in the textbook for the circuit. Assume that the initial voltage of the capacitor is 1 V and the initial voltage of the
capacitor is 3 V.
Figure 2.47 (b) is redrawn as shown in Figure 3.
Step 8 Of 18
In Figure 3, consider the drain and source interchange their roles after a definite time. So that the elements connected in the source and drain are
interchanged which is shown in Figure 4.
The modified circuit of Figure 3 is shown in Figure 4.
Step 9 Of 18
Consider the expression for the drain current in terms of q and dt.
Here, q is the charge of electron.

Refer to Figure 4, write the expression for the voltage at node X.
…… (1)
Refer to Figure 4, write the expression for the drain voltage.
…… (2)
Since, .
In Figure 4, the voltage at node X goes up until the NFET device turns off when .
Substitute 2 V for and 0.7 V for .
Step 10 Of 18
Assume that the NFET device is in saturation region. Here, the assumption is correct only if
Rewrite the equation (1).
Substitute for t.
Substitute 1.3 V for .
Step 11 Of 18
Substitute for t.
Substitute for .
Therefore,
Step 12 Of 18
Refer to Figure 4, write the expression for the drain current in the NFET device .
Substitute for .
Rearrange the equation.
…… (3)
Here, consider .
Step 13 Of 18
…… (4)
Substitute 0 for t and q to find k.
Step 14 Of 18
Step 15 Of 18
Substitute for .
Step 16 Of 18
In Figure 5, at time the voltage at node X is equal to 1 V. After sometime, the voltage at node X gradually raise from 1 V and reaches to 1.3
V. Further increase in time, the voltage at node X remains constant. At time , the current is negative. After increase in time, the current
gradually increasing until it reaches to zero.
Step 17 Of 18
(c)
Refer to Figure 2.47 (c) in the textbook for the circuit. Assume that the initial voltage of the capacitor is 1 V and the initial voltage of the
capacitor is 3 V.
Figure 2.47 (c) is redrawn as shown in Figure 3.
Step 18 Of 18
Refer to Figure 6, at time , the gate voltage is , the source voltage is and the node voltage is . Hence, the NFET
device is in off condition and the device is not turned on. So that, the circuit remains in this state. Thus, the voltage at node X is and
the current .
In Figure 7, the voltage at node X remains constant at 4 V and the current .

Question:
Sketch VX as a function of time for each circuit in Fig. 2.53. The initial voltage of each capacitor is shown.
Figure 2.53
Step 1 Of 19
(a)
Refer to Figure 2.48 (a) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V, and the
initial voltage of the capacitor is 1 V.
In Figure 2.48 (a), the voltage at node X goes up until the NFET device turns off when . Here, is the threshold voltage and
is the input voltage.
Step 2 Of 19
Consider the expression for the drain current in the NFET device .
Here, is the mobility of electrons, is the gate voltage, is the gate oxide capacitance per unit area, W is the channel width, and is the
channel length, and is the node voltage at point X.
Consider the expression for the drain current .
Substitute for .
…… (1)
Here, consider .
Step 3 Of 19
…… (2)
Substitute 0 for t and 1 V for to find k.
Step 4 Of 19
Substitute 0 for t.
Step 5 Of 19
Draw the plot for as a function of time as shown in Figure 1.
In Figure 1, at time the voltage at node X is equal to 1 V. After sometime, the voltage at node X gradually raise from 1 V and reaches to the
maximum voltage 2.3 V. Further increase in time, the voltage at node X remains constant.
Thus, the plot drawn for the voltage at node X as a function of time is shown in Figure 1.
Step 6 Of 19
(b)
Refer to Figure 2.48 (b) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V and the initial voltage of the capacitor
is 1 V.
In Figure 2.48 (b), consider the NFET device turned on at , and discharges of capacitor until the voltage at node X equal to zero.
Assume that the NFET device operates in triode region.
Here, is the gate voltage.
Step 7 Of 19
Substitute for .
…… (3)
Here, consider .
Rewrite the equation.
…… (4)
Substitute 0 for t and 1 for to find k in equation (4).
Step 8 Of 19

Substitute 0 for t.
Step 9 Of 19
In Figure 2, at time the voltage at node X is 1 V. Further increase in time, the voltage at node X gradually decreases until it reaches to zero.
Step 10 Of 19
(c)
Refer to Figure 2.48 (c) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V and the initial voltage of the capacitor
is 2 V.
Refer to Figure 2.48 (c), at time , the node voltage at X is and the NFET device in saturation region.
In Figure 2.48 (c), the voltage at node X goes up until the NFET device turns off when .
That is, the voltage at node X decreases until it reaches the voltage at .
Therefore, the NFET device moves into triode region.
For :
Consider the expression for the voltage at node X.
Substitute for .
Step 11 Of 19
For :

Substitute for .
…… (5)
Here, consider .
Step 12 Of 19
Reduce the equation.

Step 13 Of 19
In Figure 3, the voltage at node X starts the voltage at 2 V due to the voltage across the capacitor when and at the voltage reaches
to 5V. Further increase in time results that the voltage starts decreasing but whereas at the voltage at node X is equal to 2.3 V. When ,
the voltage at node X gradually decreasing and reaches to zero.
Step 14 Of 19
(d)
Refer to Figure 2.48 (d) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V and the
Refer to Figure 2.48 (d), at time , the node voltage at X is and the NFET device in saturation region.
Step 15 Of 19
In Figure 2.48 (d), the voltage at node X goes up until the NFET device turns off when .

That is, the voltage at node X decreases until it reaches the voltage at .
Therefore, the NFET device moves into triode region.
For :
Substitute for .
Step 16 Of 19
For :
Substitute for .
…… (6)
Here, consider .
Step 17 Of 19

…… (7)
Step 18 Of 19
Step 19 Of 19

In Figure 4, the voltage at node X starts the voltage at 6 V when and at the voltage reduced to 3V. Further increase in time results
that the voltage starts decreasing but whereas at the voltage at node X is equal to 2.3 V. When , the voltage at node X gradually
decreasing and reaches to zero.
Question:
Sketch VX as a function of time for each circuit in Fig. 2.54. The initial voltage of each capacitor is shown.
Figure 2.54
Step 1 Of 21
(a)
Refer to Figure 2.49 (a) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V, and the
The modified circuit of Figure 2.49 (a) is shown in Figure 1 for .
In Figure 1, consider the NFET device is in triode region for .
…… (1)
Here, is the mobility of electrons, is the gate voltage, is the gate oxide capacitance per unit area, W is the channel width, and is the
channel length, and is the node voltage at point X.
Step 2 Of 21
Consider the voltage at node X goes up until the NFET device turns off when . Here, is the threshold voltage and is the
input voltage.
Refer to Figure 1, the drain-source voltage is equal to . The voltage at node X is .
Step 3 Of 21
Substitute for .
…… (2)
Here, consider .
Step 4 Of 21

…… (3)
Step 5 Of 21
Substitute 0 for t and for to find k in equation (3).
Step 6 Of 21

In Figure 2, when the voltage at node X is equal to zero. At time , the voltage at node X is equal to . After sometime, the voltage
at node X gradually raising from and reaches to zero.
Step 7 Of 21
(b)
Refer to Figure 2.49 (b) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V, and the
The modified circuit of Figure 2.49 (b) is shown in Figure 3 for .
Step 8 Of 21
In Figure 3, consider the NFET device is in saturation region for .

…… (4)
Consider the voltage at node X goes up until the NFET device turns off when . Here, is the threshold voltage and is the
input voltage.
Step 9 Of 21
Refer to Figure 3, the voltage at node X is .
Substitute for .
Substitute for .
…… (5)
Step 10 Of 21
Substitute 0 for t and 0 for to find k in equation (5).

Step 11 Of 21

In Figure 4, at time the voltage at node X is 0 V. Further increase in time, the voltage at node X gradually increases until it reaches to the
maximum voltage 2.3 V and remains constant.
Step 12 Of 21
(c)
Refer to Figure 2.49 (c) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V, and the
In Figure 2.49 (c), at , the drain voltage is , , and . Therefore, the drain-source voltage is and the
current . Hence, the circuit remains in this condition. That is, and .
Step 13 Of 21

In Figure 5, when the voltage at node X is equal to 3 V due to the voltage across the capacitor . When the voltage reaches to 6
V. Further increase in time results that the voltage remains constant at 6 V.
Step 14 Of 21
(d)
Refer to Figure 2.49 (d) in the textbook for the circuit. Assume that the input voltage varies from 0V to 3 V, the drain-drain voltage is 3 V, the
initial voltage of the capacitor is 3 V, and the initial voltage of the capacitor is 3 V.
In Figure 2.49 (d), assume that the device remains in the saturation region until the NFET device turned off when gate-source voltage is 0.7 V.
Refer to Figure 2.49 (d);
Consider the expression for the voltage across the capacitor .
Since, . Therefore,
…… (6)
Consider the expression for the voltage across the capacitor .
Since, . Therefore,
…… (7)
Step 15 Of 21
Consider the assumption is correct only if when .

Consider the expression for the drain current in terms of q and dt.
Here, q is the charge of electron.

Therefore, rewrite the equation.
…… (8)
Step 16 Of 21
Substitute for q in equation (8).
Step 17 Of 21
Using this assumption and refer to Figure 2.49 (d), write the expression for the drain current in the NFET device .
Substitute for .
…… (9)
Here, consider .
Step 18 Of 21

…… (9)
Substitute 0 for t and 0 for to find k.
Step 19 Of 21
Refer to Figure 2.49 (d), consider the expression for the voltage at node X.
…… (10)
Step 20 Of 21
Substitute 0 for t.
Step 21 Of 21
In Figure 6, the voltage at node X starts the voltage at 6 V due to the voltage across the capacitors and when and at the
voltage reaches to 9V. Further increase in time results that the voltage starts decreasing and reaches the node voltage is equal to
.
Question:
The transit frequency, fT, of a MOSFET is defined as the frequency at which the small-signal current gain
of the device drops to unity while the source and drain terminals are held at ac ground.
(a) Prove that
Note that fT does not include the effect of the S/D junction capacitance.
(b) Suppose the gate resistance, RG, is significant and the device is modeled as a distributed set of
n transistors, each with a gate resistance equal to RG/n. Prove that the fT of the device is
independent of RG and still equal to the value given above.
(c) For a given bias current, the minimum allowable drain-source voltage for operation in
saturation can be reduced only by increasing the width and hence the capacitances of the
transistor. Using square-law characteristics, prove that
This relation indicates how the speed is limited as a device is designed to operate with lower
supply voltages.
Step 1 Of 12
(a)
Figure 1 shows the MOS device capacitances of the circuit as follows:
In Figure 1, apply Kirchhoff’s current law at node .

Here, is the complex parameter, is the gate-source voltage, is the gate-drain capacitance per unit width, and is the gate-source
capacitance per unit width.
Step 2 Of 12
Consider the expression for the output current .
Here, is the transconductance.

Write the expression to calculate the short-circuit current gain.
…… (1)
Step 3 Of 12
Consider the complex plane . Here, is the transit angular frequency.
Substitute for s in equation (1).
Consider that the magnitude of current gain is equal to 1. That is,
Substitute for .
…… (2)
Step 4 Of 12
Write the general expression for the transit angular frequency.
Here, is the transit frequency.
…… (3)
Thus, the transit frequency is .
Step 5 Of 12
(b)
Figure 2 shows the MOSFET device that is modeled as a distributed set of n transistors as follows:
Step 6 Of 12
Figure 3 shows the equivalent circuit model for a distributed set of n transistors as follows:
Refer to Figure 3; consider the expression for current .
…… (4)
Here, i is an integer, which is .
Step 7 Of 12
Consider the expression for the input current using Kirchhoff’s current law in Figure 3.
…… (5)
Equate equation (4) and (5).
…… (6)
Equate the integer terms in equation (6).
, , ,
Step 8 Of 12
Consider the expression for the output current in Figure 3.
…… (7)
From equation (7), consider the first term of the output current . That is,
Step 9 Of 12
Consider the expression for the short-circuit current gain.
Substitute for s.
Consider that the magnitude of current gain is equal to 1. That is,
Step 10 Of 12
Substitute for .
…… (8)
Thus, the transit frequency is independent of gate resistance and the value of is .
Step 11 Of 12
(c)
Write the expression for the transconductance .
Here, is the mobility of electrons, is the threshold voltage, is the gate oxide capacitance per unit area, W is the channel width, and L is
the channel length.
Consider that the total capacitance of parallel capacitors and is approximately equal to . That is,
Here, is the gate oxide capacitance per unit area.
Step 12 Of 12
…… (9)
Consider that the minimum drain-source voltage to operate the device in saturation region is done by increasing the width. Obviously, the device
length is reduced for the respective increase in width using ratio. From equation (7), it is analyzed that the transit frequency increases with
the lower value of device length L. Therefore, the speed of the MOSFET device is limited to operate with lower supply voltage.
Thus, the transit frequency is , and the speed of the MOSFET device limited to operate with lower supply voltage is
explained using the transit frequency relationship.
Question:
Calculate the fT of a MOS device in the subthreshold region and compare the result with that obtained in
Prob. 2.13.
The transit frequency, fT, of a MOSFET is defined as the frequency at which the small-signal current gain
of the device drops to unity while the source and drain terminals are held at ac ground.
(a) Prove that
Note that fT does not include the effect of the S/D junction capacitance.
(b) Suppose the gate resistance, RG, is significant and the device is modeled as a distributed set of
n transistors, each with a gate resistance equal to RG/n. Prove that the fT of the device is
independent of RG and still equal to the value given above.
(c) For a given bias current, the minimum allowable drain-source voltage for operation in
saturation can be reduced only by increasing the width and hence the capacitances of the
transistor. Using square-law characteristics, prove that
This relation indicates how the speed is limited as a device is designed to operate with lower
supply voltages.
Step 1 Of 3
Refer to Problem 2.13 in the textbook.
Consider the general expression for the transit frequency .
…… (1)
Here,
is the transconductance, is the gate-drain capacitance per unit width, and is the gate-source capacitance per unit width.
Write the general expression for the transconductance .
…… (2)
Here,
is the drain current and is the volt equivalent of temperature, which is .

Consider the expression for the subthreshold.
Step 2 Of 3
…… (3)
Substitute equation (2) in equation (3).
…… (4)
Thus, the transit frequency of a MOS device in the subthreshold region is .
Step 3 Of 3
Consider the overlap capacitance per unit width is .
…… (5)
Consider the expression for the transit frequency using square-law characteristics.
…… (6)
Equate equations (5) and (6).
…… (7)
From equation (7), the value of drain current is increased by increasing the value of width with remaining terms as constant.
Thus, the result obtained for transit frequency of a MOS device is with the transit frequency using square-law
characteristics .
Question:
For a saturated NMOS device having W = 50 μm and L = 0.5 μm, calculate all the capacitances. Assume
that the minimum (lateral) dimension of the S/D areas is 1.5 μm and that the device is folded as shown in
Fig. 2.33(b). What is the fT if the drain current is 1 mA?
Figure 2.33
Step 1 Of 14
Figure 1 shows the substrate connection of Figure 2.32 (b) in textbook.
In Figure 1, the gate is represented as ‘G’, the source is represented as ‘S’, and the drain is represented as ‘D’.
By referring to Figure 2.32 (b) in the textbook, consider the expression for the gate-drain capacitance per unit widthas follows:
…… (1)
Here, the overlap capacitance per unit width is and the channel width is .
Write the expression for the overlap capacitance per unit width.
…… (2)
Here, is the gate oxide capacitance per unit area and is the source/drain side diffusion.
…… (3)
Step 2 Of 14
…… (4)
Here, is the permittivity of the oxide, which is and is the gate oxide thickness.
…… (5)
Step 3 Of 14
Substitute for , for , and for Win equation (3).
…… (6)
Consider the scale factor for femto (f).
Step 4 Of 14
By referring to Figure 2.32 (b) in the textbook, consider the expression for the gate-source capacitance per unit widthas follows:
Step 5 Of 14
Substitute for in equation.
Substitute for , for , for , and for Win equation.

…… (7)
The modified Figure of 2.32 (b) in textbook is redrawn as shown in Figure 2.
Consider the general expression for the drain current .
…… (8)
Here,
is the drain current, is the mobility of electrons, is the gate-source voltage, is the threshold voltage, is the gate oxide
capacitance per unit area.
Refer to Table 2.1 in the textbook for the terms and .
Substitute for , for , for , 0.7 V for , for , and for in

equation (8).
Substitute the unit for in equation.

Consider . Therefore, .
Step 6 Of 14
By referring to Figure 2.32 (b) in the textbook, consider the expression for the drain junction capacitance as follows:
…… (9)
Step 7 Of 14
Here,
The source-drain bottom-plate junction capacitance per unit area is , the source-drain sidewall junction capacitance per unit length is , and
E is the lateral dimension of the source-drain areas.
Write the expression for the source-drain bottom-plate junction capacitance per unit area.
Refer to Table 2.1 in the textbook for the term and .
Substitute 0.9 V for , for , 0.6 for , and for in equation.
Write the expression for the source-drain sidewall junction capacitance per unit length.

Substitute 0.9 V for , for , 0.2 for , and for in equation.
Step 8 Of 14
Substitute for , for , for ,and for E in equation (9).
…… (10)
Step 9 Of 14
Refer to Figure 2.32 (b) in the textbook.
Consider the expression for the source junction capacitance as follows:
…… (11)
Consider and .
Step 10 Of 14
By referring to Figure 2.32 (b) in the textbook, consider the expression for the gate junction capacitance as follows:
…… (12)
Here, is the drain capacitance.
Step 11 Of 14
Write the expression for the depletion region capacitance.
Here, q is the electron charge, is the doping concentration of the substrate, is the dielectric constant of silicon.
Substitute for q, for , for ,0.9 V for , for , and for in

equation.
Substitute for , for , for , and for in equation (12).
…… (13)
Step 12 Of 14
Write the expression for transconductance .
Substitute for , for , and 0.7 V for in equation.
Step 13 Of 14
Write the expression for the transit frequency .

Here, the transconductance is , the gate-drain capacitance per unit width is , and the gate-source capacitance per unit width is .
Substitute for , for , and for in equation.
Substitute the unit for in equation.
Step 14 Of 14
Substitute Hz for in equation.
…… (14)
Consider the scale factor for giga (G).
Thus, the capacitances are , , , , and . The transit frequency is

.
Question:
Consider the structure shown in Fig. 2.55. Determine ID, as a function of VGS and VDS, and prove that the
structure can be viewed as a single transistor having an aspect ratio W/(2L). Assume that λ = γ = 0.
Figure 2.55
Step 1 Of 4
The structure of Figure 2.50 in the textbook is modified as shown in Figure 1.
Step 2 Of 4
Refer to Figure 1;
Case I:
Consider that the NFET device operates in the triode region. Consider the conditions that exist before the device enters into the triode region
are and .
Consider that the NFET device operates in the triode region. Consider the conditions that exist before the device enters into the triode region
are and .
Write the expression for the drain current in the NFET device .
…… (1)
W is the channel width, and is the channel length, and is the node voltage at point X.
Write the expression for the drain current in the NFET device .
…… (2)

In Figure 1, the drain current flow in the circuit remains the same. Therefore, equate equations (1) and (2).
…… (3)
…… (4)
From Figure 1, the drain current in NFET device is equal to . That is,
Substitute for .
…… (5)
Write the expression for the drain current for the device operating in the triode region.
…… (6)
By comparing equation (6) with equations (4) and (5), the aspect ratio is in the triode region when the circuit is viewed as a single-transistor
circuit.
Step 3 Of 4
Case II:
Consider that the NFET device operates in the triode region and must operate in the saturation region.
…… (7)
…… (8)
In Figure 1, the drain current flows in the circuit remains same. Therefore, equate equations (7) and (8).
…… (9)
…… (10)
Since,
Substitute for to find .
…… (11)
Write the expression for the drain current for the device operating in the saturation region.
…… (12)
By comparing equation (12) with equations (10) and (11), the aspect ratio is in the triode region when the circuit is viewed as a single-
transistor circuit.
Step 4 Of 4
From Figure 1, consider that the NFET device must be in the triode region since is always positive. That is,
Therefore, device is in the triode region.
From Figure 1, consider for , the NFET device is in the triode region. That is, . Since from the conditions that
exist in the triode region are and .
Consider that if the device is in the saturation region, then the transistor must also be in the saturation region. Hence, the structure is
observed as a single-transistor circuit with an aspect ratio as .
Thus, the drain current is and the structure is viewed as a single-transistor circuit with aspect ratio
as is .
Question:
For an NMOS device operating in saturation, plot W/L versus VGS − VTH if (a) ID is constant, and (b) gm is
constant.
Step 1 Of 4
(a)
Consider the general expression for the drain current .
…… (1)
Here,
is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width, L is the length, is the gate-source voltage, and
…… (2)
Consider is constant and modify equation (2).
…… (3)
From equation (3),
…… (4)
Consider the difference between the gate-source voltage and the threshold voltage is .
Likewise, substitute the various values of in equation (4) to obtain the respective which are tabulated in Table 1.
Figure 1 shows the plot versus when is constant.
Thus, the Figure 1 shows the plot drawn between and when is constant.
Step 2 Of 4
(b)
…… (5)
…… (6)
Consider is constant and modify equation (6).
…… (7)
From equation (7),
…… (8)
Step 3 Of 4
Consider .
Likewise, substitute the various values of in equation (8) to obtain the respective which are tabulated in Table 2.
Step 4 Of 4
Figure 2 shows the plot versus when is constant.
Thus, the Figure 2 shows the plot drawn between and when is constant.
Question:
Explain why the structures shown in Fig. 2.56 cannot operate as current sources even though the transistors
are in saturation.
Figure 2.56
Step 1 Of 2
Refer to Figure 2.51 (a) in the textbook.
In Figure 2.51 (a), current flows through the source (S) terminal of an MOS device. The other terminals such as gate (G) and drain (D) are
connected to the ground terminal. In this circuit, consider that the transistor is in the saturation region. Here, the current that flows in the circuit is
mainly due to the supply voltage applied to the source terminal. Thus, the circuit cannot operate as a current source.
Step 2 Of 2
In Figure 2.51 (b), current flows in the source (S) terminal of an MOS device but toward the supply voltage. The other terminals such as gate
(G) and drain (D) are connected to drain voltage . For the given structure, the circuit cannot operate as the current source because current
that flows in the circuit is mainly due to supply voltage and drain voltage even when the transistor is in saturation. But only an ideal current source
must provide a constant current, which is independent of its voltage.
Thus, the reason for why the structures shown in Figure 2.51 cannot operate as the current source is explained.
Question:
Considering the body effect as “back-gate effect,” explain intuitively why γ is directly proportional to
and inversely proportional to Cox.
Step 1 Of 3
Write the expression for threshold voltage .
…… (1)
Here, is the difference between the work function of the polysilicon gate and silicon substrate, is the Fermi potential, which is
, is the charge in the depletion region, and is the gate oxide capacitance per unit area.
From Equation (1), the terms and are constant values. Now, if there are any changes in the threshold voltage, it means that it comes
from the term . That is,
…… (2)
…… (3)
Here, is the body effect coefficient, which is , is the threshold voltage, which is , and is the bulk
voltage at source.
From Equation (3),
…… (4)
Step 2 Of 3
Consider the expression from the PN junction theory for the charge in the depletion region .
…… (5)
Here, is the doping concentration of the substrate, is the dielectric constant of silicon, and q is the electron charge.
Equate Equations (2) and (4).
…… (6)
From Equation (5), the charge in the depletion region is directly proportional to . Therefore, substitute for in
Equation (6).
…… (7)
From Equation (7), it is clear that the body effect coefficient is directly proportional to and inversely proportional to the gate oxide
capacitance per unit area .
Step 3 Of 3
Thus, from the PN junction theory, the charge in the depletion region is directly proportional to so that the body effect coefficient is
directly proportional to and inversely proportional to the gate oxide capacitance per unit area.
Question:
A “ring” MOS structure is shown in Fig. 2.57. Explain how the device operates and estimate its equivalent
aspect ratio. Compare the drain junction capacitance of this structure with that of the devices shown in Fig.
2.33.
Figure 2.57
Figure 2.33
Step 1 Of 3
Refer to Figure 2.52 in the textbook.
In Figure 2.52, by neglecting the edges, the Figure must look like the four MOSFETs that are connected in parallel.
Modify the diagram as shown in Figure 1.
Step 2 Of 3
A “ring” MOS structure of the device must operate like a traditional MOSFET. That is, by changing the width (W) of a channel along which a hole
or electron charge carrier flows. The charge carriers move in the channel at source (S) terminal and exit through the drain (D) terminal. The width
(W) of the channel is controlled by the voltage on an electrode called as gate (G) and is placed between source (S) and drain (D).
From Figure 1, the aspect ratio of each MOSFET is , but the overall equivalent aspect ratio for the four MOSFET is .
Thus, the MOS structure of device operation is explained and the equivalent aspect ratio for the given MOS structure is .
Step 3 Of 3
From Figure 1, consider the expression for the drain junction capacitance as follows:
…… (1)
Here,
Width is , the source-drain bottom-plate junction capacitance per unit area is , and the source-drain sidewall junction capacitance per unit
length is .
By referring to Figure 2.32 (a) in the textbook, consider the expression for the drain junction capacitance as follows:
…… (2)
Substitute 4W for W in Equation (2) for the aspect ratio of .

…… (3)
By referring to Figure 2.32 (b) in the textbook, consider the expression for the drain junction capacitance as follows:
…… (4)
Substitute 4W for W in Equation (4) for the aspect ratio of .
…… (5)
By comparing Equation (2) and Equations (4) and (5), the value of source-drain sidewall junction capacitance per unit length in a ring
structure is less than that in folded and traditional structures, but the source-drain bottom-plate junction capacitance per unit area of a “ring”
structure is higher than that of the other two structures (that is, ).
Thus, the drain junction capacitance of Figure 2.52 is with the two structures of Figure 2.32.
Question:
Suppose we have received an NMOS transistor in a package with four unmarked pins. Describe the
minimum number of dc measurement steps using an ohmmeter that is necessary to determine the gate,
source/drain, and bulk terminals of the device.
Step 1 Of 2
Draw the simple diagram of MOSFET connection with an ohmmeter as shown in Figure 1.
Step 2 Of 2
Consider that NMOS transistor consists of four unmarked pins.
The following steps are used to identify the terminals of the MOSFET using an ohmmeter.
• Initially, one probe of the ohmmeter is connected to one terminal and anotherprobeis connected to one of theremaining three terminals of the
MOSFET to find the bulk-source or bulk-drain terminal of the MOSFET. In this case,a total of 12 dc experiments are required.
• In total 12 experiments, 2 terminals lead to alow resistive path (that is, conduction occurs between two paths) and one shows a high resistive
path (that is, no conduction).
• Once two terminals with low resistive pathsare obtained, an experiment is conducted between the cathode of the junction (bulk) and the
remaining two terminals of the MOSFET.
• Connect the negative probe of the ohmmeter to the cathode junction of the MOSFET and connect another probe to one of the remaining two
terminals.
• If the connected path has high resistance, then the obtained terminal is ground.
• If the connected path has low resistance, then the obtained terminal is either a source or drain.
• With the help of a bulk terminal, in the worst case, 8 experiments are required to identify the gate, source, and drain of the NMOSFET.
Thus, the minimum number of dc measurement steps required to identify the four terminals of NMOS isexplained.
Question:
Repeat Prob. 2.21 if the type of the device (NFET or PFET) is not known.
Step 1 Of 4
Draw the simple diagram of MOSFET connection with an ohmmeter as shown in Figure 1.
Step 2 Of 4
Consider that an unknown transistor is available.
The following steps are used to identify the terminals of the MOSFET using an ohmmeter.
• Initially, one probe of the ohmmeter is connected to one terminal and anotherprobeis connected to one of the remaining three terminals of the
MOSFET to find the bulk-source or bulk-drain terminal of the MOSFET. In this case,a total of 12 dc experiments are required.
• In total 12 experiments, 2 terminals lead to a low resistive path (that is, conduction occurs between two paths) and one shows a high resistive
path (that is, no conduction).
• Once two terminals with low resistive pathsare obtained, an experiment is conducted between the cathode of the junction (bulk) and the
remaining two terminals of the MOSFET.
Step 3 Of 4
After the 3rd step, consider the two cases.
Case 1: Connect the negative probe of the ohmmeter to the cathode junction of the MOSFETand connect another probe to one of the remaining
two terminals.
• If the connected path has high resistance, then the obtained terminal is groundterminal of NFET.
• If the connected path has low resistance, then the obtained terminal is either a source or drain of NFET.
• With the help of a bulk terminal, in the worst case, 8 experiments are required to identify the gate, source, and drain of the MOSFET.
Step 4 Of 4
Case 2: Connect the positive probe of the ohmmeter to the cathode junction of the MOSFETand connect another probe to one of the remaining
two terminals.
• If the connected path has high resistance, then the obtained terminal is ground terminal of PFET.
• If the connected path has low resistance, then the obtained terminal is either a source or drain of PFET.
• With the help of a bulk terminal, in the worst case, 8 experiments are required to identify the gate, source, and drain of the MOSFET.
Thus, the minimum number of dc measurement steps required to identify the NFET or PFET is explained.
Question:
For an NMOS transistor, the threshold voltage is known, but μnCox and W/L are not. Assume that λ = γ = 0.
If we cannot measure Cox independently, is it possible to devise a sequence of dc measurement tests to
determine μnCox and W/L? What if we have two transistors and we know that one has twice the aspect ratio
of the other?
Figure 2.57
Step 1 Of 2
Consider the condition that the NMOS transistor operates in the saturation region.
Write the expression for the drain current in the saturation region .
…… (1)
W and are the channel width and length, respectively.
When the values of , , , and are known, then the drain current is determined. If threshold voltage is alone known but the
values of and are not defined, then it is not possible to determine the values of and , where the constant is a dependent
value. Since the DC model of the MOSFET drain current equation has the product of and , it is not possible to determine and
with only known value of .
Thus, , the terms and cannot be determined if only the threshold voltage is known.
Step 2 Of 2
Consider two transistors where one transistor is with an aspect ratio and the other transistor is with an aspect ratio . When is the only
known parameter and the other parameters are unknown and is a dependent value, it is not possible to obtain the different independent
equations for each transistor. Both the equations exist with the product of and so that it is not possible to determine and . If
the difference between the aspect ratio of two transistors is a known value, from that relation, it is possible to obtain and .
Thus, , even if the aspect ratios of two transistors are known as and , it is not possible to obtain the values and .
Question:
Sketch IX versus VX for each of the composite structures shown in Fig. 2.58 with VG as a parameter. Also,
sketch the equivalent transconductance. Assume that λ = γ = 0.
Figure 2.58
Step 1 Of 17
(a)
Redraw the circuit as shown in Figure 1.
Refer to Figure 1;
Case I:
When , the device is in off condition. Therefore, the drain current .
For :
In this range, consider the device is in off condition. Hence, the current is equal to zero. Therefore, the transconductance of the device is
. Since, .
For :
Consider the expression for the current .
Here, is the mobility of holes, is the gate voltage, is the threshold voltage for PMOS device, is the supply voltage, is the gate
oxide capacitance per unit area, W is the channel width, and is the channel length.
Step 2 Of 17
Figure 2 shows the characteristic curve drawn between the voltage and the current .
In Figure 2, the characteristic curve shows that the current increases with increases in the voltage . This variation arises when the voltage
is greater than the voltage with minimum increase in current .
Step 3 Of 17
Figure 3 shows the curve drawn between the transconductance and the voltage .
In Figure 3, the transconductance decrease with increase in voltage when it is greater than . Since, transconductance is
inversely proportional to .
Step 4 Of 17
Case II:
When , the device is in off condition.
For :
In this condition, the device is in the triode region and the device is in off condition. Therefore, the expression for the current is
determined as follows:
Here, is the mobility of electrons and is the threshold voltage for NMOS device.
Step 5 Of 17
In the triode region, consider the expression for the transconductance of NMOS device .
Step 6 Of 17
For :
In this condition, the device is in the saturation region and the device is in off condition. Therefore, the expression for the current is
determined as follows:
In saturation region, consider the expression for the transconductance of NMOS device .
Step 7 Of 17
For :
During this condition, the devices and are in saturation region.
In saturation region, consider the expression for the transconductance of NMOS device and PMOS device .
Step 8 Of 17
Figure 4 shows the characteristic curve drawn between the voltage and the current .
In Figure 4, the voltage increases with increase in current linearly upto and remains constant until . Further increase in
voltage results that increase in current .
Step 9 Of 17
Figure 5 shows the curve drawn between the transconductance and the voltage .
Step 10 Of 17
In Figure 5, the voltage increases with increase in transconductance linearly upto and remains constant until . Further increase in
voltage results that decrease in transconductance .
Thus, the characteristics curve is drawn between the current and the voltage . The equivalent transconductance curve is also drawn
between the transconducatance and .
Step 11 Of 17
(b)
The circuit is redrawn as shown in Figure 6.
Refer to Figure 6;
Case I:
When , the device is in off condition. Hence, the current is equal to zero. Therefore, the transconductance of the device is
. since, .
Step 12 Of 17
Case II:
When , the device is in off condition.
For :
In this condition, consider the device is in off condition and the current is equal to zero. Therefore, the transconductance of the device is
. since, .
Consider the device is turned on and the device still in triode region. Therefore, the expression for the current is determined as
follows:
Step 13 Of 17
Write the expression for voltage when the device goes into saturation.
Here, consider .
Step 14 Of 17
Now, consider the device goes into triode region. Then, the current is determined as follows:
For :
Under this condition, consider the expression for the current .
Therefore, consider the expression for the transconductance of PMOS device .
Step 15 Of 17
For :
Under this condition, consider the expression for the current .
Therefore, consider the expression for the transconductance of NMOS device .
Step 16 Of 17
Figure 7 shows the sketch drawn between the voltage and the current .
In Figure 7, the voltage increase with increase in current linearly after . When it reaches to , then the
current remains constant with increase in voltage .
Step 17 Of 17
Figure 8 shows the sketch drawn between the transconductance and the voltage .
In Figure 8, the transconductance decreases after it reaches with increase in voltage . When it reaches to
, then sudden raise in transconductance with positive value and varies linearly as shown in Figure 8.
Thus, the characteristics curve is drawn between the current and the voltage . The equivalent transconductance curve is also drawn
between the transconducatance and .
Question:
An NMOS current source with ID = 0.5 mA must operate with drain-source voltages as low as 0.4 V. If the
minimum required output impedance is 20 kΩ, determine the width and length of the device. Calculate the
gate-source, gate-drain, and drain-substrate capacitance if the device is folded as in Fig. 2.33 and E = 3 μm.
Figure 2.33
Step 1 Of 8
For NFET:
Step 2 Of 8
Consider the channel length L is and the threshold voltage .
Write the expression for the output resistance .
…… (1)
Here, is the channel-length modulation coefficient and is drain current.
Refer to Table 2.1 in the textbook for the term for NMOS model.
…… (2)
Consider the expression for the drain-source voltage.
…… (3)
Here, is the gate-source voltage and is the threshold voltage.
Substitute 0.7 V for and 0.4 V for in equation (3).
Consider . Therefore, .
Step 3 Of 8
Write the general expression for the drain current in saturation region.
…… (4)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, and is the effective channel
length, which is .
…… (5)
…… (6)

…… (7)
Step 4 Of 8
Refer to Table 2.1 in the textbook for the terms , , and for NMOS model.
Substitute for , for , for , 0.7 V for , for , and for in

equation (5).
Substitute the unit for 1 .
Thus, the channel width and length of the device are and respectively.
Step 5 Of 8
Consider the expression for the gate-source capacitance per unit width.
…… (8)
Here, L is the length and is the overlap capacitance per unit width.
Consider the overlap capacitance per unit width is .
Substitute for , for , for , and for in equation.
…… (9)
Consider the scale factor for femto (f).
Step 6 Of 8
Consider the expression for the gate-drain capacitance per unit width.
Step 7 Of 8
Consider the expression for the drain-substrate capacitance per unit width.
…… (10)
Here, is the source-drain bottom-plate junction capacitance per unit area and is the source-drain sidewall junction capacitance per unit
length.
Substitute 0.9 V for , for , 0.6 for , and for .
Step 8 Of 8
Substitute for , for , for , and for E in equation (10).
…… (11)
Thus, the gate-source, gate-drain, and drain-substrate capacitances of the device are , , and
respectively.
Question:
Consider the circuit shown in Fig. 2.59, where the initial voltage at node X is equal to VDD. Assuming that λ
= γ = 0 and neglecting other capacitances, plot VX and VY versus time if (a) Vin is a positive step with
amplitude V0 > VTH, and (b) Vin is a negative step with amplitude V0 = VTH.
Figure 2.59
Step 1 Of 6
(a)
For :
The modified circuit of Figure 2.54 is shown in Figure 1.
Refer to Figure 1;
Case I:
Consider the conditions that exist at node X when (before applying the pulse).
Consider the conditions that exist at node Y when (before applying the pulse).
Here, is the mobility of electrons, is the drain-drain voltage, is the threshold voltage, is the gate oxide capacitance per unit area,
is the tail current, W is the channel width, and is the channel length.
Case II:
Consider the conditions that exist at node X when (after applying the pulse).
Consider the conditions that exist at node Y when (after applying the pulse).
Substitute for .
Here, is the starting amplitude of input voltage.

Case III:
Consider the conditions that exist at node X for .
Consider the conditions that exist at node Y for .
Step 2 Of 6
When , the initial voltage is . Refer to Figure 1; if , then the NMOS transistor operates in the triode region.
Consider the expression for the drain current in triode region when the conditions exist at .
Consider if , then the drain current as follows:
…… (1)

Consider the expression for the gate-source voltage.
Step 3 Of 6
Consider the expression for the drain-source voltage.
…… (2)
Step 4 Of 6
Refer to Figure 1; apply Kirchhoff’s current law at node Y to determine the current through capacitor . That is,
…… (3)
Write the expression for the current through capacitor .

…… (4)
Consider .
Modify the equation.
…… (5)
Here, is constant, which is .

Apply the integration on both sides of equation (5) as follows:
…… (6)
Here, C is the constant that is considered as .
Substitute for C in equation (6).
Step 5 Of 6
…… (7)
Case IV:
Consider the conditions that exist for .
Substitute for t in equation (7).
Consider the conditions that exist at node X when .
Consider the conditions that exist at node Y when .
Use Cases I, II, and IV; for , the voltage at node X is . For , the voltage at node X is . For , the voltage at node
X drops to the voltage level of and enters into saturation.
Thus, Figure 2 is sketched between and t. In Figure 2, the voltage waveform starts rising from to reach up to , decreasing
up to , and remains constant at .
Use Cases I, II, and IV; for , the voltage at node Y is . For , the voltage at node Y is . For , the voltage at
node Y drops to the voltage level of .
Thus, Figure 3 is sketched between and t. In Figure 3, the voltage waveform starts rising from to reach up to ,
decreasing up to , and remains constant at .
Thus, the sketch is drawn for voltages and versus time , which is shown in Figure 2 and Figure 3.
Step 6 Of 6
(b)
For :
Case I:
Consider the conditions that exist at node X when (before applying the pulse).
Consider the conditions that exist at node Y when (before applying the pulse).
Case II:
Consider the conditions that exist at node X when (after applying the pulse).
Consider the conditions that exist at node Y when (after applying the pulse).
Substitute for .
Refer to Figure 1 in Part (a); after applying the negative step input pulse in , the NMOS transistor remains in the saturation region and the
current flows in the circuit do not change. That is, .
Use Cases I and II; for , the voltage at node X is . For , the voltage at node X is . Thus, Figure 4 shows the waveform
drawn between and t. In Figure 4, the voltage starts decreasing from till the threshold voltage and remains constant at
with voltage .
Refer to Figure 4, the saturation region exists at . That is,
Use Cases I and II; That is, for , the voltage at node Y is . For , the voltage at node Y decreases and saturates at the voltage
of .
Thus, Figure 5 shows the plot between and t. In Figure 5, the voltage starts decreasing from upto and remains
constant at .
Refer to Figure 5, the saturation region exists at . That is,
Thus, the sketch is drawn for voltages and versus time , which is shown in Figure 4 and Figure 5.
Question:
An NMOS device operating in the subthreshold region has a ζ of 1.5. What variation in VGS results in a
tenfold change in ID? If ID = 10 μA, what is gm?
Step 1 Of 3
…… (1)
Here,
is the saturation current, is the gate-source voltage, and is the volt equivalent of temperature, which is .
Consider the variation in gate-source voltage as , then the drain current is calculated using equation (1).
…… (2)
Consider the variation in gate-source voltage as , then the drain current is calculated by using equation (1).
…… (3)
Dividing equation (3) by (2).
…… (4)
Since, the ratio of drain currents is ten-fold change (that is, ).
…… (5)
Take ln on both sides of the equation (5).
…… (6)
…… (7)
Substitute for q, for , for k, and 300 K for T in equation (7).
Substitute the unit V for .
Thus, the variation in gate-source voltage is .
Step 2 Of 3
Consider the general expression for the transconductance.
…… (9)
…… (10)
Step 3 Of 3
Substitute for , for q, for , for k, and 300 K for T in equation (10).
Substitute for J.

Question:
Consider an NMOS device with VG = 1.5 V and VS = 0. Explain what happens if we continually decrease
VD below zero or increase Vsub above zero.
Step 1 Of 2
The NMOS device is ON when the gate-source voltage is greater than threshold voltage of the transistor. That is, . Therefore, the
transistor must operate in the triode region or linear region.
The schematic diagram of the NMOS device with and is shown in Figure 1.
Step 2 Of 2
For :
Refer to Figure 1; if the drain voltage , then the source, S and drain, D terminals interchange their roles, and therefore, the NMOS device
enters the triode region.
…… (1)
Consider the expression for the source-bulk potential difference.
…… (2)
Substitute 0 for in equation.
…… (3)
Write the expression for the change in threshold voltage.
…… (4)
For :
Consider that if the bulk voltage increases, then the threshold voltage decreases (That is, the value obtained for the change in threshold
voltage is negative using equation (4). Hence, therefore, the drain current in the NMOS transistor increases.
Thus, the increase of the substrate voltage greater than zero volt and the drain voltage lesser than zero volt is explained for the NMOS transistor
with and .
Question:
Consider the arrangement shown in Fig. 2.60. Explain what happens to the pinch-off point as VG increases.
Figure 2.60
Step 1 Of 0
There is no solution to this problem yet.
Question:
From Fig. 2.20, plot ID vs. VGS − VTH if W/L is constant, VGS − VTH vs. ID if W/L is constant, and W/L vs.
VGS − VTH if ID is constant.
Figure 2.20 Approximate MOS transconductance as a function of overdrive and drain current.
Step 1 Of 0
Question:
Plotted in Fig. 2.61 are the charactersitics of a square-law NMOS device with W/Ldrawn = 5 μm/40 nm an
tox = 18Å. Here, VGS is incremented in equal steps. Estimate μn, VTH, λ, and the VGS steps.
Figure 2.61
Step 1 Of 0
Question:
For the circuit of Fig. 3.13, calculate the small-signal voltage gain if (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, and
ID1 = ID2 = 0.5 mA. What is the gain if M2 is implemented as a diode-connected PMOS device(Fig. 3.16)?
Figure 3.16 CS stage with diodeconnected PMOS device.
Step 1 Of 9
For diode-connected NMOS device:
Consider the general expression to calculate transconductance.
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width, L is the length and is the drain current.
Substitute for .
Refer to Table 2.1 in the textbook for the term in NMOS model.
Step 2 Of 9
Consider the expression to calculate the output voltage.
Here, is the drain-drain voltage and is the gate-source voltage.
Similarly, the expression to calculate the drain-source voltage is,
Consider the expression to calculate the threshold voltage.
Here, is the threshold voltage with zero, is the body effect coefficient, is the source-bulk voltage and is a surface potential.
Step 3 Of 9
Consider the expression to calculate the drain current.
Here, is the threshold voltage, is the channel-length modulation coefficient and is the drain-source voltage.
Substitute for , for , for .
Here, the output voltage is . Therefore,
Refer to Table 2.1 in the textbook for the terms , , , , and in NMOS model.
Substitute for , for , for , for , for , for , for ,

for and for .

…… (2)
Solve equation (2) to find by trial and error method as shown.
Similarly, by substituting various values for , the values are calculated and tabulated in Table 1.
From Table 1, for the voltage is approximately equal to 1 and equation (2) is satisfied.
Therefore, the source-bulk voltage is,
Step 4 Of 9
Use equation (1) to find .
Substitute for , for , for and for .

Modify equation (1) to find as:
Step 5 Of 9
Consider the expression to calculate the output resistance .
Here, is the channel-length modulation coefficient, is the output resistance of the device and is the output resistance of the device
.

Consider the expression to calculate the back-gate transconductance.
Substitute for , for , for and for in the equation.
Consider the expression to calculate the output impedance.
Substitute for , for , for and .

Step 6 Of 9
Consider the expression to calculate the small-signal voltage gain.
Step 7 Of 9
For diode-connected PMOS device:
Modify the equation (1) to find as:
Refer to Table 2.1 in the textbook for term in PMOS model.

Modify the equation (1) to find as:
Substitute for .
Refer to Table 2.1 in the textbook for the term in PMOS model.
Step 8 Of 9
Substitute for , for and .
Step 9 Of 9

Thu, the value of the small-signal voltage gain for diode-connected NMOS device is and for diode-connected PMOS device is
.
Question:
In the circuit of Fig. 3.18, assume that (W/L)1 = 50/0.5, (W/L)2 = 50/2, and ID1 = ID2 = 0.5 mA when both
devices are in saturation. Recall that λ ∝ 1/L.
(a) Calculate the small-signal voltage gain.
(b) Calculate the maximum output voltage swing while both devices are saturated
.
Figure 3.18 CS stage with current-source load.
Step 1 Of 9
(a)
Consider the expression to calculate transconductance.
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width, L is the length and is the drain current.
Substitute for .
Step 2 Of 9
Consider the expression for the output resistance .
…… (2)
Use equation (2) to find for NMOS device .
Use equation (2) to find for PMOS device .
Step 3 Of 9
Refer to Table 2.1 in the textbook for the terms in NMOS model.
Substitute for , for , for and for in the equation (1).

Step 4 Of 9
Substitute for , for and for .
Thus, the value of the small-signal voltage gain for the circuit is .
Step 5 Of 9
(b)
For device in the edge of the triode region:

Here, is the drain-source voltage, is the gate-source voltage, and is the threshold voltage.
Consider the expression to calculate the drain current if is in the edge of the triode region.
Substitute for .
Substitute for , for , for , for and for .
…… (3)
Step 6 Of 9
From Table 1, for , equation (3) is satisfied.
Therefore, the drain-source voltage is,
Step 7 Of 9
For device in the edge of the triode region:

Consider the expression to calculate the drain current if is in the edge of the triode region.
Substitute for .
Refer to Table 2.1 in the textbook for the term and in PMOS model.
…… (4)
Step 8 Of 9

From Table 2, at the equation (4) is approximately equal to zero and satisfied.
Therefore, the source-drain voltage is,
Step 9 Of 9
Consider the expression to calculate the maximum output voltage when both devices are saturated.
Here, is the drain-drain voltage.
Thus, the value of the maximum output voltage swing when both devices are saturated is .
Question:
In the circuit of Fig. 3.4(a), assume that (W/L)1 = 50/0.5, RD = 2 kΩ, and λ = 0.
(a) What is the small-signal gain if M1 is in saturation and ID = 1 mA?
(b) What input voltage places M1 at the edge of the triode region? What is the small-signal gain
under this condition?
(c) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain
Figure 3.4 (a) Common-source stage, (b) input-output characteristic, (c) equivalent circuit in the deep triode
region, and (d) small-signal model for the saturation region.
Step 1 Of 20
(a)
Consider the expression to calculate transconductance of in saturation and .
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the channel length and is the
drain current.
Substitute for .
Refer to Table 2.1 in the textbook for the parameter value of in NMOS model.

Step 2 Of 20
Refer to Table 2.1 in the textbook for the parameter value of in NMOS model .
Step 3 Of 20
Step 4 Of 20
Here, is the drain resistance.
Step 5 Of 20
Step 6 Of 20
Thus, the value of small gain voltage is .
Step 7 Of 20
(b)
For device at the edge of the triode region:

…… (2)
Here, is the gate-source voltage and is the threshold voltage.
Refer to Table 2.1 in the textbook for the value of threshold voltage in NMOS model.
Substitute for in the equation (2).
Consider the expression to calculate the drain current using the Figure 3.3 (a) in the textbook.
Here, is the drain supply voltage.

Substitute for .
…… (3)
Step 8 Of 20
…… (4)
Step 9 Of 20
Solve equation (4) to find by trial and error method as follows:
From Table 1, for the voltage the function value is equal to 1 and the equation (4) is satisfied.
Therefore, the gate-source voltage is,
Step 10 Of 20
Consider the expression to calculate transconductance at the edge of the triode region.

Step 11 Of 20
Step 12 Of 20
Consider the expression to calculate the small-signal voltage gain at the edge of the triode region.
Thus, the value of the input voltage of device at the edge of the triode region is and the small-signal gain is .
Step 13 Of 20
(c)
Consider the expression to calculate the output voltage using the Figure 3.3 (a) in the textbook.

The device drives into the triode region by . Therefore, the drain-source voltage is expressed as,
Substitute for .
Step 14 Of 20
Step 15 Of 20
Substitute for , for , for , for , for and for .

…… (5)
Step 16 Of 20
From Table 2, for the voltage the function value is equal to 1 and the equation (5) is satisfied.
Therefore, the gate-source voltage is,
Step 17 Of 20
Consider the expression to calculate transconductance at the point where is into the triode region.

Step 18 Of 20
Consider the expression to calculate the output resistance at the point where is into the triode region.
Step 19 Of 20
Consider the expression to calculate the output impedance at the point where is into the triode region.

Step 20 Of 20
Consider the expression to calculate the small-signal voltage gain at the point where is into the triode region.
Thus, the value of the input voltage of device into the triode region is and the small-signal gain is .
Question:
Suppose the common-source stage of Fig. 3.4(a) is to provide an output swing from 1 V to 2.5 V. Assume
that (W/L)1 = 50/0.5, RD = 2 kΩ, and λ = 0.
(a) Calculate the input voltages that yield Vout = 1 V and Vout = 2.5 V.
(b) Calculate the drain current and the transconductance of M1 for both cases.
(c) How much does the small-signal gain, gm RD, vary as the output goes from 1 V to 2.5 V?
(Variation of small-signal gain can be viewed as nonlinearity.)
Figure 3.4 (a) Common-source stage, (b) input-output characteristic, (c) equivalent circuit in the deep triode
region, and (d) small-signal model for the saturation region.
Step 1 Of 14
(a)
For :
Consider the expression to calculate the drain current using the Figure 3.3 (a) in the textbook.
…… (1)
Here, is the drain supply voltage, is the output voltage and is the drain resistance.
Substitute for , for and for in equation (1).
Step 2 Of 14
Consider the expression to calculate the input voltage using the Figure 3.3 (a) in the textbook.
…… (2)
Here, is the threshold voltage, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the
channel length and is the drain current.
Substitute for .
Step 3 Of 14
Refer to Table 2.1 in the textbook for the parameter value of and threshold voltage in NMOS model.
Substitute for , for , for , for and for in the equation (2).
Step 4 Of 14
For :

Step 5 Of 14
Thus, the value of the input voltage for is and for is .
Step 6 Of 14
(b)
From part (a), the drain current for is,
From part (a), the drain current for is,
Step 7 Of 14
For :
Consider the expression to calculate transconductance of NMOS device in saturation and .
…… (3)

Step 8 Of 14
For :
Thus, for and , the value of the drain current is and respectively and the value of the
transconductance is and respectively.
Step 9 Of 14
(c)
For :
…… (4)
Step 10 Of 14
…… (5)
Step 11 Of 14
…… (6)
For :
Step 12 Of 14
For :

Step 13 Of 14
Step 14 Of 14
Thus, the value of small gain voltage for and are and respectively.
Question:
Calculate the intrinsic gain of an NMOS device and a PMOS device operating in saturation with W/L =
50/0.5 and |ID| = 0.5 mA. Repeat these calculations if W/L = 100/1.
Step 1 Of 8
Case (i): For NMOS device,

…… (1)
drain current.
Substitute for .
Refer to Table 2.1 in the textbook for the term and in NMOS model.
Step 2 Of 8

Step 3 Of 8
…… (2)
Substitute for and for in the equation (2).
Consider the expression to calculate the intrinsic gain.
…… (3)
Step 4 Of 8
For PMOS device:
…… (4)
Step 5 Of 8
Step 6 Of 8
Case (ii): For NMOS device,

…… (5)
Step 7 Of 8
For PMOS device:

Step 8 Of 8
Thus, the value of the intrinsic gain of an NMOS device and a PMOS device for is and and for is
and respectively.
Question:
Assuming a constant L, plot the intrinsic gain of a satuated device versus the gate-source voltage if (a) the
drain current is constant, (b) W is constant.
Step 1 Of 9
(a)
Consider the expression to calculate the drain current for the saturated NMOS device.
…… (1)
Here, is the threshold voltage, is the gate-source voltage, is the drain-source voltage, is the mobility of electrons, is the gate
oxide capacitance per unit area, W is the channel width, L is the channel length and is the channel-length modulation coefficient.
Consider the expression to calculate the transconductance for the saturated NMOS device.
…… (2)
Step 2 Of 9
Step 3 Of 9
Consider the expression to calculate the output resistance for the saturated device.
Consider the expression for the intrinsic gain , by substituting for and for .
Substitute for .
…… (3)
The equation (3) shows the intrinsic gain expression.
Step 4 Of 9
Substitute for .
Step 5 Of 9
Step 6 Of 9
Refer to Table 2.1 in the textbook for the parameter value of , and threshold voltage in NMOS model.

…… (4)
Step 7 Of 9
Refer the intrinsic gain expression in equation (4), the drain current which is directly proportional to the intrinsic gain is constant. Here, the
change occurs in the value of which is indirectly proportional to intrinsic gain.

The value of the gate source voltage in equation (4) starts from the value greater than the threshold voltage.
Since, and are indirectly proportional, the different conditions provides the following relationship for different width
and length ratios.
The plot for versus gate source voltage for constant drain current is drawn as Figure 1.
Thus, the plot for the intrinsic gain of a saturated device versus the gate source voltage for constant drain current is drawn.
Step 8 Of 9
(b)
Refer the intrinsic gain expression in equation (4), the ratio of channel width and length which is indirectly proportional to intrinsic gain is
constant. Here, the change occurs in the value of drain current which is directly proportional to intrinsic gain.
Since, and are directly proportional, the different conditions provides the following relationship for different drain
currents.
Step 9 Of 9
The plot for and the gate source voltage for constant channel width and length ratio is drawn as Figure 2.
Thus, the plot for the intrinsic gain of a saturated device versus the gate source voltage for constant width and length is drawn.
Question:
Assuming a constant L, plot the intrinsic gain of a saturated device versus W/L if (a) the gate-source voltage
is constant, (b) the drain current is constant.
Step 1 Of 9
(a)
…… (1)
Here, is the threshold voltage, is the gate-source voltage, is the drain-source voltage, is the mobility of electrons, is the gate
oxide capacitance per unit area, W is the channel width, L is the channel length and is the channel-length modulation coefficient.
…… (2)
Step 2 Of 9
Step 3 Of 9
Consider the expression to calculate the output resistance for the saturated device.
Consider the expression for the intrinsic gain , by substituting for and for .
Substitute for .
…… (3)
The equation (3) shows the intrinsic gain expression.
Step 4 Of 9
Substitute for .
Step 5 Of 9
Step 6 Of 9
Refer to Table 2.1 in the textbook for the parameter value of , and threshold voltage in NMOS model.

…… (4)
Step 7 Of 9
Refer the intrinsic gain expression in equation (4), the gate source voltage which is indirectly proportional to the intrinsic gain is constant. Here,
the change occurs in the value of drain current which is directly proportional to intrinsic gain.
The value of the channel width and length ratio in equation (4) starts from the value greater than the threshold voltage.
Since, and are directly proportional, the different conditions provides the following relationship for different drain
currents.
The plot for versus channel width and length ratio for constant gate source voltage is drawn as Figure 1.
Thus, the plot for the intrinsic gain of a saturated device versus the channel width and length ratio for constant gate source voltage is drawn.
Step 8 Of 9
(b)
Refer the intrinsic gain expression in equation (4), the drain current which is directly proportional to intrinsic gain is constant. Here, change
occurs in the value of the gate source voltage which is indirectly proportional to intrinsic gain.
Since, and are indirectly proportional, the different conditions provides the following relationship for different gate
source voltages.
Step 9 Of 9
The plot for versus channel width and length ratio for constant drain current is drawn as Figure 2.
Thus, the plot for the intrinsic gain of a saturated device versus the channel width and length ratio for constant drain current is drawn.
Question:
An NMOS transistor with W/L = 50/0.5 is biased with VG = +1.2 V and VS = 0. The drain voltage is varied
from 0 to 3 V.
(a) Assuming the bulk voltage is zero, plot the intrinsic gain versus VDS.
(b) Repeat part (a) for a bulk voltage of −1 V
.
Step 1 Of 17
(a)
In saturation region:
Consider the expression to calculate the drain source voltage for the saturated NMOS device.
Here, is the gate source voltage and is the threshold voltage.
Refer to Table 2.1 in the textbook for the value of in NMOS model.
Step 2 Of 17
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width and L is the channel length.
…… (1)
Here, is the channel length modulation coefficient and is the drain source voltage.
Step 3 Of 17
Consider the expression to calculate the threshold voltage for the NMOS device with body effect.
…… (2)
Here, is the body effect coefficient and is the surface potential.

Step 4 Of 17
Consider the expression to calculate the output resistance for the saturated NMOS device.
Here, is the drain current.
Substitute for .
Step 5 Of 17
Substitute for and for to find the intrinsic gain .
…… (3)
Step 6 Of 17
Substitute for , for , for and for in equation (3).

Step 7 Of 17
In triode region:
The intrinsic gain of the NMOS device in the triode region should include the channel length modulation, because neglecting the coefficient leads to
a discontinuity at the transition point between the saturation and triode.
Consider the expression to calculate the transconductance for the NMOS device in the triode region.
Here, is the channel length modulation coefficient.

Consider the expression to calculate the output resistance for the NMOS device in the triode region.
Step 8 Of 17
Substitute for and for to find the

intrinsic gain .
…… (4)
Step 9 Of 17

…… (5)
Step 10 Of 17
From the saturation of the NMOS device, the value of the drain source voltage .
Step 11 Of 17
Therefore, from the calculations, the plot for the intrinsic gain versus the drain source voltage is drawn as Figure 1.
Thus, the plot for the intrinsic gain versus the drain source voltage is drawn.
Step 12 Of 17
(b)
Refer to Table 2.1 in the textbook for the values of in NMOS model.
Substitute for , for , for and for
Step 13 Of 17
In saturation region:
Consider the equation (3) to calculate the intrinsic gain for the saturated NMOS device.
…… (6)
Step 14 Of 17
Consider the expression to calculate the drain source voltage for the saturated NMOS device.

Step 15 Of 17
In triode region:
Consider the equation (4) to calculate the intrinsic gain for the NMOS device in the triode region.
Step 16 Of 17
…… (7)
Step 17 Of 17
From the saturation of the NMOS device, the value of the drain source voltage .
Therefore, from the calculations, the plot for the intrinsic gain versus the drain source voltage is drawn as Figure 2.
Thus, the plot for the intrinsic gain versus the drain source voltage is drawn.
Question:
For an NMOS device operating in saturation, plot gm, rO, and gmrO as the bulk voltage goes from 0 to −∞
while other terminal voltages remain constant.
Step 1 Of 5
The device is NMOS and is operating in a saturation mode.
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, is the
gate source voltage and is the threshold voltage with zero for NMOS device.
Step 2 Of 5
…… (1)
Here, is the channel length modulation coefficient and is the drain source voltage.
The voltage , therefore is neglected.
Substitute for .
Step 3 Of 5
From the expression of , the plot for the transconductance is plotted till the voltage is equals to voltage . If the voltages are equal that
is , then .
Using the expression, the plot for the transconductance and the bulk voltage that goes from to is drawn as Figure 1.
Step 4 Of 5
Consider the expression to calculate the output resistance for the saturated NMOS device.
Substitute for .
From the expression of , the plot for the output resistance is plotted till the voltage is equals to voltage . If the voltages are equal that is
, then .
Using the expression, the plot for the output resistance and the bulk voltage that goes from to is drawn as Figure 2.
Step 5 Of 5
Substitute for and for to find .
Using the expression, the plot and that goes from to is drawn as Figure 3.
Thus, the plot for the transconductance , output resistance and as the bulk voltage goes from to are plotted.
Question:
Consider the circuit of Fig. 3.13 with (W/L)1 = 50/0.5 and (W/L)2 = 10/0.5. Assume that λ = γ = 0.
(a) At what input voltage is M1 at the edge of the triode region? What is the small-signal gain
(b) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain
Figure 3.13 CS stage with diode-connected load.
Step 1 Of 12
(a)
Consider the body effect coefficient is .

Here, is the input voltage and is the threshold voltage.
Step 2 Of 12
Consider the expression to calculate the drain current for the device .
Substitute for .
…… (1)
Step 3 Of 12
Consider the relation of the drain current of devices and for a negligible channel-length modulation.
…… (2)
Refer to Figure 3.9 in the textbook, since the circuit includes two NMOS devices, the threshold voltage for the devices are equal. That is,
.
Step 4 Of 12
Step 5 Of 12
…… (3)
Step 6 Of 12
Step 7 Of 12
Consider the expression to calculate the small-signal voltage gain for the circuit with negligible body effect coefficient.
Step 8 Of 12
(b)
For device into the triode region by :

Step 9 Of 12
The device drives into the triode region by . Therefore, the output voltage is expressed as,
Step 10 Of 12
Consider the expression to calculate the drain current for the device at the point where is into the triode region.
Consider the relation of the drain current of device and for a negligible channel-length modulation.

Step 11 Of 12
Substitute for .
Step 12 Of 12
Substitute for .
Question:
Repeat Problem 3.10 if body effect is not neglected.
Consider the circuit of Fig. 3.13 with (W/L)1 = 50/0.5 and (W/L)2 = 10/0.5. Assume that λ = γ = 0.
(a) At what input voltage is M1 at the edge of the triode region? What is the small-signal gain
(b) What input voltage drives M1 into the triode region by 50 mV? What is the small-signal gain
Figure 3.13 CS stage with diode-connected load.
Step 1 Of 13
(a)
Refer to Figure 3.9 in the textbook. The two transistors in the circuit are NMOS model.
Consider the body effect in the transistors and the body effect coefficient is not neglected.
Consider the modulation coefficient is zero.


Consider the expression to calculate the threshold voltage for the device with body effect.
Step 2 Of 13
Substitute for .
Substitute for .
Step 3 Of 13
Consider the relation of the drain current of devices and with a channel-length modulation.
…… (1)
Refer to Figure 3.9 in the textbook, since the circuit includes two NMOS devices, the threshold voltage for the devices are equal. That is,
.
…… (2)
Step 4 Of 13
Refer to Table 2.1 in the textbook for the values of , and in NMOS model.
Substitute for , for , for , for , for and for in equation (2).
…… (3)
Step 5 Of 13
Solve equation (3) to find by trial and error method as follows:
Similarly, by substituting various values for in equation (3), the values are calculated and tabulated in Table 1.
From Table 1, for the function value is approximately equal to 1 and the equation (1) is satisfied.
Therefore, the input voltage is,
Step 6 Of 13
The output voltage is,
Step 7 Of 13
Consider the expression to calculate the body effect coefficient for the NMOS device.
…… (4)
Step 8 Of 13
Consider the expression to calculate the small-signal voltage gain for the circuit with body effect coefficient.
Step 9 Of 13
(b)
For device into the triode region by :
The output voltage is,
The device drives into the triode region by . Therefore, the output voltage is expressed as,
Step 10 Of 13
Substitute for .
Step 11 Of 13
Consider the relation of the drain current of device and with a channel-length modulation.

Step 12 Of 13
Step 13 Of 13
Question:
In the circuit of Fig. 3.17, (W/L)1 = 20/0.5, I1 = 1 mA, and IS = 0.75 mA. Assuming λ = 0, calculate (W/L)2
such that M1 is at the edge of the triode region. What is the small-signal voltage gain under this condition?
Figure 3.17
Step 1 Of 8
Consider the modulation coefficient is zero.

Consider the expression to calculate the current for the device .
…… (1)
Consider the expression to calculate the current for in the circuit.
…… (2)
Here, is the mobility of holes, is the drain-drain voltage, is the output voltage and is the current source.
Step 2 Of 8
Substitute for in the equation.

Refer to Table 2.1 in the textbook for the value of in NMOS model.
Substitute for and for to find .
Step 3 Of 8
…… (3)
Refer to Table 2.1 in the textbook for the values of and in NMOS model.
Substitute for , for , for , for and for in equation (3).
Step 4 Of 8
Step 5 Of 8
…… (4)
Refer to Table 2.1 in the textbook for the values and in PMOS model.
Substitute for , for , for , for , for , for , for

and for in equation (4).
Step 6 Of 8
Consider the expression to calculate transconductance for the device .
Here, is the current of the device .

Here, is the current of the device .
Refer to Figure 3.13 in the textbook, the total current is expressed as,
Step 7 Of 8
Consider the expression to calculate the small-signal voltage gain for Figure 3.13 in the textbook.
Step 8 Of 8
Substitute for , for , for , for , for , for and
for .
Thus, the value of as the device at the edge of the triode region is and the small-signal voltage gain is .
Question:
Plot the small-signal gain of the circuit shown in Fig. 3.17 as IS goes from 0 to 0.75I1. Assume that M1 is
always saturated, and neglect channel-length modulation and body effect.
Figure 3.17
Step 1 Of 5
Consider the channel length modulation and body effect coefficient is zero.
current of the device .
Here, is the mobility of holes and is the current of the device .
Step 2 Of 5
Refer to Figure 3.13 in the textbook, the total current is expressed as,
Here, is the current source.

Step 3 Of 5
Consider the expression to calculate the small-signal voltage gain for Figure 3.13 in the textbook.
Here, is the transconductance for the device and is the transconductance for the device .
Substitute for .
…… (1)
Step 4 Of 5
The source current varies from to .
For :
Step 5 Of 5
For :

Using the source current ranges from to , the small signal gain for the circuit is drawn as Figure 1.
Thus, the small signal gain of the circuit in Figure 3.13 for the current source ranges from to has been plotted.
Question:
The circuit of Fig. 3.18 is designed to provide an output voltage swing of 2.2 V with a bias current of 1 mA
and a small-signal voltage gain of 100. Calculate the dimensions of M1 and M2.
Figure 3.18 CS stage with current-source load.
Step 1 Of 7
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the channel length and is
the minimum output voltage.
Take square root on both sides of the equation.
Consider the expression to calculate the maximum output voltage for the device .
Here, is the drain supply voltage, is the drain current and is the mobility of holes.
Step 2 Of 7
Consider the expression to calculate the output voltage swing.
…… (1)
Substitute for .
Step 3 Of 7
Refer to Table 2.1 in the textbook for the term in NMOS model and in PMOS model.
Substitute for , for and , for , for and for in equation (1).
Reduce the equation as follows.

…… (2)
Step 4 Of 7
…… (3)
Refer to Table 2.1 in the textbook for the value of for the NMOS and PMOS models.
Use equation (3) to find for NMOS device .
Use equation (3) to find for PMOS device .
Step 5 Of 7
Here, is the transconductance for the device .
Step 6 Of 7
Consider the expression to calculate the intrinsic gain of the transistor .

Step 7 Of 7
Thus, the value of dimension for the device is and for the device is .
Question:
Sketch Vout versus Vin for the circuits of Fig. 3.78 as Vin varies from 0 to VDD. Identify important transition
points.
Figure 3.78
Step 1 Of 24
Apply Kirchhoff’s current law (KCL) at the node point in the circuit.
…… (1)
Step 2 Of 24
The input voltage varies from to .
When , the output voltage is non-zero due to presence of the bias voltage .
When the input voltage further increases, it reaches the point of voltage , that is,
Therefore, at the input voltage , the respective output voltage is .
Step 3 Of 24
When the input voltage further increases, it reaches the value , that is,
Therefore, for the input , the respective output voltage is .
Step 4 Of 24
Using the calculations, the plot for the output voltage versus input voltage for Figure 3.67 (a) is drawn as Figure 1.
Step 5 Of 24
Apply KCL at the node point in the circuit.

Step 6 Of 24
…… (2)
Step 7 Of 24
When the input voltage, ranges from to that is , the device is in off state. When the input voltage is greater than the
threshold voltage that is , the device turns on.
Initially, the input voltage is zero, that is,
Step 8 Of 24
For the input voltage , the output voltage is expressed as follows using the equation (2).
When the input voltage further increases, it reaches the threshold value , that is,

Step 9 Of 24
When the input voltage further increases that is , the device turns on and operates in saturation region.
Therefore, the operation of the device in saturation region shows as a linear decrease in input-output characteristics as it reaches to triode region
due to increase in transistor resistivity.
When the input voltage further increases again, the device enters into the triode region. In the triode region transistor resistance increases so
the output is reduces. The output voltage can written as,
Step 10 Of 24
Using the calculations, the plot for the output voltage versus input voltage for Figure 3.67 (b) is drawn as Figure 2.
Step 11 Of 24
Refer to Figure 3.67 (c) in the textbook.
When the input voltage, ranges from to that is , the device is in off state.
Refer to the circuit, when the device is in off state, the total output voltage is equal to the voltage . That is, for the input , the
output voltage is,
Step 12 Of 24
When the input voltage is greater than the threshold voltage that is , the device turns on and operates in saturation region.
When the input voltage further increases again, the device enters into the triode region, when the output voltage is,
The operation of the device in saturation region and triode region is represented as a linear decrease in the input-output characteristics.
Step 13 Of 24
When the device enters and operates in the triode region, the device behaves like a resistor device.
Therefore, the output voltage of the circuit is calculated as follows using the voltage division rule.
When the output voltage is , the device operates in the deep triode region and is represented as constant curve in the characteristics.
Step 14 Of 24
Using the calculations, the plot for the output voltage versus input voltage for Figure 3.67 (c) is drawn as Figure 3.
Step 15 Of 24
Refer to Figure 3.67 (d) in the textbook.
Refer to the circuit, when the device is in off state, the total output voltage is equal to the zero. That is, for the input , the output
voltage is,
Step 16 Of 24
When the input voltage is greater than the threshold voltage that is , the device turns on and operates in saturation region.
When the input voltage further increases again, the device enters into the triode region, when the output voltage is,
The operation of the device in saturation region and triode region is represented as a linear increase in the input-output characteristics.
Step 17 Of 24
When the device enters and operates in the triode region, the device behaves like a resistor device.
Therefore, the output voltage of the circuit is calculated as follows using the voltage division rule.
When the output voltage is , the device operates in the deep triode region and is represented as constant curve in the characteristics.
Step 18 Of 24
Using the calculations, the plot for the output voltage versus input voltage for Figure 3.67 (d) is drawn as Figure 4.
Step 19 Of 24
Refer to Figure 3.67 (e) in the textbook.
Apply KCL at the node point in the circuit.
…… (3)
Step 20 Of 24
Initially, the input voltage is zero, that is,

Step 21 Of 24
For the input voltage , the output voltage is expressed as follows using the equation (3).
When the input voltage further increases, it reaches the threshold value , that is,
Step 22 Of 24
When the input voltage further increases that is , the device turns on.
Step 23 Of 24
Therefore, the operation of the device in a region shows as a linear increase in input output characteristics till the input voltage reaches . That
is,
Step 24 Of 24
Using the calculations, the plot for the output voltage versus input voltage for Figure 3.67 (e) is drawn as Figure 5.
Thus, the plot for the output voltage versus input voltage for the circuit of Figure 3.67 has been sketched.
Question:
Sketch Vout versus Vin for the circuits of Fig 3.79 as Vin varies from 0 to VDD. Identify important transition
points.
Figure 3.79
Step 1 Of 17
When the input voltage ranges from to , that is, , the device is in the off state and the device is in the triode region
due to the bias voltage .
Refer to the circuit, when the device is in the off state, the total output voltage is equal to the voltage . That is, for the input ,
the output voltage is
Step 2 Of 17
When the input voltage is greater than the threshold voltage, that is, , the device turns on and operates in the saturation region.
When , the device operates only in the triode region.
When the input voltage further increases, it reaches the value , that is
For the input , both the devices and operate in the saturation region, where the output voltage equals to .
That is, when , the device is in the saturation region and is in the triode region and when at , both
the devices operate in the saturation region.
Step 3 Of 17
For the input , the device enters into the triode region and the device operates in the saturation region where the output voltage
for is written as,
Initially, when , the output is and from that the linear decrease occurs in the curve for the increasing input voltages.
Step 4 Of 17
Step 5 Of 17
Refer to Figure 3.68 (b) in the textbook, the input voltage is connected to the PMOS device .
When the input voltage ranges from to , that is, , the device operates in the triode region.
For the input , the output voltage is greater than the value , that is,
Step 6 Of 17
When the input voltage increases, it reaches the value , that is,
For the input , the device enters into the saturation region, when the output voltage is
The operation of the device in the saturation region is represented as a linear decrease for increasing input voltages in the input-output
characteristics.
Step 7 Of 17
For the input , the device ends the operation in the saturation region, when the output voltage is
That is, for the output voltage , the device operates in the saturation region.
Further increase in the input voltage, that is, , the characteristics provide the constant curve with the output voltage
until reaches the value .
Step 8 Of 17
Step 9 Of 17
When the input voltage ranges from to , that is, , both the devices and is in the off state.
the output voltage is,
Step 10 Of 17
When the input voltage is greater than the threshold voltage 1, that is, , the device turns on and operates in the saturation region
and the device is in the off state.
The operation of the devices in the saturation region and triode region is represented as a linear decrease in the input-output characteristics.
Step 11 Of 17
When the input voltage further increases, it reaches the value,
Then, both the devices and start to operate in the saturation region, when the output voltage is,
Step 12 Of 17
For the input , the device enters into the triode region and the device operates in the saturation region when the output voltage is
Initially, when , the output is and from that the linear decrease occurs in the curve for the increasing input voltages.
Step 13 Of 17
Step 14 Of 17
The input voltage is connected to the source resistance ; therefore, when , the output voltage is also zero, that is .
When the input voltage begins to increase from zero, that is , the device operates in a triode region due to the bias voltage
and the device operates in a saturation region due to the bias voltage .
During the input voltage range , the output voltage curves begin to increase linearly in the input-output characteristics.
Step 15 Of 17
For the input , both the devices and operate in the saturation region, when the output voltage is
The operation of the device in the saturation region is represented as a linear increase for increasing input voltages in the input-output
characteristics.
Step 16 Of 17
For the input , the device begins to operate in a saturation region and the device enters into the triode region, when the output
voltage is
That is, for the output voltage , both the devices operate in the saturation region.
Further increase in the input voltage, that is , the characteristics provide the increasing curve and the constant with the output voltage
until the reaches the value .
Step 17 Of 17
Thus, the plot for the output voltage versus input voltage for the circuit of Figure 3.68 has been sketched.
Question:
Sketch Vout versus Vin for the circuits of Fig. 3.80 as Vin varies from 0 to VDD. Identify important transition
points.
Figure 3.80
Step 1 Of 18
When the input voltage ranges from to , that is , the device is in the off state and the device is in the triode region
due to the bias voltage .
Refer to the circuit, when the device is in the off state, the total output voltage is equal to zero. That is, for the input , the output
voltage is,
Step 2 Of 18
When the input voltage is greater than the threshold voltage 1,that is, , the device turns on and operates in the saturation region.
When , the device operatesonly in the triode region.
Step 3 Of 18
When the input voltage increases, it reaches the value , that is
For the input , both the devices and operate in the saturation region where the output voltage is
That is, when , the device is in the saturation region and is in the triode region, and when , both the
devices operate in the saturation region.
Step 4 Of 18
For the input , the output voltage is
Initially, when , the output is and from that, the linear increase occurs in the curve for the increasing input voltages.
Step 5 Of 18
Step 6 Of 18
When the input voltage ranges from to , that is, , the device is in the off state, though the device includes the bias
voltage , due to the zero input voltage, the device is also in the off state and the device is in the deep triode region due to the input
common mode voltage and the bias voltage .
Step 7 Of 18
When the input voltage is greater than the threshold voltage 1, that is, , the devices and turn on and operate in the saturation
region and the device operate in the triode region.
The operation of the devices in the saturation region and triode region is represented as a linear decrease in the input-output characteristics.
Step 8 Of 18
For the input , all the devices , , and operate in the saturation region, when the output voltage is,
The operation of the devices in the saturation region is represented as a linear decrease for increasing input voltages in the input-output
characteristics.
Step 9 Of 18
For the input , the devices and operate in a saturation region and the device operate in a triode region, when the output
voltage is,
That is, for the output voltage , all the devices , , and operate in the saturation region.
Step 10 Of 18
For the input , the devices and enter into the triode region and the device operate in a saturation region.
Further increase in the input voltage, that is, , the characteristics provide the constant curve until the voltage reaches the
value .
Step 11 Of 18
Step 12 Of 18
Refer to Figure 3.69 (c) in the textbook, the input voltage is connected to the PMOS device .
When the input voltage ranges from to , that is, , the device is in the saturation region due to the connected bias voltage
, the device is in the saturation region due to the input common mode voltage and the bias voltage , and the PMOS device operate
in the triode region.
Step 13 Of 18
For the input , all the devices , , and operate in the saturation region, when the output voltage is
The operation of the devices in the saturation region is represented as a linear decrease in the input-output characteristics.
Step 14 Of 18
When the input voltage further increases, it reaches the value , that is,
For the input , the devices and operate in a saturation region and the device enters into the triode region, when the output
voltage is,
The operation of the devices in the saturation region and triode region is represented as a linear decrease for increasing input voltages in the input-
output characteristics.
For the input , the devices and operate in a triode region and the device operates in a saturation region, when the output
voltage is,
Step 15 Of 18
For the input , the devices and enter into the deep triode region and the device is in the off state, when the output
voltage is,
Step 16 Of 18
Step 17 Of 18
Refer to Figure 3.69 (d) in the textbook, the input voltage is connected to the PMOS device .
The output voltage is placed between the devices and . When the input voltage ranges as , the output voltage is
expressed as,
The operation of the devices in a region is represented as a constant curve for increasing input voltages in the input-output characteristics.
Step 18 Of 18
When the input voltage further increases, it reaches the value that ranges as , the output voltage decreases
linearly and reaches zero at the input voltage of . That is,
Thus, the plot for the output voltage versus input voltage for the circuit of Figure 3.69has been sketched.
Question:
Sketch IX versus VX for the circuits of Fig. 3.81 as VX varies from 0 to VDD. Identify important transition
points.
Figure 3.81
Step 1 Of 21
Refer to Figure 3.70 (a) in the textbook, the circuit is redrawn as Figure 1.
Step 2 Of 21
Refer to Figure 1, the current is expressed as follows,
…… (1)
Consider the expression to calculate the charging voltage of that is using the Figure 1.

Step 3 Of 21
Consider the expression to calculate the drain current for the NMOS device .
Refer to Figure 1, the voltage .
Substitute for .
Step 4 Of 21
…… (2)
The voltage varies from to .
When the voltage is zero, there is no current in reverse, therefore, .
Substitute for and in equation (2).
Step 5 Of 21
When the voltage , ranges from to that is , the device is in triode region due to the input common
mode voltage and the bias voltage .
When the voltage increases, it reaches the value , that is
For the input , the device is operated in the saturation region. The equation of is in linear expression form, therefore the
curve is represented as a straight line.
Step 6 Of 21
For the input , the current .
When the voltage further increases, it reaches the value , that is

Step 7 Of 21
Substitute for .
Step 8 Of 21
Using the calculations, the plot for the current versus voltage for Figure 3.70 (a) is drawn as Figure 2.
Step 9 Of 21
Refer to Figure 3.70 (b) in the textbook, the circuit is redrawn as Figure 3.
Step 10 Of 21
…… (3)
Consider the expression to calculate the drain current for the PMOS device .
Refer to Figure 2, the gate source voltage of the device is expressed as,
Step 11 Of 21
Consider the expression to calculate the current .
Substitute for for .

Substitute for .
…… (4)
Step 12 Of 21
When the voltage , ranges from to , the device is operated in a saturation region.
For the voltage ranges, , the current is expressed as,
Step 13 Of 21
For the input , the device is in off state and the curve is represented as a straight line until the voltage reaches
.
Step 14 Of 21
When the voltage further increases, it reaches the value , that is,
Step 15 Of 21
Using the calculations, the plot for the current versus voltage for Figure 3.70 (b) is drawn as Figure 4.
Step 16 Of 21
Refer to Figure 3.70 (c) in the textbook, the circuit is redrawn as Figure 5.
Step 17 Of 21
…… (5)
When the voltage , ranges from to that is , the device is operated in a triode region due to the bias voltage and the
curve is increased linearly from the negative value.
Refer to Figure 5, the voltage .
Substitute for .
Step 18 Of 21
Consider the expression to calculate the voltage using the Figure 5.

Substitute for .
Step 19 Of 21
When the voltage ranges from to that is , the device is operated in a saturated region.
When the voltage increases, it reaches the value in the axis range between , that is
For the input , the current .
Step 20 Of 21
Consider the expression to calculate the voltage using the Figure 5.
Substitute for .
For the input , the device is in off state and the curve is represented as a straight line until the voltage reaches .
When the voltage further increases, it reaches the value , that is,
Step 21 Of 21
Using the calculations, the plot for the current versus voltage for Figure 3.70 (c) is drawn as Figure 6.
Thus, the plot for the current versus voltage for the circuit of Figure 3.70has been sketched.
Question:
Sketch IX versus VX for the circuits of Fig. 3.82 as VX varies from 0 to VDD. Identify important transition
points.
Figure 3.82
Step 1 Of 9
(a)
When , the current flows to (consider as battery or capacitor), then the charged can cause to flow current, which flows
through .
From Figure 3.71 (a), the current is equal to the current in starting in reverse direction. That is when (no voltage and will be
charged by ),
…… (1)
At the large number of , the current is equal to .
…… (2)
Step 2 Of 9
From equations (1) and (2), when increases from 0 to , the transistor is in saturation and is in the triode region. When
varies between to , both the transistors are in the saturation region.
Write the expression for the charging voltage in .
…… (3)
When reaches to level, the current flows through the due to . And the transistor gets turned OFF and remains in
saturation. For the further increase in , the current , until goes to zero volts.
The plot for versus is drawn as shown in Figure 1.
Thus, the plot for versus is drawn.
Step 3 Of 9
(b)
Assume that initially that can be written as .
With respect to bias voltages and threshold voltages of the transistors, at the starting stage of , lowest values and are in the triode
region, whereas is in the saturation region. Furthermore increase in results that pushes in to the saturation region. The transistor state
of condition also depends on parameter of their aspect ratios and bias voltages.
Step 4 Of 9
Consider the point at drain of both as Y. If these voltages at Y are equal to , the transistors operate in
saturation and moves into the triode region.
As the voltage is equal to , the current is saturated. In this region, the transistor is in saturation, is OFF (since
increases further), and is in the triode region.
Step 5 Of 9

Step 6 Of 9
(c)
Assume that all the transistors in the circuit are in the saturation region for and .
From the plot in Figure 3, initially, the current flows to that is equal to . When the voltages and are equal, no current flows, that is,
, and both devices operate in the triode region. Further increasing , the current flows through the transistors. When
is equal to , the current flows maximum and is saturated, in this stage, both transistors are in the saturation mode. As it is assumed
that , most of the current flowing through when , the is more negative in the starting point, and most of the
current flows through from when is maximum, so the is more positive and saturated.

Step 7 Of 9
(d)
Assume , initially , as the current from flows to . At this stage, when , the current is exactly equal and in
reverse direction to drain current of . Therefore, results as negative maximum for .
As increases step by step and reaches the quiescent point where , when varies to , the maximum positive current flows
from . Here, gate inputs are commonly connected through to node, so that the transistors are in saturation region for all the ranges of
.

Step 8 Of 9
(e)
Refer to Figure 3.71 (e) in the textbook.
Consider initially , then it will charge by the current flows through , that is,
for .
In the initial stage, the transistor is in the triode region and is in the saturation region until reaches to .
While increasing the voltage , when current increased through from negative, both transistors enter into the saturation region. At the
point when is reached, then the cutoff point occurs and current starts to increase gradually to the highest value as is
supplied, that means is in saturation and is in triode. For the value of , can be reached to the maximum possible value.

Step 9 Of 9
(f)
Refer to Figure 3.71 (f) in the textbook.
Initially , the voltage at increases with the current from that is equal to the current through . Here, the current is as follows:
Assume that varies from 0 to . Starting at , operates in the triode region and operates in the saturation region. When
varies from 0 and reaches the point where , and operate in the saturation region. The point where for is called
as the quiescent condition. By further increasing and reaching the voltage of , turns into the saturation region and turns off,
and the maximum possible current flows that is equal to .

Question:
Assuming all MOSFETs are in saturation, calculate the small-signal voltage gain of each circuit in Fig. 3.83
(λ ≠ 0, γ = 0).
Figure 3.83
Step 1 Of 13
(a)
All the MOSFETs are in saturation region.
Based upon the condition of gate source voltage and threshold voltage, the state of the device is determined.
The device operated in triode region for the gate source voltage with smaller drain source voltage similarly, the device works in saturation
region for with larger .
Step 2 Of 13
The Figure 3.72 (a) in the textbook is redrawn as Figure 1.
Apply Kirchhoff’s Current Law (KCL) for the node in Figure 1.
Here, is the input voltage, is the output voltage, is the transconductance, is the drain resistance and is the output resistance.

Step 3 Of 13
Consider the expression to calculate the small signal voltage gain.
…… (1)
Thus, the expression for the small signal voltage gain is .
Step 4 Of 13
(b)
The Figure 3.72 (b) in the textbook is redrawn as Figure 2.
Apply KCL for the node in Figure 2.

Simplify the equation
Step 5 Of 13
(c)
The Figure 3.72 (c) in the textbook is redrawn as Figure 3.
Step 6 Of 13

Step 7 Of 13
(d)
The Figure 3.72 (d) in the textbook is redrawn as Figure 4.
Apply KCL for the node and in Figure 4.
…… (2)
…… (3)
Simplify the equation (3)
Step 8 Of 13
Simplify the equation (2).
Substitute for .
Step 9 Of 13
Step 10 Of 13
Step 11 Of 13
(e)
The Figure 3.72 (e) in the textbook is redrawn as Figure 5.
Apply KCL for the node and in Figure 5.
…… (4)
…… (5)
Simplify the equation (4)
Step 12 Of 13
Substitute for .
Step 13 Of 13

Question:
Assuming all MOSFETs are in saturation, calculate the small-signal voltage gain of each circuit in Fig. 3.84
(λ ≠ 0, γ = 0)).
Figure 3.84
Step 1 Of 25
(a)
All the MOSFETs are in saturation region.
Based upon the condition of gate source voltage and threshold voltage, the state of the device is determined.
The device operated in triode region for the gate source voltage with smaller drain source voltage similarly, the device works in saturation
region for with larger .
Step 2 Of 25
The Figure 3.73 (a) in a textbook is redrawn as Figure 1.
Apply Kirchhoff’s Current Law (KCL) for the node and in Figure 1.
…… (1)
…… (2)
Here, is the input voltage, is the output voltage, is the transconductance and is the output resistance.

Step 3 Of 25
Substitute for .
Step 4 Of 25
Step 5 Of 25
Consider the expression to calculate the small signal voltage gain.
…… (3)

Step 6 Of 25
(b)
The Figure 3.73 (b) in the textbook is redrawn as Figure 2.
Consider the expression to calculate the equivalent transconductance of the circuit in Figure 2.
Consider the expression to calculate the output resistance.
Step 7 Of 25
…… (4)
Step 8 Of 25
Step 9 Of 25
(c)
The Figure 3.73 (c) in the textbook is redrawn as Figure 3.
The only difference between the Figure 2 and Figure 3 is that the resistance is looking up at the source .

Step 10 Of 25
Step 11 Of 25
(d)
The Figure 3.73 (d) in the textbook is redrawn as Figure 4.
Consider the expression to calculate the equivalent transconductance of the circuit in Figure 4.
Step 12 Of 25

Step 13 Of 25
(e)
The Figure 3.73 (e) in the textbook is redrawn as Figure 5.
Step 14 Of 25
The only difference between the Figure 4 and Figure 5 is that the resistance is looking up at the source .

Step 15 Of 25
Step 16 Of 25
(f)
The Figure 3.73 (f) in a textbook is redrawn as Figure 6.
…… (5)
…… (6)
Rearrange the equation
Step 17 Of 25
Substitute for .
Step 18 Of 25
Step 19 Of 25
(g)
The Figure 3.73 (g) in a textbook is redrawn as Figure 7.
…… (7)
…… (8)
Step 20 Of 25
Step 21 Of 25
Substitute for .
Step 22 Of 25
Step 23 Of 25
(h)
The Figure 3.73 (h) in a textbook is redrawn as Figure 8.
Step 24 Of 25
…… (9)
…… (10)
Step 25 Of 25
Substitute for .

Question:
Sketch VX and VY as a function of time for each circuit in Fig. 3.85. The initial voltage across C1 is equal to
VDD.
Figure 3.85
Step 1 Of 26
(a)
Consider the expression to calculate the voltage at the point .
Here, is the capacitor voltage and is the drain voltage.
At time, , the capacitor voltage becomes .
Substitute for .
Step 2 Of 26
Consider the expression to calculate the drain for the NMOS device .
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, is the bias
voltage and is the threshold voltage.
…… (2)
Step 3 Of 26
Equate the equations (1) and (2).
Step 4 Of 26
It is assumed that the voltage at point is, , therefore the device is always saturated.
…… (3)
…… (4)
Consider the expression to calculate the current across the capacitor .
…… (5)
Step 5 Of 26
Step 6 Of 26
Step 7 Of 26
Using the expression , the plot for the voltage as a function of the time is drawn as Figure 1.
Step 8 Of 26
Integrate on both sides of the equation.

…… (6)
Here, because the value of the voltage at point , .
Step 9 Of 26
Step 10 Of 26
Thus, the voltages and as a function of time for the circuit in Figure 3.74 (a) have been sketched.
Step 11 Of 26
(b)
The drain current of the NMOS device is zero, therefore the device is operated in a deep triode region, and it leads to make the
voltage as zero potential.
That is the voltage at the point is,
Step 12 Of 26
Consider the expression to calculate the voltage at the point at time when the device starts in saturation region.
…… (7)
…… (8)
Step 13 Of 26

…… (9)
Step 14 Of 26
The device enters into the triode region when,
Consider the expression to calculate the drain for the NMOS device for the time .
…… (10)
Step 15 Of 26
Step 16 Of 26
Step 17 Of 26
Step 18 Of 26
Thus, the voltages and as a function of time for the circuit in Figure 3.74 (b) have been sketched.
Step 19 Of 26
(c)
Consider the expression to calculate the voltage at the point at time when both the devices are in saturation region.
…… (11)
…… (12)
Step 20 Of 26
Step 21 Of 26
…… (13)
Step 22 Of 26
…… (14)
Step 23 Of 26
Consider the expression to calculate the voltage at the point .
Substitute for .
…… (15)
Step 24 Of 26
Consider the expression to calculate the voltage at the point at time .
Consider the expression to calculate the voltage at the point at time when the device enters the triode region and the device still
in the saturation region.
Step 25 Of 26
Substitute for .
…… (16)
The device also enters into the triode region when the voltage at the point is, . The regime of the voltages continues until
the voltage and drops and the capacitor charges up to .
Therefore, for , both the devices and are in saturation region, for , the device is in triode region and the device
in saturation region and for , both the devices and are in triode region.
Step 26 Of 26
Using the expression in equation (13), the plot for the voltage as a function of the time is drawn as Figure 5.
Using the expression in equation (16), the plot for the voltage as a function of the time is drawn as Figure 6.
Thus, the voltages and as a function of time for the circuit in Figure 3.74 (c) have been sketched.
Question:
In the cascode stage of Fig. 3.59, assume that (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, ID1 = ID2 = 0.5 mA, and RD
= 1 kΩ.
(a) Choose Vb such that M1 is 50 mV away from the triode region.
(b) Calculate the small-signal voltage gain.
(c) Using the value of Vb found in part (a), calculate the maximum output voltage swing. Which
device enters the triode region first as Vout falls?
(d) Calculate the swing at node X for the maximum output swing obtained above.
Figure 3.59 Cascode stage.
Step 1 Of 25
(a)
Consider the expression to calculate the drain source voltage for the saturated NMOS device .
…… (1)
Here, is the gate source voltage and is the threshold voltage.
Consider the expression to calculate the drain current for the saturated NMOS device
…… (2)
…… (3)
Step 2 Of 25
Substitute for .
Step 3 Of 25
Step 4 Of 25
Step 5 Of 25
Consider the expression for the bias voltage for the device which is away from the triode region.
Substitute for .
Step 6 Of 25
Step 7 Of 25
Rearrange the equation (2) for the device .

Step 8 Of 25
Step 9 Of 25
Consider the expression to calculate the bias voltage.
Thus, the value of the bias voltage for the device away from the triode region is .
Step 10 Of 25
(b)
Consider the expression to calculate the transconductance for the saturated NMOS device .

Step 11 Of 25
Step 12 Of 25
Consider the expression to calculate the body effect coefficient for the NMOS device .
Step 13 Of 25
Step 14 Of 25
Consider the expression of the bulk transconductance of the device .
Step 15 Of 25
Consider the expression to calculate the output resistance for both the devices since
Therefore,
Consider the expression to calculate the equivalent transconductance of the circuit.
Substitute for , for , for , for and .

Step 16 Of 25
Substitute for , for , for , for and ..
Step 17 Of 25
Step 18 Of 25
Thus, the value of the small signal voltage gain is .
Step 19 Of 25
(c)
From part (b), the small signal voltage gain from input to the node is obtained.
Consider the expression to calculate the output resistance at node .
Substitute for , for , for , for and .
Step 20 Of 25
Consider the expression to calculate the small-signal voltage gain at node .
Step 21 Of 25
Consider the expression to calculate the varying input voltage that is .
The device is away from the triode region.
Step 22 Of 25
Consider the expression to calculate the varying output voltage.

Consider the expression to calculate the minimum output voltage.
Step 23 Of 25
Since, the calculated gate source voltage value is less that the threshold value, the maximum value of the output voltage is equal to drain voltage
. That is,
Substitute for .
Thus, the value of the maximum output voltage swing is .
Step 24 Of 25
(d)
Consider the expression to calculate the varying output voltage.
Consider the expression to calculate the input voltage.
Step 25 Of 25
Consider the expression to calculate the varying voltage at node .

Therefore, the maximum output swing at node is calculated as follows,
Thus, the value of the maximum output swing at node is .

Question:
Consider the circuit of Fig. 3.23 with (W/L)1 = 50/0.5, RD = 2 kΩ, and RS = 200 Ω.
(a) Calculate the small-signal voltage gain if ID = 0.5 mA.
(b) Assuming λ = γ = 0, calculate the input voltage that places M1 at the edge of the triode region.
What is the gain under this condition?
Figure 3.23 CS stage with source degeneration.
Step 1 Of 20
(a)
Refer to Figure 3.16 in the textbook. The transistor in the circuit is NMOS model.
Here, is the channel-length modulation coefficient and is the drain current.
Step 2 Of 20
Consider the expression to calculate the source voltage.
Here, is the source resistance.

Step 3 Of 20
Step 4 Of 20
Here, is the drain resistance and is the drain voltage.
Consider the expression to calculate the drain source voltage.
Step 5 Of 20
Here, is the gate-source voltage, is the drain-source voltage, is the mobility of electrons, is the gate oxide capacitance per unit
area, W is the channel width and L is the channel length.
Step 6 Of 20
…… (1)
Step 7 Of 20
Substitute for .
Step 8 Of 20
Refer to Table 2.1 in the textbook for the parameter value of and in NMOS model.
Substitute for , for , for , for , for and for in the equation
(1).

Step 9 Of 20
Consider the expression to calculate the body effect coefficient for the NMOS device.
Step 10 Of 20
Step 11 Of 20
Consider the expression to calculate the outputresistance.

Step 12 Of 20
Consider the expression to calculate the total output impedance.
Step 13 Of 20
Thus, the value of the small signal voltage gain is .
Step 14 Of 20
(b)
Consider .
…… (2)
Here, is the input voltage.

Consider the expression to calculate the input voltage.

Step 15 Of 20
Substitute for
Substitute for , for , for , for , for and for in the equation
(1).
Step 16 Of 20
Factorize the equation.
Here, the least value of is considered for further calculation.
Step 17 Of 20

Step 18 Of 20
Substitute for , for , for , for , for and for in the

equation (1).
Step 19 Of 20
Step 20 Of 20

Thus, the value of the input voltage is and the value of the small signal voltage gain is .
Question:
Suppose the circuit of Fig. 3.22 is designed for a voltage gain of 5. If (W/L)1 = 20/0.5, ID1 = 0.5 mA, and Vb
= 0 V:
(a) Calculate the aspect ratio of M2.
(b) What input level places M1 at the edge of the triode region? What is the small-signal gain
(c) What input level places M2 at the edge of the saturation region? What is the small-signal gain
Figure 3.22 CS stage with triode load.
Step 1 Of 41
(a)
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, is the
drain-source voltage, is the channel-length modulation coefficient and is the drain current.
Step 2 Of 41
Substitute for .
Step 3 Of 41
Refer to Table 2.1 in the textbook for the parameter value of and in NMOS model.
…… (2)
Step 4 Of 41
Consider the expression to calculate the output resistance for NMOS device .
Step 5 Of 41
Consider the expression to calculate the output resistance for PMOS device .
Step 6 Of 41
Refer to Table 2.1 in the textbook for the parameter value of in PMOS model.
Step 7 Of 41
The drain source voltage value is large therefore the channel length modulation effect for the device is not neglected. Therefore, the drain
source voltage can be calculated using iterations.
First iteration:
The drain source voltage is assumed as and substituted in equation (2).
Step 8 Of 41
Here, is the output resistance.

…… (3)
Step 9 Of 41
Consider the expression to calculate the output resistance for PMOS device .
…… (4)
Here, is the mobility of holes, is the drain voltage and is the threshold voltage.
Assume the value of as .
…… (5)
Consider the expression to calculate the drain current for PMOS device .
Substitute for .
…… (6)
Step 10 Of 41
Multiply the equations (5) and (6).
Step 11 Of 41
Refer to Table 2.1 in the textbook for the parameter value of in PMOS model.

The lowest source drain voltage is used for further calculations, that is,
Step 12 Of 41
Second iteration:
From the first iteration, the value of drain source voltage or is .
Step 13 Of 41
Step 14 Of 41
…… (7)

Step 15 Of 41
Third iteration:
From the second iteration, the value of drain source voltage or is .
Step 16 Of 41
Step 17 Of 41
…… (8)
Step 18 Of 41
Fourth iteration:
From the third iteration, the value of drain source voltage or is .
Step 19 Of 41

…… (9)
Step 20 Of 41
From third and fourth iteration, the value obtained for the drain source voltage is , therefore it is used to calculate the aspect ratio.
Thus, the value of the aspect ratio is .
Step 21 Of 41
(b)

Here, is the gate-source voltage.
…… (10)
Consider the expression to calculate the drain for the PMOS device .
…… (11)
Step 22 Of 41
Substitute for .
Step 23 Of 41
Factorizing the equation provides the following values.
Therefore, the value of the output voltage with minimum positive value is used for further calculation. That is,
Step 24 Of 41
Consider the expression for the output voltage for the device at the edge of the triode region.
…… (12)
Refer to Table 2.1 in the textbook for the value of threshold voltage in NMOS model.
Step 25 Of 41
Step 26 Of 41
From the calculations, the device is no longer in the triode region because,
Therefore, the value of the output voltage is recalculated by assuming that the device in saturation region.
…… (13)
Consider the expression to calculate the drain for the PMOS device .
…… (14)
Step 27 Of 41
Substitute for .
Step 28 Of 41
and for .
Step 29 Of 41
Factorizing the equation provides the following values.
Therefore, the value of the output voltage with positive value is used for further calculation. That is,
Step 30 Of 41
…… (15)
Step 31 Of 41

Step 32 Of 41
Consider the expression to calculate transconductance at the edge of the triode region.
…… (16)
Step 33 Of 41
…… (17)

Step 34 Of 41
Consider the expression to calculate the small-signal voltage gain at the edge of the triode region.
…… (18)
Step 35 Of 41
(c)
Step 36 Of 41
Step 37 Of 41

, for , for and for .
Therefore, the input voltage is,
Step 38 Of 41
Step 39 Of 41

Step 40 Of 41
Step 41 Of 41
Thus, the value of the input voltage of device at the edge of the saturation region is and the small-signal gain is
.
Question:
Sketch the small-signal voltage gain of the circuit shown in Fig. 3.22 as Vb varies from 0 to VDD. Consider
two cases:
(a) M1 enters the triode region before M2 is saturated;
(b) M1 enters the triode region after M2 is saturated.
Figure 3.22 CS stage with triode load.
Step 1 Of 3
Refer to Figure 3.15 in the textbook for the CS stage with triode load.
When a MOS device operated in a deep triode region, then it behaves as a resistor therefore it can serves as a load in CS stage.
The channel charge is modulated using the gate source voltage of the device and exceeds the threshold voltage is called as overdrive voltage. The
overdrive voltage must be increased in order to enter the NMOS device to triode region before the saturation of the PMOS device .
Step 2 Of 3
The plot for the voltage gain as the bias voltage varies from to for the case that device enters into the triode region before the
device saturation is drawn as Figure 1.
The plot for the voltage gain as the bias voltage varies from to for the case that device enters into the triode region after the device
saturation is drawn as Figure 2.
Step 3 Of 3
The NMOS device enters into the triode region before the device saturates leads to drop the drain source voltage , since the gate
source voltage is constant. It states, that the voltage increases by increasing the drain current and it is not possible if the PMOS
device operates in saturation region.
The transconductance in the Figure 1 is higher than the transconductance in Figure 2. Therefore, the small signal voltage gain is higher in Figure
1 at the bias voltage than comparing with the Figure 2.
Since the bias voltage sweeps all the way from to , the overall voltage gain in Figure 1 is lesser than the gain in Figure 2.
Thus, the plots for the small-signal voltage gain versus voltage for the circuit with two different cases have been sketched.
Question:
A source follower can operate as a level shifter. Suppose the circuit of Fig. 3.37(b) is designed to shift the
voltage level by 1 V, i.e., Vin − Vout = 1 V.
(a) Calculate the dimensions of M1 and M2 if ID1 = ID2 = 0.5 mA, VGS2 − VGS1 = 0.5 V, and λ = γ =
0.
(b) Repeat part (a) if γ = 0.45 V−1 and Vin = 2.5 V. What is the minimum input voltage for which
M2 remains saturated?
Figure 3.37 Source follower using (a) an ideal current source, and (b) an NMOS transistor as a current
source.
Step 1 Of 11
(a)
The source follower using an NMOS transistor is drawn as Figure 1.
Refer to Figure 1, the circuit is designed to shift the voltage level by . That is,
Here, is the input voltage and is the output voltage.
Consider the expression to calculate the gate-source voltage of the device .
Consider the expression to calculate the drain current for the device when .
…… (1)
threshold voltage.
…… (2)
Here, is the bulk voltage.
Step 2 Of 11
Refer to Table 2.1 in the textbook for the value of parameter in NMOS model.
Substitute for .
Step 3 Of 11
Refer to Table 2.1 in the textbook for the terms and in NMOS model.
Substitute for .
Step 4 Of 11
Consider the expression that relates the gate-source voltages of the devices and .
Here, is the gate-source voltage of device and is the gate-source voltage of device .
Substitute for .
…… (3)
Refer to Figure 1, the bulk voltage is the gate-source voltage of the device .
Step 5 Of 11
Thus, the aspect ratio value of dimensions for the device is and for the device is .
Step 6 Of 11
(b)
Consider the body effect coefficient is,
The circuit is designed to shift the voltage level by . That is,
Substitute for .
Consider the expression that relates the gate-source voltages of the devices and .
Substitute for .
Step 7 Of 11
Consider the expression to calculate the threshold voltage for the device .
…… (4)
Refer to Table 2.1 in the textbook for the terms and in NMOS model.
Step 8 Of 11
Step 9 Of 11
Step 10 Of 11
Substitute for , for , for , for and for in the equation.

Step 11 Of 11
Consider the expression to calculate the output voltage for which the device remains saturated.
Substitute for .

Thus, the aspect ratio value of dimensions for the device is and for the device is . The value of the
minimum input voltage for which the device remains saturated is .
Question:
Sketch the small-signal gain, Vout/Vin, of the cascode stage shown in Fig. 3.59 as Vb goes from 0 to VDD.
Assume that λ = γ = 0.
Figure 3.59 Cascode stage.
Step 1 Of 5
Refer to Figure 3.50 in the textbook, the basic configuration of the cascode stage where the NMOS device produces a small signal drain
current that is proportional to the input voltage and provides route for the generated current to the drain resistance.
The small signal gain of the cascode stage for the bulk voltages ranges from to is drawn as Figure 1.
Step 2 Of 5
Refer to Figure 1, the large scale behavior of the cascode stage is divided as stages (i), (ii), (iii) and (iv).
In stage (i), the bulk voltage is less than the value of the threshold voltage that is .
In this stage, both the devices and are in off state that is and for the neglected sub-threshold condition. In
other words, is saturated and is in off state in triode region.
Step 3 Of 5
In stage (ii), the bulk voltage slightly increases and exceeds , then the device produces current and the output voltage drops. The gate
source voltage increases due to increasing drain current and causes fall in the voltage .
As a result, operates in triode region and in saturation. Increasing the bulk voltages increases of and similarly increasing the
output impedance of t increases the voltage gain of cascode stage.
Step 4 Of 5
In stage (iii), both the devices and are in saturation state. Increase in the transconductance of device along with the increasing bulk
voltage forms the slight increasing variation in the gain.
In this stage, the small signal voltage gain attains the maximum value.
Step 5 Of 5
In stage (iv), the output voltage and voltage are nearly equal which results the device in the triode region.
Therefore, the total output impedance decreases down which in turn decreases and provides a similar change in small signal voltage gain.
Thus, the small signal gain of the cascode stage for the bulk voltage from to is sketched.
Question:
The cascode of Fig. 3.70 is designed to provide an output swing of 1.9 V with a bias current of 0.5 mA. If γ =
0 and (W/L)1−4 = W/L, calculate Vb1, Vb2, and W/L. What is the voltage gain if L = 0.5 μm?
Figure 3.70 NMOS cascode amplifier with PMOS cascode load.
Step 1 Of 22
Refer to Figure 3.60 in the textbook, the devices , are NMOS and the devices , are PMOS.
Consider the expression that relates the bias voltages and threshold voltages of the devices in the circuit.
Here, is the base voltage, is the output voltage and is the threshold voltage.
Refer to Table 2.1 in the textbook for the value of in NMOS model and in PMOS model.
Step 2 Of 22
The channel width and length ratio is equal for all the four devices. That is,
Consider the expression of the bias current for the NMOS device .
Substitute for .
…… (1)
Step 3 Of 22
Consider the expression of the bias current for the NMOS device .
Substitute for .
…… (2)
Step 4 Of 22
Consider the expression of the bias current for the PMOS device .
Step 5 Of 22
Substitute for .
…… (3)
Step 6 Of 22
Consider the expression of the bias current for the PMOS device .
Substitute for .
…… (4)
Step 7 Of 22
Consider the expression to calculate the output swing of the circuit in Figure 3.60.
Here, is the drain voltage and is the drain source voltage.

Rewrite the equation with respective to individual device’s bias and threshold voltage.
…… (5)
Substitute the equations (1), (2), (3) and (4) in equation (5).
Square on both sides of the equation to simplify it.
…… (6)
Step 8 Of 22
Substitute for .
Step 9 Of 22
Refer to Table 2.1 in the textbook for the parameter value of in NMOS model and in PMOS model.
Substitute for , for and for in the equation (6).
Step 10 Of 22
Consider the expression to calculate the drain source voltage of .
Substitute for .
Step 11 Of 22
Therefore,
Step 12 Of 22
Consider the expression to calculate the drain source voltage of .
Substitute for .
Step 13 Of 22
Substitute for .
Therefore, the value of is,
Step 14 Of 22
Substitute for .
Step 15 Of 22
Therefore, the source drain voltage is
Therefore, the devices and are at the edge of the triode region.
Step 16 Of 22
Consider the expression to calculate the transconductance for the saturated NMOS devices and . That is,

Therefore,
Step 17 Of 22
Consider the expression to calculate the transconductance for the saturated PMOS devices and . That is,
Therefore,
Step 18 Of 22
Consider the expression to calculate the output resistance for the NMOS devices and . That is,
Therefore,
Step 19 Of 22
Consider the expression to calculate the output resistance for the PMOS devices and . That is,
Therefore,
Step 20 Of 22
Substitute for and , for and .
Step 21 Of 22
Substitute for , for and , for and for and .

Step 22 Of 22
Thus, the value of the bias voltages and are and respectively, the value of the width and length ratio is
and the value of the small signal voltage gain is .
Question:
Consider the gate-source voltage of M1 in Fig. 3.23(a): VGS = Vin − ID RS. Determine ΔVGS in response to a
change in Vin and show that it decreases as gm RS increases. How does this trend show that the circuit
becomes more linear?
Figure 3.23 CS stage with source degeneration.
Step 1 Of 0
Question:
Prove that the voltage gain from VDD to Vout in Fig. 3.21 is given by
Figure 3.21 Arrangement for studying supply sensitivity of CS stage with active load.
Step 1 Of 0
Question:
In the circuit shown in Fig. 3.86, prove that
where Vout1 and Vout2 are small-signal quantities and λ, γ > 0.

Figure 3.86
Step 1 Of 0
Question:
The CG stage of Fig. 3.51(a) is designed such that its input resistance (seen at node X) matches the signal
source resistance, RS. If λ, γ > 0, prove that
Also, prove that
Figure 3.51 (a) CG stage with finite transistor output resistance; (b) small-signal equivalent circuit.
Step 1 Of 0
Question:
Calculate the voltage gain of a source follower using the lemma Av = −Gm Rout. Assume that the circuit
drives a load resistance of RL and λ, γ > 0.
Step 1 Of 0
Question:
Calculate the voltage gain of a common-gate stage using the lemma Av = −Gm Rout. Assume a source
resistance of RS and λ, γ > 0.
Step 1 Of 0
Question:
How many amplifier topologies can you create using each of the structures shown in Fig. 3.87 and no other
transistors? (The source and drain terminals can be swapped.)
Figure 3.87
Step 1 Of 0
Question:
Suppose the total capacitance between adjacent lines in Fig. 4.2 is 10 fF and the capacitance from the
drains of M1 and M2 to ground is 100 fF.
(a) What is the amplitude of the glitches in the analog output in Fig. 4.2(a) for a clock swing of 3
V?
(b) If in Fig. 4.2(b), the capacitance between L1 and L2 is 10% less than that between L1 and L3,
what is the amplitude of the glitches in the differential analog output for a clock swing of 3 V?
Figure 4.2 (a) Corruption of a signal due to coupling; (b) reduction of coupling by differential operation.
Step 1 Of 3
(a)
Refer to Figure 4.2 (a) in the textbook shows a signal corruption due to coupling.
The simplified equivalent circuit with a clock swing of 3 V is drawn as shown in Figure 1.
Consider the change in voltage (amplitude) across line is calculated by using voltage division principle as:

Thus, for a clock signal of 3 V the change in voltage amplitude (glitches) in the analog output is .
Step 2 Of 3
(b)
Refer to Figure 4.2(b) in the textbook shows coupling reduction by differential equation.
The simplified equivalent circuit with a clock swing of 3 V is drawn as shown in Figure 2.
Consider the change in voltage across line is calculated by using voltage division principle as:
Substitute for and for in equation.
Consider the change in voltage across line is calculated by using voltage division principle as:
Step 3 Of 3
The net difference in voltage between the lines and is,
Substitute 0.273 V for and 0.248 V for .
Thus, for a clock signal of 3 V the change in voltage amplitude (glitches) in the differential analog output is .
Question:
Sketch the small-signal differential voltage gain of the circuit shown in Fig. 4.9(a) if VDD varies from 0 to 3
V. Assume that (W/L)1−3 = 50/0.5, Vin,CM = 1.3 V, and Vb = 1 V.
Figure 4.9 (a) Differential pair sensing an input common-mode change; (b) equivalent circuit if M3 operates
in the deep triode region; (c) common-mode input-output characteristics.
Step 1 Of 4
Refer to Figure 4.8 (a) in the textbook, which shows a differential pair circuit with tail current applied by NFET.
Consider the expression for tail current.
…… (1)
Here, is the threshold voltage for NMOS, which is 0.7 V, is the mobility of electrons, is the gate source voltage, W is the channel
width, L is the channel length, and is the gate oxide capacitance per unit area.
Step 2 Of 4
Consider the expression for .
Substitute for .
…… (2)
Refer to Table 2.1 (NMOS) in the textbook for the term , which is and for the term , which is .

In Figure 4.8 (a), the base voltage is the gate source voltage , which is 1 V. That is, .
Substitute for , for , for , and 1 V for in equation (1).
Step 3 Of 4
Consider the expression for drain-drain voltage.
Here, is the common-mode input voltage, is the drain resistance, and is the tail current.
Substitute 1.3 V for , 0.7 V for , and for .
Step 4 Of 4
In Figure 4.8 (a), consider and vary the drain-drain voltage from 0 V to 3 V. Consider , as the mosfets
gate potential is less positive when compared to source potential, both the mosfets and are OFF, which leads to drain current
. Therefore, the NFET device operates in the triode region since creates an reverse layer in the transistor.
Consider is further positive. Then, the mosfet device is replaced by a resistor as shown in Figure 4.8 (b) in the textbook. For
, mosfet devices and are turned ON, which tends to rise in drain current , , and peak voltage . For a sufficient
high value of , the voltage of mosfet drives beyond ; thus the device drives into the saturation region. If common-
mode input voltage is increased further, the mosfet devices and enter the deep triode region.
The plot for small-signal differential voltage gain versus drain-drain voltage is sketched as shown in Figure 1
Thus, the sketch for versus is drawn.

Question:
Construct the plots of Fig. 4.9(c) for a differential pair using PMOS transistors.
Figure 4.9 (a) Differential pair sensing an input common-mode change; (b) equivalent circuit if M3 operates
in the deep triode region; (c) common-mode input-output characteristics.
Step 1 Of 5
In Figure 4.8 (a), consider and vary the drain-drain voltage from 0 V to 3 V. Consider , as the mosfets
gate potential is less positive when compared to the source potential, both the mosfets and are OFF, which lead to drain
current . Therefore, the NFET device operates in the triode region.
Consider is further positive. Then, the mosfet device is replaced by a resistor as shown in Figure 4.8 (b) in the textbook. For
, mosfet devices and are turned ON, which tends to rise in drain current , , and peak voltage . For a sufficient
high value of , the voltage of mosfet drives beyond ; thus the device drives into the saturation region. If common-
mode input voltage is increased further, the mosfet devices and enter the deep triode region.
Step 2 Of 5
The sketch for , versus is drawn as shown in Figure 1.
In Figure 4.38 (a), the mosfets and turn on when . At is minimum, the magnitude of drain currents is . Consider
when (both devices allows the current flow due to gate voltage), the drain currents and is equal to the tail current . When
increasing the common-mode input voltage the tail current remains constant. When the mosfets and enter into triode region,
the drain currents gradually decreases and both the devices act as a resistor so that they stop the current flow. At the point of the
currents and reduces to the smallest values.
Step 3 Of 5
The sketch for versus is drawn as shown in Figure 2.
The voltage at the node P initially exists at and increases linearly for till it reaches to at the point of
varied to . The voltage remains constant for further increase in . Thus, is equal to at , and gets
saturated at the voltage level of for all in the region of .
Step 4 Of 5

Step 5 Of 5
In Figure 4.8(a), consider the expression for using ohms law.
Substitute for .
The value of exists at . When increasing the common-mode input voltage the output voltage remains constant for small
increment in saturation region. As drop to its smallest value when themosfets and enter into the triode region, the output voltage
gradually decreases. By further increasing , the mosfets and turns off and the output voltage is zero.
Thus, the plots for , , versus are drawn.

Question:
In the circuit of Fig. 4.11, (W/L)1,2 = 50/0.5 and ISS = 0.5 mA.
(a) What is the maximum allowable output voltage swing if Vin,CM = 1.2 V?
(b) What is the voltage gain under this condition?

Figure 4.11 Maximum allowable output swings in a differential pair.
Step 1 Of 6
Consider the expression for maximum output voltage in a differential pair.
…… (1)
Here, is the drain voltage.

Consider the expression for minimum output voltage in a differential pair.
…… (2)
Here, is the common-mode input voltage and is the threshold voltage which is 0.7 V.
Step 2 Of 6
(a)
Substitute 3 V for in equation (1).
Consider the expression of the maximum allowable swing at the output voltage.

Thus, the maximum allowable output voltage swing is .
Step 3 Of 6
(b)
Consider the expression for voltage gain.
…… (3)
Here, is the transconductance and is the drain resistance.

Consider the expression for transconductance.
…… (4)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, is the drain current, W is the gate width and L is the gate
length.
Consider the general expression for drain current.
Here, is the tail current.
Substitute 0.5 mA for .
Step 4 Of 6
…… (5)
Here, is the permittivity of the oxide which is and is the gate oxide thickness.
…… (6)
Refer to Table 2.1 (NMOS) in the textbook for the term .
Refer to Table 2.1 (NMOS) in the textbook for the term .

Step 5 Of 6
Consider the expression to find the drain resistance.
Substitute 3 V for , 0.5 V for and for .
Step 6 Of 6
Thus, the voltage gain is .

Question:
A differential pair uses input NMOS devices with W/L = 50/0.5 and a tail current of 1 mA.
(a) What is the equilibrium overdrive voltage of each transistor?
(b) How is the tail current shared between the two sides if Vin1 − Vin2 = 50 mA?
(c) What is the equivalent Gm under this condition?
(d) For what value of Vin1 − Vin2 does the Gm drop by 10%? By 90%?
Step 1 Of 11
(a)
Consider the expression for equilibrium over drive voltage of a transistor
…… (1)
Here, is the drain current, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width and L is the gate
length.
Substitute 1 mA for in equation.
Step 2 Of 11
…… (2)
Refer to Table 2.1 (NMOS) in the textbook for the term , which is .
Step 3 Of 11
Substitute for , for , 0.5 mA for and for in equation (1).
Thus, the equilibrium overdrive voltage of each transistor is .
Step 4 Of 11
(b)
Consider the general expression for difference between drain current.
Substitute for , for , for , 1 mA for and 50 mV for in equation.

Step 5 Of 11
Consider the expression to find .
Substitute 0.5 mA for and for in equation.
Substitute 0.5 mA for and for in equation.
Thus, the tail current shared between the two sides are and .
Step 6 Of 11
(c)
Consider expression of voltage difference,
Consider the general expression for equivalent .
…… (3)
Substitute for , for , for , 1 mA for and 50 mV for in equation (3).
Simplify further.
Simplify the value.

Thus, the value of equivalent is .
Step 7 Of 11
(d)
Consider, , equation (3) becomes,
Substitute for , for , for and 1 mA for in equation.
Step 8 Of 11
Rearrange equation (3).
Square both sides of equation.
…… (4)
Consider the expression from equation (4).
…… (5)
…… (6)
Modify equation (4).
Consider the small value. Therefore,
…… (7)
Step 9 Of 11
Find the value of drop by 10%.
Substitute for , for , for and for in equation.

Substitute 1 mA for , for , for and for in equation (5).
Step 10 Of 11
Substitute for A and for B in equation (7).

Step 11 Of 11
Thus, the drop by , when the value of is equal to and the drop by , when the value of is equal to
.
Question:
Repeat Problem 4.5 with W/L = 25/0.5 and compare the results.
Step 1 Of 0
Question:
Repeat Problem 4.5 with a tail current of 2 mA and compare the results.
Step 1 Of 12
(a)
Consider the expression for equilibrium over drive voltage of a transistor
…… (1)
length.
Substitute 2 mA for .
Step 2 Of 12
Substitute for .
…… (2)
Step 3 Of 12
Substitute for , for , 1 mA for and for in equation (1).
Thus, the equilibrium overdrive voltage of each transistor is .
Step 4 Of 12
(b)
Consider the expression for difference between drain current.
Substitute for , for , for , 2 mA for and 50 mV for .
Step 5 Of 12
Simplify the expression.
Step 6 Of 12
Substitute 1 mA for and 0.258 mA for .
Substitute 1 mA for and 0.258 mA for .
Thus, the tail current shared between the two sides are and , respectively.
Step 7 Of 12
(c)
Consider the voltage difference,
Consider the general expression for equivalent .

…… (3)
Substitute for , for , for , 2 mA for and 50 mV for in equation (3).
Thus, the value of equivalent is .

Step 8 Of 12
(d)
Consider, , equation (3) becomes,
Substitute for , for , for and 2 mA for .
Step 9 Of 12
Square both sides of equation.
…… (4)
In equation (4), consider,
…… (5)
…… (6)
Consider the small value. Therefore,
…… (7)
Step 10 Of 12
Substitute for .

Substitute 2 mA for , for , for and for in equation (5).
Step 11 Of 12
Substitute for .
Step 12 Of 12

In this case, overdrive voltage and is increased, but the linearity range of is same as the transconductance value for .
Thus, for a value of the drop by and for a value of the drop by .
Question:
Sketch ID1 and ID2 in Fig. 4.19 versus Vin1 − Vin2. For what value of Vin1 − Vin2 are the two currents
equal?
Figure 4.19
Step 1 Of 5
Refer Figure 4.17 in the textbook.
Consider the expression for drain current .
…… (1)
Here, is the threshold voltage for NMOS, which is 0.7 V, is the mobility of electrons, is the gate oxide capacitance per unit area, W
is the gate width, L is the gate length, and is the input voltage for NFET .
…… (2)
Here, is the input voltage for NFET .
Consider the expression for tail current .
…… (3)
Here, are the drain currents.
Step 2 Of 5
Consider .

Step 3 Of 5
…… (4)
…… (5)
Step 4 Of 5
Subtract equation (1) from equation (2) to find the value of in which the two drain currents are equal.
Step 5 Of 5
The plot for drain currents and versus the input voltage is sketched as shown in Figure 1.
Consider varies from to . If input voltage is more negative than , the NFET is off and NFET is on and the
drain current is equal to the tail current . If input voltage is brought near to , the NFET slowly turns on and draws a fraction
of tail current from the drain resistance , thereby lowering . As , the drain current of NFET decreases.
The two MOSFETs are asymmetric differential pair devices. The variation of drain currents for the differential input is shown at
different points. At the point , the relationship between drain current and with tail current is and .
Thus, when the two drain currents are equal, the value of is .
Question:
Consider the circuit of Fig. 4.32, assuming (W/L)1,2 = 50/0.5 and RD = 2 kΩ. Suppose RSS represents the
output impedance of an NMOS current source with (W/L)SS = 50/0.5 and a drain current of 1 mA. The
input signal consists of Vin,DM = 10 mVpp and Vin,CM = 1.5 V + Vn(t), where Vn(t) denotes noise with a peak-
to-peak amplitude of 100 mV. Assume that ∆R/R = 0.5%.
(a) Calculate the output differential signal-to-noise ratio, defined as the signal amplitude divided by
the noise amplitude.
(b) Calculate the CMRR.
Figure 4.32 Effect of CM noise in the presence of resistor mismatch.
Step 1 Of 5
Refer to Figure 4.28 in the textbook shows the effect of CM noise in the presence of resistor mismatch.
Consider the expression for differential-mode to differential-mode conversion.
…… (1)

Consider the expression for common-mode to differential-mode conversion.
…… (2)
Here, is the tail resistance and is the difference between drain resistance.
Step 2 Of 5
Consider the general expression for signal-to-noise ratio.
Here, is the common-mode input voltage and is the differential-mode input voltage.
…… (3)
Step 3 Of 5
…… (4)
length.
Refer to Table 2.1 in the textbook for the term , which is and for the term , which is .
…… (5)
…… (6)

Here, is bias current.
Step 4 Of 5
Consider the expression for tail resistance.
Here, is lambda for NMOS, which is 0.1.
Substitute 0.1 for and for .
Substitute for , 0.05 for and for in equation (3).
Convert the value of SNR to decibel.
Thus, the output differential signal-to-noise ratio is .
Step 5 Of 5
Consider the expression for common-mode rejection ratio.
Substitute for , 0.05 for and for .
Convert the value of CMRR to decibel.
Thus, the value of CMRR is .

Question:
Repeat Problem 4.9 if ∆R = 0, but M1 and M2 suffer from a threshold voltage mismatch of 1 mV.
Consider the circuit of Fig. 4.32, assuming (W/L)1,2 = 50/0.5 and RD = 2 kΩ. Suppose RSS represents the
output impedance of an NMOS current source with (W/L)SS = 50/0.5 and a drain current of 1 mA. The
input signal consists of Vin,DM = 10 mVpp and Vin,CM = 1.5 V + Vn(t), where Vn(t) denotes noise with a peak-
to-peak amplitude of 100 mV. Assume that ∆R/R = 0.5%.
(a) Calculate the output differential signal-to-noise ratio, defined as the signal amplitude divided by
the noise amplitude.
(b) Calculate the CMRR.
Figure 4.32 Effect of CM noise in the presence of resistor mismatch.
Step 1 Of 9
Refer to Figure 4.28 in the textbook shows the effect of CM noise in the presence of resistor mismatch.
Consider the general expression for differential-mode to differential-mode conversion.
…… (1)

Consider the general expression for common-mode to differential-mode conversion.
…… (2)
Here, is the tail resistance and is the change in drain resistance.
Step 2 Of 9
Consider the general expression for signal-to-noise ratio.
Here, is the common-mode input voltage and is the differential-mode input voltage.
…… (3)
Step 3 Of 9
Consider the general expression for transconductance.
…… (4)
Here, is the gate source voltage, is the threshold voltage, mobility of electrons, is the gate oxide capacitance per unit area, W is
the gate width and L is the gate length.
From equation (4), change in transconductance is,
…… (5)
Here, is the threshold voltage.
Step 4 Of 9
…… (6)
…… (7)

Step 5 Of 9
Here, is the bias current.
Step 6 Of 9
Step 7 Of 9
Consider the general expression for tail resistance.
Here, is lambda for NMOS, which is 0.1.
Substitute 0.1 for and for in equation.

Convert the value of SNR to decibel.
Thus, the output differential signal-to-noise ratio is .
Step 8 Of 9
Consider the general expression for common-mode rejection ratio.
Substitute for and for in equation.
Step 9 Of 9
Substitute for , for and for in equation.

Question:
Suppose the differential pair of Fig. 4.37(a) is designed with (W/L)1,2 = 50/0.5, (W/L)3,4 = 10/0.5, and ISS =
0.5 mA. Also, ISS is implemented with an NMOS device having (W/L)SS = 50/0.5.
(a) What are the minimum and maximum allowable input CM levels if the differential swings at the
input and output are small?
(b) For Vin,CM = 1.2 V, sketch the small-signal differential voltage gain as VDD goes from 0 to 3 V.
Figure 4.37 Differential pair with (a) diode-connected and (b) current-source loads.
Step 1 Of 8
(a)
Consider the expression for output differential voltage.
…… (1)
Here, is the gate source voltage, is the threshold voltage, is the mobility of electrons, is the gate oxide capacitance per unit area,
W is the gate width and L is the gate length.
…… (2)
Refer to Table 2.1 (NMOS) in the textbook for the term , which is , for the term , which is and for the term
, which is .
Substitute for and for in Equation (2).

Step 2 Of 8
Step 3 Of 8
Consider the expression for drain current.
Substitute 0.5 mA for in equation.
Consider the expression for output differential voltage of NFET transistor .

Step 4 Of 8
Consider the expression for common-mode minimum input voltage.
…… (3)
Consider the expression for gate-source voltage .
Here, is the threshold voltage for NMOS, which is 0.7 V.
Substitute 0.7 V for , 0.193 V for and 0.273 V for .
Step 5 Of 8
Consider the expression for common-mode maximum input voltage.
…… (4)
Consider the expression for gate-source voltage of PFET transistor .
Here, is the threshold voltage for PMOS, which is 0.8 V.
Substitute 0.8 V for , for , for , for and for .

Substitute 1.61 V for , 0.7 V for and 3 V for in equation (4).
Thus, the minimum allowable input CM level is and the maximum allowable input CM level is .
Step 6 Of 8
(b)
Consider the expression for drain-drain voltage.
Substitute 1.2 V for , 161 V for and 0.7 V for in equation.
Step 7 Of 8
Consider the expression for the small-signal differential voltage gain.

Step 8 Of 8
The plot for small-signal differential voltage gain versus drain-drain voltage is sketched as shown in Figure 1.
From Figure 1, the transistor and enters into saturation at 2.11 V voltage of .
Thus, the sketch for versus is drawn.

Question:
In Problem 4.11, suppose M1 and M2 have a threshold voltage mismatch of 1 mV. What is the CMRR?
Step 1 Of 6
Refer to Figure 4.32(a) in the textbook shows the differential pair with diode-connected.
In Figure 4.32(a), due to the threshold voltage mismatch of NFET and causes an unequal drain currents of and . As a result, the
transconductance and , and the transconductance and is not equal. That is,
The modified equivalent circuit of Figure 4.32 (a) is drawn as shown in Figure 1.
Step 2 Of 6
Refer to Figure 1.
Consider the expression for drain current in Figure 1.

Here, is the transconductance, is the common-mode input voltage and is the peak voltage.
Consider the expression for drain current in Figure 1.
Consider the expression for output voltage .
Substitute for .
Substitute for .
Step 3 Of 6
In Figure 1, using half circuit concept consider the MOSFET and .

Consider the expression for small-signal differential gain.
…… (1)
Consider the expression for transconductance of transistor .
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width and L is the gate length.
Consider the expression for transconductance of transistor .
Here, is the mobility of electrons.

Step 4 Of 6
…… (2)
Consider the drain current in Figure 1. Assume the devices are identical in dimensions, and are identical in
dimensions.
Step 5 Of 6
In Figure 1, using half circuit concept consider the MOSFET and .

Consider the expression for small-signal differential gain.
…… (3)
Consider the expression for transconductance .

…… (4)
Consider the drain current in Figure 1.
Thus, the small signal differential gain for both half circuits is same.
Step 6 Of 6
…… (5)
Here, is the differential-mode gain and is the common-mode to differential-mode gain.
For an ideal differential amplifier the common-mode to differential-mode gain is zero, for the condition . That is .
Thus, the common-mode rejection ratio is infinity.

Question:
In Problem 4.11, suppose W3 = 10 μm, but W4 = 11 μm. Calculate the CMRR.
Step 1 Of 9
Refer to Figure 4.32(a) in the textbook shows differential pair with diode connected.
…… (1)

…… (2)
Here, is the tail resistance and is the difference between drain resistances.
…… (3)
length.
Step 2 Of 9
Substitute for .

Step 3 Of 9
Step 4 Of 9
Step 5 Of 9
Consider the expression for tail resistance.
Here, is lambda for PMOS, which is 0.2.
Substitute 0.2 for and for .
Step 6 Of 9

…… (4)
Step 7 Of 9
Consider the expression for drain resistances.
Here, and is the transconductances.
…… (5)
Consider the expression for transconductances.
Step 8 Of 9
Step 9 Of 9
Substitute for , 0.0465 for and for in equation (4).

Question:
For the differential pairs of Fig. 4.37(a) and (b), calculate the differential voltage gain if ISS = 1 mA, (W/L)1,2
= 50/0.5, and (W/L)3,4 = 50/1. What is the minimum allowable input CM level if ISS requires at least 0.4 V
across it? Using this value for Vin,CM, calculate the maximum output voltage swing in each case.
Step 1 Of 10
Refer to Figure 4.32 (a) in the textbook shows the differential pair with diode-connected.
Consider the expression to find the small-signal differential gain.
…… (1)
…… (2)
Here, is the transconductance for NMOS, is the transconductance for PMOS, is the mobility of electrons, is the gate
width and gate length for NMOS and is the gate width and gate length for PMOS.
Step 2 Of 10

Thus, the differential voltage gain for Figure 4.32 (a) is .
Step 3 Of 10
Refer to Figure 4.32 (b) in the textbook shows the differential pair with current source loads.
Consider the expression to find the small-signal differential gain.
…… (3)
Here, is the on-resistance and is the output resistance at the operating point.
Step 4 Of 10
Consider the expression of transconductance for NMOS.
…… (4)
Here, is the Drain current, mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width and L is the gate
length.
Substitute for .
Step 5 Of 10
Step 6 Of 10
Refer to Table 2.1 in the textbook for the term , which is for NMOS and for the term , which is for PMOS.
For , tends to .
Consider the expression for on-resistance.
Here, is lambda for NMOS.
For length , the channel-length modulation coefficient tends to . Therefore, the channel-length modulation coefficient
will be half for .
That is,
Consider the expression for output resistance at the operating point.
Here, is lambda for PMOS.

Thus, the differential voltage gain for Figure 4.32 (b) is .
Step 7 Of 10
Consider, the tail current needs a minimum of 0.4 V across it.

Consider the expression for minimum allowable input voltage for both the circuits.
…… (5)
Here, is the gate source voltage.
Consider the expression for gate-source voltage of .
Here, is the threshold voltage, which is 0.7 V for NMOS.
Substitute 0.7 V for , for , for , for and for .

Thus, for minimum allowable input voltage for both the circuits is .
Step 8 Of 10
Consider the expression to find the maximum output voltage swing.
Here, is the drain-drain voltage, which is 3 V and is the threshold voltage for PMOS, which is .
Substitute 3 V for and for .
Consider the expression for the minimum output voltage swing if mosfet enters the triode region.
Here, is the threshold voltage for NMOS, which is 0.7 V and 0.97 V for .
Step 9 Of 10
Consider the expression for the minimum output voltage swing if all the tail current enters through moseft .
…… (6)
Consider the expression for gate-source voltage.
Substitute 3 V for , for , for , for , for and for .

Consider the expression for the maximum output voltage swing.
Substitute for , and 1.18 V for .
The maximum output voltage swing is,
Thus, the maximum output voltage swing for Figure 4.32 (a) is .
Step 10 Of 10
…… (7)
Consider the expression for gate-source voltage.

Substitute 3 V for , for and for in equation (7).
The maximum output voltage swing is,
Thus, the maximum output voltage swing for Figure 4.32 (b) is .
Question:
In the circuit of Fig. 4.39(a), assume that ISS = 1 mA and W/L = 50/0.5 for all the transistors.
(a) Determine the voltage gain.
(b) Calculate Vb such that ID5 = ID6 = 0.8(ISS/2).
(c) If ISS requires a minimum voltage of 0.4 V, what is the maximum differential output swing?
Figure 4.39 Addition of current sources to increase the voltage gain with (a) diode-connected loads and (b)
resistive loads.
Step 1 Of 12
a.
Refer to Figure 4.33 in the textbook, shows the addition of current sources to increase the voltage gain.
The Figure 4.33 illustrates the idea to lower the of the load devices by reducing their current rather than their aspect ratio as shown in Figure 1.
Step 2 Of 12
…… (1)
Here, is the transconductance and is the output resistance of transistor.
Express and in terms of device dimensions. Therefore, equation (1) will be,
…… (2)
Here, is the mobility of electron.
Step 3 Of 12
Refer to Table 2.1 in the textbook for the term , which is and the term , which is .
Substitute 1 mA for , for and for in equation (2).
Step 4 Of 12
b.
The drain current is,

Consider the expression to find the gate-source voltage .
Here, is the drain voltage and is the bias voltage.
Step 5 Of 12
…… (3)
Here, is the threshold voltage for PMOS, which is , is the drain current, is the gate oxide capacitance per unit area, W is the
gate width, and L is the gate length.
Step 6 Of 12
…… (4)
…… (5)
Refer to Table 2.1 in the textbook for the term , which is .
Step 7 Of 12
Substitute for , 3 V for , 0.8 V for , for , for and for in equation
(3).
Thus, the base bias voltage is .
Step 8 Of 12
c.
Consider the expression for maximum output voltage in a differential pair.
Substitute 1.74 V for , 3 V for and 0.8 V for in equation.
Step 9 Of 12
Consider the general expression for minimum output voltage in a differential pair.
…… (6)
Here, is the threshold voltage for NMOS, which is 0.7 V.
Consider the expression to find the gate source voltage .
Step 10 Of 12

Step 11 Of 12
Consider the expression to find the gate source voltage .
Substitute 0.8 V for , for , for , for and for in equation.
Step 12 Of 12
Substitute 1.12 V for , for , 0.4 V for and 3 V for in equation (6).
Consider the expression of maximum differential output swing.

Substitute 2.2 V for and 1.88 V for in equation.
Thus, the maximum differential output swing is .

Question:
Assuming that all the circuits shown in Fig. 4.44 are symmetric, sketch Vout as (a) Vin1 and Vin2 vary
differentially from zero to VDD, and (b) Vin1 and Vin2 are equal and vary from zero to VDD.
Figure 4.44
Step 1 Of 13
Refer to Figure 4.38 (a) in the textbook:
(a)
In Figure 4.38 (a), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
and enter into the deep triode region, and the output voltage gradually decreases till it reaches the minimum voltage level at the point
of and remains constant for a further increase in .

Step 2 Of 13
(b)
The value of exists at . When increasing the input voltage , the output voltage remains constant for small increment in the
saturation region. When and enter into the triode region, the output voltage gradually decreases. The output voltage is equal to
at , and gets saturated at the voltage level of for all in the region of
.
Thus, the plots for versus and versus are sketched as shown in Figures 1 and 2.
Step 3 Of 13
Refer to Figure 4.38(b) in the textbook:
(a)
In Figure 4.38(b), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
and enter into the deep triode region, and the output voltage gradually decreases till it reaches the minimum voltage level and remains
constant for a further increase in .
Step 4 Of 13
(b)
The value of exists at and remains constant till reaches the threshold voltage . For the further increase in the input voltage ,
the mosfet device and enter into the triode region.
Step 5 Of 13
Therefore, the output voltage gradually decreases till it reaches the minimum voltage level at the point of and remains
constant for all in the region of

Step 6 Of 13
Refer to Figure 4.38(c) in the textbook:
(a)
In Figure 4.38(c), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
Step 7 Of 13
(b)
the mosfet devices and enter into the triode region. Therefore, the output voltage gradually decreases till it reaches the minimum
voltage level at the point of and remains constant for all in the region of
Step 8 Of 13
Refer to Figure 4.38(d) in the textbook:
(a)
In Figure 4.38 (d), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
and enter into the deep triode region, and the output voltage gradually decreases till it reaches the minimum voltage level at the point of
and remains constant for a further increase in .
Step 9 Of 13

Step 10 Of 13
(b)
The value of exists at . When increasing the input voltage , the output voltage remains constant for small increment in the
saturation region. When and enter into the triode region, the output voltage gradually decrease. The output voltage is equal to
at , and gets saturated at the voltage level of for all in the region of
.
Step 11 Of 13
Refer to Figure 4.38(e) in the textbook.
(a)
In Figure 4.38 (e), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
and enter into the deep triode region, and the output voltage linearly decreases till it reaches the minimum voltage level at the point of
and remains constant for a further increase in .
Step 12 Of 13
(b)
the mosfet and enters into the triode region. Therefore, the output voltage gradually decreases till it reaches the minimum voltage
level at the point of and remains constant for all in the region of
Step 13 Of 13

Question:
Assuming that all the circuits shown in Fig. 4.45 are symmetric, sketch Vout as (a) Vin1 and Vin2 vary
differentially from zero to VDD, and (b) Vin1 and Vin2 are equal and vary from zero to VDD.
Figure 4.45
Step 1 Of 6
Refer to Figure 4.39(a) in the textbook:
(a)
In Figure 4.39 (a), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
and enter into the deep triode region, and the output voltage gradually decreases till it reaches the minimum voltage level at the point
of and remains constant for further increase in .

Step 2 Of 6
(b)
The value of exists at the level of for all smallest values of and remains constant till the inputs of both devices reach the threshold
voltage . By the further increase in input voltage (increase in inputs ), the output voltage gradually decreases till it reaches the
minimum voltage level at the point of and remains constant for a further increase in .
Step 3 Of 6
(a)
In Figure 4.38 (b), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
Step 4 Of 6
(b)
The mosfets and turn ON when . When increasing the input voltage , the output voltage exists at
and remains constant. When the mosfet devices and enter into the triode region, the output voltage
gradually decreases till it reaches to minimum voltage level of at the point when is equal to . That is output voltage is
equal to at , and gets saturated at the voltage level of for all in the region of
.
Thus, the plots for versus and versus is sketched as shown in Figures 3 and 4.
Step 5 Of 6
Refer to Figure 4.39(c) in the textbook:
(a)
In Figure 4.38 (c), for , the mosfet devices and are turned ON. If the input voltage is increased further, the mosfet devices
constant for further increase in .
Step 6 Of 6
(b)
The value of exists at for the smallest range of . When increasing the input voltage , the output voltage remains constant
for small increment in the saturation region. When and enter into the triode region, the output voltage gradually decrease. The
output voltage is equal to at , and gets saturated at the voltage level of for all in the
range of all .
Question:
Assuming that all the transistors in the circuits of Figs. 4.44 and 4.45 are saturated and λ ≠ 0, calculate the
small-signal differential voltage gain of each circuit.
Figure 4.44
Figure 4.45
Step 1 Of 15
Refer to Figure 4.38(a) in the textbook.
The simplified circuit of the first stage in Figure 4.38(a) is drawn as shown in Figure 1.
Consider the input voltage of the differential input as . Here, the differential input voltage that is .
In Figure 1, consider the expression for the small-signal differential voltage gain.
Thus, the small-signal differential voltage gain is .

Step 2 Of 15
Refer to Figure 4.38(b) in the textbook.
The simplified circuit of the first stage in Figure 4.38(b) is drawn as shown in Figure 2.
In Figure 2, consider the expression for small-signal differential voltage gain.
Step 3 Of 15
Refer to Figure 4.38(c) in the textbook.
The simplified circuit of first stage of the mirror circuit in Figure 4.38(c) is drawn as shown in Figure 3.

Step 4 Of 15
Refer to Figure 4.38(d) in the textbook.
The simplified circuit of first stage of the mirror circuit of Figure 4.38(d) is drawn as shown in Figure 4.
Step 5 Of 15
Step 6 Of 15
Refer to Figure 4.38(e) in the textbook.
The simplified circuit of first stage of the mirror circuit of Figure 4.38(e) is drawn as shown in Figure 5.
Figure 6 shows a modified small-signal equivalent circuit.

Step 7 Of 15
…… (1)
…… (2)
Step 8 Of 15
Modify equation (1) as shown.
Substitute for .
Step 9 Of 15

Where .
The small-signal differential voltage gain of circuit is,
Step 10 Of 15
The simplified circuit of first stage of the mirror circuit of Figure 4.39(a) is drawn as shown in Figure 7.
Step 11 Of 15
Step 12 Of 15
The simplified circuit of first stage of the mirror circuit of Figure 4.39(b) is drawn as shown in Figure 8.
Thus, the small-signal differential voltage gain is
.
Step 13 Of 15
Figure 4.39(c) is modified as shown in Figure 9.
Consider the output resistance and are neglected in the circuit.
Consider the expression for current at node and .
Adding both the equations,
…… (3)
In Figure 9, consider the expression for voltage .
Step 14 Of 15
The simplified circuit of the first stage of mirror circuit of Figure 4.39(c) is drawn as shown in Figure 10.
In Figure 10, consider the expression for small-signal differential voltage gain of circuit.
Step 15 Of 15
If , then the circuit becomes unstable and the small-signal equivalent model is not valid.

Question:
Consider the circuit shown in Fig. 4.46.
(a) Sketch Vout as Vin1 and Vin2 vary differentially from zero to VDD.
(b) If λ = 0, obtain an expression for the voltage gain. What is the voltage gain if W3,4 = 0.8W5,6?
Figure 4.46
Step 1 Of 4
(a)
Refer to Figure 4.40 in the textbook. Assume the circuit is a fully symmetric differential amplifier and the differential input voltage as the
difference among the input voltages and . That is . The output voltage is varies depending on the tail current flow through
the device .
Consider varies from to . If is more negative than , the NFET is off and is on. If is brought near to ,
the NFET slowly turns on and draws a part of tail current . Hence, lowering since turn into more positive than and
drives large current than . So drops below .

Thus, the sketch for versus as and varies differentially is drawn.
Step 2 Of 4
(b)
The simplified equivalent circuit of Figure 4.40 is drawn as shown in Figure 2.

…… (1)
Step 3 Of 4
Here, is the gate source voltage, is the threshold voltage, is the mobility of electrons, is the gate oxide capacitance per unit area,
W is the gate width and L is the gate length.
Consider the expression for transconductance of PFET and .
Consider the expression for transconductance of PFET and .
Step 4 Of 4
Since the of PFET and is equal to of PFET and , then the transconductance is,
…… (2)
Consider the gate width,

Question:
For the circuit shown in Fig. 4.47,
(a) Sketch Vout, VX, and VY as Vin1 and Vin2 vary differentially from zero to VDD.
(b) Calculate the small-signal differential voltage gain.
Figure 4.47
Step 1 Of 3
(a)
Consider the circuit is a fully symmetric differential amplifier and the differential input voltage is the difference among the input voltages and
.
Consider the expression for differential input voltage.
The output voltage varies depending on the tail current flowing through the mosfet . Consider the voltage varies from to .
If the input voltage is more negative than the input voltage , then the NFET is off and is on. If is brought near to , the
NFET slowly turns on and draws a part of tail current. Hence, lowering since turn into more positive than and drives
large current than . So drops below .

Thus, the sketch for , , versus as and varies differentially is drawn.
Step 2 Of 3
(b)
The simplified equivalent circuit of Figure 4.41 is drawn as shown in Figure 3.
Here, is the differential input voltage in terms of and .
Step 3 Of 3
Thus, the small-signal differential voltage gainis .

Question:
Assuming no symmetry in the circuit of Fig. 4.48 and using no equivalent circuits, calculate the small-signal
voltage gain (Vout)/(Vin1 − Vin2) if λ = 0 and γ ≠ 0.
Figure 4.48
Step 1 Of 8
In Figure 4.42, apply superposition principle by short circuit the input voltage source and open circuit the tail current source . The
modified equivalent circuit with active input voltage source is drawn as shown in Figure 1.
Write the expression for gate transconductance of NFET when .
…… (1)
Here, is the current and is the input voltage.

The equivalent resistance in Figure 1.
Here, are the source resistances, is the gate transconductance and is the transconductance due to body effect.
Step 2 Of 8
In Figure 1, apply Kirchhoff’s voltage law to the circuit.
Substitute for .
Substitute for .
Step 3 Of 8
In Figure 4.42, apply superposition principle by short circuit the input voltage source and open circuit the tail current source . The modified
equivalent circuit with active input voltage source is drawn as shown in Figure 2.
Write the expression for gate transconductance of NFET when .
…… (2)
Here, is the current and is the input voltage.

The equivalent resistance in Figure 2.
Here, is the resistance, is the transconductance and is transconductance due to the body effect.
Step 4 Of 8
Substitute for .
Substitute for .
Step 5 Of 8
Figure 4.42 is modified and redrawn as shown in Figure 3
Step 6 Of 8
Refer to Figure 3.
Consider the expression for output current .
Consider the expression for output current .
…… (3)
Step 7 Of 8
…… (4)
Step 8 Of 8
Consider the expression for small-signal voltage gain.
Substitute for .
Thus, the small-signal voltage gain is,
.
Question:
Due to a manufacturing defect, a large parasitic resistance has appeared between the drain and source
terminals of M1 in Fig. 4.49. Assuming λ = γ = 0, calculate the small-signal gain, common-mode gain, and
CMRR.
Figure 4.49
Step 1 Of 19
The modified equivalent circuit of Figure 4.43 is shown in Figure 1.
In Figure 1, consider the transconductance , backgate transconductance and output resistance as shown.
Step 2 Of 19
…… (1)
…… (2)
In Figure 1, apply Kirchhoff’s current law to the closed loop of the circuit.
Step 3 Of 19
Consider the expression for output difference voltage of the circuit.
…… (3)
Consider the expression for common-mode output voltage of the circuit.
…… (4)
…… (5)
…… (6)
Add equation (5) and (6).
Step 4 Of 19
…… (7)
…… (8)
Step 5 Of 19
Add equation (7) and (8).

Step 6 Of 19
Step 7 Of 19
Step 8 Of 19
Step 9 Of 19
Modify the equation in terms of .
…… (9)
Step 10 Of 19

Step 11 Of 19
Modify the equation in terms of .
…… (10)
Step 12 Of 19
Consider if .
…… (11)
Step 13 Of 19
In Figure 1, apply Kirchhoff’s voltage law to the closed loop of the circuit.
…… (12)
Consider the expression for output voltage of the circuit.
…… (13)
Step 14 Of 19
Substitute for .
Step 15 Of 19
Consider the expression for input voltage .
Step 16 Of 19
Substitute for .
The equation is modified as shown.
…… (14)
Step 17 Of 19
Consider the expression for small-signal gain of the circuit.
…… (15)
Consider the expression for differential input voltage
…… (16)
Substitute equation (9) and (10) in equation (16) as follows:
…… (17)
Substitute equation (14) and (17) in equation (15) as follows:
Step 18 Of 19
Consider the expression for common-mode gain of the circuit.
Consider the expression for differential-mode gain of the circuit.
Step 19 Of 19
Thus, the small-signal gain is
,
common-mode gain is and common-mode rejection ratio is .
Question:
Due to a manufacturing defect, a large parasitic resistance has appeared between the drains of M1 and M4
in the circuit of Fig. 4.50. Assuming λ = γ = 0, calculate the small-signal gain, common-mode gain, and
CMRR.
Figure 4.50
Step 1 Of 7
Consider in the circuit.
As , therefore for a differential input, symmetry in the input is large enough to the tail node to be ground.
Figure 1 shows a grounded tail node with tail resistance .
…… (1)
In Figure 4.44, consider the transconductance , since but the transconductance is not equal to .

Step 2 Of 7
Figure 4.44 is modified as shown in Figure 2.
Substitute for .
…… (2)
Substitute for .
…… (3)
Step 3 Of 7
…… (4)
In Figure 2, consider the expression for current in the circuit.
Step 4 Of 7
Substitute for I.
From equation (2),
Substitute for .
Substitute for .
Step 5 Of 7
Consider the expression for small-signal gain.
Substitute for .
Substitute for .
Step 6 Of 7
Substitute 0 for .
As , the common-mode gain is zero. That is, .
Step 7 Of 7
Consider the expression for common-mode rejection ration.
Thus, the small-signal gain is , common-mode gain is and the common-mode rejection ratio is
.
Question:
In the circuit of Fig. 4.51, all of the transistors have a W/L of 50/0.5, and M3 and M4 are to operate in the
deep triode region with an on-resistance of 2 kΩ. Assuming that ID5 = 20 μA and λ = γ = 0, calculate the
input common-mode level that yields such resistance. Sketch Vout1 and Vout2 as Vin1 and Vin2 vary
differentially from 0 to VDD.
Figure 4.51
Step 1 Of 7
Consider the expression for drain current in saturation region.
Here, is the drain current, mobility of electrons, is lambda, is the gate oxide capacitance per unit area, W is the gate width, L is the
gate length, is the threshold voltage, is the gate-source voltage and is the drain-source voltage.
Substitute 0 for .
…… (1)
Consider the expression for on-resistance.
…… (2)
Step 2 Of 7
Refer to Table 2.1 in the textbook for the term , which is , for the
term , which is and for the term , which is .
Substitute for .
The equation becomes,
Substitute V for .
Step 3 Of 7
In Figure 4.45, consider the tail current,

Here, tail current is .
Substitute for .
Substitute 0.7 V for , for , for , for , for , for .
Step 4 Of 7
Consider the expression to find the drain-drain voltage .
Here, , is the gate-source voltage and is the common-mode input voltage.

Substitute 3 V for , 13.83 V for and 0.739 V for .
Consider the expression to find the drain-source voltage .
Consider the condition for the PMOS devices and to enter into the triode region.
Step 5 Of 7
Consider the expression for drain voltage .
Consider the expression to find the difference in voltage between the drain voltage and gate voltage.
Step 6 Of 7
In Figure 4.45, consider the common-mode input voltage is the gate voltage . Therefore, the equation becomes,
Substitute 2.98 V for and for .
Consider the condition for the NMOS devices and to enter into the saturation mode.

Step 7 Of 7
Thus, the input common-mode level is and the plot for and for the differential varying from 0 to is
drawn as shown in Figure 1.
Question:
In the circuit of Fig. 4.37(b), (W/L)1−4 = 50/0.5 and ISS = 1 mA.
(a) What is the small-signal differential gain?
(b) For Vin,CM = 1.5 V, what is the maximum allowable output voltage swing?
Step 1 Of 10
a.
Consider the general expression for small signal differential gain.
…… (1)
Here, is the Transconductance and is the small-signal output resistance of transistor.

Here, is the Tail current.
Step 2 Of 10
For NMOS device:
Consider the general expression for the transconductance .
…… (2)
Here, is the drain current, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width, and L is the gate
length.
…… (3)
…… (4)
Step 3 Of 10
Substitute for , for , for and for in equation (2) to find the
transconductance .
Step 4 Of 10
For NMOS device:
…… (5)
Step 5 Of 10
Step 6 Of 10
For PMOS device:
…… (6)
Step 7 Of 10
Thus, the small-signal differential gain is .
Step 8 Of 10
b.
Consider the general expression for minimum output voltage in a differential pair.
Here, is the common-mode input voltage and is the threshold voltage, which is 0.7 V.
Consider the general expression for maximum output voltage in a differential pair.
…… (7)
Here, is the drain voltage.
Step 9 Of 10
Refer to Table 2.1 in the textbook for the term , which is and the term , which is .
From Part (a), .
Substitute 3 V for , for , for , for and for in equation (7).
Step 10 Of 10
The maximum allowable swing at the output voltage is,

Question:
In the circuit of Fig. 4.39, assume that M5 and M6 have a small threshold voltage mismatch of ∆V and ISS
has an output impedance RSS. Calculate the CMRR.
Figure 4.39 Addition of current sources to increase the voltage gain with (a) diode-connected loads and (b)
resistive loads.
Step 1 Of 8
…… (1)

…… (2)
Here, is the tail resistance and is the difference between drain resistances.
Step 2 Of 8
Consider the expression for drain resistance.
Here, are the output resistances.

…… (3)

From equation (3), the change in drain current is,
Step 3 Of 8
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, is the gate-
source voltage and is the threshold voltage.
Differentiate the equation with respect to as follows:
Here, is the drain-drain voltage and is the base voltage.
Consider the expression for change in drain current .
…… (4)
Step 4 Of 8
Consider the general expression for transconductance.
Differentiate the equation with respect to .

Step 5 Of 8
Therefore,
…… (5)
Step 6 Of 8
Consider the expression for drain resistance.
Differentiate the equation with respect to .
Substitute for .
Therefore,
Substitute for .
Step 7 Of 8
Substitute for .
Substitute for .
Substitute for .
…… (6)
Consider the MOSFET and carry of the drain current of MOSFET and
, the current through it is reduced by a factor of five. Therefore, the current gain is,
Step 8 Of 8
Substitute for .
Thus, the common-mode rejection ratio is .
Question:
What happens if RSS in Eq. (4.56) becomes very large? Can we obtain the same result by analyzing a
differential pair having an ideal tail current source but gm1 ≠ gm2?
Step 1 Of 0
Question:
In Example 4.5, how much input dc imbalance can be tolerated if the small-signal gain must not drop by
more than 5%?
Example 4.5
Step 1 Of 0
Question:
In the lemma illustrated in Fig. 4.20, suppose channel-length modulation is not neglected. Assuming the two
devices are connected to two equal load resistors, explain intuitively why the lemma still holds.
Figure 4.20 Illustration of why node P is a virtual ground.
Step 1 Of 0
Question:
Does the lemma in Fig. 4.20 still hold if the devices have body effect? Explain.
Step 1 Of 0
Question:
Repeat Example 4.7 using Method I.
Example 4.7
Figure 4.23
Figure 4.22 Application of the half-circuit concept.
Step 1 Of 0
Question:
Prove the lemma illustrated in Fig. 4.20 if the tail current source is replaced by a resistor RT.
Step 1 Of 0
Question:
What happens to the plots on Fig. 4.13 as W/L increases? Determine the area under the Gm plot and use the
result to explain why the peak Gm must increase as W/L increases.
Figure 4.13 Variation of drain currents and overall transconductance of a differential pair versus input
voltage.
Step 1 Of 0
Question:
Assuming that I1 and ISS in Fig. 4.52 are ideal and λ, γ > 0, determine Vout1/Vin and Vout2/Vin.
Figure 4.52
Step 1 Of 0
Question:
In Problem 4.11, suppose M3 and M4 have a threshold voltage mismatch of 1 mV. Calculate the CMRR.
Step 1 Of 0
Question:
In Fig. 5.2, assume that (W/L)1 = 50/0.5, λ = 0, Iout = 0.5 mA, and M1 is saturated.
(a) Determine R2/R1.
(b) Calculate the sensitivity of Iout to VDD, defined as ∂ Iout/∂VDD and normalized to Iout.
(c) How much does Iout change if VTH changes by 50 mV?
(d) If the temperature dependence of μn is expressed as μn ∝ T−3/2 but VTH is independent of

temperature, how much does Iout vary if T changes from 300°K to 370°K?
(e) What is the worst-case change in Iout if VDD changes by 10%, VTH changes by 50 mV, and T
changes from 300°K to 370°K?
Figure 5.2 Definition of current by resistive divider.
Step 1 Of 15
(a)
Refer Table 2.1 in the textbook for the model parameters of NMOS and PMOS devices.
Consider the values for NMOS device.
Here, is the permittivity of free space and has the value of .
Substitute for .
Consider the expression for gate oxide capacitance per unit area .
Here, is the permittivity of the silicon oxide, and is the thickness of the oxide layer.
Substitute for , and for .
Step 2 Of 15
…… (1)
Here, is gate oxide capacitance per unit area, W is the width, L is the length, is the gate-to-source voltage, is the threshold voltage,
and is the mobility of NMOS.
Here, is the drain current, is the gate-to-source voltage, and is the threshold voltage.
…… (2)
Step 3 Of 15
Consider the expression for effective length .
Here, is the total length, and is the amount of side diffusion.
Refer to Fig. 5.2 in the textbook for MOSFET circuit.

Step 4 Of 15
Substitute for .
…… (3)
Step 5 Of 15
The drain current is same as the output current .
Substitute for .
Consider the value of as .

Modify equation (3) for effective length.
Substitute for , for , for W, for , for , for , and for .
Step 6 Of 15

Thus, the obtained value of is .
Step 7 Of 15
(b)
Consider the term is used to represent .
…… (4)
Modify equation (4) for effective length.
Substitute for .
Substitute for .
Substitute for .
…… (5)
Differentiate with respect to .

Step 8 Of 15
Divide by to find the sensitivity of to .
Step 9 Of 15
Substitute for .

Thus, the sensitivity of to is .
Step 10 Of 15
(c)
Differentiate equation (5) with respect to .
Substitute for .
Substitute for , for W, for , for , for , for , for , and

for .
Thus, the change in output current is
Step 11 Of 15
(d)
Consider the mobility is dependent upon temperature and is independent of temperature.
Step 12 Of 15
Modify equation (5) as dependent on temperature.
Differentiate with respect to

Step 13 Of 15
Substitute for .
Substitute for T, for , for , and for .
Thus, the change in as temperature vary is .
Step 14 Of 15
(e)
Modify equation (5) as dependent on temperature and worst-case change in with respect to , T, and .
Substitute for .
…… (6)
Find the value of .

Substitute for .
Substitute for , for W, for , for , for , for , for , for

, for , and for in equation (6).
Step 15 Of 15
Find the worst case change in .
Thus, the worst case change in is .

Question:
Consider the circuit of Fig. 5.7. Assuming IREF is ideal, sketch Iout versus VDD as VDD varies from 0 to 3 V.
Figure 5.7
Step 1 Of 2
Refer to Figure 5.6 in the textbook for the circuit.
Consider that the reference current is ideal.
Refer to Figure 5.6; the output current until the supply voltage is equal to the threshold voltages . For the supply
voltage , the MOSFETS are off, MOSFET is in the triode region, and MOSFET is on. When the supply voltage
reaches the threshold voltage of and , a small amount of current starts to flow to the output, but very it is a very small
current until the MOSFET is in the saturation mode.
Consider the expression for the gate-to-source voltage of MOSFET 3 .
Here,
is the reference current, is threshold voltage, is the constant parameter, and is the ratio of width to length in MOSFET.
At , the output current increases and is approximately equal to the reference current .
Step 2 Of 2
At , the output current is exatly equal to the reference current . The increment in results in an increase in the
drain-to-source voltage of .
The graph of versus is plotted with the range of from 0 to 3 V as shown in Figure 1.
Thus, the graph of versus is plotted.
Question:
In the circuit of Fig. 5.8, (W/L)N = 10/0.5, (W/L)P = 10/0.5, and IREF = 100 μA. The input CM level applied
to the gates of M1 and M2 is equal to 1.3 V.
(a) Assuming λ = 0, calculate VP and the drain voltage of the PMOS diode-connected transistors.
(b) Now take channel-length modulation into account to determine IT and the drain current of the
PMOS diode-connected transistors more accurately.
Figure 5.8 Current mirrors used to bias a differential amplifier.
Step 1 Of 0
Question:
In the circuit of Fig. 5.11, sketch Vout versus VDD as VDD varies from 0 to 3 V.
Figure 5.11
Step 1 Of 2
In the circuit, when the supply voltage is less than the threshold voltage , MOSFETS are OFF, the current is
equal to zero , and the output voltage is zero .
When the condition , the MOSFET is in the triode mode; when it is linearly approaching the saturation, MOSFETS
are ON with the output voltage increasing linearly when the supply voltage is increased. When the condition
, all the MOSFETS are ON, and as the supply voltage increases, the drain-to-source voltage of MOSFET
1 increases. Hence, the current increases as .
The graph of versus is plotted with the range of from 0 to 3 V as shown in Figure 1.
Step 2 Of 2
Thus, the graph of versus is plotted.

Question:
Consider the circuit of Fig. 5.12(a), assuming (W/L)1−3 = 40/0.5, IREF = 0.3 mA, and γ = 0.
(a) Determine Vb such that VX = VY.
(b) If Vb deviates from the value calculated in part (a) by 100 mV, what is the mismatch between
Iout and IREF?
(c) If the circuit fed by the cascode current source changes VP by 1 V, how much does VY change?
Figure 5.12 (a) Cascode current source, (b) modification of mirror circuit to generate the cascode bias
voltage, and (c) cascode current mirror.
Step 1 Of 5
(a)
Consider the expression for the base voltage .
…… (1)
Here, is the gate to source voltage of transistor .
Consider the expression for the gate to source voltage of transistor .
Here, W is the channel width, is the channel length, is the reference current, is the source/drain side diffusion, and is the threshold
voltage for NMOS transistor.
Substitute 40 m for W, 0.5 m for L, for , 0.7 V for , for , and for .
Thus, the base voltage is .
Step 2 Of 5
(b)
Consider the expression for the output current through the transistor when base voltage is greater than threshold voltage.
…… (2)
Here, is the channel-length modulation coefficient and is the change in base voltage.
Consider the change in base voltage is .
From equation (2), consider the expression for the relationship of mismatch between the change in output current and the reference current.
Thus, the mismatch between the change in output current and the reference current is .
Step 3 Of 5
(c)
Consider if the voltage at point P increase by 1 V, then the voltage increases by .

Consider the expression for the output current through the transistor when supply voltage is greater than threshold voltage.
…… (3)
Here, is the change in voltage at node X.
…… (4)
Equate equation (3) and (4) to find the change in voltage at node X.
…… (5)
Step 4 Of 5
Substitute 40 m for W, 0.5 m for L, for , for , for . for , and for in
equation (5) to find .
Solve the characteristic equation to find .
Consider to choose the minimum value from . Therefore, .
Step 5 Of 5
Refer to Figure 5.9(a) in the textbook; consider the expression for the change in voltage at node Y.
Thus, the change in voltage at node Y is .

Question:
The circuit of Fig. 5.18(b) is designed with (W/L)1,2 = 20/0.5, (W/L)3,0 = 60/0.5, and IREF = 100 μA.
(a) Determine VX and the acceptable range of Vb.
(b) Estimate the deviation of Iout from 300 μA if the drain voltage of M3 is higher than VX by 1 V.
Figure 5.18 Modification of cascode mirror for low-voltage operation.
Step 1 Of 7
(a)
Consider the expression for the voltage at node X .
Consider the expression for the gate to source voltage of transistor .
Here, W is the channel width, is the channel length, is the reference current, is the source/drain side diffusion, and is the threshold
voltage for NMOS transistor.
Substitute for .
……. (1)
From equation (1), consider the expression for saturation drain voltage for the transistor .
……. (2)
……. (3)
Step 2 Of 7
Substitute 20 m for W, 0.5 m for L, for , for , and for in equation (2).
Substitute for and 0.7 V for in equation (3).
Step 3 Of 7
Consider the expression for the base voltage .
……. (4)
Calculate the gate to source voltage of NMOS transistor .
Here, is the body effect coefficient and is the Fermi potential.
Step 4 Of 7
From Table 2.1, the values of parameters , , and for NMOS model are 0.7 V, 0.45 , and 0.7 V respectively.
Substitute 0.45 for , for , 0.7 V for and .
That is, if the base voltage increases means the transistors and moved into triode region and the voltage at node A is approximately
equal to node voltage at X. Likewise, the voltage at node B is approximately equal to drain voltage of the transistor . Since, as long as drain
voltage of the transistor is not drop the voltage below saturation drain voltage of the transistor , and the output current should follows
the reference current .
Thus, the voltage at node X is and the acceptable range of is .

Step 5 Of 7
(b)
Consider the drain voltage of the transistor increase by 1 V and thereby the base voltage is increased by .
…… (5)
Here, is the change in voltage at node X.
…… (6)
Step 6 Of 7
Equate equation (5) and (6) to find the change in voltage at node X.
…… (7)
Refer to Part (a);
Substitute 60 m for W, 0.5 m for L, for , for , for . for , and for to
find .
Solve the characteristic equation to find .
Consider to choose the minimum value from . Therefore, .
Step 7 Of 7
Substitute for , for , for , for , and for in equation (5) to find .
Thus, the deviation of output current is .
Question:
The circuit of Fig. 5.23(a) is designed with (W/L)1−4 = 50/0.5 and ISS = 2I1 = 0.5 mA.
(a) Calculate the small-signal voltage gain.
(b) Determine the maximum output voltage swing if the input CM level is 1.3 V.
Figure 5.23 (a) Differential pair with current-source load; (b) circuit for calculation of Gm; (c) circuit for
calculation of Rout.
Step 1 Of 5
(a)
Refer to Figure 5.17(a) in the textbook for the differential pair with current source load circuit.
Modify Figure 5.17(a) for DC bias as shown in Figure 1.
Step 2 Of 5
Consider that for bias purpose and for small signal analysis.

…… (1)
The Saturation voltage for NMOS transistors 1 and 2 are 0.157 V when theb current .
Substitute 0.5 mA for and 0.157 V for in equation (1).
Consider the expression for the output resistance of PMOS transistor , which is equal to output resistance of NMOS transistor .
Substitute 0.5 mA for and 0.2 for .
Calculate the output resistance.
Step 3 Of 5
Write the expression for the small signal gain.
Substitute for and 3.18 mS for .
Thus, the small-signal voltage gain is .
Step 4 Of 5
(b)
Write the expression for the minimum output voltage.
…… (2)
Consider the maximum output voltage when MOSFET in triode.
…… (3)
Write the expression for the maximum output voltage swing.
…… (4)
Step 5 Of 5
Refer to Table 2.1 in the textbook.
From Table 2.1, the values of parameters , , and for NMOS model are 0.7 V, 0.45 , and 0.7 V respectively.
Calculate the threshold voltage for NMOS transistors.
Substitute 0.7 V for , 0.45 for , and 0.9 V for .
Substitute equations (2) and (3) in (4).
Substitute 3 V for , 1.3 V for , and 0.76 V for .
Thus, the maximum output voltage swing is .

Question:
Consider the circuit of Fig. 5.29(a) with (W/L)1−5 = 50/0.5 and ID5 = 0.5 mA.
(a) Calculate the deviation of Vout from VF if |VTH3| is 1 mV less than |VTH4|.
(b) Determine the CMRR of the amplifier.

Figure 5.29
Step 1 Of 6
(a)
Refer to Figure 5.22(a) in the textbook for the circuit.
Assume the current through the transistor is equal to the current through the transistor however the threshold voltage for the transistor
is not equal to the threshold voltage for the transistor .
Consider the expression for the current through the transistor when supply voltage is greater than threshold voltage.
…… (1)
Here, W is the channel width, is the channel length, is the channel-length modulation coefficient, is the constant parameter, is the
source/drain side diffusion, is the gate-source voltage for transistor , and is the threshold voltage for transistor .
Assume, .
…… (2)
Step 2 Of 6
Consider the expression for the current through the transistor when supply voltage is greater than threshold voltage.
…… (3)
Assume is 1mV less than . Therefore, equation (3) is rewritten as follows:

…… (4)
Step 3 Of 6
Equate equation (2) and (4).
Calculate the deviation of from .
Substitute for .
Thus, the deviation of from is .
Step 4 Of 6
(b)
Consider the expression for common mode rejection ratio .
…… (5)
Here, is the differential mode gain and is the common mode gain.
Step 5 Of 6
Refer to Figure 5.22(a) in the textbook; consider the expression for the differential mode gain.
Here, is the transconductance of the transistor , is the output resistance of the transistor , and is the output
resistance of the transistor .
Refer to Figure 5.22(a) in the textbook; consider the expression for the common mode gain.
Here, is the transconductance of the transistor .
Step 6 Of 6
Substitute for and for in equation (5) to find .
Thus, the common mode rejection ratio of the amplifier is
.
Question:
Sketch VX and VY as a function of VDD for each circuit in Fig. 5.52. Assume the transistors in each circuit
are identical.
Figure 5.52
Step 1 Of 16
(a)
Refer to Figure 5.33(a) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.33(a) is redrawn as shown in Figure 1.
In Figure 1, consider the current through transistor is and the current through transistor is . Consider if , then all the
transistors are in off condition. Therefore, the voltage at node X and Y is equal to the drain-to-drain voltage (that is, ).
When , the transistors and is turned on. In Figure 1, the transistors and are symmetric so that the gate to source
voltage for both the transistors remain the same. Therefore, the current and .
Consider the expression for the gate to source voltage for the transistor .
…… (1)
Step 2 Of 16
Consider the expression for the drain current of transistor .
Here,
is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width, L is the length, is the gate-source voltage, and
Refer to Figure 1. Consider that drain current of transistor is equal to the current through the transistor . Therefore,
…… (2)
Here, consider .
Step 3 Of 16
Using quadratic equation, rewrite the equation.
Since , write the expression for the voltage at node X and Y.
Step 4 Of 16
Figure 2 shows the plot drawn for and as a function of .
In Figure 2, the curve shows the voltage at node X and Y, which is equal to the gate to source voltage of transistor and . When
, the voltage increases linearly with an increase in drain-to-drain voltage as shown in Figure 2.
Thus, the plot drawn for the voltage at node X and voltage at node Y as a function of is shown in Figure 2.
Step 5 Of 16
(b)
Refer to Figure 5.33 (b) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.33 (b) is redrawn as shown in Figure 3.
Step 6 Of 16
transistors are in off condition. Therefore, the voltage at node X and Y is equal to the drain-to-drain voltage (that is, ).
When , the transistors and is turned on. In Figure 3, the transistors and are symmetric so that the gate to source
voltage for both the transistors remains the same. Therefore, the current and . In this condition, there is no current overflow
through the resistor .
Step 7 Of 16
Consider the expression for the gate to source voltage for the transistor .
…… (3)
Consider the expression for the drain current of transistor .
Here,
is the mobility of electrons, is the gate oxide capacitance per unit area, W is the width,L is the length, is the gate-source voltage, and
Refer to Figure 1. Consider that drain current of transistor is equal to the current through the transistor . Therefore,
…… (4)
Here, consider .
…… (5)
Step 8 Of 16
Using quadratic equation, rewrite the equation (5).
Since , write the expression for the voltage at node X and Y.

In Figure 4, the voltage at node X or voltage at node Y increases linearly with an increase in voltage. Since, .
Step 9 Of 16
(c)
Refer to Figure 5.33 (c) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.33 (c) is redrawn as shown in Figure 5.
Step 10 Of 16
In Figure 5, consider the current through transistor is and the current through transistor is .
Consider if , then all the transistors are in off condition and hence no current flows through the transistors and . Therefore, the
only current flows in the circuit through the resistor and .
In this condition, the voltage at node X using voltage division rule is and the voltage at node Y is .
When , the transistors and is turned on. In Figure 1, if the transistors and are turned on, then the current
because the gate to source voltage for both the transistors remains same. However, the voltage at node Y is greater than the voltage at node X
because the current through the resistor consist of , which is greater than the current through the resistor .
Step 11 Of 16

In Figure 6, the curve increases linearly with an increase in drain-to-drain voltage upto the threshold voltage when the transistor is in off
condition. Further increase in drain-to-drain voltage, and the voltage at node X again increases with the condition of transistors and on.
Likewise, the curve for voltage at node Y reassembles the same as like that of the curve for the voltage at node X but it is greater than .
Step 12 Of 16
(d)
Refer to Figure 5.33 (d) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.33 (d) is redrawn as shown in Figure 7.
Step 13 Of 16
transistors are in off condition. Therefore, the voltage at node X and Y is equal to the drain-to-drain voltage (that is, ) and the current
.
When , the transistors and is turned on and the resistor at the source of the transistor causes the gate to source voltage
of the transistor less than the gate to source voltage of the transistor . Therefore, the current and voltage . For some point,
the gate to source of the transistor becomes large enough so that the transistor moves into triode region, which is shown in Figure 8.
Step 14 Of 16

In Figure 8, the curve increases linearly with an increase in drain-to-drain voltage upto the threshold voltage when the transistor is in off
condition. Further increase in drain-to-drain voltage and the voltage at node X again increases with the condition of transistors and on.
After sometime, the voltage at node X remains constant with the condition of transistor in triode region and the transistor in on condition.
Step 15 Of 16
In Figure 8, the curve voltage at node Y increases linearly with an increase in drain-to-drain voltage upto when the transistor is in off
condition. Further increase in cause the voltage at node Y to decrease to some extent with the condition of transistors and on. After
sometime, the voltage at node Y remains constant with the condition of transistor in triode region and the transistor in on condition. That is,
and it is shown in Figure 8.
Step 16 Of 16
(e)
Refer to Figure 5.33 (e) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.33 (e) is redrawn as shown in Figure 9.
In Figure 9, when , the transistors and is turned on and the resistor at the source of the transistor causes the gate to
source voltage of the transistor greater than the gate to source voltage of the transistor . Therefore, the current and voltage
. Since, the transistor is diode connected so that transistor should never goes into the triode region.
In Figure 10, the curve increases linearly with increase in drain-to-drain voltage upto the threshold voltage when the transistor in off
condition. Further increase in drain-to-drain voltage results the voltage at node X increases with the condition of transistors and on.
Similarly, the voltage at node Y increases linearly with increase in drain-to-drain voltage upto when the transistor in off condition.
Further increase in results that the voltage at node Y start increasing to some extent with the condition of transistors and on but the
voltage at node Y is greater than the voltage at node X.
Question:
Sketch VX and VY as a function of VDD for each circuit in Fig. 5.53. Assume the transistors in each circuit
are identical.
Figure 5.53
Step 1 Of 6
(a)
Refer to Figure 5.34(a) in the textbook for the circuit.
Figure 5.34 (a) is redrawn as shown in Figure 1.
Step 2 Of 6
Refer to Figure 1; consider if , then all the transistors are in off condition. Therefore, the voltage at node X is equal to the drain-to-drain
voltage (that is, ) and the voltage at node Y is floating between the ground and since it is isolated from one or the other node.
Consider if , then all the transistors are turned on so that the voltage at the two nodes are determined as follows:
At node X:
At node Y:
Assume that if the threshold voltage for transistor is equal to the threshold voltage for transistor , then transistors and are moved to
the triode region always with .
Step 3 Of 6
For :
In this range, transistors and are turned on and and are moved to the triode region.
Consider the expression for the voltage at nodeX.
Consider the expression for the voltage at node Y.
or
On comparing and , the value of the voltage at node Xis greater than the value of the voltage at node Y ( that is, ).
Figure 2 shows the plot drawn for and as a function of as follows:
Step 4 Of 6
In Figure 2, transistor is in off condition upto . When the voltage is greater than , then transistors and are turned on and
transistors and are inthe triode region. In this curve, the voltage at node X islinearly increased with an increase in the voltage as a function
of . On the other hand, the voltage at node Ylinearly increases when the voltage is greater than . For the voltage less than , the voltage is
floating between the ground and .
Thus, the plot drawn for the voltage at node X and the voltage at node Y as a function of is shown in Figure 2.
Step 5 Of 6
(b)
Refer to Figure 5.34 (b) in the textbook for the circuit.
For :
Consider that currents and for transistors and are equal to . That is, .
Consider the expression for the voltage at node Y.
For :
In this range, consider that transistor is in off condtion and transistors and are in on condition.
Consider that currents and for transistors and are equal. That is, . This is because the gate to source voltage for transistors
and is equal. Hence, the voltages at node X and node Y are equal. Consider if , then the gate to source voltage for transistor is
equal to zero.
Step 6 Of 6
Figure 3 shows the plot drawn for and as a function of as follows:
In Figure 3, the voltage at node X or the voltage at node Ylinearly increases with an increase in voltage.Hence, .
Thus, the plot drawn for the voltage at node X and the voltage at node Y as a function of is shown in Figure 3.
Question:
For each circuit in Fig. 5.54, sketch VX and VY as a function of V1 for 0 < V1 < VDD. Assume the transistors
in each circuit are identical.
Figure 5.54
Step 1 Of 11
(a)
Refer to Figure 5.35 (a) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.36(a) is redrawn as shown in Figure 1.
In Figure 1, consider that current through transistor is , the current through transistor is , and the current through the resistor is
.
For :
Consider that NMOS transistors and are always in on condition. Therefore, the current through transistor is equal to current through
the transistor . That is, .
Step 2 Of 11
Refer to Figure 1, write the expression for the current through transistor .
…… (1)
Here, is the current due to the supply voltage .
Consider the expression to calculate the current due to the supply voltage using Ohm’s law.
…… (2)
Refer to Figure 1, consider the expression for the current through transistor using Kirchhoff’s current law at node Y.
…… (3)
Step 3 Of 11
…… (4)
Step 4 Of 11
Draw the plot for and as a function of as shown in Figure 2.

Refer to Figure 2, the curve for voltage at node Y and voltage at node X for the range . When the supply voltage increases, the
current increases and therefore, the voltage at node X and the voltage at node Y also increases. In this curve, the voltage is greater because
in equation (4) shows the linear combination of but the starting point of is less than because of constant subtraction of
.
Thus, the plot drawn for the voltage at node X and voltage at node Y as a function of for the range is shown in Figure 2.
Step 5 Of 11
(b)
Figure 5.36(b) is redrawn as shown in Figure 3.
In Figure 3, consider that current through transistor is , the current through transistor is , and the current through the resistor is
.
When the supply voltage , then the current through transistor is equal to current through the transistor , that is, . Therefore,
the current is equal to the reference current. Also, consider that voltage at node X and node Y are approximately equal and the change in
current through the resistor is equal to zero.
Step 6 Of 11
Consider if the supply voltage increases, then the current through the transistor slowly decreases and some of part of the reference current
flows through the resistor . Hence, the voltage at node X increases and the voltage at node Y decreases with the value . After
sometime, the supply voltage is large enough and so the transistor is turned off. Therefore, the voltage at node Y is equal to .
Thereafter the voltage at node X and voltage at node Y remain at constant voltage.

Step 7 Of 11
In Figure 4, the curve is drawn for voltage range for the voltage at node X and the voltage at node Y.
In this curve, increases linearly with an increase in supply voltage upto some extent when the transistors and is in on condition.
Further increase in supply voltage and the voltage at node X increases with the condition of transistors in on condition and in off
condition. The curve for is shown in Figure 4 for the range . Likewise, the curve for voltage at node Y reassembles the same way
as the curve for the voltage at node X but is in flipped position. During the condition of transistors on and off, the change in the magnitude
of voltage exists between and is and is shown in figure 4.
Step 8 Of 11
(c)
Refer to Figure 5.35 (c) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Figure 5.36(c) is redrawn as shown in Figure 5.
In Figure 5, consider the current through transistor is , the current through transistor is , and the current through the resistor is
.
When the supply voltage , then the current through transistor is equal to current through the transistor (that is, ) and also
consider the voltage at node X and node Y as approximately equal. If there is a small variation between and , then the gate to source voltage
of transistors and is not equal to .
Step 9 Of 11
Consider if the supply voltage increases, then the current through the transistor slowly decreases and some of part of the additional current
flows through the transistor . Therefore, the current through the transistor increases.
Refer to Figure 5, find the expression for the voltage at node Y using Ohm’s law.
…… (5)
After a while, the supply voltage is large enough and so the transistor is turned off. Therefore, the voltage at node Y is equal to
. Thereafter, the voltage at node X and voltage at node Y remain at constant voltage.
Step 10 Of 11
In Figure 6, the curve is drawn for voltage range for the voltage at node X and the voltage at node Y.
Step 11 Of 11
Refer to Figure 6, increases linearly with an increase in supply voltage upto some extent when the transistor and in on condition.
Further increase in supply voltage , the voltage at node X increases when the condition of transistors in on condition and in off
condition. From equation (5), the voltage at node Y is greater than the voltage at node X due to the additional drop of . When the condition
of transistors on and off, the change in magnitude of voltage exists between and is and is shown in Figure 6.
Question:
For each circuit in Fig. 5.55, sketch VX and VY as a function of V1 for 0 < V1 < VDD. Assume the transistors
in each circuit are identical.
Figure 5.55
Step 1 Of 4
(a)
Refer to Figure 5.36 (a) in the textbook for the circuit. In this circuit, assume that all the transistors are identical.
Consider the voltage at node X is constant until the supply voltage reaches the voltage greater than or equal to . In this circuit,
primarily the NMOS transistor is in triode region with the voltage at node Y until the NMOS transistor is in saturation region. Therefore,
write the expression for the voltage at node Y.
Here, is the supply voltage, is the transconductance of the NMOS transistor , and is the resistance of the resistor.
Consider, if the NMOS transistor is in saturation region, then the voltage at node Y is .
Step 2 Of 4

In Figure 1, the voltage at node X is constant for the range . The voltage at node Y increases linearly with an increase in supply voltage
upto some extent when the transistor in triode region, is in on condition, and is in off condition. Further increase in supply voltage
, the voltage at node Y increases when the condition of transistors and is on, and is in off condition. The curve for is shown in
Figure 1 for the range .
Step 3 Of 4
(b)
Consider if the supply voltage , then transistors and are in off condition and the transistor is in on condition. Therefore, the
voltage at node Y is equal to and the voltage at node X is . Here, consider .
Consider the supply voltage increases with the increase in the same amount until it reaches .When transistors and is turned
on, the voltage at node Y drops down due to until the transistor turned off.
Consider if the transistor is turned off, then the voltage at node X is equal to drain to source voltage of the transistors and , (that is,
) and the voltage at node Y is .
When , the transistor is turned on to increase the current through the NMOS transistors and . Therefore, consider the
expression for the voltage at node Y.
. Here, consider as the current flow through the transistor .
Step 4 Of 4
In Figure 2, the curve is drawn for voltage range for the voltage at node Xand the voltage at node Y. In this curve, increases
linearly with an increase in supply voltage upto some extent when the transistors and are in OFF condition, and is in ON condition.
Further increase in supply voltage , the voltage at node X increases with the condition of transistors and on, and in off condition.
The curve for is shown in Figure 1 for the range . Likewise, the curve for voltage at node Y reassembles the same way as the
curve for the voltage at node X, but is in flipped position as shown in Figure 2.
Question:
For each circuit in Fig. 5.56, sketch VX and VY as a function of IREF.
Figure 5.56
Step 1 Of 6
(a)
Refer to Figure 5.37 (a) in the textbook for the circuit.
In this circuit, consider the current through transistor is and the current through transistor is . When , the current and
are supplied by the drain-to-drain voltage through the resistor .
Consider the expression for the current through the NMOS transistors and when the base voltage greater than the threshold voltage.
Here, is the mobility of electrons, is the gate-source voltage for the transistors and , is the threshold voltage, is the gate
oxide capacitance per unit area, W is the width, and is the length.
Consider the expression for the gate-source voltage for the transistors and .
Refer to Figure 5.37 (a) in the textbook; consider the voltage at node X is . Therefore, .
Refer to Figure 5.37 (a) in the textbook; consider the voltage at node Y is .
Step 2 Of 6
When the reference current increases, then the current increases and therefore, the gate to source voltage for transistors and are also
increases with equal magnitude and it is equal to the voltage at node X . That is, .
In Figure 5.37 (a), apply Kirchhoff’s current law to find the voltage at node Y as a function of and .

In Figure 1, the curve for voltage at node Y decrease with increase in reference current whereas the curve for the voltage at node X increase with
increase in reference current.
Step 3 Of 6
(b)
Consider the current through transistor is , the current through transistor is , and the current through the transistor is .When
, the current , and are equal and all the three transistors is in on condition.
Consider the expression for the current through transistors , , and, when the base voltage greater than the threshold voltage.
Consider the expression for the gate-source voltage for transistors , , and, .
Refer to Figure 5.37 (b) in the textbook; consider the voltage at node X is . Therefore, .
Refer to Figure 5.37 (b) in the textbook; consider the voltage at node Y is . Therefore,
Step 4 Of 6
When the reference current increases, the gate to source voltage of transistors and increase and the voltage at node Y drops down. So
that, the gate to source voltage of the transistor starts decreasing until the transistor is turned off. Therefore, the transistors and
acts as a current mirror for the reference current. Consider if the reference current gets larger value, then the drop increase to a point when
the transistor moves to the triode region and it should not withstand on the reference current.
Step 5 Of 6
Draw the plot for and as a function of .
In Figure 2, the curve increases linearly with increase in reference current upto some extent when the transistor in on condition. Further
increase in reference current, the voltage at node X again increase with the condition of transistors and on, and in off condition.
Similarly, the increase the reference current results that the node voltage increase with condition of transistor in triode, in on, and in
off condition. Likewise, the curve for voltage at node Y reassembles the same as like the curve for the voltage at node X but it is in flipped position
with the transistor conditions remains same which is shown in Figure 2.
Step 6 Of 6
(c)
Refer to Figure 5.37 (c) in the textbook for the circuit.
In this circuit, consider if , then all transistors are in saturation region with node voltage . When the reference current is turned on,
then the NMOS transistor moves into triode region and then the PMOS transistor moves into triode region. Therefore, the voltage at
node X and Y are determined as follows:
At node X:
At node Y:

In Figure 2, at the voltage at node X is equal to the voltage at node Y. Further increase in reference current results decrease and
increase.
Question:
For the circuit of Fig. 5.57, sketch Iout, VX, VA, and VB as a function of (a) IREF, (b) Vb.
Figure 5.57
Step 1 Of 4
(a)
In this circuit, consider thatthe output current follows the reference current for all values of reference current until the voltage at node Xis
greater than .
Consider if the NFET devices and move into triode region, then the voltage at nodesA and B remains the same because the devices
and stillprovide similar currents. When the reference current increases, the voltage at nodesA and B decreasesbecause the gate-voltage source
of NFET devices and increases. When the reference current increases, the voltage at node X increases because the gate-source voltage of
NFET devices and increases.
For , the NFET device enters into the triode region and decreases the output current with respect to the reference current.
Step 2 Of 4
Draw the plot for , , , and as a function of as shown in Figure 1.

In Figure 1, the curve shows that for , , and as a function of . Thevoltage at nodesA and B decreases gradually from some
magnitude of voltage with the increase in the reference current. The voltage at node X gradually increase from some magnitude of voltage with the
increase in the reference current.
In Figure 1, the curve shows that for as a function of . The output current increases linearly with the increase in the reference currentto
some extent. When the device enters into the triode region, the output current remains constant with an increase in the reference current.
Thus, the plot drawn for the voltage at node X, the voltage at node A, the voltage at node B, and the output current as a function of is shown
in Figure 1.
Step 3 Of 4
(b)
For the reference current, consider if the voltage is less than 1 V of gate-source voltage, then the voltage at node Xincreases to large voltage to
flow through the NFET devices and .
Consider the expression for the current through the NFET device when the input voltage is greater than the threshold voltage.
channel-length modulation coefficient, is the gate oxide capacitance per unit area,W is the width, and is the length.
Refer to Figure 5.38, consider the voltage , the voltage at nodesA and B are and the current , respectively. When the
voltage increases, it means thatthe voltage at nodesA and B increases to turn on the NFET devices and . Therefore, the voltage at node
X is equal to . Further increase in the voltage results in the NFET devices and entering into triode region, whereas the NFET
devices and are still in the saturation region.
Step 4 Of 4
Draw the plot for , , , and as a function of as shown in Figure 2.
In Figure 2, the curve shows that for , , and as a function of . Thevoltage at node A increases gradually to some extent and remains
constant with the an increase in voltage , but the curve exists within the voltage .The voltage at node B increases gradually to some extent
and remains constant with the increase in voltage , but the curve is greater than the voltage at node A. The voltage curve exists within the
voltage .The voltage at node Xdecreases gradually from some magnitude of voltage with the increase in voltage and settles down the
voltage to the voltage at node A.
In Figure 2, the curve shows that for as a function of . The output current increases linearly with the increase in the voltage upto .
When the devices and enter into the triode region, the output current remains constant with an increase in voltage .
Thus, the plot drawn for the voltage at node X, the voltage at node A, the voltage at node B, and the output current as a function of is shown
in Figure 2.
Question:
In the circuit shown in Fig. 5.58, a source follower using a wide transistor and a small bias current is
inserted in series with the gate of M3 so as to bias M2 at the edge of saturation. Assuming M0–M3 are
identical and λ ≠0, estimate the mismatch between Iout and IREF if (a) γ = 0, (b) γ ≠ 0.
Figure 5.58
Step 1 Of 16
(a)
Refer to Figure 5.39 in the textbook for MOSFET circuit.
Here,
is the gate-oxide thickness of MOSFET, and is the mobility of NMOS FET.
Consider the MOSFET’s - are identical to each other.

Consider the expression for drain current of MOSFET.
…… (1)
Here,
is the drain current, is the mobility of NMOS FET, is the width to length ratio, is the gate-to-source voltage, is the channel
length modulation, is the drain-to source voltage and is the threshold voltage.
The drain current of MOSFET is equal to .
Step 2 Of 16
Modify equation (1) for MOSFET .
Substitute for .
…… (2)
The same reference current is flowing through the drain terminal of the MOSFET .
Since, the MOSFET’s - are identical to each other the ratio of MOSFET’s - are same.
Substitute for .
Substitute for .
…… (3)
Step 3 Of 16
Refer to Figure 5.9 (c) in the textbook for cascode current mirror.
The circuit forms by the combination of MOSFET’s , , and is same as cascode current mirror.
In cascode mirror circuit, and may not be equal to because the voltage applied to the MOSFET depends upon voltage
due to the small bias current in series with gate terminal of MOSFET and gate-to source voltage of MOSFET .
Write the expression for .
Substitute for .
…… (4)
Step 4 Of 16
Consider the value of is approximately equals to .
In this case, the gate-to-source voltage of MOSFET is approximately equals to gate-to-source voltage of MOSFET .
In basic current mirror circuit, gate-to-source voltage of MOSFET is approximately equals to gate-to-source voltage of MOSFET .
The drain current of MOSFET is equal to and same current is flowing through drain terminal of MOSFET .
Step 5 Of 16
Substitute for .
…… (5)
Step 6 Of 16
Substitute for .
…… (6)
Step 7 Of 16

Substitute for .
Step 8 Of 16
Divide equation (5) by equation (3).
…… (7)
Step 9 Of 16
Thus, the estimated mismatch between and for is

(b)
Consider the expression for threshold voltage with body effect.
…… (8)
Here,
is the work function, is the source-bulk potential difference, is the body effect coefficient, and is threshold voltage with .
In circuit, the source-bulk potential difference of MOSFET is 0, because the source terminal of is connected to ground.
Step 10 Of 16
Substitute 0 for .
Re-arrange the expression.

Step 11 Of 16
In circuit, the source-bulk potential difference of MOSFET is , because the source terminal of is connected to gate terminal of
MOSFET .
Substitute for .
Step 12 Of 16
In circuit, the source-bulk potential difference of MOSFET is , because the source terminal of is connected to drain terminal of
MOSFET .
Step 13 Of 16

Substitute for .
Substitute for .
Step 14 Of 16
In circuit, the source-bulk potential difference of MOSFET is , because the source terminal of is connected to gate
terminal of MOSFET and source terminal of MOSFET is connected to drain terminal of MOSFET .
Substitute for .
Substitute for .
…… (9)
Step 15 Of 16
Step 16 Of 16
Modify equation (7) for .
Substitute for , for ,
for , and
for .
Thus, the estimated mismatch between and
for is,
.
Question:
Sketch VX and VY as a function of time for each circuit in Fig. 5.59. Assume the transistors in each circuit
are identical.
Figure 5.59
Step 1 Of 12
(a)
Refer to the circuit for Figure 5.40 (a).
Write the expression for the voltage at node Y.
or,
Here, is the current through device .
In Figure 5.40 (a), the current varies with respect to .
Step 2 Of 12
Consider the transistors are in saturation region. Since all the transistors in the current mirror circuit are identical, the current is,
The gate to source voltage is,
Step 3 Of 12
Refer to Figure 5.40 (a), the gate and drain of are shorted so that and are same.
The voltage is the voltage across the channel and capacitor.

Therefore, the voltage at point X can be written as,
At , the voltage is applied at the gate input terminal. Since the both devices are biased at the reference current the device
operates in saturation region. The currents flows through both transistors equal to . Here, flows through to capacitor . The
capacitor charges with respect to the current continuously from 0 to .
Write the expression of capacitor voltage.
At the initial stage at the voltage at X is lesser than . Thus the voltage .
As capacitor charges more, the voltage can be increased linearly. When then enters in to triode region, then it improves the
channel resistance and reduces. Therefore, the voltage gets decreases whereas will increases up to at the time .
Step 4 Of 12
Therefore,
For voltage :
At initial time , and .
For the time , increases to approximately .
For voltage :
At initial time , and .
For the time , decreases.
Draw the plot of and versus time as shown in Figure 1.

Thus, the plot of and versus time is drawn.
Step 5 Of 12
(b)
Refer to the circuit Figure 5.40 (b).
The gate and drain of are shorted then and are same. The voltage node X is same as . Here, is equals to a constant bias
voltage that applies at the gate due to bias current for all the time of circuit operation. Thus, the voltage is constant for all .
Consider initially both transistor are in saturation mode and .
Write the expression for the voltage .
Here, is the current through .
Step 6 Of 12
At the starting is maximum as , so that at starting is a smaller value since drop is maximum. The voltage is smaller value and
greater then at . The current varies from to and decreases as enters in to triode region. Therefore,
increases and it can be reach to at the time .
Step 7 Of 12
Now draw the plot of and versus time as shown in Figure 2.

Step 8 Of 12
(c)
Refer to the circuit Figure 5.40 (c).
The capacitor has the initial voltage . The device discharges the capacitor from starting of the circuit operation until the voltage at the node
X is equal to threshold voltage of the device . That is . The transistor drain and gate are shorted so that . When the
voltage at node X reaches the current through reaches to zero from maximum initial current, that is .
So that, at initial time, the voltage is equals to the initial voltage of capacitor and drops until .
Step 9 Of 12
The two transistors are identical, so that same current can allowed to flow.
Write the expression of , in terms of .
As varies from maximum to zero, increases from minimum to maximum at time .

Step 10 Of 12
(d)
Refer to the circuit Figure 5.40 (d).
The capacitor has initial voltage approximately equal to . Transistor is start to conduct due to the charge from the capacitor. The
charge from the capacitor flows in the path through and gate node of to . Therefore, consider that and are in ON state in the
initial stage. The voltage at the node Y is maximum at starting and decreases during the operation as the voltage discharges in capacitor through
. That means, as capacitor discharges the current through reduces whereas the current through increases thereby the voltage is
increases slightly.
Therefore, the voltage is maximum initially, and reduces to minimum at time in the circuit operation. The voltage is at a constant value that
is less then , and increases slightly as circuit operating at time as discharges.
Step 11 Of 12
Step 12 Of 12
(e)
Refer to the circuit Figure 5.40 (e).
Assume that the two transistors are in ON state, and in saturation region.
The capacitor has the initial voltage connected across where . Transistor can sustain with when or
during the circuit operation. As capacitor discharges the voltage increases up to . The current indicates that transistor
became as open switch so that total can reflect at X. When the voltage increasing at X, the transistor enters in to triode region, the
resistance of increases so that the current though it reduces, so that the voltage is reduces to its minimum value at the time .

Question:
are identical.
Figure 5.60
Step 1 Of 6
(a)
Refer to the circuit in Figure 5.41(a) in the textbook.
At thestarting of the circuit operation, the capacitor has 0 V that is connected to source terminal. The transistor is in ON position due to the
voltage applied at the gate with respect to source current. When in starting at , the voltage at node X is equal to
. After the circuit is in operation, the current through will reach the current, that both currents and are equal.At
the instant of starting the voltage, is greater than .
The voltage at node Y can be written as follows:
As the current flows to capacitor , the voltage across the capacitor increases. When the capacitor gets full charge capacity, it will be open
circuited and makes turn off. Now, the voltage at X increases up to to sustain device with and the voltage at node Y
increases to .
Step 2 Of 6
The plot of and as the function time is drawn as shown in Figure 1.

Thus, the plot of and as the function time is drawn.
Step 3 Of 6
(b)
Refer to the circuit in Figure 5.41(b) in the textbook.
At , devices and are ON state with the gate voltage applied due to reference current source . At thestarting of the circuit
operation, capacitor with voltage supplies the current to the path of , so that capacitor starts discharge through . Therefore, the
voltage at node X at the time of very starting instant of the operation is very high due to the capacitor voltage and ; at this instant, device is
in off position due to the high voltage at node X.
The voltage at X drops as the capacitor discharges and allows the current through . Now, current will reach anequal amount of current .
When , the capacitor stops to discharge and holds the voltage on the same level. The voltage at node Y slightly increases due to an
increase in .
Step 4 Of 6
The graph between and with respect to time is drawn as shown in Figure 2.
Step 5 Of 6
(c)
Atthe starting of the circuit operation, transistors and are ON due to the gate voltage applied by . Device is ON due to voltage
of capacitor .
The voltage at Y node is,
As quick as discharges the drain to source voltage of decreases then gate to source voltage is increases that makes the voltage at node X
is low in very small amount. As voltage decreases and the level is true, then the current through gets nil, that means no
current flows from capacitor through . Since, the current stops, the voltage at reaches at constant level and no further reduction in
voltage.
Step 6 Of 6
The characteristics of and as a function time is drawn in Figure 3.

Question:
are identical.
Figure 5.61
Step 1 Of 2
Refer to Figure 5.42 (a) in the textbook for MOSFET circuit.
In Figure, as one terminal of the capacitor is connected to ground, the charge stored in the capacitor is zero.
Consider the value of time (t) equals to zero.
In Figure, the source terminal of the MOSFET is directly connected to . So, at , the voltage appeared at turns “ON”
MOSFET , which results in flow of current through . The drain terminal of the MOSFET is directly connected to gate terminal of
MOSFET and there is no connection between the capacitor and point X. Hence, there is no flow of current through the capacitor.
Therefore, the full voltage applied at is appeared at point .
…… (1)
In Figure, the capacitor starts to charge up when the drain current of MOSFET is equal to drain current of MOSFET
.
Write the expression for voltage appeared at point .
…… (2)
Use equations (1) and (2) to sketch and as a function of time (t) as shown in Figure 1.
Thus, sketch of and as a function of time (t) is shown in Figure 1.
Step 2 Of 2
Refer to Figure 5.42 (b) in the textbook for MOSFET circuit.
In Figure, one terminal of the capacitor is connected to point X.
Consider the value of time (t) equals to zero.
In Figure, the source terminal of the MOSFET is directly connected to . So, at , the voltage appeared at turns “ON”
MOSFET , which results in flow of current through . The drain terminal of the MOSFET is directly connected to gate terminal of
MOSFET and one terminal of the capacitor . Hence, the capacitor gets charged due to flow of current. Therefore, the voltage at point
doesn’t reach instantaneously. Instead of that slowly charges to . Similarly, also slowly charges to .
Draw and as a function of time (t) as shown in Figure 2.

Thus, sketch of and as a function of time (t) is shown in Figure 2.
Question:
The circuit shown in Fig. 5.62 exhibits a negative input inductance. Calculate the input impedance of the
circuit and identify the inductive component.
Figure 5.62
Step 1 Of 3
Draw the small signal model of the circuit as shown in Figure 1.
Step 2 Of 3
Consider the expression for input impedance.
Here, is the applied input voltage, and is the input current.
Substitute for .
…… (1)
From Figure 1, write the expression for the voltage underthe condition of all are identical transistors.

…… (2)
Step 3 Of 3
Consider all transistors identical and have equal transconductance.
…… (3)
In equation (3), the value of negative capacitance is and negative resistance is .
Thus, the input impedance of the circuit is and capacitive component is .

Question:
Due to a manufacturing defect, a large parasitic resistance, R1, has appeared in the circuits of Fig. 5.63.
Calculate the gain of each circuit if λ > 0.
Figure 5.63
Step 1 Of 0
Question:
In digital circuits such as memories, a differential pair with an active current mirror is used to convert a
small differential signal to a large single-ended swing (Fig 5.64). In such applications, it is desirable that the
output levels be as close to the supply rails as possible. Assuming moderate differential input swings (e.g.,
∆V = 0.1 V) around a common-mode level Vin,CM and a high gain in the circuit, explain why Vmin depends
on Vin,CM.
Figure 5.64
Step 1 Of 3
The differential pair of inputs are have certain level of . The bias current shows the variation on the change of , that causes to the
change in transconductance.
If is very low, the minimum values of two inputs and leads to turn off and , and considerable level of clipping occurs at the
output. So that, maintaining a proper input CM level is important.
Step 2 Of 3
Write the voltage expression at the point P in Figure 5.45 in the textbook.
Consider that, and are in saturation. Then, the deferential input minimum voltage is required at each input is,
Substitute for .
…… (1)
Here, gate-source and drain-source voltages are dependents on the basic parameters of the devices.
Step 3 Of 3
From equation (1), the minimum gate input is to satisfy the relation where is preferably at low level. So that, is the dependent and
should follow the relation in equation (1) for the selected to keep transistor devices in operation.
Thus, is depend on the input CM level and it is explained.

Question:
Sketch VX and VY for each circuit in Fig. 5.65 as a function of time. The initial voltage across C1 is shown.
Figure 5.65
Step 1 Of 3
(a)
In the initial time, transistors and are in ON position in the triode region since these two devices have the current path by capacitor and
gate input 1.5 V. Capacitor starts the discharge. The voltage at node X is very high in starting time and keep discharging through both
transistors and . When the voltage at node X drops to a certain level that allows the current through transistors and , then and
gets turned ON. Once transistors and are in ON state, the voltage at node X becomes saturated. After transistors and
come to ON state, enters saturation and is still in the triode region until the current though makes the voltage at node Y equal to the
voltage at node X. At certain time of the circuit operation, both the voltages at nodesX and Y are equal .
The graph for voltages and isdrawn with respect to the time as shown in Figure 1.
Thus, the plot of voltages and as a function of time is drawn.
Step 2 Of 3
(b)
Node X is at the drain of transistor ; initially, voltage is at the lowest value , where . Therefore, the initial voltage at
node X is
Transistor is in the triode region and is in ON state. The current through charges capacitor . Since is in the triode region and the
currents in and increase where the transistors cannot sustain for high currents at the range of the tail current, Since the voltage at node Y
increases as to keep in the triode region to control the current through it at thestarting. Therefore, in the initial stage, the voltages at Y
and X can be considered as high and level. After sometime of the circuit operation, the voltage at node Y will reduce as
capacitor gets charged.
When the voltages are at equal position until the capacitor charges, the voltage gets saturated at some constant level with very slight variations.
The graph for voltages and aredrawn with respect to time as shown in Figure 2.
Step 3 Of 3
(c)
The capacitor is charged with 0 V initially and connected between drain and source of ,which makes the drain and source of short.
Transistor operates in the triode region and allows the minimum current flow through it. Capacitor is charged from 0 V with current from
. As capacitor is charging more than 0 V, the terminals drain and sources are not shorted, and also the current flow through starts
slowly. The current through increases until voltage is high enough to keep in the saturation region and allows the maximum current
through . After sometime of the circuit operation, the voltages at X and Y reach an equal level and get saturated.The initial stage of
the voltages at Y and X can be considered as high and level.
The graph for voltages and are drawn with respect to time as shown in Figure 3.
Question:
If in Fig. 5.66, ∆V is small enough that all of the transistors remain in saturation, determine the time
constant and the initial and final values of Vout.
Figure 5.66
Step 1 Of 2
The small-signal model of the circuit as shown in Figure 1.
Step 2 Of 2
Consider the initial value of is and the initial value of .
Write the expression for the final output voltage (wich is equal to ).
Here,
are transconductances of MOSFETS respectively.

Consider the expression for the final value of input voltage.
Substitute for .
Consider the expression for the final value of output voltage.
Substitute for .
From Figure 1, the expression for the time constant is,
Thus, the time constant is and the initial and final values of are and respectively.
Question:
For a device operating in the subthreshold region, we have
(a) If the device is in the deep triode region, VDS « VT. Using exp(−ϵ) ≈ 1−ϵ, determine the on-
resistance.
(b) If the device is in saturation, VDS » VT. Compute the transconductance.
(c) Find the relation between gm,B and Ron,R in Fig. 5.43(d) using the above results.
Figure 5.43 CS stage biasing with (a) VB fighting Vin, (b) ac coupling to set the dc value of VX to VB, (c) use
of a current mirror, (d) a large resistor realized by MR, and (e) accurate VGS generation for MR.
Step 1 Of 0
Question:
Determine the corner frequency resulting from Cin in Fig. 5.47(d). For simplicity, assume C1 is a short
circuit.
Figure 5.47 (a) Complementary CS stage, (b) self-biased topology, (c) accurate definition of bias current,
and (d) use of ac coupling at input.
Step 1 Of 0
Question:
Determine the supply rejection of the circuit shown in Fig. 5.67.
Figure 5.67
Step 1 Of 0
Question:
In the circuit of Fig. 6.3(c), suppose the amplifier has a finite output resistance Rout.
(a) Explain why the output jumps up by ∆V before it begins to go down. This indicates the
existence of a zero in the transfer function.
(b) Determine the transfer function and the step response without using Miller’s theorem.
Figure 6.3
Step 1 Of 3
(a)
Refer to Figure 6.2(c) in the textbook for the amplifier circuit.
Draw the small signal model for the circuit as shown in Figure 1.
From Figure 1, the amplifier circuit forms a high pass network.
As the amplifier circuit forms the high pass network, the output of the circuit follows the input signal when there is a step at the input. Then, the
circuit’s output settle down to as the steady state.
Thus, the reason for jumping of the circuit’s output is described.
Step 2 Of 3
(b)
Apply Kirchhoff’s current law at node in Figure 1.
…… (1)
Here,
is the output voltage, is the output resistance, is the forward path capacitance, is the input voltage, and is the amplification
gain.
Rewrite and rearrange the expression in equation (1).
Step 3 Of 3
Consider for step response.
Therefore, .
Consider the expression for step response.
Apply Inverse Laplace transformation on both sides of the expression.
As step input for the circuit is , substitute for .
Thus, the transfer function and step response of the circuit are and , respectively.
Question:
Repeat Problem 6.1 if the amplifier has an output resistance Rout and the circuit drives a load capacitance
CL.
Step 1 Of 4
(a)
Refer to Figure 6.2(c) in the textbook for the amplifier circuit.
From Figure 1, the amplifier circuit forms a high pass network.
As the amplifier circuit forms the high pass network, the output of the circuit follows the input signal when there is a step at the input. Then, the
circuit’s output settle down to as the steady state.
Thus, the reason for jumping of the circuit’s output is described.
Step 2 Of 4
(b)
…… (1)
Here,
is the output voltage, is the output resistance, is the forward path capacitance, is the load capacitance, is the input voltage,
and is the amplification gain.
Rewrite and rearrange the expression in equation (1).
Step 3 Of 4
Consider for step response.
Therefore, .
Consider the expression for step response.
Apply Inverse Laplace transformation on both sides of the expression.
As step input for the circuit is , substitute for .
Step 4 Of 4
Thus, the transfer function and step response of the circuit are and ,
respectively.
Question:
The CS stage of Fig. 6.13 is designed with (W/L)1 = 50/0.5, RS = 1 kΩ, and RD = 2 kΩ. If ID1 = 1 mA,
determine the poles and the zero of the circuit.
Figure 6.13 (a) High-frequency model of a common-source stage, and (b) simplified circuit using Miller’s
approximation.
Step 1 Of 7
Refer to Figure 6.10 in the textbook for high-frequency model of a common-source stage.
Refer to Figure 6.12 in the textbook for the equivalent circuit of high-frequency model of a common-source stage.
From the circuit, the transistor is a NMOS device.
Consider the expression for zero of the circuit.
…… (1)
Here, is the transconductance of the MOSFET and is the gate to drain capacitance in the circuit.
Step 2 Of 7
Consider the two poles of the circuit in Figure 6.12 as:
Write the equation of the denominator as:
The coefficient of s will becomes for the condition of the pole is much farther from the origin.
Substitute for , and

for , then the denominator equation is simplified as:
Thus, the expression for denominator polynomial of the transfer function of the circuit is,
…… (2)
Here, is the source resistance, is the drain resistance, is the gate to source resistance in the circuit, is the drain to ground
capacitance in the circuit.
Step 3 Of 7
Consider the expression for transconductance of the MOSFET in the circuit.
…… (3)
Here, is the drain current in the circuit, is the gate to source voltage (or input voltage) in the circuit, and is threshold voltage of the
NMOS device.
Consider the expression for drain current in the circuit.
…… (4)
Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, W is the channel width, L is the
channel-length, is the channel-length modulation coefficient, and is the drain to source voltage.
Consider the source/drain side diffusion in the MOSFET, so that the channel length of the device (L) is equal to .
…… (5)
Here, is the channel length and is the source/drain side diffusion length.
Consider the expression for capacitance per unit area.
…… (6)
Here, is the permittivity of the silicon oxide and is the thickness of the oxide layer.
Step 4 Of 7
Refer Table 2.1 in the textbook for the level 1 SPICE model parameters for NMOS and PMOS devices.
The value of width and length of the MOSFET is very small. So, consider the unit width and length is in .

Here, is the permittivity of free space and has the .
Substitute for .
From the circuit in the Figure 6.10 in the textbook, write the expression for .
…… (7)
Here, is the positive voltage applied to the circuit.
Consider the value of as 3 V.
Substitute 3 V for , for , and for in equation (7).
Modify equation (4) when source/drain side diffusion occurs in the MOSFET.
Substitute for , for , for , for W, for , 0.7 V for , 0.1 for , and 1 V for
.
Simplify the expression for .

Step 5 Of 7
Substitute for , 1.0035 V for , and 0.7 V for in equation (3).
Consider the expression for gate to drain capacitance in the circuit.
…… (8)
Here, is the gate-drain overlap capacitance per unit width.
From the table 2.1 in the textbook, consider the value of for NMOS device as .
Step 6 Of 7
Substitute for and for W in equation (8).
Step 7 Of 7
Consider the expression for gate to source capacitance in the circuit.
Substitute for , for W, for , and for .

Consider the expression for drain to ground capacitance in the circuit as .
Substitute for , for , for , for , for , and for in

equation (2).
Simplify the quadratic expression and obtain the roots (poles of the circuit).
Therefore, write the poles of the circuit.
Thus, the zero and poles of the circuit are , , and , respectively.
Question:
Consider the CS stage of Fig. 6.16, where I1 is realized by a PMOS device operating in saturation. Assume
that (W/L)1 = 50/0.5, ID1 = 1 mA, and RS = 1 kΩ.
(a) Determine the aspect ratio of the PMOS transistor such that the maximum allowable output
level is 2.6 V. What is the maximum peak-to-peak swing?
(b) Determine the poles and the zero.

Figure 6.16
Step 1 Of 21
(a)
Refer to Figure 6.13 in the textbook for a common-source stage circuit.
Draw the circuit as shown in Figure 1 when the current (in the circuit in Figure 6.13) is realized by the PMOS device.
Step 2 Of 21
Consider the expression to find the bias voltage in the circuit in Figure 1.
…… (1)
Here, is the maximum allowable output voltage level and is threshold voltage of the PMOS device.
Substitute 2.6 V for and for in equation (1).
Consider the output DC bias voltage (drain to source voltage) as 1.5 V as the two devices (PMOS and NMOS) are operating in saturation.
Step 3 Of 21
Consider the expression for drain current for NMOS device in the circuit .
…… (2)
From the Table 2.1 in the textbook, the threshold voltage of the NMOS device is 0.7 V.
…… (3)
Step 4 Of 21
…… (4)
Substitute for .
Step 5 Of 21
Step 6 Of 21
…… (5)
Substitute for , for , for , for W, for , 0.7 V for , 0.1 for , and 1.5 V for
.
Step 7 Of 21
From the circuit in Figure 1, is the input voltage to the NMOS device.
Therefore, the value of is 0.9969 V.
Modify equation (5) for the PMOS device in the circuit.

…… (6)
The channel length is same for both PMOS and NMOS devices. Therefore, the value of is .
From Table 2.1 in the textbook, the value of is and the value of is .
Substitute for and for in equation (3) to obtain the channel length of the PMOS device.
Step 8 Of 21
From the circuit in Figure 1, the value of is same as .
Substitute for , for , for , for , 3 V for , 1.8 V for , for , 0.2 for
, and 1.5 V for in equation (6).
Step 9 Of 21
Simplify the expression for of a PMOS device.
From obtained results, write the aspect ratio of PMOS device.
Step 10 Of 21
Consider the expression to find the maximum peak-to-peak swing.
…… (7)
Here, is the low-level output voltage.

Consider the expression to find low-level output voltage.
Thus, the aspect ratio of PMOS device and maximum peak-to-peak swing are and , respectively.
Step 11 Of 21
(b)
Consider the expression to find the zero.
…… (8)
Here, is the transconductance of the MOSFET and is the gate to drain capacitance of the MOSFET .
Consider the expression for the characteristic equation to find the poles. Poles are the roots of the characteristic equation.
…… (9)
Here, is the source resistance, is the drain resistance, is the gate to source resistance of the MOSFET , is the drain to
ground capacitance of the MOSFET .
Step 12 Of 21
Consider the expression for transconductance of the MOSFET (NMOS device) in the circuit.
Substitute for , 0.9969 V for , and 0.7 V for .
Step 13 Of 21
Consider the expression for gate to drain capacitance in the circuit.
…… (10)
Here, is the gate-drain overlap capacitance per unit width and is the channel width of the MOSFET .
Step 14 Of 21
Consider the expression to find the drain resistance (output port resistance).
…… (11)
Here, and are channel resistances of MOSFETs and , respectively.

Rewrite equation (11).
…… (12)
Step 15 Of 21
Substitute for , for , and 1.5 V for .
Step 16 Of 21

Substitute for , for , and 1.5 V for .
Step 17 Of 21
Step 18 Of 21
Consider the expression for gate to source capacitance of MOSFETs .
Substitute for , for , for , and for .
Consider the expression for drain to ground capacitance of the NMOS device as .
Step 19 Of 21
Substitute for , for , for , for , for , and for

in equation (9).
Step 20 Of 21
Step 21 Of 21
Simplify the quadratic expression and obtain the roots (poles of the circuit).
Therefore, write the poles of the circuit.
Thus, the zero and poles of the circuit are , , and
, respectively.
Question:
A source follower employing an NFET with W/L = 50/0.5 and a bias current of 1 mA is driven by a source
impedance of 10 kΩ. Calculate the equivalent inductance seen at the output.
Step 1 Of 9
Refer to Figure 6.21 in the textbook for equivalent output impedance of a source follower.
Consider the expression to find the equivalent inductance seen at the output in the circuit.
…… (1)
Here, is the transconductance of the MOSFET, is the gate to source capacitance, and is the source resistance.
Consider the expression for transconductance of the MOSFET in the circuit.
…… (2)
Here, is the drain current (bias current) in the circuit, is the gate to source voltage (or input voltage) in the circuit, and is threshold
voltage of the NMOS device.
Step 2 Of 9
Consider the expression for drain current in the circuit.
…… (3)
Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, W is the channel width,L is the
Consider the channel-length modulation coefficient as 0.
…… (4)
Step 3 Of 9
…… (5)
…… (6)
Step 4 Of 9
Here, is the permittivity of free space and has .
Substitute for .
Step 5 Of 9
Modify equation (4) whensource/drain side diffusion occurs in the MOSFET.
Step 6 Of 9
Substitute for , for , for , for W, for , and 0.7 V for .

Step 7 Of 9
Substitute for , 1.0184 V for , and 0.7 V for in equation (2).
Step 8 Of 9
Consider the expression for gate to source capacitance in the circuit.
Step 9 Of 9
Thus, the equivalent inductance seen at the output in the circuit is .

Question:
Neglecting other capacitances, calculate the input impedance of each circuit shown in Fig. 6.58.
Figure 6.58
Step 1 Of 9
(a)
Refer to Figure 6.36 (a) in the textbook for the common-source stage circuit.
Consider input voltage and current as and , respectively and redraw the circuit as shown in Figure 1 to obtain the input impedance of the
circuit.
Step 2 Of 9
Consider the expression for input impedance of the circuit.
…… (1)
Here, is the input voltage in the circuit and is the input current in the circuit.
Consider the expression for input current from the circuit in Figure 1.
…… (2)
Here, is the capacitance in the circuit and is the voltage at node in the circuit.
Step 3 Of 9
From the circuit in Figure 1, input current is equal to .
…… (3)
Here, is the transconductance of the MOSFET .

Rearrange the expression for .
Thus, the input impedance of the circuit is .
Step 4 Of 9
(b)
Refer to Figure 6.36 (b) in the textbook for the common-source stage circuit.
Redraw the circuit as shown in Figure 2 to obtain the input impedance of the circuit.
Step 5 Of 9
In Figure 2, and are transconductances of MOSFETs and , respectively, and , are output resistances of MOSFETs
and , respectively.
Step 6 Of 9
As the output resistances of the MOSFETs are in parallel, find the equivalent output resistance .
Consider the overall transconductance of the MOSFETs as . Write the expression for .
Simplify the circuit in Figure 2 and redraw the circuit as shown in Figure 3.
Step 7 Of 9
…… (4)
Apply Kirchhoff’s current law (KCL) at node in the circuit in Figure 3.
…… (5)
Apply KCL at node in the circuit in Figure 3.

Step 8 Of 9

Step 9 Of 9
(c)
Refer to Figure 6.36 (c) in the textbook for the common-source stage circuit.
Redraw the circuit as shown in Figure 4 to obtain the input impedance of the circuit.
In figure 4, is the backgate transconductance of the MOSFETs .
…… (6)
From the circuit in Figure 4, write the expression for the current .

Question:
Estimate the poles of each circuit in Fig. 6.59.
Figure 6.59
Step 1 Of 9
Circuit in Figure 6.37 (a):
Refer to Figure 6.37 (a) in the textbook for the required circuit.
Step 2 Of 9
From the circuit in Figure 1, three nodes are existed in the circuit. Therefore, the circuit has three poles.
Use the Miller effect approximation and write the expression for the pole at the node .
Here, is the source resistance, is the transconductance of the MOSFET , is the output resistance of the MOSFET , is
the gate-to-drain capacitance of the MOSFET , and is the gate-to-source capacitance of the MOSFET .
Here, is the drain-bulk capacitance of the MOSFET , is the gate-to-drain capacitance of the MOSFET , is the gate-to-
source capacitance of the MOSFET , is the transconductance of the MOSFET , is the output resistance of the MOSFET , and
is the gate-to-drain capacitance of the MOSFET .
Step 3 Of 9
Here, is the drain-bulk capacitance of the MOSFET .
Thus, the poles of the circuit are , , and ,

respectively.
Step 4 Of 9
Circuit in Figure 6.37 (b):
Refer to Figure 6.37 (b) in the textbook for the required circuit.
Draw the small signal model for the circuit.
Step 5 Of 9
Consider the parameters as follows:
Use the considered parameters, simplify the circuit in Figure 2, and redraw the simplified small signal model circuit as shown in Figure 3.
Step 6 Of 9
Rearrange the expression.
…… (1)
From equation (3), substitute for .
…… (2)
Step 7 Of 9
…… (3)
Step 8 Of 9
Multiply equations (1), (2), and (3) on both sides of the expressions.
Step 9 Of 9
From the transfer function, write the poles of the circuit.
Thus, the poles of the circuit are , , and , respectively.

Question:
Calculate the input impedance and the transfer function of each circuit in Fig. 6.60.
Figure 6.60
Step 1 Of 41
Step 2 Of 41
Simplify and draw the equivalent circuit for the circuit in Figure 1 as Figure 2.
Consider the capacitances , , and as follows:
Step 3 Of 41
…… (1)
Step 4 Of 41
…… (2)
Step 5 Of 41
Multiply equations (1) and (2on both sides of the expressions.
Step 6 Of 41
Simplify the expression for the transfer function of the circuit.
Step 7 Of 41
Consider input voltage and current as and , respectively and redraw the circuit as shown in Figure 3 to obtain the input impedance of the
circuit.
Step 8 Of 41
Consider the expression to find the input impedance of the circuit.
…… (3)
Consider the expression for in the circuit in Figure 3.
Step 9 Of 41

Thus, the transfer function and input impedance of the circuit is and
, respectively.
Step 10 Of 41
Step 11 Of 41
…… (4)

Step 12 Of 41
Step 13 Of 41
…… (5)
Step 14 Of 41
Multiply equations (4) and (5) on both sides of the expressions.
Step 15 Of 41

Step 16 Of 41
Step 17 Of 41

, respectively.
Step 18 Of 41
Circuit in Figure 6.38 (c):
Refer to Figure 6.38 (c) in the textbook for the required circuit.
Step 19 Of 41

…… (6)
Step 20 Of 41
…… (7)
Step 21 Of 41
Step 22 Of 41
Step 23 Of 41
Step 24 Of 41
, respectively
Circuit in Figure 6.38 (d):
Refer to Figure 6.38 (d) in the textbook for the required circuit.
Step 25 Of 41
…… (8)
Step 26 Of 41

Step 27 Of 41
…… (9)
Step 28 Of 41
Step 29 Of 41

, respectively
Step 30 Of 41
Circuit in Figure 6.38 (e):
Refer to Figure 6.38 (e) in the textbook for the required circuit.
Step 31 Of 41
Consider the capacitances and as follows:

…… (10)
Step 32 Of 41
Step 33 Of 41
…… (11)
Step 34 Of 41

Step 35 Of 41
, respectively
Step 36 Of 41
Circuit in Figure 6.38 (f):
Refer to Figure 6.38 (f) in the textbook for the required circuit.
Step 37 Of 41

…… (12)
Step 38 Of 41
Step 39 Of 41
…… (13)
Step 40 Of 41
Step 41 Of 41
, respectively.
Question:
Calculate the gain of each circuit in Fig. 6.61 at very low and very high frequencies. Neglect all other
capacitances and assume that λ = 0 for circuits (a) and (b) and γ = 0 for all of the circuits.
Figure 6.61
Step 1 Of 20
Redraw equivalent simplified circuit as shown in Figure 1.
Step 2 Of 20
Gain at low frequency:
…… (1)
At low frequency, the node becomes virtual ground. Therefore, .
As the voltage gain , substitute for .
Step 3 Of 20
Gain at high frequency:
At high frequency, both the capacitors become short circuit. Then, .

Find the voltage gain at high frequency.
Thus, the voltage gain of the circuit at low and high frequencies are and , respectively.
Step 4 Of 20
At low frequency, the capacitors gets open circuit. Redraw the circuit as shown in Figure 2.
Step 5 Of 20
Consider the expression for voltage gain from the circuit in Figure 2.
…… (2)
Here, is the transconductance of the device and is the output resistance of the device .
…… (3)
Here, is the channel-length modulation coefficient of the PMOS device, is the drain current of the device , and is the drain to
source voltage of the device .
Step 6 Of 20
As , substitute 0 for in equation (3).

At high frequency, the capacitor become short circuit. Redraw the circuit as shown in Figure 3.
Step 7 Of 20
…… (4)
Here, is the output resistance of the device .
…… (5)
Here, is the channel-length modulation coefficient of the NMOS device, is the drain current of the device , and is the drain to
Step 8 Of 20

Step 9 Of 20
At low frequency, both the capacitors gets open circuit. Redraw the circuit as shown in Figure 4.
Ignore the resistors , , and redraw the circuit as shown in Figure 5.

Step 10 Of 20

At high frequency, both the capacitors become short circuit. Redraw the circuit as shown in Figure 6.
Step 11 Of 20
…… (6)
Here, is the impedance looking into , is the transconductance of the device , and is the impedance looking into .
Step 12 Of 20
Step 13 Of 20
Step 14 Of 20
Step 15 Of 20
…… (7)
Substitute for .
Step 16 Of 20
At high frequency, both the capacitors become short circuit. Redraw the circuit as shown in Figure 8.
Step 17 Of 20
Draw the small-signal model for the circuit in Figure 8 as Figure 9.
Step 18 Of 20
…… (8)
Step 19 Of 20
Step 20 Of 20
Thus, the voltage gain of the circuit at low and high frequencies are and ,
respectively.
Question:
Calculate the gain of each circuit in Fig. 6.62 at very low and very high frequencies. Neglect all other
capacitances and assume that λ = γ = 0.
Figure 6.62
Step 1 Of 12
At low frequency, the capacitor gets open circuit. Redraw the circuit as shown in Figure 1.
Step 2 Of 12
…… (1)
Here, is the transconductance of the device , is the output resistance of the device , and is the output resistance of the device
.
…… (2)
Here, is the channel-length modulation coefficient of the NMOS device, is the drain current of the device , and is the drain to
Step 3 Of 12
…… (3)
Here, is the channel-length modulation coefficient of the PMOS device, is the drain current of the device , and is the drain to
Step 4 Of 12
At high frequency, the capacitor become short circuit. Redraw the circuit as shown in Figure 2.
Step 5 Of 12
As the capacitor gets short circuit, the output resistance of the devices become zero.
From equation (1), the gain is directly related to the output resistance of the devices. As the output resistance of the devices become zero, the gain
becomes zero at high frequency.
Step 6 Of 12
Step 7 Of 12
Draw the half-circuit for the circuit in Figure 3 as shown in Figure 4. Note that the voltage becomes virtual ground.
Step 8 Of 12
…… (4)
Here, is the output impedance in the circuit.
Here, is the output impedance of the device and is the resistance in the circuit.
As , rewrite the expression.
Step 9 Of 12
At high frequency, both the capacitors gets short circuit. Redraw the circuit as shown in Figure 5.
Step 10 Of 12
Draw the half-circuit for the circuit in Figure 5 as shown in Figure 6.
Step 11 Of 12
Write the expression for the gain from the circuit in Figure 6.
…… (5)
Write the expression for the gain from the circuit in Figure 6.
…… (6)
Multiply equations (5) and (6).
Step 12 Of 12
Question:
Consider the cascode stage shown in Fig. 6.63. In our analysis of the frequency response of a cascode stage,
we assumed that the gate-drain overlap capacitance of M1 is multiplied by gm1/(gm2 + gmb2). Recall from
Chapter 3, however, that with a high resistance loading the drain of M2, the resistance seen looking into the
source of M2 can be quite high, suggesting a much higher Miller multiplication factor for CGD1. Explain why
CGD1 is still multiplied by 1 + gm1/(gm2 + gmb2) if CL is relatively large.
Figure 6.63
Step 1 Of 5
Refer to Figure 6.41 in the textbook for the cascode stage.
From the figure, the load impedance is the impedance across the capacitor .
Write the expression for load impedance.
Draw the small signal model for the circuit in Fig.6.41 as shown in Figure 1.
Step 2 Of 5
…… (1)
Here,
is the output voltage, is the load impedance, is the output resistance, are trans conductance parameters, and is the input
voltage.
Simplify the expression in equation (1).
…… (2)
Step 3 Of 5
Write the expression for current in the circuit.
…… (3)
Consider the expression for impedance in the circuit.

Step 4 Of 5
Write the expression for Miller multiplication factor for .
Substitute for .
…… (4)
If is relatively large, then the impedance in the circuit is much lesser than the resistance .
That is, when is a relatively large value.

Therefore, rewrite equation (4).
Step 5 Of 5
From the calculation, the Miller multiplication factor for is when is considered as a large value.
From the analysis, the load impedance has negligible effect on the Miller multiplication factor when is considered as a large value. As the
load impedance does not affect much on the Miller multiplication factor, the is still multiplied by when is relatively a
large value.
Thus, the reason for why is still multiplied by when is relatively a large value is described.
Question:
Neglecting other capacitances, calculate ZX in the circuits of Fig. 6.64. Sketch |ZX | versus frequency.
Figure 6.64
Step 1 Of 11
Consider input voltage and current as and , respectively and draw the small-signal model for the circuit as shown in Figure 1.
Step 2 Of 11
Consider the expression to find the impedance of the circuit in Figure 1.
…… (1)

Step 3 Of 11
Substitute for .
Step 4 Of 11
Step 5 Of 11
Find at .
Step 6 Of 11
Find at .
From the analysis, sketch versus frequency as shown in Figure 2.
Thus, the impedance in the circuit is and the plot of versus frequency is drawn and shown in Figure 2.
Step 7 Of 11
Consider input voltage and current as and , respectively and draw the small-signal model for the circuit as shown in Figure 3.
Step 8 Of 11
Substitute for .
Step 9 Of 11

Step 10 Of 11
Find at .
Find at .
Step 11 Of 11
From the analysis, sketch versus frequency as shown in Figure 4.
Thus, the impedance in the circuit is and the plot of versus frequency is drawn and shown in Figure 4.
Question:
The common-gate stage of Fig. 6.31 is designed with (W/L)1 = 50/0.5, ID1 = 1 mA, RD = 2 kΩ, and RS = 1
kΩ. Assuming λ = 0, determine the poles and the low-frequency gain. How do these results compare with
those obtained in Problem 6.9?
Figure 6.31 Common-gate stage at high frequencies.
Step 1 Of 19
Refer to Figure 6.23 in the textbook for the required circuit.
Step 2 Of 19
Write the transfer function for the circuit in Figure 1.
…… (1)
Here, is the transconductance of the device , is the backgate transconductance of the device , is the drain resistance in the
circuit, is the source resistance in the circuit, is the source capacitance in the circuit, and is the drain capacitance in the circuit.
Step 3 Of 19
As , no body effect in the circuit. Therefore, choose the value of such that the voltage is approximately zero.
Consider the expression for drain current for the device in the circuit.
…… (2)
channel-length, is the gate-to-source voltage of the device, is the drain-to-source voltage of the device, is the threshold voltage of
the NMOS device, and is the channel-length modulation coefficient of the NMOS device.
…… (3)
Step 4 Of 19
From the table, write the values of required parameters.
…… (4)
From the table, the value of for NMOS device is .

Step 5 Of 19
…… (5)
Substitute for .
Step 6 Of 19
Substitute for , for , for , for , for ,and0.7 V for .
Step 7 Of 19

Consider the expression for transconductance of the device in the circuit.
Step 8 Of 19
…… (6)
Here, is the body effect coefficient and is the Fermi potential.

Write the required parameters from the Table 2.1 in the textbook for NMOS device.
Step 9 Of 19
Substitute for , 0.9 V for , and for in equation (6).
Step 10 Of 19
…… (7)
Here, is the drain junction capacitance.
…… (8)
Here, The source-drain bottom-plate junction capacitance per unit area is , the source-drain sidewall junction capacitance per unit length is
, and E is the lateral dimension of the source-drain areas.
…… (9)
The voltage is equal to .
Substitute 0.9 V for , for , 0.45 for , and for in equation (9).
Step 11 Of 19
Step 12 Of 19
Step 13 Of 19
…… (10)
Here, is the source junction capacitance and is the gate source capacitance.
Step 14 Of 19
…… (11)
Consider and .
Substitute for .
Step 15 Of 19
From the circuit in Figure 1, two nodes are existed in the circuit. Therefore, the circuit has two poles.
Step 16 Of 19
Write the expression for the pole .
Step 17 Of 19
Step 18 Of 19
Consider the expression to find low frequency gain in the circuit.
Step 19 Of 19
From the analysis, the poles for common-gate stage circuit are much larger than the poles in Problem 6.9 in the textbook since the miller effect is
not existed in the common-gate configuration (current problem).
Thus, the poles of the circuit are , , and the low frequency gain is .
Question:
Suppose that in the cascode stage of Fig. 6.34, a resistor RG appears in series with the gate of M2. Including
only CGS2, neglecting other capacitances, and assuming λ = γ = 0, determine the transfer function.
Figure 6.34 High-frequency model of a cascode stage.
Step 1 Of 6
Refer to Figure 6.25 in the textbook for the high frequency model of a cascode stage circuit.
Consider a resistor appears in series with the gate of the NMOS device , consider only the capacitance , and neglect other
capacitances in the circuit.
Redraw the circuit as shown in Figure 1 to meet the desired conditions.
Step 2 Of 6
Draw the small-signal model for the circuit in Figure 1 as Figure 2.
Step 3 Of 6

…… (1)
Step 4 Of 6
…… (2)
Step 5 Of 6
Rearrange and simplify the expression.

…… (3)
Step 6 Of 6
Divide equation (2) with equation (3).
Thus, the transfer function of the circuit is .

Question:
Apply the method of Fig. 6.18 to the circuit of Fig. 6.41(b) to determine the zero of the transfer function.
Figure 6.18 Calculation of the zero in a CS stage.
Figure 6.41 (a) Simplified high-frequency model of differential pair with active current mirror; (b) circuit of
(a) with a Thevenin equivalent.
Step 1 Of 3
Refer to Figure 6.15 in the textbook for the calculation of zero in a CS stage circuit.
From the method in Figure 6.15 in the textbook, for a finite .

Apply the method and redraw the circuit as shown in Figure 1.
Step 2 Of 3
As the output is shorted to the ground, the current becomes zero at , which is equal to .
From the circuit in Figure 1, current through the device equals to the current when .
…… (1)
From the circuit, consider the expression for .
Step 3 Of 3
From the circuit, consider the expression for .
Rearrange the expression for zero of the transfer function.
Thus, the zero of the transfer function is .

Question:
The circuit of Fig. 6.42(a) is designed with (W/L)1,2 = 50/0.5 and (W/L)3,4 = 10/0.5. If ISS = 100 μA, K = 2,CL
= 0, and RD is implemented by an NFET having W/L = 50/0.5, estimate the poles and zeros of the circuit.
Assume the amplifier is driven by an ideal voltage source.
Figure 6.42
Step 1 Of 30
Refer to Figure 6.32 (a) in the textbook forthe required circuit.
Draw the half-circuit for the circuit in Figure 6.32 (a) as shown in Figure 1.
Step 2 Of 30
From the circuit, . Write the transfer function for the circuit in Figure 1.
Here, is the gate-to-drain capacitance of the MOSFET , is the transconductance of the MOSFET , is the
transconductance of the MOSFET , is the capacitance at node X, is the output resistance of the MOSFET , is the output
resistance of the MOSFET , and is the load capacitance.
Consider the expression for drain current for PMOS device in the circuit.
…… (1)
Here, is mobility of charge carriers in the PMOS device, is the gate oxide capacitance per unit area, W is the channel width,L is the
channel-length, is the bias voltage, is the threshold voltage of the PMOS device, is the channel-length modulation coefficient of the
PMOS device, and is the voltage at node X in the circuit.
Step 3 Of 30
…… (2)
Step 4 Of 30
From the table, the value of for PMOS device is .
…… (3)
Substitute for .
Step 5 Of 30
Substitute for , for , for , for , for , 3 V for , for , and 0.2
for .
Step 6 Of 30
Solve the polynomial expression and obtain the value of .
Consider the value of as 1.94 V and ignore the remaining two values.
Consider the expression for drain current for NMOS device in the circuit.
…… (4)
Here, is mobility of charge carriers in the NMOS device, is the threshold voltage of the NMOS device, and is the channel-length
modulation coefficient of the NMOS device.
Step 7 Of 30
…… (5)
From Table 2.1 in the textbook, the value of is for NMOS device, the value of is 0.7 V, the value of is , and
the value of is .
Substitute for and for in equation (2) to obtain the channel length of the NMOS device.
Step 8 Of 30
Substitute for , for , for , for W, for , 0.7 V for , for , and 1.94
V for in equation (5).
Step 9 Of 30
Consider the expression for transconductance of the MOSFET (NMOS device) in the circuit.
Step 10 Of 30
Step 11 Of 30
Consider the expression for transconductance of the MOSFET (PMOS device) in the circuit.
Substitute for , 3 V for , 1.94 V for , and for .
Step 12 Of 30
Consider the expression for transconductance of the MOSFET (PMOS device) in the circuit.
Substitute for .
Consider the expression for gate to drain capacitance of the MOSFET .
…… (6)
Here, is the gate-drain overlap capacitance per unit width and is the channel width of the MOSFET .
Step 13 Of 30
Consider the expression for in the circuit.
…… (7)
Consider the drain resistance in the circuit is implemented by a device .
Consider the expression to find in the circuit.
…… (8)
Here,
is the width of the NMOSFET , is the source-drain bottom-plate junction capacitance per unit area, is the source-drain sidewall
junction capacitance per unit length, and E is the lateral dimension of the source-drain areas.
Write the expression for the source-drain bottom-plate junction capacitance per unit area. …… (9)
Refer to Table 2.1 in the textbook for the term and for NMOS device.
Step 14 Of 30
Step 15 Of 30
Step 16 Of 30
Step 17 Of 30
Consider the expression to find in the circuit.
…… (10)
Here,
is the width of the PMOSFET .
Refer to Table 2.1 in the textbook for the term and for PMOS device.
Step 18 Of 30
Step 19 Of 30
Write the expression to find .

Step 20 Of 30
Modify equation (6) for the NMOSFET .
…… (11)
Step 21 Of 30
Consider the expression for output impedance in the circuit.
…… (12)
Here, is the output impedance of the PMOSFET and is the output impedance of the NMOSFET .

Step 22 Of 30
Step 23 Of 30
Step 24 Of 30
…… (13)
Consider the expression for gate to source capacitance of the PMOSFET .
Step 25 Of 30
From the circuit, .
Substitute for .
Step 26 Of 30
Substitute for .
Modify equation (6) for the PMOSFET .
…… (14)
From the table 2.1 in the textbook, consider the value of for PMOS device as .
Step 27 Of 30
Step 28 Of 30
Substitute for , for , for , for , for

, for , and for in equation (13).
Step 29 Of 30
From the circuit in Figure, the circuit has two poles and one zero.
Consider the expression to find the zero in the circuit.
Step 30 Of 30
Thus, the zero, poles of the circuit are , , and , respectively.

Question:
A differential pair driven by an ideal voltage source is required to have a total phase shift of 135° at the
frequency where its gain drops to unity.
(a) Explain why a topology in which the load is realized by diode-connected devices or current
sources does not satisfy this condition.
(b) Consider the circuit shown in Fig. 6.65. Neglecting other capacitances, determine the transfer
function. Explain under what conditions the load exhibits an inductive behavior. Can this circuit
provide a total phase shift of 135° at the frequency where its gain drops to unity?
Figure 6.65
Step 1 Of 14
(a)
Draw the two types of differential pair common-source stage circuits as shown in Figure 1.
Step 2 Of 14
Simplify the circuit in Figure 1 as common-source amplifier with different load resistance and capacitance as shown in Figure 2.
Step 3 Of 14
From the circuit, . Write the transfer function for the circuit in Figure 2.
…… (1)
Here, is the gate-to-drain capacitance of the MOSFET , is the transconductance of the MOSFET , is the capacitance in the
circuit, and is the drain resistance.
For diode connected load:
Here, is the transconductance of the PMOS device in the circuit.
Here, is the drain junction capacitance of the NMOS device, is the drain junction capacitance of the PMOS device, and is the
gate source capacitance of the PMOS device in the circuit.
Step 4 Of 14
For current mirror connected load:

Here, is the output resistance of the NMOS device and is the output resistance of the PMOS device in the circuit.
Here, is the gate drain capacitance of the PMOS device in the circuit.
Step 5 Of 14
Rewrite the transfer function of the circuit in equation (1).
From the expression, write the zero and pole of the circuit.
Step 6 Of 14
From the expressions of zero and pole in the circuit, it is clear that the zero is much larger than the dominant pole. Therefore, the maximum phase
shift can be achieved with the circuit is about before the gain drops to unity.
Thus, the topology in which the load is realized by diode connected loads or current mirror loads does not attain the total phase shift of
before the gain drops to unity.
Step 7 Of 14
(b)
Draw the half-circuit for the circuit in Figure 6.43 as shown in Figure 3.
Step 8 Of 14
At low frequency:
At low frequency, the capacitors get open circuit and the PMOS device becomes diode connected device in the circuit in Figure 3. Then, the
output impedance in the circuit becomes .
At high frequency:
At low frequency, the capacitors get short circuit and the PMOS device becomes current source device in the circuit in Figure 3. Then, the
output impedance in the circuit becomes .
The output impedance (load) exhibit inductive behavior when .
Step 9 Of 14
Draw the small-signal model for the circuit as shown in Figure 4 to obtain the transfer function.
Step 10 Of 14
Rearrange the expression .
Step 11 Of 14
Step 12 Of 14
Substitute for .

Step 13 Of 14
From the transfer function, write zero of the circuit.
From the denominator of the transfer function, use the formula of sum of two roots of quadratic expression and write the expression for sum of two
poles of the circuit.
Step 14 Of 14
From the circuit, and the value of is at least . Therefore, the sum of two poles is greater than .
As , at least one of the poles are greater than the zero of the circuit and consequently the maximum phase shift can be
achieved with the circuit is about before the gain drops to unity.
Thus, the transfer function of the circuit is , the load exhibits inductive behavior when
, and the circuit cannot attain the total phase shift of before the gain drops to unity.
Question:
Repeat Example 6.3, but assume that I1 is replaced with a resistor R1.
Example 6.3
Figure 3.54 Input resistance of a CG stage with ideal current-source load.
Step 1 Of 0
Question:
A resistively-degenerated common-source stage bootstraps CGS in a manner similar to a source follower.
Estimate the input capacitance of such a stage.
Step 1 Of 0
Question:
Determine the transfer function of a CG stage with a resistance RG in series with the gate, including only
CGS and CGD. Assume λ = γ = 0.
Step 1 Of 0
Question:
Determine the transfer function of a CG stage with a resistance RG in series with the gate, including only
CGD and CDB. Assume λ = γ = 0.
Step 1 Of 0
Question:
Determine the transfer function of a differential pair with current-source loads for differential signals.
Assume that each input is driven by a series resistance of RS.
Step 1 Of 0
Question:
Consider a circuit containing only one capacitor, C1. We set the main input to zero and apply a current
source, IX, in parallel with C1, obtaining the voltage across it, VX, and hence VX (s)/IX (s) (Fig. 6.66). This
impedance has the same pole as the main transfer function. Prove that the pole is given by 1/(R1C1), where
R1 is the resistance seen by C1.
Figure 6.66
Step 1 Of 0
Question:
Repeat Example 6.22, but with λ > 0 and γ > 0.
Example 6.22
Step 1 Of 0
Question:
Prove that the −3-dB bandwidth of N first-order identical gain stages is given by , where ωp
denotes the pole of one stage.
Step 1 Of 0
Question:
Prove that if CGD = 0, then Eq. (6.30) reduces to the product of two transfer functions that can simply be
obtained by association of poles with the input and output nodes.
Step 1 Of 0
Question:
A common-source stage incorporates a 50-μm/0.5-μm NMOS device biased at ID = 1 mA along with a load
resistor of 2 kΩ. What is the total input-referred thermal noise voltage in a 100-MHz bandwidth?
Step 1 Of 8
Consider the expression for input-referred noise voltage of common-source stage circuit.
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, and is the load
resistance.
…… (2)
Here, is the drain current, is mobility of charge carriers, is the gate oxide capacitance per unit area, W is the channel width, and L is the
channel length.
Step 2 Of 8
Consider the NMOS device is in saturation region and the length of the device (L) is equal to effective length due to the source/drain side
diffusion.
…… (3)
Here, is the channel length which is equal to , and is the source/drain side diffusion.
Modify equation (2) for NMOS device.
Substitute for L.
…… (4)
Consider the expression for capacitance per unit area .
…… (5)
Step 3 Of 8
Refer Table 2.1 in the textbook for the model parameters of NMOS devices.

Substitute for .
Substitute for , and for in equation (5).
Step 4 Of 8
Step 5 Of 8
Substitute for , for , for W, for , and for in equation (4).
Step 6 Of 8
Substitute for F.
Consider the value of T is equal to a standard room temperature (that is ).
Step 7 Of 8
Re-arrange equation (1).
Substitute for , for k, for T and for .
Step 8 Of 8
Consider the relation between total input noise and input-referred noise voltage (rms).
Here, is the input-referred noise voltage, and BW is the bandwidth.
Substitute for , and 100 MHz for BW.
Thus, the total input-referred thermal noise voltage is rms.

Question:
Consider the common-source stage of Fig. 7.42. Assume that (W/L)1 = 50/0.5, ID1 = ID2 = 0.1 mA, and VDD
= 3 V. If the contribution of M2 to the input-referred noise voltage (not voltage squared) must be one-fifth of
that of M1, what is the maximum output voltage swing of the amplifier?
Figure 7.42
Step 1 Of 8
Refer to Figure 7.35 in the textbook for MOSFET amplifier circuit.
Consider the expression for total noise voltage at gate of MOSFET .
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance of ,and is the
transconductance of .
…… (2)
channel length.
Step 2 Of 8
diffusion.
…… (3)
Here, is the is the channel length which is equal to , and is the source/drain side diffusion.
Modify equation (2) for NMOS device .
Substitute for L.
…… (4)
Modify equation (2) for PMOS device .
Substitute for L.
…… (5)
Step 3 Of 8
…… (6)
Substitute for .
Since the value of is same for PMOS and NMOS devices, the value of is same for both devices.
The value of width and length of the MOSFET is very small. So consider the unit width and length is in .
Step 4 Of 8
Here, is the source/drain side diffusion of NMOS device .

Step 5 Of 8
Substitute for , for , for , for , and for in equation (4).
Substitute for F.
Step 6 Of 8
Modify the equation (1).
Consider the contribution of for input-referred voltage is one-fifth of . Thus, the relation between and is written as,
…… (7)
…… (8)

Step 7 Of 8
Consider the expression for maximum output voltage swing of the amplifier.
Here, is the threshold voltage of MOSFET , is the positive voltage applied to the circuit, is the gate-source voltage of ,
is the threshold voltage of MOSFET , and is the gate-source voltage of .
…… (9)
From the circuit the branch current of the cascade transistors and are equal.
Step 8 Of 8
Thus, the maximum output voltage swing of the amplifier is .

Question:
Using the distributed model of Fig. 7.21(c) and ignoring the channel thermal noise, prove that, for gate noise
calculations, a distributed gate resistance of RG can be replaced by a lumped resistance equal to RG/3.
(Hint: model the noise of RGj by a series voltage source and calculate the total drain noise current. Watch
for correlated sources of noise.)
Figure 7.21 (a) Layout of a MOSFET indicating the terminal resistances; (b) circuit model; (c) distributed
gate resistance.
Step 1 Of 18
Refer to Figure 7.19(c) in the textbook for distributed model of gate resistance.
Modify Figure as shown in Figure 1.
Step 2 Of 18
Write the expression for transconductance
…… (1)
Here, is the transconductance, I is the current, and V is the applied gate voltage.
In Figure 1, the gate voltage applied to the MOSFET is .
Here, is the transconductance of the MOSFET , is the drain current of MOSFET , and is the voltage of which is
applied to gate terminal of the MOSFET .
Step 3 Of 18
Here, is the transconductance of the MOSFET , is the drain current of MOSFET , and is the voltage of which is
applied to gate terminal of the MOSFET .
Step 4 Of 18
Similarly, the gate voltage applied to the MOSFET is .
Here, is the transconductance of the MOSFET , is the drain current of MOSFET , and is the voltage of
which is applied to gate terminal of the MOSFET .
Step 5 Of 18
Modify Figure 1 for the total voltage applied at gate terminal as shown in Figure 2.
Step 6 Of 18
Write the expression for total drain current.

…… (2)
Consider the value of transconductance as and which is same for all resistances connected to gate terminal of the MOSFET’s in distributed
model.
…… (3)
Step 7 Of 18
Consider the noise voltages applied at gate terminal of each MOSFET’s are uncorrelated to each other.
An uncorrelated noise voltage sources are represented by and total noise current is represented by .
Modify Figure 1 for noise sources as shown in Figure 3.
Step 8 Of 18
Modify equation (1) for MOSFET with noise sources.
Here, is the transconductance of the MOSFET , is the drain noise current of MOSFET , and is the noise voltage of
which is applied to gate terminal of the MOSFET .
Step 9 Of 18

Here, is the transconductance of the MOSFET , is the drain noise current of MOSFET , and is the noise voltage
of which is applied to gate terminal of the MOSFET .
Step 10 Of 18
Similarly, the gate voltage applied to the MOSFET is .
Here, is the transconductance of the MOSFET , is the drain noise current of MOSFET , and is the noise
voltage of which is applied to gate terminal of the MOSFET .
Step 11 Of 18
Modify Figure 2 for the total noise voltage applied at gate terminal as shown in Figure 4.
Step 12 Of 18
Write the total rms noise current due to independent noise sources.
Substitute for , for ,and for .

…… (4)
Consider the value of resistance as and which is same for all MOSFET’s connected in distributed model.
Step 13 Of 18
Since, the values of resistance is same, the noise voltage applied to the gate terminal also same.
Consider the expression for thermal noise voltage.
…… (5)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, B is the bandwidth, and R is the resistance.
Modify equation (5) for gate noise voltage .
…… (6)
Step 14 Of 18
Step 15 Of 18

…… (7)
Step 16 Of 18
Consider the value of n reaches to infinity.
Substitute for n in equation (7).
Step 17 Of 18
Modify equation (1) for total noise current.
Substitute for .
…… (8)
Step 18 Of 18
In equation (6), the noise voltage at single gate terminal depends upon . In equation (8), the total gate noise voltage of distributed model
depends upon lumped resistance .
Thus, the gate noise voltage of distributed model is and in this expression the resistance is replaced by lumped resistance equal to
.
Question:
Prove that the output noise current of Fig. 7.39(c) is given by Eq. (7.73).
Figure 7.39 Equivalent CS stages.
Step 1 Of 6
Refer to Figure 7.33 (c) in the textbook for equivalent common-source stage circuit.
Write the formula for the output noise current of the circuit for the Figure 7.33 (c).
…… (1)
Here, is the current in the noise source, is the impedance connected to source terminal of the MOSFET, is the transconductance, and
is the output resistance.
Step 2 Of 6
Modify the circuit as shown in Figure 1.
Step 3 Of 6
Draw the small-signal model of Figure 1 as shown in Figure 2.
Step 4 Of 6
Apply Kirchhoff’s Current Law (KCL) to drain terminal of the MOSFET in Figure 1 to write the expression for .
…… (2)
Here, is the drain current, and is the current in the noise source.
Apply current divider rule at source terminal in Figure 2 to write the expression for .

…… (3)
Step 5 Of 6
…… (4)
Step 6 Of 6
The derived expression of and the output noise current in equation (1) are same.
Thus, the output noise current of the common-source stage circuit is shown as,
.
Question:
Calculate the input-referred flicker noise voltage of the circuit shown in Fig. 7.70.
Figure 7.70
Step 1 Of 5
Consider the expression for output noise voltage.
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, and is the output
resistance.
…… (2)
Here, is the transconductance, and is the output resistance.
…… (3)
Here, is the voltage gain, and is the output noise voltage.
Step 2 Of 5
Draw the small-signal model of the circuit.
Step 3 Of 5
Consider the total transconductance in Figure 1.
Here, is the transconductance of MOSFET , and is the transconductance of MOSFET .

Consider the total output resistance in Figure 1.
Here, is the output resistance of MOSFET , and is the output resistance of MOSFET .
…… (4)
Step 4 Of 5
Consider the expression for total noise voltage referred to the gate of when is equal to .
…… (5)
The total input-referred noise voltage of the circuit is equal to the total noise voltage referred to the gate of when the voltage gain of the
circuit is considered as equal to . That is,
Here, is the input noise voltage of the circuit, and is the total noise voltage referred to the gate of .
…… (6)
Step 5 Of 5
In equation (6), increasing the value of increases the input-referred noise voltage and decreases as the value of increases.
Therefore, the input-referred noise voltage of Figure 7.35 increases as the value of increases and decreases as the value of increases.
In equation (4), increasing the value of and decreases the input noise-referred voltage . Therefore, the input noise voltage of the
circuit in Figure 7.50 decreases as the value and increases.
Thus, the input-referred noise voltage is and result is compared with .

Question:
Calculate the input-referred thermal noise voltage of each circuit in Fig. 7.71. Assume that λ = γ = 0.
Figure 7.71
Step 1 Of 0
Question:
Calculate the input-referred thermal noise voltage of each circuit in Fig. 7.72. Assume that λ = γ = 0.
Figure 7.72
Step 1 Of 11
(a)
Consider the expression to calculate the output resistance of the circuit.
Consider the expression to calculate the output noise voltage using the circuit.
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, is the source
resistance and is the feedback resistance.
…… (1)
Step 2 Of 11
Consider the expression to calculate the small signal voltage gain of the circuit.
…… (2)
Consider the expression to calculate the input referred thermal noise voltage.
…… (3)
Step 3 Of 11
Substitute the equations (1) and (2) in equation (3).
Step 4 Of 11
Thus, the expression for the input-referred thermal noise voltage is
Step 5 Of 11
(b)
Consider the expression to calculate the output resistance of the circuit.

…… (4)
Step 6 Of 11
…… (5)
Step 7 Of 11

.
Step 8 Of 11
(c)
Refer to Figure 7.52 (c) in the textbook for MOSFET circuit.
…… (6)
Step 9 Of 11
…… (7)
Step 10 Of 11
(d)
Refer to Figure 7.52 (d) in the textbook for MOSFET circuit.
Step 11 Of 11

Thus, the expression for the input-referred thermal noise voltage is .
Question:
Calculate the input-referred thermal noise voltage and current of each circuit in Fig. 7.73. Assume that λ = γ
= 0.
Figure 7.73
Step 1 Of 15
(a)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, is the drain
resistance and is the gate resistance.
Step 2 Of 15
…… (1)

Step 3 Of 15
Consider the expression to calculate the input-referred noise current using the circuit.
Substitute for .
Thus, the expression for the input-referred thermal noise voltage and current is and
respectively.
Step 4 Of 15
(b)
Step 5 Of 15

Step 6 Of 15
Step 7 Of 15
Substitute for .
respectively.
Step 8 Of 15
(c)
Step 9 Of 15
Step 10 Of 15
Step 11 Of 15
Substitute for .
Thus, the expression for the input-referred thermal noise voltage is and thermal noise current
is .
Step 12 Of 15
(d)
Consider the expression to calculate the current gain across the resistor .
Consider the expression to calculate the current gain across the resistor .
Consider the expression to calculate the output noise current using the circuit.
…... (2)
Step 13 Of 15
…… (3)
Step 14 Of 15
Substitute the equation (2) in equation (3).
Step 15 Of 15
Substitute for .
Thus, the expression for the input-referred thermal noise voltage is and
thermal noise current is .
Question:
Calculate the input-referred thermal noise voltage and current of each circuit in Fig. 7.74. Assume that λ = γ
= 0.
Figure 7.74
Step 1 Of 17
(a)
Consider the expression to calculate theoutput noise voltage using the circuit.
Here,k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductanceand is the drain
resistance.
Step 2 Of 17
…… (1)
Step 3 Of 17
Substitute for .
respectively.
Step 4 Of 17
(b)
Step 5 Of 17

Step 6 Of 17
Substitute for .
respectively.
Step 7 Of 17
(c)

Step 8 Of 17
Step 9 Of 17
Substitute for .
Step 10 Of 17
respectively.
Step 11 Of 17
(d)
Step 12 Of 17
Step 13 Of 17
Substitute for .
respectively.
Step 14 Of 17
(e)
Refer to Figure 7.51 (e) in the textbook for MOSFET circuit.
Step 15 Of 17
Step 16 Of 17
Step 17 Of 17
Substitute for .
Thus, the expression for the input-referred thermal noise voltage and current is .
Question:
Calculate the input-referred 1/f noise voltage and current of Fig. 7.49 if the two capacitors are removed.
Figure 7.49
Step 1 Of 4
Consider the transconductance of all NMOS transistors are equal to each other.
Consider the transconductance of all PMOS transistors are equal to each other.
Consider input is shorted to ground.
In this case, the output depends only on MOSFETs , and .
Write the expression for output noise voltage .
Here,
is the gate oxide capacitance per unit area, is the width, L is the length, is the output resistance of MOSFET , is the output
resistance of MOSFET , is the noise factor, for flicker noise coefficient of NMOS, for flicker noise coefficient of PMOS, ,
and are transconductance of MOSFET , , and respectively.
Substitute for .
Step 2 Of 4
In this case, voltage gain of the circuit depends only on MOSFETs , and .
Write the expression for voltage gain.
Here,
is the transconductance of MOSFET , and is the backgate transconductance.

…… (1)
Step 3 Of 4
Consider input is open circuited.
In this case, the output depends only on MOSFETs , , and .
Consider the expression for output impedance when the input is open .
Step 4 Of 4
Find the input-referred noise current.

Substitute for .
Thus, the input-referred noise voltage is and input-referred noise current is
.
Question:
Calculate the input-referred 1/f noise voltage of the source follower shown in Fig. 7.51.
Figure 7.51 (a) Source follower; (b) circuit including noise sources.
Step 1 Of 5
Consider the expression for input noise voltage with flicker noise.
…… (1)
Here, K is a process-dependent constant on the order of , is the gate oxide capacitance per unit area, is the flicker noise, W is
the channel width, and L is the channel length.
…… (2)
Here, is the transconductance, and is the output resistance.
…… (3)
Step 2 Of 5
Consider the input noise voltage of the circuit is equal to input noise voltage with flicker noise.
…… (4)
…… (5)
Step 3 Of 5
Refer to Figure 7.42 in the textbook for source follower circuit.
Draw the small signal model of the circuit as shown in Figure 1.
Step 4 Of 5
Write the expression for the output resistance .
Here, is the output resistance of MOSFET , is the transconductance of MOSFET , is the output resistance of MOSFET
, and is the backgate transconductance of MOSFET .
In Figure 7.42, the voltage gain of the circuit is related to MOSFET .

Modify equation (2) for the voltage gain of the circuit.
Modify equation (2) for the voltage gain of MOSFET .
Modify equation (2) for the voltage gain of MOSFET .
The total output noise voltage of the circuit is sum of output noise voltage of MOSFET’s and .
Modify equation (5) for total output noise voltage of the circuit.
…… (6)
Modify equation (4) for the input noise voltage of MOSFET .
Modify equation (4) for the input noise voltage of MOSFET .

Step 5 Of 5
Thus, the input-referred noise voltage is .

Question:
Assuming that λ = γ = 0, calculate the input-referred thermal noise voltage of each circuit in Fig. 7.75. For
part (a), assume that gm3,4 = 0.5gm5,6.
Figure 7.75
Step 1 Of 6
(a)
Consider the expression for output noise voltage .
…… (1)
Here,
k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, and is the output
resistance.
…… (2)
Here,
is the transconductance, and is the output resistance.
…… (3)
Here,
is the voltage gain, and is the output noise voltage.
Step 2 Of 6
Find the transconductance of the circuit.
Consider is used to represent the output resistance.
Consider the term is used to represent the output noise voltage of the circuit.
…… (4)
Step 3 Of 6
Modify equation (2) for the voltage gain of the circuit used for part (a).
Consider the transconductance of MOSFET and are same.
Modify equation (3) for the circuit of part (a).
Thus, the input-referred thermal noise voltage is .
Step 4 Of 6
(b)
Find the transconductance of the circuit.
Consider is used to represent the output resistance.
Consider the term is used to represent the output noise voltage of the circuit.
Step 5 Of 6
…… (5)
Step 6 Of 6
Modify equation (2) for the voltage gain of the circuit used for part (b).
Modify equation (3) for the circuit of part (b).

Question:
Consider the degenerated common-source stage shown in Fig. 7.76.
(a) Calculate the input-referred thermal noise voltage if λ = γ = 0.
(b) Suppose linearity requirements necessitate that the dc voltage drop across RS be equal to the
overdrive voltage of M1. How does the thermal noise contributed by RS compare with that
contributed by M1?
Figure 7.76
Step 1 Of 12
(a)
Draw the small-signal model of the circuit as shown in Figure 1.
Step 2 Of 12
Apply Kirchhoff’s voltage law (KVL) for the circuit shown in Figure 1.

Here, is the transconductance of MOSFET , and is the drain resistance.
Consider the expression for voltage gain .
…… (1)
Here, is the output voltage, and is the input voltage.
Step 3 Of 12

Substitute for .
Step 4 Of 12
Write the expression for thermal noise due to .
Here, k is the Boltzmann constant, which has the value of , and T is the temperature.
Step 5 Of 12
Write the expression for thermal noise due to MOSFET .
Substitute for .
Step 6 Of 12
…… (2)

Write the expression for input thermal noise.
Modify the expression due to resistor .
Modify the expression due to resistor .
Substitute for .
Substitute for .
Step 7 Of 12
Write the expression for the output noise voltage .
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance of , and is the
source resistance.
Step 8 Of 12
Thus, the input-referred thermal noise voltage is,
Step 9 Of 12
(b)
…… (3)
Consider the expression for overdrive voltage of MOSFET.
…… (4)
…… (5)
Step 10 Of 12
The dc voltage drop across is equal to overdrive voltage of .
Substitute for overdrive voltage of .

Step 11 Of 12
Write the expression for input thermal noise due to MOSFET .
Substitute for .
…… (6)
Step 12 Of 12
Write the expression for input thermal noise due to source resistor .
…… (7)
Compare equations (6) and (7), the source resistance contributes three times more input thermal noise than the MOSFET when dc
voltage drop across is equal to overdrive voltage of .
Thus, the thermal noise contributed by is more compared with that contributed by .
Question:
Explain why Miller’s theorem cannot be applied to calculate the effect of the thermal noise of a floating
resistor.
Step 1 Of 9
Draw the simple MOSFET circuit with floating resistor connected between gate and output terminal as shown in Figure 1.
Step 2 Of 9
Step 3 Of 9
Apply Kirchhoff’s current law (KCL) for the circuit shown in Figure 2.
Substitute for .
Step 4 Of 9
…… (1)
Substitute for .
Step 5 Of 9
Write the expression for the output noise (thermal noise) voltage .
Here, k is the Boltzmann constant, which has the value of , T is the temperature, , and is the floating resistance.
…… (2)
…… (3)
Consider the miller effect:
Step 6 Of 9
In Miller circuit, feedback resistor is divided into two resistors. One resistor is connected between the supplied input and ground terminal. Second
resistor is connected between output and ground terminal.
Consider and are two resistors used in Miller circuit in terms of .
Modify Figure 2 for Miller circuit as shown in Figure 3.
Step 7 Of 9
Substitute for .
Substitute for .
…… (4)
Substitute for .
Substitute for .
Step 8 Of 9
Substitute for .
Substitute for .
…… (5)
Step 9 Of 9
Compare equations (3) and (5), the obtained expression of input thermal noise voltage using Miller circuit is different than the expression obtained
by direct method even though voltage gain is equal.
Therefore, Miller theorem cannot be applied to calculate the effect of the thermal noise of a floating resistor.
Question:
The circuit of Fig. 7.20 is designed with (W/L)1 = 50/0.5 and ID1 = 0.05 mA. Calculate the total rms thermal
noise voltage at the output in a 50-MHz bandwidth.
Figure 7.20
Step 1 Of 7
Consider the expression for output noise voltage.
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, and is the output
resistance.
…… (2)
channel length.
Step 2 Of 7
…… (3)
Here, is the channel length , and is the source/drain side diffusion length.
Substitute for L.
…… (4)

…… (5)
Step 3 Of 7
Refer Table 2.1 in the textbook for the level 1 model parameters for NMOS and PMOS devices.
Substitute for .
Step 4 Of 7
Step 5 Of 7
Substitute for F.
Consider the expression for output resistor.
…… (6)
Here, is the channel-length modulation coefficient, and is drain current.
Substitute for , and for
Step 6 Of 7
Substitute for , for k, for T and for in equation (1).
Step 7 Of 7
Consider the relation between total rms value of output noise, bandwidth and output noise voltage.
Here, is the output noise voltage, and BW is the bandwidth.
Substitute for , and 50 MHz for BW.

Thus, the total rms thermal noise voltage is rms.
Question:
For the circuit shown in Fig. 7.77, calculate the total output thermal and 1/f noise in a bandwidth [ fL, fH].
Assume that λ ≠ 0, but neglect other capacitances.
Figure 7.77
Step 1 Of 6
Here, is the transconductance, is the drain resistance, is the output resistance, is the capacitance and is the flicker noise.
Step 2 Of 6
Consider the expression to calculate the output noise voltage with flicker noise using the circuit.
Here, k is the Boltzmann constant, which has the value of , T is the temperature, K is a process-dependent constant on the order of
, is the gate oxide capacitance per unit area, W is the channel width, and L is the channel length.
…… (1)
Step 3 Of 6
The flicker noise occurs in the bandwidth of . Therefore, rewrite the equation (1) as follows to calculate the total output thermal and
noise.
...... (2)
Step 4 Of 6
Assume the following to reduce the integral part in equation (2).
Rewrite the equation using integral substitution.
Step 5 Of 6
Step 6 Of 6
Thus, the expression for the total output thermal and noise for a bandwidth is
.
Question:
Suppose in the circuit of Fig. 7.42, (W/L)1,2 = 50/0.5 and ID1 = |ID2| = 0.5 mA. What is the input-referred
thermal noise voltage?
Figure 7.42
Step 1 Of 7
Refer to Figure 7.35 in the textbook for MOSFET amplifier circuit.
Consider the expression for total noise voltage at gate of MOSFET .
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance of ,and is the
transconductance of .
…… (2)
channel length.
Step 2 Of 7
If MOS device is in saturation region, the length of the device (L) is equal to .
…… (3)
Here, is the channel length , and is the source/drain side diffusion.
Substitute for L.
…… (4)
Substitute for L.
…… (5)
Step 3 Of 7
…… (6)
Substitute for .
Step 4 Of 7
Here, is the source/drain side diffusion length of NMOS device.

Step 5 Of 7
Substitute for F.
Step 6 Of 7
Here, is the source/drain side diffusion length of PMOS device.
Substitute for F.
Step 7 Of 7
Substitute for , for , for k, and for T in equation (1).

Question:
The circuit of Fig. 7.42 is modified as depicted in Fig. 7.78.
(a) Calculate the input-referred thermal noise voltage.
(b) For a given bias current and output voltage swing, what value of RS minimizes the input-
referred thermal noise?
Figure 7.42
Figure 7.78
Step 1 Of 8
(a)
Step 2 Of 8
Apply Kirchhoff’s voltage law (KVL) for the circuit shown in Figure 1.
Here, is the transconductance of MOSFET , and is the output resistance.
…… (1)
Here, is the output resistance of MOSFET , is the output resistance of MOSFET , is the transconductance of , and is
the source resistance.
Step 3 Of 8

Substitute for .
Step 4 Of 8
Write the expression for thermal noise due to .
…… (2)
Here, k is the Boltzmann constant, which has the value of , and T is the temperature.
Substitute for .
…… (3)
Step 5 Of 8
Substitute for .
…… (4)
Step 6 Of 8
Write the expression for the output noise voltage .
Step 7 Of 8
Modify equation (1) for noise voltage.
…… (5)
Thus, the input-referred thermal noise voltage is,
Step 8 Of 8
(b)
From equation (2), write the relation between and .
The input-referred thermal noise voltage occurs due to MOSFET is independent of .

From equation (5), total input-referred thermal noise voltage of the circuit is summation of input-referred thermal noise voltage occurs due to
MOSFET , MOSFET and resistor .
Since, and are inversely proportional to , the large value of minimizes the input-referred thermal noise voltage of the
circuit.
Thus, the value of must be large enough to minimize the input-referred thermal noise voltage of the circuit.
Question:
A common-gate stage incorporates an NMOS device with W/L = 50/0.5 biased at ID = 1 mA and a load
resistor of 1 kΩ. Calculate the input-referred thermal noise voltage and current.
Step 1 Of 7
Consider the expression for input-referred noise voltage of common-gate stage.
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, is the backgate
transconductance and is the load resistance.
Consider the expression for input-referred noise current of common-gate stage.
…… (2)
…… (3)
channel length.
Step 2 Of 7
Consider the source/drain side diffusion effect for the MOSFET, so that the length of the device (L) is equal to .
…… (4)
Substitute for L.
…… (5)
…… (6)
Substitute for .
Step 3 Of 7
Step 4 Of 7
Step 5 Of 7
Substitute for F.
Step 6 Of 7
Neglect the body effect of the MOSFET. So, the value of becomes zero.
Step 7 Of 7
Substitute for k, for T and for in equation (2).

Thus, the input-referred thermal noise voltage and current is and respectively.
Question:
The circuit of Fig. 7.48 is designed with (W/L)1 = 50/0.5, ID1 = ID2 = 0.5 mA, and RD = 1 kΩ.
(a) Determine (W/L)2 such that the contribution of M2 to the input-referred thermal noise current
(not current squared) is one-fifth of that due to RD.
(b) Now calculate the minimum value of Vb to place M2 at the edge of the triode region. What is
the maximum allowable output voltage swing?
Figure 7.48 Noise contributed by bias-current source.
Step 1 Of 12
(a)
Refer to Figure 7.39 in the textbook for MOSFET circuit in which noise contributed by bias current source.
The input-referred thermal noise current is occurs due to resistance and MOSFET .
Consider the expression for input-referred thermal noise current due to resistance .
Here, k is the Boltzmann constant, which has the value of , T is the temperature, and is the drain resistance.
Consider the expression for input-referred thermal noise current due to MOSFET .
Here, is the transconductance of MOSFET .

Consider the expression for total input-referred thermal noise current.

Take square root on both sides.
Step 2 Of 12
Consider the contribution of for input-referred voltage is one-fifth of . Thus, the relation between and is written as,
Substitute for .
Step 3 Of 12
…… (1)
channel length.
…… (2)
Substitute for .
Step 4 Of 12
Step 5 Of 12
Here, is the drain current of MOSFET , is mobility of charge carriers of NMOS device, is the gate oxide capacitance per unit
area, is the aspect ratio of MOSFET .

Take square of the expression.
Thus, the obtained value of is .
Step 6 Of 12
(b)
…… (3)

Step 7 Of 12
diffusion.
…… (4)
Here, is the channel length that is equal to , and is the source/drain side diffusion.
area, is the aspect ratio of MOSFET .
Step 8 Of 12
Substitute for L.
…… (5)
Step 9 Of 12
Substitute for , for , for , for ,and for in equation (5).

Step 10 Of 12
…… (6)
Step 11 Of 12
Re-write equation (6).
Consider the value of threshold voltage for all MOSFET .
Consider the expression for minimum value of to place MOSFET at the edge of the triode region by neglecting the body effect.
Substitute for .
Step 12 Of 12
Consider the expression for maximum output voltage swing.
Here, is the positive voltage applied to the circuit.
Substitute 3V for , for , and for .
Thus, the minimum value of required to place at the edge of the triode region is and the maximum output voltage swing is
.
Question:
Design the circuit of Fig. 7.48 for an input-referred thermal noise voltage of and maximum output
swing. Assume that ID1 = ID2 = 0.5 mA.
Figure 7.48 Noise contributed by bias-current source.
Step 1 Of 11
Refer to Figure 7.37 in the textbook for CG stage circuit.
Consider the expression for input noise voltage.
…… (1)
Here,
k is the Boltzmann constant and has the constant value of , T is the temperature, is the drain resistor, is the
transconductance of MOSFET, and is the back gate transconductance of MOSFET.
Refer to Figure 7.39 in the textbook for noise contributed by bias current source.
Consider the body effect of MOSFETs is neglected .
Substitute 0 for .

Substitute for .
…… (2)
Step 2 Of 11
Consider the room temperature as .
Substitute for T, and for k in equation (2).
…… (3)
Step 3 Of 11
…… (4)
Here,
is the drain current, is the gate-to-source voltage, and is the threshold voltage.

…… (5)
Step 4 Of 11
Consider the term for and for .
…… (6)
…… (7)
…… (8)
Step 5 Of 11
The value of overdrive voltage is very small and in the range of mV. Consider the value of overdrive voltage of MOSFET that is
equals to 0.562V.

Step 6 Of 11
The same drain current flows through MOSFET’s and , both MOSFET’s are identical to each other.
…… (9)
…… (10)
Substitute for .
Find the value of output swing.
Step 7 Of 11
Step 8 Of 11
…… (11)
is the drain current, is the gate oxide capacitance per unit area, is the mobility of NMOS, is the width, and is the length.

…… (12)
Step 9 Of 11
…… (13)
Substitute for .
Step 10 Of 11

Step 11 Of 11
Consider the threshold voltage of MOSFET’s is .
Find the value of .
Substitute for .
Substitute for , and Substitute for .
Thus, obtained value of and is and maximum output swing is .

Question:
Consider the circuit of Fig. 7.49. If (W/L)1−3 = 50/0.5 and ID1−3 = 0.5 mA, determine the input-referred
thermal noise voltage and current.
Figure 7.49
Step 1 Of 11
Consider the expression for the input-referred noise voltage.
…… (1)
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance of , is the
transconductance of , and is the backgate transconductance of .
Consider the expression for the input-referred noise current of common-gate stage.
…… (2)
…… (3)
channel length.
Step 2 Of 11
Consider the source/drain side diffusion for the MOSFET, so that the length of the device (L) is equal to .
…… (4)

Substitute for L.
…… (5)
Substitute for L.
…… (6)
…… (7)
Step 3 Of 11
Substitute for .
Step 4 Of 11
Here, is the source/drain side diffusion length of NMOS device.
Step 5 Of 11
Step 6 Of 11
Substitute for F.
Since the MOSFETs and are identical, the value of is same as .
Substitute for .
Step 7 Of 11
Here, is the source/drain side diffusion length of PMOS device.
Step 8 Of 11

Substitute for F.
Step 9 Of 11
Neglect the body effect of the MOSFET. So, the value of becomes zero.
Step 10 Of 11

Step 11 Of 11
Substitute for k, for T, for , and for in equation (2).
Thus, the input-referred thermal noise voltage and current is and respectively.
Question:
The circuit of Fig. 7.49 is designed with (W/L)1 = 50/0.5 and ID1−3 = 0.5 mA. If an output swing of 2 V is
required, estimate by iteration the dimensions of M2 and M3 such that the input-referred thermal noise
current is minimum.
Figure 7.49
Step 1 Of 13
Consider the expression for input-referred noise current.
…… (1)
Here, k is the Boltzmann constant and has the constant value of , T is the temperature, is the transconductance of MOSFET
, and is the transconductance of MOSFET .
…… (2)
is the drain current, is the gate oxide capacitance per unit area, is the mobility of NMOS, is the width, and is the effective
length.
…… (3)
Here,
is the effective length, is the total length, and is the amount of side diffusion.
Step 2 Of 13
Consider the length and width of the MOSFET’s are in micro meter range.

Step 3 Of 13
…… (4)
Substitute for .
Modify equation (4) for NMOS FET.
Step 4 Of 13

Step 5 Of 13
…… (5)
Here,
…… (6)
Step 6 Of 13
Consider the term to represent .
…… (7)
Substitute 1 for x.
Substitute 2 for x in equation (7).
Substitute 3 for x in equation (7).
Substitute for in equation (5)

Find the output swing.
Substitute for , for Output swing, and for .
…… (8)
Step 7 Of 13
Substitute for .
Substitute for .
…… (9)
…… (10)
Step 8 Of 13
The drain current of all transistor is same.

To minimize the input thermal-noise current, the value of must be same as .
Step 9 Of 13
…… (11)
Substitute for .
Step 10 Of 13

Step 11 Of 13
Modify equation (4) for PMOS FET.
Step 12 Of 13
Step 13 Of 13

Thus, the required dimension of MOSFET is and dimension of MOSFET is .
Question:
The source follower of Fig. 7.51 is to provide an output resistance of 100 Ω with a bias current of 0.1 mA.
(a) Calculate (W/L)1.
(b) Determine (W/L)2 such that the input-referred thermal noise voltage (not voltage squared)
contributed by M2 is one-fifth of that due to M1. What is the maximum output swing?.
Figure 7.51 (a) Source follower; (b) circuit including noise sources.
Step 1 Of 8
(a)
Consider the body effect and the resistances and are neglected.
…… (1)
Here,
is the transconductance of MOSFET .

…… (2)
Here,
is the drain current, is the gate oxide capacitance per unit area, is the mobility of NMOS, is the width, and is the length.
Step 2 Of 8
…… (3)
Substitute for .
Step 3 Of 8
Thus, the value of is .

Step 4 Of 8
(b)
Consider the expression for total noise voltage referred to the gate of MOSFET .
…… (4)
The input-referred thermal noise voltage (not voltage squared) contributed by MOSFET is one-fifth due to MOSFET .
Substitute for .
Step 5 Of 8
The current flow through MOSFET is same as MOSFET .
Substitute for .
…… (5)
Modify equation (5) for MOSFET

Step 6 Of 8
Step 7 Of 8
Consider the threshold voltage of MOSFET is .

Substitute for .
…… (6)
Substitute for .
Step 8 Of 8
Find the output swing.
Thus, the maximum output sing is .

Question:
The cascode stage of Fig. 7.52(a) exhibits a capacitance CX from node X to ground. Neglecting other
capacitances, determine the input-referred thermal noise voltage.
Figure 7.52 (a) Cascode stage; (b) noise of M2 modeled by a current source; (c) noise of M2 modeled by a
voltage source.
Step 1 Of 4
Refer to Figure 7.43 (a) in the textbook. The cascode stage circuit exhibits a capacitance from the node to the ground.
Here, k is the Boltzmann constant, which has the value of , T is the temperature, is the transconductance, is the drain
resistance, is the angular frequency and is the capacitance.
…… (1)
Step 2 Of 4
…… (2)
Step 3 Of 4
…… (3)

Step 4 Of 4
Thus, the expression for the input-referred thermal noise voltage is .
Question:
Determine the input-referred thermal and 1/f noise voltages of the circuits shown in Fig. 7.79 and compare
the results. Assume that the circuits draw equal supply currents.
Figure 7.79
Step 1 Of 0
Question:
Repeat the analysis in Example 7.13 but assume that λ > 0.
Example 7.13
Step 1 Of 0
Question:
Suppose the circuit of Fig. 7.38(a) is driven by a finite source impedance, as shown in Fig. 7.80. Assume that
λ = 0, and neglect the noise of RS.
(a) Determine the output noise voltage of the circuit.
(b) In a manner similar to the analysis of Fig. 7.37, compute in terms of Vn,RF and Vn,M1 the input-
referred noise voltage and current, paying close attention to their correlation.
Figure 7.38
Figure 7.80
Figure 7.37 CS stage driven by a source impedance.
(c) Using superposition of voltages and currents (not powers), calculate the output noise voltage in
terms of Vn,in and In,in, as obtained in (b). Now make the substitutions and
. Is this result the same as that derived in (a)?
Step 1 Of 0
Question:
Consider the circuits in Figs. 7.39(c) and (d), but include CGS and a noiseless impedance Z1 in series with
the gate. Derive expressions for In,out1 and In,out2. Does the lemma hold in this case?
Step 1 Of 0
Question:
Repeat Example 7.14 while including CGS and an impedance Z1 in series with the gate. Does the lemma
hold in this case?
Example 7.14
Figure 7.40
Step 1 Of 0
Question:
Model the thermal noise of M1 in Fig. 7.49 by a voltage source in series with its gate and assuming the input
is open,
(a) Determine the resulting output voltage. (The voltage gain for a degenerated CS stage was
derived in Chapter 3.)
(b) Nowrefer this voltage to the input as a current and compare the result with the contributions of
M2 and M3.
Figure 7.49
Step 1 Of 0
Question:
Figure 7.81 shows a noiseless amplifier driven by a source resistance of RS. If the amplifier can be modeled
by a low-frequency gain of A0 and a single pole at ω0, determine the total integrated noise at the output due
to RS.
Figure 7.81
Step 1 Of 0
Question:
Considering only thermal noise in Fig. 7.82, determine the output noise spectrum and the total integrated
noise. Assume that λ > 0.
Figure 7.82
Step 1 Of 0
Question:
Calculate the input-referred thermal and flicker noise of the circuit shown in Fig. 7.83, where the output of
interest is ID3 − ID4. Consider two cases: (a) the current sources are ideal, and (b) the current sources are
realized by MOSFETs. Neglect channel-length modulation and body effect.
Figure 7.83
Step 1 Of 0
Question:
Consider the circuit of Fig. 8.3(b), assuming that I1 is ideal and gm1rO1 cannot exceed 50. If a gain error of
less than 5% is required, what is the maximum closed-loop voltage gain that can be achieved by this
topology? What is the low-frequency closed-loop output impedance under this condition?
Figure 8.3 (a) Simple common-source stage; (b) circuit of (a) with feedback.
Step 1 Of 3
Refer to Figure 8.3 (b) in the textbook for the simple common-source stage circuit with feedback.
Consider the expression for closed-loop voltage gain for the circuit in the figure.
…… (1)
Here,
is the input voltage, is the output voltage, is the transconductance of the MOSFET, is the output resistance, and are
capacitors in the circuit.
Consider the expression for closed-loop voltage gain when the term is sufficiently a large value.
…… (2)
As the required gain error is less than 5%, rewrite the expression.
Step 2 Of 3
Substitute 50 for .
Equation (2) is the maximum closed-loop voltage gain. Therefore, substitute 1.63 for in equation (2).
Consider the absolute value for the gain and rewrite the expression.
Step 3 Of 3
Consider the expression for low-frequency closed-loop output impedance for the circuit in the figure.
Rewrite the expression.
Substitute 50 for and 1.63 for .

Thus, the maximum closed-loop voltage gain achieved in the topology is and low-frequency closed-loop output impedance is .
Question:
In the circuit of Fig. 8.8(a), assume that (W/L)1 = 50/0.5, (W/L)2 = 100/0.5, RD = 2 kΩ, and C2 = C1.
Neglecting channel-length modulation and body effect, determine the bias current of M1 and M2 such that
the input resistance at low frequencies is equal to 50 Ω.
Figure 8.8 (a) Common-gate circuit with feedback; (b) open-loop circuit; (c) calculation of input resistance.
Step 1 Of 4
Refer to Figure 8.7 (a) in the textbook for the common-gate circuit with feedback.
Neglect the channel-length modulation, body effect of the MOSFET in the circuit, and consider the expression for input resistance of the closed-
loop circuit for the circuit in the figure.
…… (1)
Here, is the transconductance of the MOSFET , is the transconductance of the MOSFET , is the drain resistance, and
are capacitance of capacitors in the circuit.
Consider the expression for transconductance of a MOSFET.
…… (2)
Here, is the process transconductance parameter, which is , is the gate width to length ratio of the MOSFET, and is the bias
current of the MOSFET.
Step 2 Of 4
Modify equation (2) for transconductance of .
…… (3)
Here, is the gate width to length ratio of and is the bias current of .
Modify equation (2) for transconductance of .
…… (4)
Here, is the gate width to length ratio of and is the bias current of .
From the circuit in the Figure 8.7 (a) in the textbook, . Therefore, substitute for and simplify the expression.
Rearrange the equation for the expression of .
Step 3 Of 4
Consider the value of process transconductance parameter as .
As , substitute for .
Rearrange the expression to obtain the value of .
Simplify the quadratic expression and find the value of .
As the conductance is always a positive value, ignore the negative value and writhe transconductance of .
Step 4 Of 4
Rearrange equation (1) for .

As , the value of is .
Thus, the bias current of and are and , respectively.

Question:
Calculate the output impedance of the circuit shown in Fig. 8.9(a) at relatively low frequencies if RD is
replaced by an ideal current source.
Figure 8.9 (a) CS stage with feedback; (b) calculation of output resistance.
Step 1 Of 2
Refer to Figure 8.8 (a) in the textbook for the CS stage circuit with feedback.
Consider the expression for output impedance of the circuit in the figure.
…… (1)
Here, is the transconductance of the MOSFET , is the transconductance of the MOSFET , is the drain resistance, is the
source resistance, and are capacitance of capacitors in the circuit.
Rewrite equation (1).
…… (2)
Step 2 Of 2
is replaced by an ideal current source. As the internal resistance of ideal current source is infinity, the value of becomes infinite.

At relatively low frequencies, , so that neglect 1 in numerator. Therefore, rewrite the expression.
Thus, the output impedance of the circuit is .

Question:
Consider the example illustrated in Fig. 8.11. Suppose an overall voltage gain of 500 is required with
maximum bandwidth. How many stages with what gain per stage must be placed in a cascade? (Hint: first
find the 3-Db bandwidth of a cascade of n identical stages in terms of that of each stage.)
Figure 8.11 Amplification of a 20-MHz square wave by (a) a 10-MHz amplifier and (b) a cascade of two
100-MHz feedback amplifiers.
Step 1 Of 4
Refer to Figure 8.10 for amplification of a 20-MHz square wave by 20-MHz amplifier and cascade of two 100-MHz feedback amplifiers.
Consider the bandwidth of each stage of an amplifier as .

Consider the overall amplifier consists of n-stages (cascade connection of n identical amplifiers).
Consider the expression for magnitude of the voltage gain of the overall amplifier at frequencies.
The voltage gain at frequencies is , substitute for and for .

Take square on both sides of the expression.
Simplify and rewrite the expression.
…… (1)
Step 2 Of 4
Consider the product of voltage gain and frequency as k and write the expression for overall voltage gain of the amplifier with maximum
bandwidth.
…… (2)
Take the natural log on both sides of the expression.
…… (3)
Take the natural log on both sides of equation (1).
Divide the expression with equation (3).
Step 3 Of 4
Further, simplify the expression.
Differentiate with respect to on both sides of the expression.
As , substitute 0 for .

Therefore, the gain per stage of the overall amplifier is 1.67.
Step 4 Of 4
Take natural log on both sides of the expression.
Rearrange the expression for n.
Thus, number of stages require to attain the overall voltage gain of 500 and the gain per stage are and , respectively.
Question:
If in Fig. 8.22(b), amplifier A0 exhibits an output impedance of R0, calculate the closed-loop voltage gain and
output impedance, taking into account loading effects.
Figure 8.22 (a) Amplifier with output sensed by a resistive divider; (b) voltage-voltage feedback amplifier.
Step 1 Of 3
Refer to Figure 8.18 (b) in the textbook for the voltage-voltage feedback amplifier.
Consider the expression for closed-loop voltage gain for the circuit in the figure.
…… (1)
Here, is the open-loop voltage gain, is the loop gain, is the feedback factor, and is the low-frequency gain.
Consider the expression for loop gain in the circuit.
…… (2)
Here, is the resistance of resistors in the circuit and is the gain of transimpedance amplifier for the feed forward path.
Consider the expression for open-loop voltage gain of the circuit.
…… (3)
Here, is amplifier transimpedance.
Step 2 Of 3
From equations (2) and (3), substitute for and for in equation (1).
Step 3 Of 3
…… (4)
Here, is the output impedance of the open-loop of the circuit.

Consider the expression for output impedance of the open-loop of the circuit.
Thus, the closed-loop voltage gain and output impedance of the circuit are and
, respectively.
Question:
Consider the circuit of Fig. 8.25(a), assuming that (W/L)1,2 = 50/0.5 and (W/L)3,4 = 100/0.5. If ISS = 1 mA,
what is the maximum closed-loop voltage gain that can be achieved if the gain error is to remain below 5%?
Figure 8.25
Step 1 Of 12
Consider the expression for closed-loop voltage gain in the circuit.
…… (1)
Here, is the open-loop voltage gain and is the loop gain in the circuit.
Consider the expression to find open-loop voltage gain in the circuit.
…… (2)
Here, , are capacitances in the circuit.
Step 2 Of 12
Consider the expression to find the loop gain in the circuit.
…… (3)
Here, is the transconductance of MOSFET , is the output resistance of MOSFET , and is the output resistance of MOSFET
.
Consider the expression to find the transconductance of MOSFET .
…… (4)
Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, channel width to length ratio
of MOSFET , and is the bias current of MOSFET .
From the table, the value of is .
Step 3 Of 12
…… (5)
Substitute for .
Step 4 Of 12
From the circuit, the bias current of MOSFET is half of the value of .
Substitute .
Step 5 Of 12

Step 6 Of 12
Step 7 Of 12
Consider the expression to find the output resistance of the MOSFET .
…… (6)
Here, is the channel-length modulation coefficient for NMOS device and is the bias current of MOSFET .
From the Table 2.1 in the textbook, the value of is .
Substitute .
Step 8 Of 12
…… (7)
Here, is the channel-length modulation coefficient for PMOS device and is the bias current of MOSFET .
Step 9 Of 12

From the circuit, the bias current of MOSFET is equal to the bias current of MOSFET .
Step 10 Of 12
Step 11 Of 12
As the gain error is to be remained below 5%, write the expression to satisfy the condition.
Substitute for .
Substitute for .
Step 12 Of 12
Consider the value of as 1.2868.
Thus, the maximum closed-loop voltage gain that can be achieved when the gain error is to remain below 5% is .
Question:
The circuit of Fig. 8.42 can operate as a transimpedance amplifier if Iout flows through a resistor, RD2,
connected to VDD, producing an output voltage. Replacing RS with an ideal current source and assuming
that λ = γ = 0, calculate the transimpedance of the resulting circuit. Also, calculate the input-referred noise
current per unit bandwidth.
Figure 8.42
Step 1 Of 7
Refer to Figure 8.36 in the textbook for the current-current feedback circuit.
Connect a resistor to the bias voltage , replace the resistor in the circuit with an ideal current source, and redraw the circuit as shown
in Figure 1.
Step 2 Of 7
Consider the expression for transimpedance in the circuit.
…… (1)
Here, is the output voltage in the circuit and is the input current in the circuit.
From the circuit in Figure 1, the output current in the circuit is equal to the input current.
…… (2)
Consider the expression for output voltage in the circuit.

Step 3 Of 7
Redraw the circuit in Figure 1 to find the input-referred noise current per unit bandwidth as shown in Figure 2.
Step 4 Of 7
From the circuit in Figure 2, write the expression for output current.
…… (3)
Here, is the voltage at node X in the circuit, is the voltage at node Y in the circuit, and is the transconductance of the MOSFET .
Consider the expression for voltage in the circuit.
…… (4)
Here, is the transconductance of the MOSFET .

Consider the expression for voltage in the circuit.
…… (5)
Step 5 Of 7
From equations (4) and (5), substitute for and for in equation (3).
Step 6 Of 7
…… (6)
Step 7 Of 7
Consider the expression for output current of the circuit in Figure 2 when the input-referred noise current is applied to the circuit.
…… (7)
Thus, the transimpedance and input-referred noise current per unit bandwidth in the circuit are and
, respectively.
Question:
For the circuit of Fig. 8.51(a), calculate the closed-loop gain without neglecting G12 I2. Prove that this term
can be neglected if .
Figure 8.51 Voltage-voltage feedback circuit with (a) feedback network represented by a G model and (b) a
simplified G model.
Step 1 Of 5
Refer to Figure 8.38 (a) in the textbook for the voltage-voltage feedback circuit with feedback network represented by a G model.
From the circuit in the figure, use the Kirchhoff’s voltage law (KVL) and write the expression for input voltage.
…… (1)
Here,
is the input voltage, is the input current, is the input impedance, is the current through , is the short circuit output
impedance, is the open circuit voltage gain, and is the output voltage.
From the circuit in the Figure, . Therefore, substitute for in equation (1).
…… (2)
Apply Kirchhoff’s current law (KCL) at in the circuit in the Figure 8.38 (a).
…… (3)
Here,
is the forward gain, is the voltage across , is the output impedance, is the open circuit input admittance, and is the short
circuit reverse current gain.
Step 2 Of 5
From the circuit in the figure, write the expression for .

Rearrange the expression for input current.
Rearrange the expression for closed-loop voltage gain .
…… (4)
Step 3 Of 5
If , neglect the effect of and rewrite the equation (4).
…… (5)
Step 4 Of 5
Neglect the term in the circuit and redraw the circuit as shown in Figure 1.
Step 5 Of 5
Apply KCL at in the circuit in Figure 1.
Substitute for .
Rearrange the expression for input current.

Rearrange the expression for closed-loop voltage gain .
As the obtained expression is same as the expression in equation (5), the term can be neglected when .
Thus, the closed-loop voltage gain without neglecting the term is and the term can
be neglected when .
Question:
Calculate the loop gain of the circuit in Fig. 8.54 by breaking the loop at node X. Why is this result
somewhat different from G21 Av,open?
Figure 8.54
Step 1 Of 6
Refer to Figure 8.41 in the textbook for a voltage-voltage feedback circuit.
Redraw the circuit by breaking the loop at node X as shown in Figure 1.
Step 2 Of 6
Consider the expression for the current pass through the resistor in the circuit in Figure 1.
…… (1)
Here, is the transconductance of the MOSFET , is the feedback resistance in the circuit, is the drain resistance of the MOSFET
, and is the source resistance in the circuit.
Write the expression for current through the MOSFET (current through the resistance ) from the circuit in Figure 1.
Substitute for .
Step 3 Of 6
The loop gain for the circuit can be obtained by multiplying the current with . Therefore, write the expression for loop gain.
Substitute for .
…… (2)
Step 4 Of 6
Consider the expression for open-loop gain of the circuit.
…… (3)
Step 5 Of 6
Consider the expression for open circuit voltage gain for the circuit.
…… (4)
Use equations (3), (4), and write the expression for loop gain .
Step 6 Of 6
…… (5)
Observe equations (2) and (5). From the analysis, the loop gain in equation (2) provides accurate results compare to the loop gain in equation (5)
since the loop gain neglects the signal-propagating path from input to the output through the feedback network.
Thus, the loop gain of the circuit is and it provides accurate results than the loop gain .
Question:
Using feedback techniques, calculate the input and output impedance and voltage gain of each circuit in Fig.
8.95.
Figure 8.95
Step 1 Of 27
Use the voltage-current feedback technique and redraw the circuit as shown in Figure 1 to obtain the input impedance, output impedance, and
closed-loop voltage gain in the circuit.
Step 2 Of 27
Consider the expression for input impedance of closed-loop circuit.
…… (1)
Here, is the input impedance of open-loop circuit and is the loop-gain in the circuit.
Write the expression for input impedance of open-loop circuit from the circuit in Figure 1.
Here, is the transconductance of MOSFET .
Step 3 Of 27
Here, is the transconductance of MOSFET , is the output resistance of MOSFET , and is the resistance in the circuit.
From the circuit, the value of tends to infinity for the closed-loop circuit. Therefore, substitute for .
Step 4 Of 27
Consider the expression for output impedance of closed-loop circuit.
…… (2)
Step 5 Of 27
Here, is the output impedance of open-loop circuit.

Consider the expression for output impedance of open-loop circuit.

Step 6 Of 27
Step 7 Of 27
Consider the expression for closed-loop voltage gain in the circuit.
…… (3)
Here, is the open-loop voltage gain.


Step 8 Of 27
Step 9 Of 27
Step 10 Of 27
Redraw the circuit as shown in Figure 2 to obtain the input impedance, output impedance, and closed-loop voltage gain in the circuit.
Step 11 Of 27
Here, is the output resistance of MOSFET .

Step 12 Of 27
Step 13 Of 27
Step 14 Of 27
Step 15 Of 27
Step 16 Of 27
Step 17 Of 27

Step 18 Of 27
Step 19 Of 27
Step 20 Of 27
Step 21 Of 27
Step 22 Of 27
Step 23 Of 27
simplify the expression.

Step 24 Of 27
Step 25 Of 27
Step 26 Of 27
Thus, the input impedance, output impedance, and voltage gain of the circuit in Figure 8.57 (a) are , , and ,
respectively.
The input impedance, output impedance, and voltage gain of the circuit in Figure 8.57 (b) are , , and ,
respectively.
The input impedance, output impedance, and voltage gain of the circuit in Figure 8.57 (c) are , , and , respectively.
Step 27 Of 27
The input impedance, output impedance, and voltage gain of the circuit in Figure 8.57 (d) are , , and
, respectively.
Question:
Using feedback techniques, calculate the input and output impedances of each circuit in Fig. 8.96.
Figure 8.96
Step 1 Of 7
Use the voltage-voltage feedback technique and write the expression for input impedance in the circuit.
…… (1)
Here, is the capacitance of the capacitor in the circuit and is the transconductance of the MOSFET .
Simplify equation (1).
Step 2 Of 7
Consider the expression to find the output resistance in the circuit in Figure 8.58 (a) in the textbook.
…… (2)
Here, is the output channel resistances of MOSFET.

As , neglect the component in the denominator and rewrite the expression.

Step 3 Of 7
…… (3)
Here, is the transconductance of the MOSFET and is the transconductance of the MOSFET .
Step 4 Of 7
Consider the expression to find the output resistance in the circuit in Figure 8.58 (b) in the textbook.
Step 5 Of 7
Step 6 Of 7
Consider the expression to find the output resistance in the circuit.
Substitute for .
Step 7 Of 7
Thus, the input and output resistances of the circuit in Figure 8.58 (a) are and , respectively.
The input and output resistances of the circuit in Figure 8.58 (b) are and , respectively.
The input and output resistances of the circuit in Figure 8.58 (c) are and , respectively.
Question:
Consider the circuit of Fig. 8.54(a), assuming that (W/L)1 = (W/L)2 = 50/0.5, λ = γ = 0, and each resistor is
equal to 2 kΩ. If ID2 = 1 mA, what is the bias current of M1? What value of Vin gives such a current?
Calculate the overall voltage gain.
Figure 8.54
Step 1 Of 16
Refer to Figure 8.41 (a) in the textbook for a voltage-voltage feedback circuit.
Step 2 Of 16
Consider the expression for bias current of the MOSFET from the circuit in Figure 1.
…… (1)
Here, is the bias voltage, is the drain resistance of the MOSFET , and is the voltage at node X.
Consider the expression for bias current of the MOSFET .
…… (2)
Here, is mobility of charge carriers in the PMOS device, is the gate oxide capacitance per unit area, W is the channel width, L is the
Step 3 Of 16
From the table, write the required parameters.
…… (3)
Step 4 Of 16
Substitute for .
Step 5 Of 16
Substitute for , for , for , for W, for , 3 V for , for , and 0 for in
equation (2).
Step 6 Of 16
Substitute 3 V for , 1.4774 V for , and for in equation (1).
Step 7 Of 16
Step 8 Of 16

Substitute for .
Step 9 Of 16
Step 10 Of 16
…… (4)
Here, is mobility of charge carriers in the NMOS device, is the threshold voltage of NMOS device, and is the input voltage.
Substitute for , for , for , for W, for , 1.6817 V for , 0.7 V for , and 0
for in equation (4).
Step 11 Of 16
Consider the expression for open-loop gain of the circuit.

…… (5)
Here, is the transconductance of the MOSFET and is the transconductance of the MOSFET .
Substitute for , 2.7185 V for , 1.6817 V for , and 0.7 V for .
Step 12 Of 16
Substitute for ,3 V for , 1.4774 V for , and for .
Step 13 Of 16
Substitute for , for , for , for , for , and for in equation (5).
Step 14 Of 16
Consider the expression for closed-loop gain of the circuit.
…… (6)
Here, is the open circuit voltage gain for the circuit.
Step 15 Of 16
Consider the expression for open circuit voltage gain for the circuit.
Step 16 Of 16
Substitute 6.0435 for and 0.5 for in equation (6).
Thus, the bias current of the MOSFET , input voltage , open-loop gain, and closed-loop gain of the circuit are , ,
, and respectively.
Question:
Suppose the amplifier of the circuit shown in Fig. 8.22 has an open-loop transfer function A0/(1 + s/ω0) and
an output resistance R0. Calculate the output impedance of the closed-loop circuit and plot the magnitude as
a function of frequency. Explain the behavior.
Figure 8.22 (a) Amplifier with output sensed by a resistive divider; (b) voltage-voltage feedback amplifier.
Step 1 Of 6
Refer to Figure 8.18 in the textbook for the amplifier circuit.
…… (1)
Here, is the output impedance of the open-loop of the circuit, is the loop gain, is the feedback factor, and is the low-
frequency gain.
b …… (2)
Here, , are the resistance of resistors in the circuit, is the output resistance, and is the frequency at zero of the transfer function.
Step 2 Of 6
Consider the expression for output impedance of the open-loop of the circuit.

Step 3 Of 6
Find the final value of closed-loop output impedance.
Step 4 Of 6
The zero of the transfer function locates at and pole locates at .
Step 5 Of 6
From the analysis, draw the magnitude of the closed-loop output impedance with respect to frequency as shown in Figure 1.
Step 6 Of 6
From Figure 1, the closed-loop output impedance reduces slightly as the loop gain gets a smaller value.
Thus, the closed-loop output impedance of the circuit is and it impedance reduces slightly as the loop gain
gets a smaller value.
Question:
Calculate the input-referred noise voltage of the circuit shown in Fig. 8.25(a) at relatively low frequencies.
Figure 8.25
Step 1 Of 7
Refer to Figure 8.21(a) in the textbook for the feedback configuration of a voltage-voltage feedback circuit.
The input referred noise voltage is same as the input voltage of the open-loop circuit. Therefore, redraw the circuit as shown in Figure 1.
Step 2 Of 7
From the circuit in Figure 1, write the expression for output voltage.
Here, is the input noise voltage, and , are the capacitances in the circuit.
Consider the formula of the relation between closed loop gain with input and output referred noise voltages
…… (1)
Step 3 Of 7
Write the expression of total noise voltage referred at .
…… (2)
Step 4 Of 7
Write the expression of flicker noise voltage of and (both are NMOS devices) due to the frequency.
, and
The total flicker noise voltage is,
…… (3)
Step 5 Of 7
Write the expression of flicker noise voltage of and (both are PMOS devices) due to the frequency.
, and
The total flicker noise voltage is,

…… (4)
Step 6 Of 7
From equation the total input referred noise voltage can be written the sum of all the noise in equation (2), (3) and (4) for the total circuit.
…… (5)
Substitute the equations (2), (3) and (4) in equation (5) to find the input referred noise voltage of the circuit at low frequencies.
…... (6)
Here, is the Boltzmann’s constant, is the absolute temperature, is the transconductance of MOSFETS , is the
transconductance of MOSFETS , is the transconductance parameter of a NMOS device, W is the channel width, L is the channel-
length, is the capacitance per unit area, is the frequency, and is the transconductance parameter of a PMOS device.
Step 7 Of 7
The frequency influences the input referred noise voltage by adding the flicker noise voltage. At the lowest frequencies, the flicker is not
negligible where it is negligible at high frequencies. The equation (6) referees the total input referred noise voltage with the consideration of low
frequencies.
Thus, the input referred noise voltage of the circuit at low frequencies is, .
Question:
A differential pair with current-source loads can be represented as in Fig. 8.97(a), where R0 = rON||rOP and
rON and rOP denote the output resistance of NMOS and PMOS devices, respectively. Consider the circuit
shown in Fig. 8.97(b), where Gm1 and Gm2 are placed in a negative feedback loop.
Figure 8.97
(a) Neglecting all other capacitances, derive an expression for Zin. Sketch |Zin| versus frequency.
(b) Explain intuitively the behavior observed in part (a).
(c) Calculate the input-referred thermal noise voltage and current in terms of the input-referred
noise voltage of each Gm stage.
Step 1 Of 10
(a)
Refer to Figure 8.59 in the textbook for a differential pair with current-source loads.
From the circuit in Figure 8.59 (a), write the expression for open-loop input impedance.
Here, is the output resistance in the circuit.

Consider the expression for output resistance in the circuit.
Here, is the output resistance of NMOS device and is the output resistance of PMOS device.
Step 2 Of 10
Write the expression for closed-loop input impedance from the circuit.
…… (1)
Here, is the capacitance of the capacitor in the circuit and , are open-loop gains of the amplifiers.
…… (2)
Step 3 Of 10
From the expression, write the zero, pole, DC gain, and final value.
Rewrite equation (2) to obtain the value of DC gain.
Write the DC gain from the expression.
Step 4 Of 10
From the analysis, draw the magnitude of the closed-loop input impedance with respect to frequency as shown in Figure 1.
Thus, the expression for input impedance in the circuit is and the plot of with respect to frequency is drawn and shown
in Figure 1.
Step 5 Of 10
(b)
From Figure 1 in Part (a), heavy feedback is observed at the lower frequency and it is weakened at high frequency value. As the output impedance
of the feedback amplifier reduces, the feedback value is reduced with respect to the increase in the frequency.
Thus, the heavy feedback is observed at the lower frequency and weak feedback is observed at high frequency value.
Step 6 Of 10
(c)
Short-circuit the input terminals and obtain the output-referred thermal noise voltage from the circuit in Figure 8.59 (b) in the textbook.
Here, is the Boltzmann’s constant, is the absolute temperature, and is the transconductance of the MOSFET device.
Consider the expression for input-referred thermal noise voltage.
…… (3)
Here, is the voltage gain.

Consider the expression for voltage gain in the circuit.
Step 7 Of 10

Step 8 Of 10
Consider input terminals as open, and , as input noise of each amplifier in the circuit.
Consider the expression to obtain the expression for output noise voltage.
Step 9 Of 10
Apply current (input-referred thermal noise current) to the input terminals and obtain the output voltage.
Step 10 Of 10
Substitute for .
Thus, the input referred thermal noise voltage and current for the circuit in Figure 8.59are and , respectively.
Question:
In the circuit of Fig. 8.98, (W/L)1−3 = 50/0.5, ID1 = |ID2| = |ID3| = 0.5 mA, and RS1 = RF = RD2 = 3 kΩ.
Figure 8.98
(a) Determine the input bias voltage required to establish the above currents.
(b) Calculate the closed-loop voltage gain and output resistance.
Step 1 Of 16
(a)
Refer to Figure 8.60in the textbook for the required circuit.
The circuit is a symmetrical -network. Therefore, no current flows through the resistor in the circuit.
…… (1)
Step 2 Of 16
Consider the value of as 0.

…… (2)
Step 3 Of 16
Substitute for .
Step 4 Of 16
Substitute for , for , for , for W, for , for ,,0.7 V for , and 0 for
in equation (1).
Thus, the input bias voltage required to establish the bias currents is .
Step 5 Of 16
(b)
Step 6 Of 16
Consider the expression to find the closed-loop output resistance in the circuit.
…… (3)
Here, is the open-loop output resistance and is the loop gain.
Step 7 Of 16
Calculate the output resistance of PMOS transistor .
Here, and are identical PMOSFETs, then the output resistances are .
Step 8 Of 16
Calculate the output resistance of NMOS transistor .
Step 9 Of 16
Consider the expression to find the open-loop output resistance in the circuit.
Step 10 Of 16
…… (4)
Step 11 Of 16
Substitute , 2.473 V for , for , and 0.7 V for .
Step 12 Of 16
Consider the expression for the transconductance of the PMOS transistor .
Here, and are identical PMOSFETs, then the transconductances are .
Step 13 Of 16
Substitute for , for , for , for , for , for , for in equation (4).
Step 14 Of 16
Step 15 Of 16
Consider the expression for closed-loop voltage gain of the circuit.
…… (5)

Consider the expression to find open-loop voltage gain.
Substitute for , for , for , for , for , for , for .
Step 16 Of 16
Thus, the closed-loop output resistance and closed-loop voltage gain of the circuit are and respectively.
Question:
The circuit of Fig. 8.98 can be modified as shown in Fig. 8.99, where a source follower, M4, is inserted in
the feedback loop. Note that M1 and M4 can also be viewed as a differential pair. Assume that (W/L)1−4 =
50/0.5, ID = 0.5 mA, for all transistors RS1 = RF = RD2 = 3 kΩ, and Vb2 = 1.5 V. Calculate the closed-loop
voltage gain and output resistance, and compare the results with those obtained in the previous problem.
Figure 8.98
Figure 8.99
Step 1 Of 24
(a)
Step 2 Of 24
…… (1)

…… (2)
Here, is the output resistance of MOSFET , is the drain resistance of MOSFET , is the feedback resistance in the circuit,
and is the source resistance of MOSFET .
Step 3 Of 24
Consider the expression to find output resistance of MOSFET (PMOS device).
…… (3)
Here, is the channel length modulation coefficient of PMOS device and is the bias current of MOSFET .
From the Table 2.1 , write the value of .
Step 4 Of 24
Step 5 Of 24
…… (4)
Here, is the transconductance of MOSFET , is the output resistance of MOSFET , is the output resistance of MOSFET ,
and is the transconductance of MOSFET .
Step 6 Of 24
Consider the expression to find output resistance of MOSFET (NMOS device).
…… (5)
Here, is the channel length modulation coefficient of NMOS device and is the bias current of MOSFET .
Step 7 Of 24
From the Table 2.1, write the value of .
As both the MOSFETS , are PMOS devices, and the value of bias current is same, the output resistance of MOSFET is equal to the
output resistance of MOSFET .
Step 8 Of 24
…… (6)
Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, W is the channel width, and L is the
channel-length.
…… (7)
Step 9 Of 24
Substitute for .
Step 10 Of 24
Step 11 Of 24
Consider the expression for the transconductance of the PMOS device .
…… (8)
Here, is mobility of charge carriers in the PMOS device.
Step 12 Of 24

Step 13 Of 24
Substitute for , for , for , for , for , for , for , for

in equation (4).
Step 14 Of 24
…… (9)

Substitute for , for , for , for , for , for , for , for .

Step 15 Of 24
Step 16 Of 24
Calculations for the reference Problem 8.16 (b):
Redraw the circuit in Figure 8.60 in the textbook as shown in Figure 2.
Step 17 Of 24

Here, and are identical PMOSFETs, then the output resistances are .
Step 18 Of 24
Step 19 Of 24
Step 20 Of 24
…… (10)
Substitute , 2.473 V for , for , and 0.7 V for .

Step 21 Of 24
Here, and are identical PMOSFETs, then the transconductances are .
Substitute for , for , for , for , for , for , for in equation (10).
Step 22 Of 24

Substitute for , for , for , for , for , for , for .
Step 23 Of 24
The closed-loop output resistance and closed-loop voltage gain of the circuit are and 3.2864, respectively.
Step 24 Of 24
The closed-loop output resistance and closed-loop voltage gain with respect to Figure 1 are and ; and with respect to Figure 2 are
and 3.2864.
Thus, the closed-loop output resistance and closed-loop voltage gain of the circuit are , , respectively. The closed-loop voltage
gain is obtained as slightly larger value and the closed-loop output resistance is obtained as smaller value when compare the results with the results
in reference Problem 8.16 (b).
Question:
Consider the circuit of Fig. 8.100, where (W/L)1−4 = 50/0.5, |ID1−4| = 0.5 mA, and R2 = 3 kΩ.
Figure 8.100
(a) For what range of R1 are the above currents established while M2 remains in saturation? What
is the corresponding range of Vin?
(b) Calculate the closed-loop gain and output impedance for R1 in the middle of the range obtained
in part (a).
Step 1 Of 21
(a)
Consider the expression for bias current in the NMOS devices in the circuit.
…… (1)
channel-length, is the channel-length modulation coefficient, is the gate to source voltage of NMOS device, and is the drain to source
voltage of the NMOS device.
Consider the devices are in saturation. Then, the value of becomes zero.
Step 2 Of 21
…… (2)
Substitute for .
Step 3 Of 21
Substitute for , for , for , for W, for , 0.7 V for , and 0 for in equation
(1).
Step 4 Of 21
Consider the expression for bias current in the PMOS devices in the circuit.
…… (3)
Here, is mobility of charge carriers in the PMOS device, is the gate to source voltage of PMOS device, and is the drain to source
voltage of the PMOS device.
Substitute for , for , for , for W, for , for , and 0 for in equation
(3).
Step 5 Of 21
Consider the expression for base voltage of MOSFET in the circuit.
…… (4)
Here, is the bias voltage in the circuit.
Substitute 3 V for and 1.3108 V for in equation (4).
Draw the part of the circuit as shown in Figure 1.

Step 6 Of 21
Consider the MOSFET in saturation condition and write the expression for voltage condition.
Step 7 Of 21
Substitute 0.8892 V for , for , 0.973 V for , and 0.7 V for .
…… (5)
Step 8 Of 21
Step 9 Of 21
Substitute 0.8892 V for , for , and 0.7 V for .
…… (6)
From equations (5) and (6), write the range of .
Step 10 Of 21
Consider the expression for input voltage in the circuit.
…… (7)
Substitute for , for , and 0.973 V for to obtain the minimum value of input voltage.
Substitute for , for , and 0.973 V for in equation (7) to obtain the maximum value of input voltage.
From the calculation, write the range of .
Thus, the range of and are and , respectively
Step 11 Of 21
(b)
Redraw the circuit as shown in Figure 2 to obtain the closed-loop voltage gain and output resistance.
Step 12 Of 21
…… (8)

…… (9)
Step 13 Of 21
Here, is the output resistance of the MOSFET , is the output resistance of the MOSFET , and , are the resistances in the
circuit.
Step 14 Of 21
…… (10)

Step 15 Of 21
…… (11)
Step 16 Of 21
As the value of is the middle of the range obtained in Part (a), obtain the value of .
Step 17 Of 21
…… (12)
Here, is the transconductance of MOSFET , is the output resistance of MOSFET , and is the transconductance of
MOSFET .
As both the MOSFETS , are PMOS devices, and the value of bias current is same, the output resistance of both the MOSFETs is equal.
Step 18 Of 21
Step 19 Of 21
As both the MOSFETS , are NMOS devices in the circuit, and the value of bias current is same, the transconductance of both the
MOSFETs is equal.
Substitute for , for , for , for , for , for , and for in

equation (12).
Step 20 Of 21

…… (13)

Substitute for , for , for , for , for , for , and for .
Step 21 Of 21
Thus, the closed-loop output resistance and closed-loop voltage gain of the circuit are and respectively.
Question:
In the circuit of Fig. 8.101, suppose all resistors are equal to 2 kΩ and gm1 = gm2 = 1/(200 Ω). Assuming that
λ = γ = 0, calculate the closed-loop gain and output impedance.
Figure 8.101
Step 1 Of 13
Redraw the circuit (voltage-voltage feedback) as shown in Figure 1.
Step 2 Of 13
From Figure 1, consider the output part with MOSFET as shown in Figure 2 to obtain the input, output impedance, and open-loop voltage
gain.
Step 3 Of 13
…… (1)

Consider the expression to find the open-loop output resistance in the circuit in Figure 2.
…… (2)
Here, is the transconductance of MOSFET , is the drain resistance of MOSFET , is the feedback resistance in the circuit,
and is the source resistance of MOSFET .
Step 4 Of 13

Step 5 Of 13
Consider the expression for voltage gain of MOSFET in the circuit.
Step 6 Of 13
Substitute for , for , for , for , and for .
Step 7 Of 13
Redraw the circuit in Figure 1 as Figure 3 to find the loop gain in the circuit.
Step 8 Of 13
…… (3)
Here, is the transconductance of MOSFET and is the drain resistance of MOSFET .
Step 9 Of 13

Step 10 Of 13
…… (4)

…… (5)
Step 11 Of 13
Here, is the input resistance of the circuit in Figure 2.
Step 12 Of 13
Substitute for , for , for , for , for , for , and for in equation
(5).

Step 13 Of 13
Thus, the closed-loop output resistance and closed-loop voltage gain of the circuit are , , respectively.
Question:
A CMOS inverter can be used as an amplifier with or without feedback (Fig. 8.102). Assume that (W/L)1,2 =
50/0.5, R1 = 1 kΩ, R2 = 10 kΩ, and the dc levels of Vin and Vout are equal.
(a) Calculate the voltage gain and the output impedance of each circuit.
(b) Calculate the sensitivity of each circuit’s output with respect to the supply voltage. That is,
calculate the small-signal “gain” from VDD to Vout. Which circuit exhibits less sensitivity?
Figure 8.102
Step 1 Of 24
(a)
From the circuit, the bias currents of both the MOSFETs is equal.
…… (1)
Here, is the bias current of MOSFET and is the bias current of MOSFET .
Consider the expression for bias current of MOSFET in the circuit.
…… (2)
channel-length, is the channel-length modulation coefficient for NMOS device, is the gate to source voltage of NMOS device, and
is the drain to source voltage of the NMOS device.
Step 2 Of 24

…… (3)
Step 3 Of 24
Consider the expression for bias current of MOSFET in the circuit.
…… (4)
Here, is mobility of charge carriers in the PMOS device, is the channel-length modulation coefficient for PMOS device, is the gate to
source voltage of PMOS device, and is the drain to source voltage of the PMOS device.
…… (5)
Step 4 Of 24
Step 5 Of 24
…… (6)
Step 6 Of 24
Substitute for .
Step 7 Of 24
Substitute for , for , for W, for , 0.7 V for , and for in equation (3).
…… (7)
Step 8 Of 24
Substitute for , for , for W, for , for , and for in equation (5).
Step 9 Of 24
Substitute for and
in equation (1).
Step 10 Of 24
Solve the polynomial expression and obtain the value of input voltage.
Ignore the negative values and consider the input voltage as 1.1292 V.
Step 11 Of 24
As both the bias currents are equal, the value of bias current of MOSFET is .
Consider the expression to find the voltage gain in the circuit.
…… (8)
Step 12 Of 24
Here, is the transconductance of MOSFET , is the transconductance of MOSFET , is the output resistance of MOSFET
, and is the output resistance of MOSFET .

Substitute for , for , for , 1.1292 V for , and 0.7 V for .
Step 13 Of 24
Substitute for , for , for , 3 V for , 1.1292 V for , and for .
Step 14 Of 24
Step 15 Of 24

Step 16 Of 24
Consider the magnitude of the voltage gain.
Step 17 Of 24
Consider the expression to find output impedance of the circuit.
Step 18 Of 24
Step 19 Of 24
As both the circuits (Figure 8.64 (a) and Figure 8.64 (b)) have identical MOSFETS, the values of parameters , , , and are same as
obtained values for the circuit in Figure 1.
Consider the expression to find the voltage gain in the circuit.
Substitute for , for , for , for , for , and for .
Step 20 Of 24
Consider the magnitude of the voltage gain.

Step 21 Of 24
Consider the expression to find output impedance of the circuit.
Thus, the voltage gain and output impedance for the circuit in Figure 8.64 (a) and Figure 8.64 (b) are , , and ,
, respectively.
Step 22 Of 24
(b)
From the circuit, and .
Consider the expression for small-signal voltage gain when and in the circuit.
Step 23 Of 24
Consider the expression for small-signal voltage gain in the circuit.

Step 24 Of 24
Thus, the sensitivity of the circuit with respect to the supply voltage for the circuit in Figure 8.64 (a) and Figure 8.64 (b) are and ,
respectively, and the circuit in Figure 8.64 (b) exhibits less sensitivity.
Question:
Calculate the input-referred thermal noise voltage of the circuits shown in Fig. 8.102.
Figure 8.102
Step 1 Of 3
Refer to Figure 8.64 (a) in the textbook for the amplifier circuit without feedback.
The input referred thermal noise voltage is same as the input voltage of the open-loop circuit.
From the circuit, write the expression for input referred thermal noise voltage of the circuit.
Here, is the Boltzmann’s constant, is the absolute temperature, is the transconductance of MOSFET , and is the
transconductance of MOSFET in the circuit.
Step 2 Of 3
Refer to Figure 8.64 (a) in the textbook for the amplifier circuit with feedback.
From the circuit, write the expression for input referred thermal noise voltage of the circuit.
…… (1)
Here, , are the resistance of resistors in the circuit, is the output resistance, and is the loop gain of the circuit.
Step 3 Of 3
Thus, the input referred thermal noise voltages for the circuit in Figure 8.64 (a) and 8.64 (b)are and
, respectively
Question:
The circuit shown in Fig. 8.103 employs positive feedback to produce a negative input capacitance. Using
feedback analysis techniques, determine Zin and identify the negative capacitance component. Assume that λ
= γ = 0.
Figure 8.103
Step 1 Of 5
Redraw the circuit as shown in Figure 1 to apply the voltage-current feedback technique to the circuit.
Step 2 Of 5
Consider the expression to find the current loop gain from the circuit in Figure 1.
Here, is the output resistance of MOSFET , is the transconductance of MOSFET , is the transconductance of MOSFET
, is the transconductance of MOSFET , and is the capacitance in the circuit.
Step 3 Of 5
Consider the expression for input impedance of closed-loop circuit.

Step 4 Of 5
From the circuit, if the value of tends to infinity, substitute for .
Step 5 Of 5
From the expression, the negative capacitive component is .
Thus, the input impedance in the circuit and the negative capacitive component are and respectively.
Question:
In the circuit of Fig. 8.104, assume that λ = 0, gm1,2 = 1/(200 Ω), R1−3 = 2 kΩ, and C1 = 100 pF. Neglecting
other capacitances, estimate the closed-loop voltage gain at very low and very high frequencies.
Figure 8.104
Step 1 Of 6
At low frequency:
The capacitor gets open at low frequencies in the circuit. Therefore, open circuit the capacitor and redraw the circuit as shown in Figure 1.
Step 2 Of 6
Consider the expression to find the closed-loop voltage gain in the circuit in Figure 1.
…… (1)
Here, , , are resistances in the circuit and is the transconductance of MOSFET .
Step 3 Of 6
Step 4 Of 6
At high frequency:
The capacitor gets short circuit at high frequencies in the circuit. Therefore, short circuit the capacitor and redraw the circuit as shown in Figure 2.
Step 5 Of 6
Consider the expression to find the closed-loop voltage gain in the circuit in Figure 2.
Step 6 Of 6
Thus, the closed-loop voltage gain in the circuitat low and high frequencies are and , respectively.
Question:
(a) Derive expressions for the transconductance and output resistance of a MOSFET in the triode region.
Plot these quantities and gmrO as a function of VDS, covering both triode and saturation regions.
(b) Consider the amplifier of Fig. 9.6(b), with (W/L)1−4 = 50/0.5, ISS = 1 mA, and input CM level of 1.3 V.
Calculate the small-signal gain and the maximum output swing if all transistors remain in saturation.
(c) For the circuit of part (b), suppose we allow each PMOS device to enter the triode region by 50 mV so as
to increase the allowable differential swing by 100 mV. What is the small-signal gain at the peaks of the
output swing?
Figure 9.6 Simple op amp topologies.
Step 1 Of 26
(a)
Write the formula to find the drain current of a MOSFET.
Here, is the gate-source voltage, is the drain-source voltage, L is the channel length, W is the channel width, is the mobility of
electrons (NMOS), is the threshold voltage, and is the gate oxide capacitance for the unit area.
Write the expression of the transconductance of a MOSFET in the triode region.

From the rules of partial derivations, the second and third terms and are equal to zero since there
is no variable parameter in the functions. The term only exists since it has the variable parameters in the function.
…… (1)
Step 2 Of 26
Write the expression for the output resistance of a MOSFET in triode region.
…… (2)
Step 3 Of 26
Write the expression of a transconductance of the MOSFET in saturation region.
…… (3)
Write the expression of output resistance of the MOSFET in saturation region.
…… (4)
Here, is the channel length modulation coefficient, is the drain current.
Consider the drain current in saturation region which is equal to and it is independent of .
Step 4 Of 26
Consider the MOSFET operates in triode region for the condition , and operates in saturation region for the condition
.
Step 5 Of 26
From the equations (1), and (3), write the complete function of the transconductance .
In triode region, the transconductance varies from 0 to saturation point for the variable parameter varies from 0 to .
Consider that the aspect ratio is constant and the changes in transconductance are shown in Table 1.
Step 6 Of 26
From the Table 1, draw the plot of as a function of as shown in Figure 1.

Step 7 Of 26
From the equations (2), and (4) write the complete function of the output resistance.
In triode region, the output resistance has the minimum value at , and form the function of as the value of is increasing the
value of is increases. At the point of , the output resistance of a MOSFET enters the saturation region.
The quantity of output resistance of a MOSFET has no variations in value for all , and it is considered as a constant value since the
function is independent of .
Consider that the aspect ratio is constant and the changes in output resistance are shown in Table 2
Step 8 Of 26
Step 9 Of 26
Multiply the complete function of (transconductance) with the complete function (output resistance) to find the function of .
Substitute for .
In triode region, the quantity is 0 at , and for all the quantity is increases. The quantity enters in to
saturation region at .
The quantity has no variation in value for all , and it is considered as a constant value since the function is
independent of .
Consider that the aspect ratio is constant and the changes in quantity are shown in Table 3.
Step 10 Of 26
Thus, the transconductance and the output resistance of a MOSFET in triode region are and
respectively and the plots for transconductance, output resistance and the quantity are plotted and shown in
Figure 1, Figure 2, and Figure 3.
(b)
Refer to Figure 9.6 (b) in the textbook, consider the first stage from the circuit, and draw the circuit as shown in Figure 4. Consider the MOSFET
is an NMOS model, and MOSFET is a PMOS model.
Step 11 Of 26
Write the expression of the small signal open loop gain .
…… (5)
Here, is the transconductance of a MOSFET , is the output resistance of a MOSFET , and is the output resistance of a
MOSFET .
Write the formula to find the transconductance for the MOSFET .
Here, is an effective channel length, and is the drain current that is equal to .
…… (6)
Step 12 Of 26
Consider the expression of the gate oxide capacitance per unit area.
…… (7)
Here, is the permittivity of the oxide is, which is equal to , and is the gate oxide thickness.
Refer to Table 2.1 in the textbook, the value of is , the NMOS model channel mobility is .
Here, is an absolute permittivity which is equal to .
Substitute for .
Substitute for .
Step 13 Of 26
Write the formula to find the effective length of the MOSFET due to source/drain side diffusion.
Here, is the source-drain side diffusion length, and is same as channel length of the MOSFETs in NMOS mirror circuit.
Refer to Table 2.1 in the textbook, the source/drain side diffusion length is for NMOS circuit model is .
Consider the NMOS transistor has the width and length as and respectively to satisfy the value of aspect ratio .
Substitute for , for , for , for , 1 mA for , and for W to find .

…… (8)
Write the relationships between the units.
And
Substitute for and in equation (8).
Step 14 Of 26
Consider the drain currents through the MOSFETs and are equal in the first stage.
Write the formula to find the output resistance of the MOSFET .
…… (9)
Here, is the channel length modulation coefficient of MOSFET , is the drain current through MOSFET .
Refer to the Table 2.1 in the textbook, the value of is considered as .
Step 15 Of 26
Write the formula to find the output resistance of the MOSFET .
…… (10)
Here, is the channel length modulation coefficient of MOSFET , is the drain current through MOSFET .
Refer to the Table 2.1 in the textbook, the value of is considered as .
Substitute for , for , and for in equation (5) to find .
The small signal gain is 29.6.
Step 16 Of 26
Consider the transistors are in saturation region.
Consider the input common-mode level (CM level) of the transistor is 1.3 V which is considered as a gate input voltage to MOSFET transistor
, and threshold voltage is .
Write the condition for a MOSFET saturation region with respect to MOSFET .
Substitute 1.3 V for , 0.7 V for .
Therefore, the minimum output voltage is 0.6 V.

Step 17 Of 26
Write the formula to find the drain current of PMOS model transistor .
Assume that the channel length modulation coefficient is negligible, and then the drain current is,
…… (11)
Here, is the mobility of electrons (PMOS), is the gate source voltage of a MOSFET , and is the channel length of a MOSFET
.
Step 18 Of 26
Refer to Table 2.1 in the textbook, mobility of electrons (PMODEL) is .
Consider is equal to , and is the effective length due to the source/drain side diffusion. The diffusion length for PMOS model is
.
Step 19 Of 26
Substitute for , for in equation (11).
Substitute for .
Substitute 1 mA for , for , for , for , for , and for W.
Step 20 Of 26
Write the relationship between the units.
Substitute for .
Step 21 Of 26
Write the condition for a MOSFET saturation region with respect to MOSFET .
Here, is the drain-source voltage of MOSFET .
The maximum allowable output voltage is,
…… (12)
Consider that the input CM range level 1.3 V with 3 V supply.
Substitute 3 V for , and for in equation (12).
Therefore the output voltage varies from minimum value to maximum value.
Step 22 Of 26
Write the formula to find the one sided output swing.
Write the formula to find the differential output swing.
Substitute for .
Substitute for , and 0.6 V for to find differential output swing.
Thus, the small signal gain is , and maximum output swing is .
Step 23 Of 26
(c)
Consider that the PMOS transistor will enter in to the triode region at the condition of .
From part (b),
Then,
Consider the PMOS transistor enter the triode region at 50 mV which is equal to .
At the point of entering triode region the condition of triode and saturation region is,
Substitute 50 mV for .
Step 24 Of 26
Write the formula to find the output resistance of a PMODEL transistor in triode region by considering the effective length due to the
source/drain side diffusion.
Substitute for .
Refer to Table 2.1, threshold voltage for PMOS model transistor is .
Step 25 Of 26
Substitute for , for , for , for , and for W.
Substitute 0.408 V for , and 0.358 V for .
Write the relation between the units.
Substitute for .
Step 26 Of 26
Write the formula to find the small signal gain at peaks of the output swing when the transistor device enters the triode region
Substitute for , for , and for to find small signal gain at peaks of the output swing.
Thus, the small signal gain at peaks of the output swing in triode region is .
Question:
In the circuit of Fig. 9.9, assume that (W/L)1−4 = 100/0.5, ISS = 1 mA, Vb = 1.4 V, and γ = 0.
(a) If M5–M8 are identical and have a length of 0.5 μm, calculate their minimum width such that
M3 operates in saturation.
(b) Calculate the maximum output voltage swing.
(c) What is the open-loop voltage gain?
(d) Calculate the input-referred thermal noise voltage.

Figure 9.9 Telescopic cascode op amp with input and output shorted.
Step 1 Of 14
(a)
Draw the circuit as shown in Figure 1 with indications of voltage and . The terminals of input and output are shorted though transistor.
Step 2 Of 14
Consider the transistor is in saturation region, than voltage condition that must satisfy under the saturation region is,
Here, is the voltage at the shorted point a in the Figure 1, is the threshold voltage of NMOS device which is equal to 0.7 V.
Thus, the maximum is 0.7 V.
Step 3 Of 14
Assume are identical, and the voltages across and are constant and same since they are in a cascode current mirror circuit
configuration.
…… (1)
Here, is the gate-source voltage of transistor , and is the gate-source voltage of transistor .
From the Figure 1, the voltage is written as,

Step 4 Of 14
Write the expression to calculate the drain current though the PMOS transistor .
Here, is the he channel length modulation coefficient, is the gate-source voltage, is the drain-source voltage, L is the channel length,
W is the channel width, is the mobility of electrons, is the threshold voltage, and is the gate oxide capacitance per unit area for the
NMOS transistor .
Substitute for L.
…… (2)
Here, is an effective channel of , is the drain current which is equal to .
Step 5 Of 14
Write the formula to find the drain current of the transistor .
The drain current is same through all the transistors.
Step 6 Of 14
Consider the formula to find the gate oxide capacitance per unit area of PMOS or NMOS transistor devices.
…… (3)
Here, is the permittivity of the oxide, which is equal to , and is the gate oxide thickness.
Refer to Table 2.1 in the textbook, for a PMOS model transistor consider the value of is .
Substitute for , and for in Equation (3).
Here, the absolute permittivity is which is equal to .
Substitute for .
Simplify the value.
The value of is same for PMOS and NMOS type devices.
Step 7 Of 14
Consider the voltage in saturation. Then the value of is .
From Table 2.1 in the textbook for a PMOS model device, the channel mobility is , the threshold voltage is , the value of is
.
Substitute for the both and , for , for , for , for in equation
(2).
…… (4)
Step 8 Of 14
Modify the equation to find .
Substitute for .
…… (5)
Here, is the source/drain side diffusion length for the PMOS device, and is the same channel length of the MOSFETs in the mirror
circuit.
Refer to Table 2.1 in the textbook, for the PMOS device, the source/drain side diffusion is .
Step 9 Of 14
Substitute for for in equation (5).
Thus, the width of transistor is is .
Step 10 Of 14
(b)
Write the formula to calculate the maximum output voltage swing.
…… (6)
Write the expression to calculate the drain current though the NMOS transistor .
Here, is the gate-source voltage, is the drain-source voltage, is the mobility of electrons, is the threshold voltage, and is the
channel length modulation coefficient for NMOS.
Consider the value as 0 for the simplification.
Substitute 0 for .
Substitute for L.
Substitute for .
…… (7)
Here, is the source/drain side diffusion which is equal to , is the length .
Step 11 Of 14
Refer to Table 2.1 in the textbook, the NMOS model channel mobility is , and the threshold voltage is .
Substitute for , for , 0.7 V for , for , for , for W and 0.5
mA for in equation (7).
…… (8)
Substitute for , 0.7 V for , 0.7 V for in equation (6).
Thus, the maximum output voltage swing is .

(c)
Write the expression to calculate the open loop voltage gain of the cascode amplifier.
…… (9)
Here, is the transconductance of transistor , is the transconductance of transistor , is the transconductance of transistor ,
is the output resistance of transistor , is the output resistance of transistor , is the output resistance of transistor , is the
output resistance of transistor .
Write the formula to calculate the transconductance of NMOS model transistor .
Substitute for .
Here, is the channel length of the transistor , is the source/drain side diffusion of NMOS model which is equal to .
Substitute for , for , for , for , for W and 0.5 mA for .
…… (10)
And
Substitute for both and in equation (10).
The transistors and are identical in dimensions, so that .
Step 12 Of 14
Write the formula to calculate the transconductance of PMOS model transistor .
Substitute for .
Here, is the channel length of the transistor , is the source/drain side diffusion of PMOS model which is equal to .
Substitute for , for , for , for , for W and 0.5 mA for .
Substitute for both and .
Write the formula to calculate the output resistance of transistor NMOS model .
Therefore, and are .
Write the formula to calculate the output resistance of transistor PMOS model .
Therefore, and are .
Substitute for , for , for , for , for , for , for in

equation (9).
Thus the open loop gain of the amplifier is .
Step 13 Of 14
(d)
Since the transistors and are connected in cascode configuration, the noise induced due to these four transistors is neglected.
Step 14 Of 14
Write the expression to calculate the input-referred noise voltage of transistor .
Here, k is the Boltzmann constant which is equal to , T is the temperature in K which is equal to , is a coefficient
which is equal to .
Since the transistors and are induces the same noise the input-referred noise voltage of the both transistors is same.
Write the expression to calculate the input-referred noise voltage of transistor .
From Figure 2, the transitors and are induces the same noise.
Write the total input-referred noise voltage of the amplifier as:

Substitute for , for k, for T, for , for .
Substitute for .
Substitute for .
Thus, the input-referred noise voltage of the amplifier is .

Question:
Design the folded-cascode op amp of Fig. 9.15 for the following requirements: maximum differential swing =
2.4 V, total power dissipation = 6 mW. If all of the transistors have a channel length of 0.5 μm, what is the
overall voltage gain? Can the input common-mode level be as low as zero?
Figure 9.15 Folded-cascode op amp with cascode PMOS loads.
Step 1 Of 23
Draw the circuit of first stage of the folded cascode op amp as shown in Figure 1.
Write the formula to find the maximum output differential swing voltage of the cascode op amps.
Here, is the drain power voltage, and , , and are the overdrive voltages of the respective transistors , here j
indicates the transistor number.
Substitute 2.4 V for , and 3 V for .
…… (1)
Step 2 Of 23
Draw the circuit of folded cascade op amp circuit as shown in Figure 2.
Assume the overdrive voltages as follows:
Considers all the transistors are with constant aspect ratio and in saturation region.
Consider the relationship between overdrive voltage and electron mobility of a MOSFET in saturation region.
Here, is a constant.
Step 3 Of 23
Thus, the relationship between and is,
Transistor is a NMOS device has the larger electron mobility than PMOS devices and . The larger election mobility results in the
lower overdrive voltage of than the transistors and . Therefore, assume the overdrive voltages as,
The drain current and transconductance are in proportional relation in saturation. The larger current flows though the NMOS model transistor
. Therefore, the transistor has larger overdrive voltage due to larger drain current and lesser than the of transistors and .
Therefore, assume the overdrive voltage as,
Assume the overdrive voltage of transistors as a larger value.
The overdrive voltage values of transistors are assumed so that equation (1) should satisfy.
Step 4 Of 23
The branch current through the transistors and is same since the both transistor are identical.
Assume the total power dissipation is occurs at the transistors and due to the larger current flow, and neglect the power dissipation by
other devices.
Here, is the total power dissipated.
Substitute 3 V for , and 6 mW for .
Thus, the currents and are equal to .
Step 5 Of 23
Write the expression to calculate the drain current of the transistors .
Here, , , , L, W, , , are are the channel length modulation coefficient, gate-source voltage, drain-source voltage, channel
length, channel width, mobility of electrons, threshold voltage, and the gate oxide capacitance per unit area respectively for the NMOS transistors
.
Substitute for L, and for .

…… (2)
Here, is an effective channel length of , and is the drain current of .

From Table 2.1 in the textbook for a NMOS model:
The channel mobility is .
The value of is .
Step 6 Of 23
The condition of overdrive voltage is . Therefore,
Consider the formula to find the gate oxide capacitance per unit area of PMOS or NMOS transistor devices.
…… (3)
Here, is the permittivity of the oxide which is equal to , and is the gate oxide thickness.
Refer to Table 2.1 in the textbook, the value of is .
Step 7 Of 23
Here, an absolute permittivity is which is equal to .
Substitute for .
The value of is same for PMOS and NMOS type devices.
Step 8 Of 23
Substitute for , for , for , for , for , for in equation (2).
…… (4)
Substitute for .
…… (5)
Here, is the source/drain side diffusion length, and is the same channel length of the MOSFETs.
Refer to Table 2.1 in the textbook, for the NMOS device, the value of is .
Since the transistors and are identical, .
Step 9 Of 23
From Figure 2, consider the current at point X and Y as:
Since the current and are equal to , assume the current values as,
Step 10 Of 23
The transistors and are identical PMOS devices.
Consider the aspect ratio of transistors as:
…… (6)
From Table 2.1 in the textbook for a PMOS model:
The value of is .
Step 11 Of 23
Substitute for .
Substitute for .
…… (7)
Here, is the source/drain side diffusion length for the PMOS device.
Refer to Table 2.1 in the textbook, for the PMOS device, the value of is .
Since, the transistors and are identical
Step 12 Of 23
The transistors and are identical NMOS devices.
…… (8)
Substitute for .
Substitute for .
Since, the transistors and are identical .
Step 13 Of 23
The transistors and are identical PMOS devices. Here,
…… (9)

Step 14 Of 23
Substitute for .
Substitute for .
Since, the transistors and are identical .
Step 15 Of 23
Ignore the body effect on .
From the Figure 2, the voltage is equal to the voltage .
Step 16 Of 23
Consider the body effect for the NMOS transistor .
The voltage is equal to the voltage .

Substitute for
Here, is the threshold which is equal to 0.7 V, is source-body voltage at overdrive voltage point in saturation which is equal to
overdrive voltage, is the body effect coefficient which is equal to , and is the constant which is equal to for the NMOS
device.
Substitute for , for , 0.7 V for , 0.44 V for , 0.44 V for , 0.3 V for .
Step 17 Of 23
Consider the MOSFET body effect for the PMOS transistor .
Consider the expression to find the voltage .
Substitute for
Here, is the threshold voltage which is equal to 0.8 V, is source-body voltage at overdrive voltage point in saturation which is equal to
overdrive voltage, is the body effect coefficient which is equal to , and is the constant which is equal to for the PMOS
device.
Substitute for , for , 0.8 V for , 0.53 V for , 3 V for , 0.53 V for .
Consider the MOSFET body effect for the PMOS transistor .
Consider the expression to find the voltage .
Substitute for
Substitute for , for , 0.8 V for , 0.53 V for , 3 V for , 0.53 V for both and .
Step 18 Of 23
Write the condition for the maximum input common mode voltage level of the PMOS transistor .
Here, is the voltage across which is equal to .
Substitute 3 V for , 0.3 V for , 0.8 V for , 0.53 V for .
The maximum input common mode voltage is .
Write the condition for the minimum input common mode voltage level of the PMOS transistor .
Substitute for and 0.8 V for .
The input common mode voltage level can vary in the limit of voltage as,
Thus, yes the input CM voltage level can be as low as zero.
Step 19 Of 23
Draw the circuit diagram as shown in Figure 3 with the representation of output resistance and assume all the base voltages and are
grounded in small signal condition.
Write the expression to find the overall gain of the cascade amplifier.
…… (10)
Here, is the transconductance of the transistor , is the output resistance of the amplifier.
Consider the output resistance of the amplifier as:
…… (11)
Since the transistors and are in cascode configuration, the output resistance is,
The output resistance of transistor has the parallel combined resistance lead source in cascode configuration. Therefore, the output
resistance seen by at the output is,

…… (12)
Step 20 Of 23
Write the formula of transconductance of the transistor .
Substitute 0.5 mA for , and 0.53 V for .
Consider the same transconductance for the PMOS transistors and with same overdrive voltage and drain current. Therefore,
.
Step 21 Of 23
Write the formula of transconductance of the transistor .
Step 22 Of 23
Write the formula to find the output resistance of PMOS transistor .
Substitute for , 0.5 mA for .

The PMOS transistors , and are identical, the output resistance is,
Write the formula to find the output resistance of NMOS transistor .
Substitute for , 1 mA for .
Substitute for , for , for , for , for , for , for , and

The overall gain of the amplifier is .
Step 23 Of 23
Thus, the folded-cascode op amp is designed as:
The base voltages are , and the widths of the each transistors are,
and .
The overall gain of the amplifier is , and the input CM voltage level can be as low as zero in the limit of .
Question:
In the op amp of Fig. 9.21(b), (W/L)1−8 = 100/0.5, ISS = 1 mA, and Vb1 = 1.7 V. Assume that γ = 0.
(a) What is the maximum allowable input CM level?
(b) What is VX?
(c) What is the maximum allowable output swing if the gate of M2 is connected to the output?
(d) What is the acceptable range of Vb2?
(e) What is the input-referred thermal noise voltage?

Figure 9.21 Cascode op amps with single-ended output
Step 1 Of 17
(a)
Redraw the figure as shown in Figure 1.
Write the expression for the minimum common mode voltage level required for .
…… (1)
Here, is the voltage across the tail current , and is the gate to source voltage of .
Write the expression for of the NMOS device .
Here, is the NMOS threshold voltage and is the overdrive voltage.
…… (2)
Step 2 Of 17
Write the expression for the maximum common mode voltage required for .
…… (3)
Here, is the voltage at the node Y in the Figure 1.
The voltage can be written as .

Assume that the all devices are identical. Then, .
…… (4)
Step 3 Of 17
Write the expression for the over drive voltage
…… (5)
Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, W is the channel width, is the
channel length and is the source/drain side diffusion length, and is the drain current of .
Step 4 Of 17
…… (6)
Step 5 Of 17
Substitute for .
Step 6 Of 17
and
Step 7 Of 17
Substitute for , 0.5 mA for , for , for , for W and for in equation (5).
Subatitute 0.159 V for , 1.7 V for to find the maximum input common mode voltage level in equation (4).
Thus, the allowable CM level is .
Step 8 Of 17
(b)
Write the expression to find the overdrive voltage of (PMOS).

Here, is mobility of charge carriers in the NMOS device, is the gate oxide capacitance per unit area, W is the channel width, is the
channel length and is the source/drain side diffusion length, and is the drain current of .
Substitute for , 0.5 mA for , for , for , for W and for in equation (5).
Step 9 Of 17
Rewrite the equation as,
Step 10 Of 17
Write the expression to find the voltage at node X.
Thus, the voltage is .
Step 11 Of 17
(c)
Write the expression of maximum output swing.
…… (7)
From the symmetry of transistirs and ,
Substitute 0.859 V for , and for and in equation (7).
Thus, the maximum output swing is .
Step 12 Of 17
(d)
From part (b),
, (using symmetry).
Write the codntion that keeps the device in saturation as,
Write the expression for the relation for bias voltage and .
Substitute 1.911 V for , 1.089 V for , and 0.8 V for .
Step 13 Of 17
Write the expression for maximum as,
Thus, the possible value of voltage is,
Step 14 Of 17
(e)
Since. The circuit configuration is cascode, the noise due to is negligible.

Draw the figure as shown in Figure 2.
Write the expression for the total input thermal referred noise.
…… (8)
Here, k is the Boltzmann constant that is , T is temparture 300 K, is a constant of noise factor equal to .
Write the expression for transconductance of NMOS devices as follows:
Step 15 Of 17
Substitute for , 0.5 mA for , for , for , for W and for .
Step 16 Of 17
Write the expression for transconductance of PMOS devices as follows:
Substitute for , 0.5 mA for , for , for , for W and for .
Step 17 Of 17
Substitute for k, for , 300 K for T. for , and for in equation (8).
Thus, the input referred thermal noise is .
Question:
Design the op amp of Fig. 9.21(b) for the following requirements: maximum differential swing = 2.4 V, total
power dissipation = 6 mW. (Assume that the gate of M2 is never shorted to the output.)
Figure 9.21 Cascode op amps with single-ended output
Step 1 Of 9
Write the formula of total power dissipation .
Here, drain power voltage, is the current source.
Modify the equation to find the .
Step 2 Of 9
Write the formula to find the drain current in each branch of transistors in Figure 9.18 (b) in the textbook.
Thus, all the transistors drain currents are equal to .

The threshold voltage is .
The value of is .
The value of is .
The value of is .
The value of is .
Assume the PMOS transistors are identical and same in dimensions as:
Here, W is the channel width and L is the channel length of the transistors.
Step 3 Of 9
Write the formula to find the overdrive voltage of the PMOS transistor by neglecting the modulation coefficient.
Here, is the gate-source voltage, is the effective channel length, W is the channel width, is an electron mobility, is the threshold
voltage, are is the gate oxide capacitance per unit area, is the drain current of the transistor .
Substitute for
Substitute 1 mA for , for , for , for , for , and for .

Substitute 1 V for .
Substitute for .
Step 4 Of 9
Write the formula to find the drain voltage at point X.
Step 5 Of 9
Substitute 3 V for , and for .
Consider the condition of bias voltage swing for the transistor that results in larger output swing and the maximum open loop gain as it
entered in to the saturation. That is,
…… (1)
and are is the threshold voltages, is the gate source voltage of transistor .
The threshold voltage is equal to .
The transistor gate is shorted to transistor drain at X. Thus the gate source is equal to .
Substitute for , for , and for , for in equation (1).
Consider the larger output swing is equal to the . Choose as maximum voltage. Thus, the maximum output voltage is,
Substitute 1.3 V for , and 0.8 V for .
Step 6 Of 9
Consider one sided output swing is 1.2 V, and from the voltage constrain of assume that . Choose to the overdrive voltage of
transistors and are equal and 0.3 V. The voltage drop across the is equal to .
and
Assume that the point of drain source voltage where the device enters in to saturation as,
Step 7 Of 9
Write the formula of drain current in terms of overdrive voltage.
Here, is channel length modulation coefficient, is the gate-source voltage, is the drain-source voltage, is the effective channel
length, W is the channel width, is an electron mobility, is the threshold voltage, are is the gate oxide capacitance per unit area for the
transistor .
Rewrite the equation to find .
Substitute for ,
Substitute 0.3 V for , 0.3 V for , for , for , for , 1 mA for .
Substitute for .
Substitute for
Step 8 Of 9

Thus, all the NMOS transistors are identical and same in dimensions, and . Thus the aspect ratio is,
Step 9 Of 9
Write the formula to find the input CM level.
Substitute 0.3 V for , 0.3 V for , 0.7 V for .
Write the formula to find the bias voltage .
Substitute 1.3 V for , 0.3 V for .
Thus, the op amp designed as and with the input CM level voltage is 1.3 V and the bias voltages
and . The source current is .
Question:
If in Fig. 9.23, (W/L)1−8 = 100/0.5 and ISS = 1 mA,
(a) What CM level must be established at the drains of M3 and M4 so that ID5 = ID6 = 1 mA? How
does this constrain the maximum input CM level?
(b) With the choice made in part (a), calculate the overall voltage gain and the maximum output
swing.
Figure 9.23 Simple implementation of a two-stage op amp.
Step 1 Of 12
The branch current through the identical transistors and is equal 1 mA. The both transistors are PMOS devices.
Write the expression to calculate the drain current of the transistors .
Here, is channel length modulation coefficient, is the gate-source voltage, is the drain-source voltage, L is the channel length, W is the
channel width, is an electron mobility, is the threshold voltage, are is the gate oxide capacitance per unit area.
Substitute for L.
Substitute for as transistor is a PMOS type.
Here, is the source/drain side diffusion length, and is the same channel length of the MOSFETs.
Neglect the channel length modulation, and assume modulation coefficient as zero. Then the equation is modified as,
…… (1)
The value of is .
Step 2 Of 12
Consider the formula to find the gate oxide capacitance .
…… (2)
Here, is the permittivity of the oxide which is equal to , and is the gate oxide thickness.
Refer to Table 2.1 in the textbook, the value of is .
Substitute for .
The value of is same for PMOS and NMOS type models.
Step 3 Of 12
Substitute for , for , for , 1 mA for , for , and for W in equation

(1).
Step 4 Of 12
Therefore,
Step 5 Of 12
Write the formula to find the drain voltages of and at point X and Y.
The common mode voltage level at the drains of and is .
Step 6 Of 12
From the circuit configuration, consider the transistors and are operates in saturation if the input CM level voltage is less than the voltage
of . Therefore, consider that the two transistors and are saturation and the condition of input CM level voltage is,
Here, is the voltage at the drains of and , and is the threshold voltage of NMOS model.
Therefore, the maximum input CM level voltage .
Step 7 Of 12
(b)
Consider the folded circuit is a two stage op amp. The transistors and are in first stage, and and are in second stage.
Write the formula to find the open loop gain of the first stage.
Here, is the transconductance of , and are output resistances of and respectively.

Write the formula to find the open loop gain of the second stage.
Here, is the transconductance of , and are output resistances of and respectively.

The total gain of the folded circuit is,
…… (3)
Step 8 Of 12
Write the formula of transconductance of the NMOS transistor .
…… (4)
Here, is the effective channel length, W is the channel width, is an electron mobility, is the gate oxide capacitance per unit area and
Write the formula to calculate the drain current .
Thus the currents .

The value of is .
Step 9 Of 12
Substitute for , for , for , 0.5 mA for , for , and for in
equation (4).
Substitute the units for both and .
Write the formula to find the transconductance of the transistor .
Substitute for and 1 mA for .
Step 10 Of 12

Step 11 Of 12
Step 12 Of 12
Write the formula to calculate the maximum output voltage swing.
Substitute for .
…… (5)
Here, is the overdrive voltage of the transistor .
Write the formula to find the overdrive voltage of NMOS model
…… (6)
Consider the value of overdrive voltage at the peak drain current as:
Substitute for
Substitute 1 mA for , for , for , for , for , and for .
Substitute 3 V for , for , 0.408 V for in equation (5).
Thus, the overall gain is , and the maximum output swing is .

Question:
Design the op amp of Fig. 9.23 for the following requirements: maximum differential swing = 4 V, total
power dissipation = 6 mW, ISS = 0.5 mA.
Figure 9.23 Simple implementation of a two-stage op amp.
Step 1 Of 12
Write the formula to find the current driven by the drain power source .
Here, drain current, drain source voltage.
From the circuit the relation between , and is written as:
Assume the transistors and are identical and the currents , are equal.
Substitute for , 0.5 mA for , and 2 mA for .
Thus,
Step 2 Of 12
Write the formula of maximum differential swing at the cascade combination of and in the folded circuit.
Substitute 4 V for , 3 V for .
…… (1)
Choose the values of overdrive voltages and as to satisfy the relation in equation (1).
The overdrive voltage is equal to the drain source voltage at the point of transistor entered in to saturation.
Step 3 Of 12
Write the formula to find the aspect ratio of transistor (PMOS) in terms of overdrive voltage.
…... (2)
length, W is the channel width, is an electron mobility, is the gate oxide capacitance per unit area, and is the drain current for the
transistor .
The value of is .
The value of is .
The value of is .
The value of is .
Step 4 Of 12
Substitute 0.75 mA for , for , for , for , for , and for in equation
(2).
Step 5 Of 12
Substitute for .
Substitute for
Thus, the identical transistors width is .
Step 6 Of 12
Write the formula to find the aspect ratio of transistor (NMOS) in terms of overdrive voltage.
length, W is the channel width, is an electron mobility, is the gate oxide capacitance per unit area, and is the drain current which is
equal to for the transistor .
Substitute 0.75 mA for , for , for , for , for , and for .
Substitute for .
Substitute for
Step 7 Of 12
Assume the overdrive voltage of transistor and as .
Write the formula to find the drain current .
Thus, the branch currents .
Step 8 Of 12
Write the formula to find the aspect ratio of transistor (PMOS) in terms of overdrive voltage.
Here, is the drain source voltage equal to the overdrive voltage of the transistor .
Substitute 0.25 mA for , for , for , for , for , and for in equation (2).
Step 9 Of 12
Substitute for .
Substitute for
Step 10 Of 12
Write the formula to find the aspect ratio of transistor (NMOS) in terms of overdrive voltage.
Here, is the drain source voltage equal to the overdrive voltage of the transistor .
Substitute 0.25 mA for , for , for , for , for , and for .
Substitute for .
Substitute for
Step 11 Of 12

Substitute 3 V for , 1 V for , and 0.8 V for .
Write the formula to find the input CM level voltage as:
Here, is the voltage across the current source which is assumed as 0.3 V, and is the threshold voltage of (NMOS).
Substitute 0.3 V for , 0.7 V for , and 1 V for .
Step 12 Of 12
Substitute 3 V for , 1 V for , and 0.7 V for .
Thus the op amp is designed as follows:
The length of all the transistors is . The width of the transistors are
. The bias voltages are and the input CM level
voltage is .
Question:
Suppose the circuit of Fig. 9.24 is designed with ISS equal to 1 mA, ID9–ID12 equal to 0.5 mA, and (W/L)9−12
= 100/0.5.
(a) What CM level is required at X and Y?
(b) If ISS requires a minimum voltage of 400 mV, choose the minimum dimensions of M1–M8 to
allow a peak-to-peak swing of 200 mV at X and at Y.
(c) Calculate the overall voltage gain.

Figure 9.24 Two-stage op amp employing cascoding.
Step 1 Of 23
(a)
Refer to Figure 9.22 in the textbook for the two-stage op amp employing cascoding circuit.
Consider the expression to find the desired CM level at X and Y in the circuit.
…… (1)
Here, is the bias voltage in the circuit and is the gate-to-source voltage of MOSFET .
Consider the expression for bias current in the PMOS device in the circuit.
…… (2)
Here, is mobility of charge carriers in the PMOS device, is the gate oxide capacitance per unit area, W is the channel width, L is the
channel-length, is the channel-length modulation coefficient, and is the drain to source voltage of the PMOS device .
Step 2 Of 23
Consider the device in saturation condition, and then the value of channel-length modulation coefficient becomes .
…… (3)
Step 3 Of 23
…… (4)
Here, is the permittivity of free space and it is .
Substitute for .
Step 4 Of 23
…… (5)
From the table 2.1 in the textbook, the value of for PMOS device is .
Step 5 Of 23
Step 6 Of 23
Substitute for , for , for , for W, for , and for in equation (3).
Step 7 Of 23
Substitute 3 V for and 1.0889 V for in equation (1).
Thus, the desired CM level at X and Y in the circuit is .
Step 8 Of 23
(b)
Consider the expression to find maximum voltage at X in the circuit.
…… (6)
Here, is the peak-to-peak swing voltage at X.
Consider the expression to find minimum voltage at X in the circuit.
Step 9 Of 23
The NMOS devices , , , and are identical devices in the circuit. Therefore, the dimensions of the devices are equal.
Consider the expression for the drain current though the NMOS device .
…… (7)
Here, is mobility of charge carriers in the NMOS device, channel width to length ratio of MOSFET , is the gate-to-source
voltage of the NMOS device , is the drain-to-source voltage of the NMOS device , is the threshold voltage of the NMOS
device, and is the channel length modulation coefficient for NMOS device.
Step 10 Of 23
From the Table 2.1 in the textbook, write the values of required parameters.
Substitute .
As , , , rewrite equation (7).
…… (8)
Consider the expression for overdrive voltage of the NMOS device .
…… (9)
Here, is the minimum voltage required by the current .
Step 11 Of 23
Substitute for , for , for , for , and 0.7055 V for .
Rearrange the expression for the channel width of the device.
…… (10)
Step 12 Of 23
From the table 2.1 in the textbook, the value of for NMOS device is .

As the devices NMOS devices , , , and are identical devices in the circuit, the channel width of the devices is .
Step 13 Of 23
The PMOS devices , , , and are identical devices in the circuit. Therefore, the dimensions of the devices are equal.
Consider the expression for the drain current though the PMOS device .
…… (11)
Here, channel width to length ratio of MOSFET , is the gate-to-source voltage of the PMOS device , is the drain-to-
source voltage of the PMOS device , and is the channel length modulation coefficient for PMOS device.
Step 14 Of 23
From the Table 2.1 in the textbook, write the values of required parameters.
Substitute .
As , , , rewrite equation (11).
…… (12)
Consider the expression for overdrive voltage of the PMOS device .
Step 15 Of 23

Substitute for , for , for , for , and 04944 V for .
Rearrange the expression for the channel width of the device.
…… (13)
Step 16 Of 23
The value of for PMOS device is .
As the devices PMOS devices , , , and are identical devices in the circuit, the channel width of the devices is .
Thus, the channel width of the NMOS devices , , , and is and the channel width of the PMOS devices , , ,
and is .
Step 17 Of 23
(c)
Consider the expression to find the overall voltage gain in the circuit.
…… (14)
Here, is the transconductance of the MOSFET , is the transconductance of the MOSFET , is the transconductance of the
MOSFET , is the transconductance of the MOSFET , is the output resistance of the MOSFET , is the output resistance
of the MOSFET , is the output resistance of the MOSFET , is the output resistance of the MOSFET , is the output
resistance of the MOSFET , and is the output resistance of the MOSFET .
Step 18 Of 23
Consider the expression to find the transconductance of the MOSFET .

From the circuit, the transconductance of the MOSFET is equal to the transconductance of the MOSFET .
Step 19 Of 23
Substitute 0.5 mA for , 1.0889 V for , and for .
Step 20 Of 23

As the devices and are NMOS devices, the output resistance of the devices is equal to the output resistance of the NMOS device .
Step 21 Of 23
Step 22 Of 23
As the devices and are PMOS devices, the output resistance of the devices is equal to the output resistance of the PMOS device .
Step 23 Of 23

, for , for , and for in equation (14).
Thus, the overall voltage gain in the circuit is .

Question:
In Fig. 9.88, calculate the input-referred thermal noise if I1 and I2 are implemented by PMOS devices.
Figure 9.88
Step 1 Of 8
Refer to Figure 9.25 (c)in the textbook for the gain boosting in cascode stage circuit.
Consider two PMOS devices as and . Redraw the circuit by implementing the currents and by the PMOS devices and as
shown in Figure 1.
Step 2 Of 8
Consider the expression to find the input-referred thermal noise voltage of due to the NMOS device .
…… (1)
Here, k is the Boltzmann constant, T is the absolute temperature, is a coefficient which is equal to , and is the transconductance of the
MOSFET .
As the NMOS device is connected in cascode configuration, the noise induced due to the device is neglected.
Step 3 Of 8
Redraw the circuit in Figure 1 as Figure 2 to obtain the input-refereed thermal noise voltage due to the devices and .
Step 4 Of 8
Consider the expression for the current v in the circuit in Figure 2.
Consider the expression for the resistance in the circuit in Figure 2.
Consider the expression for the current in the circuit.
Consider the expression for the voltage at Y in the circuit.
Step 5 Of 8
Consider the expression for the voltage in the circuit.
Substitute for .
Step 6 Of 8
Step 7 Of 8
Consider the expression to find the input-referred thermal noise voltage of due to the devices and .
Substitute for .
Substitute for .
…… (2)
Step 8 Of 8
…… (3)
Compare equations (1), (2), (3),and observe that the input-referred thermal noise voltage of due to the devices and is much lesser than
the input-referred thermal noise voltage of due to the devices and . Therefore, neglect the input-referred thermal noise voltage of devices
, , and consider the total input-referred thermal noise voltage as the sum of thermal noise voltage due to the devices and .
Thus, the total input-referred thermal noise voltage in the circuit is .

Question:
Suppose that in Fig. 9.88, I1 = 100 μA, I2 = 0.5 mA, and (W/L)1−3 = 100/0.5. Assuming that I1 and I2 are
implemented with PMOS devices having (W/L)P = 50/0.5,
(a) Calculate the gate bias voltages of M2 and M3.
(b) Determine the maximum allowable output voltage swing.
(c) Calculate the overall voltage gain and the input-referred thermal noise voltage.
Figure 9.88
Step 1 Of 29
(a)
Refer to Figure 9.25 (c) in the textbook for the gain boosting in cascode stage circuit.
Consider the expression for drain current for NMOS device in the circuit.
…… (1)
channel-length, is the gate-to-source voltage of the device , is the channel-length modulation coefficient, and is the drain to
The threshold voltage of the NMOS device is 0.7 V.
Step 2 Of 29
Consider the device in saturation condition. Therefore, .

…… (2)
Step 3 Of 29
…… (3)
…… (4)
Step 4 Of 29
Substitute for .
Step 5 Of 29
…… (5)
Step 6 Of 29
Substitute 0.7 V for , for , for , for , for W, and for .
Consider the expression for gate bias voltage of the device .
…… (6)
Here, is the voltage at the node in the circuit.
From the circuit, is equal to the gate bias voltage of the device .
…… (7)
Step 7 Of 29
Modify equation (5) for thegate-to-source voltage of the NMOS device in the circuit.
…… (8)
Here, is the drain current of the device .
From the circuit, the drain current of the device is equal to the drain current of the device .
Step 8 Of 29
Substitute 0.7 V for , for , for , for , for W, and for in equation (8).
Step 9 Of 29
Consider the expression for gate bias voltage of the device .
Thus, the gate bias voltage of the devices and are and , respectively.
Step 10 Of 29
(b)
Consider two PMOS devices as and . Redraw the circuit by implementing the currents and by the PMOS devices and as
shown in Figure 1.
Step 11 Of 29
Consider the expression to find the maximum allowable output voltage swing.
…… (9)
Here, is the bias voltage to the circuit, is the overdrive voltage of the device , and is the overdrive voltage of the device .
Consider the expression to find overdrive voltage of the device .
…… (10)
Here, is the gate-to-source voltage of the device and is the threshold voltage of the PMOS device.
From the table 2.1 in the textbook, the threshold voltage of the PMOS device is .
Step 12 Of 29
The drain current of the device is equal to drain current of the device when the current source is implemented with the PMOS device
.
…… (11)
Here, is mobility of charge carriers in the PMOS device and is the drain to source voltage of the device .
Consider the device in saturation condition. Therefore, .
…… (12)
Step 13 Of 29
The channel length is same for both PMOS and NMOS devices. Therefore, the value of is .
From Table 2.1 in the textbook, the value of is and the value of is .
Substitute for and for in equation (3) to obtain the channel length of the PMOS device.
Step 14 Of 29
Step 15 Of 29
Consider the expression to find overdrive voltage of the device .
Substitute 3 V for , 0.4087 V for , 0.159 V for , and 0.7707 V for in equation (9).
Step 16 Of 29
(c)
Consider the expression to find the overall voltage gain in the circuit.
…… (13)
Here, is the transconductance of the MOSFET , is the transconductance of the MOSFET , is the transconductance of the
MOSFET , is the output resistance of the MOSFET , is the output resistance of the MOSFET , is the output resistance of
the MOSFET , is the output resistance of the MOSFET , and is the output resistance of the MOSFET .
As is limiting the gain, approximate equation (13) as follows:
…… (14)
Step 17 Of 29
Substitute for , for , for , for W, and for .
Step 18 Of 29
Step 19 Of 29
Step 20 Of 29
Consider the expression to find the input-referred thermal noise voltage due to the NMOS device .
…… (15)
Here, k is the Boltzmann constant, which is , T is the absolute room temperature, which is 300 K, is a coefficient which is equal
to , and is the transconductance of the MOSFET .
As the NMOS device is connected in cascode configuration, the noise induced due to the device is neglected.
Step 21 Of 29
Redraw the circuit in Figure 1 as Figure 2 to obtain the input-refereed thermal noise voltage due to the devices and .
Step 22 Of 29
Consider the expression for the current through the devices and in the circuit in Figure 2.
Consider the expression for the resistance in the circuit in Figure 2.
Consider the expression for the current in the circuit.
Consider the expression for the voltage at Y in the circuit.
Step 23 Of 29
Consider the expression for the voltage in the circuit.
Substitute for .
Step 24 Of 29
Step 25 Of 29
Consider the expression to find the input-referred thermal noise voltage of due to the devices and .
Substitute for .
Substitute for .
…… (16)
…… (17)
Compare equations (15), (16), (17), and observe that the input-referred thermal noise voltage of due to the devices and is much lesser
than the input-referred thermal noise voltage of due to the devices and . Therefore, neglect the input-referred thermal noise voltage of
devices , , and consider the total input-referred thermal noise voltage as the sum of thermal noise voltage due to the devices and .
…… (18)
Step 26 Of 29
Consider the expression to find the transconductance of the PMOS device .
Step 27 Of 29
Step 28 Of 29
Substitute for , 300 K for , for , for , and for in equation (18).
Step 29 Of 29

Thus, the overall voltage gain and the input-referred thermal noise voltage in the circuit are and , respectively.
Question:
In the circuit of Fig. 9.53, each branch is biased at a current of 0.5 mA. Choose the dimensions of M7 and
M8 such that the output CM level is equal to 1.5 V and VP = 100 mV.
Figure 9.53 CMFB using triode devices.
Step 1 Of 8
Draw the circuit as shown in Figure 1.
Step 2 Of 8
From Figure 1, the total drain current takes the path through a transistor when considering the first stage of the amplifier. The both deferential
transistors , and are identical.
Write the expression of the drain current for the MOSFET at the point P.
Here, is the gate-source voltage, is the drain-source voltage, L is the effective channel length of a MOSFET, W is the effective channel
width of a MOSFET, is mobility of electrons (NMOS), is the threshold voltage, and is the gate oxide capacitance per unit area.
Step 3 Of 8
Write the formula to find the drain current for the MOSFET due to source/drain side diffusion.
…… (1)
Here, is an effective channel length of the transistor .

Consider the common-mode level (CM level) of the transistors , and is 1.5 V. Consider CM level voltage as a gate input voltage to
the transistors , and , and the threshold voltage is .
Consider the drain current is the branch biased current though the transistor branch which is equal to 0.5 mA.
Step 4 Of 8
Consider the formula to find the gate oxide capacitance per unit area.
…… (2)
Here, is the permittivity of the oxide that is equal to , and is the gate oxide thickness.
Substitute for .
Step 5 Of 8
Substitute for .
Step 6 Of 8
Consider the voltage at point P in the Figure 1, is equal to the drain source voltage.

Substitute for , for , 100 mV for , 1.5 V for , 0.7 V for , and 0.5 mA for .
…… (3)
…… (4)
Step 7 Of 8
Write the formula to find the effective length of the MOSFET due to source/drain side diffusion.
…… (5)
Here, is the source/drain side diffusion, and is the same channel length of the MOSFETs in NMOS mirror circuit.
Refer to Table 2.1 in the textbook, the source/drain side diffusion is for NMOS circuit model is .
Consider that the MOSFETs in the circuit are simplest model have the channel length .
Since, the transistors and are identical in dimensions the width of both transistors are same.
Step 8 Of 8
Write the formula to find the dimensions of the transistors and .
Substitute for and , and for and to find .
Thus, the channel width of the both transistors and is , the channel length of the both transistors and is . The
aspect ratio of the both transistors and is .

Question:
Consider the CMFB network in Fig. 9.51. The amplifier sensing Vout,CM is to be implemented as a different
pair with active current mirror load.
(a) Should the input pair of the amplifier use PMOS devices or NMOS devices?
(b) Calculate the loop gain for the CMFB network.

Figure 9.51 Sensing and controlling output CM level.
Step 1 Of 12
(a)
Draw the circuit as shown in Figure 1 by indicating the MOSFETs.
Step 2 Of 12
In Figure 1, a simple amplifier is used to detect the difference between the voltage (CM level voltage) of the output voltages and
, and the applied reference voltage . The difference detected is the error voltage , it sends to the NMOS current source devices with a
negative feedback. When the both output voltages and are rises so that the voltage rises and results in increasing the drain currents
though the transistors and , and lowering the output CM-level voltage.
Step 3 Of 12
The input pair of the amplifier employs either PMOS devices or NMOS devices. The typical medium common mode voltage level is
approximately equal to 1.5 V, and gate-source voltages are in low voltage range around 0.7 V to 0.8 V.
In case of NMOS devices preferred for the input pair, when is less or approximately reaches to than the transconductance of the
NMOS devices drops to very low value of the middle voltage range of or to the low voltages of . Therefore, the normal operation of
the circuit is effected due to very less transconductance. In other hands, if PMOS devices are preferred as an input pair, the PMOS current source
devices have the ability to maintain the minimum value of transconductance, and allow the normal circuit operation.
Thus, the input pair of an error amplifier device should be the .
Step 4 Of 12
(b)
Draw the circuit diagram of the error amplifier as shown in Figure 2.
Step 5 Of 12
Draw the equivalent circuit diagram of the error amplifier using MOSFETs as shown in Figure 3.
Draw the first stage equivalent circuit diagram of the folded-cascaded amplifier with an infinite input resistance, and the transconductance , and
the output resistance as shown in Figure 4.
Step 6 Of 12
Step 7 Of 12
In Figure 4, consider is the cascaded output resistance at the output point and is the transconductance of the transistors.
Here, consider the transconductance is equal to the transconductance of each of the two differential pair and .
or
Step 8 Of 12
Write the formula of the output resistance which is a parallel equivalent of the cascaded resistances and .
…… (1)
The impedance seen by the transistor is , and the transistor has the lead source with the resistance of
Therefore the total output resistance at the cascaded resistance is,
The impedance is the output resistance of the cascaded mirror of transistors and .
Step 9 Of 12
Write the formula of open loop gain at by considering the as the input.
Substitute for , for .
…… (2)
Step 10 Of 12
Draw the circuit diagram of the error amplifier as shown in Figure 5 for the first stage of the circuit diagram to find the output resistance of an error
amplifier.
Step 11 Of 12
Consider the transconductance is equal to the transconductance of each of the two differential transistors pair and .
or
From the circuit diagram of equivalent circuit for an error amplifier in Figure 5, an error amplifier gain is,
…… (3)
In the equivalent circuit of error amplifier in Figure 5 the output resistance is the parallel equivalent of the cascaded resistors and .
Sunstitute for in equation (3).
…… (4)
Step 12 Of 12
Write the formula to find the total loop gain for the circuit of sensing and controlling output CM level (folded-cascaded amplifier) as,
…… (5)
Substitute equations (2) and (4) equation (5).
Here, the transconductances and .
Thus, the loop gain of common mode feedback circuit is, .

Question:
Repeat Problem 9.9.12b for the circuit of Fig. 9.52.
Figure 9.52 Alternative method of controlling output CM level.
Step 1 Of 10
Draw the circuit diagram of an alternative method of controlling output CM level as shown in Figure 1.
Step 2 Of 10
Draw the circuit diagram of the error amplifier as shown in Figure 2.
Step 3 Of 10
Draw the equivalent circuit diagram of the error amplifier using MOSFETs as shown in Figure 3.
Step 4 Of 10
Draw the first stage equivalent circuit diagram of the folded-cascaded amplifier with an infinite input resistance, and the transconductance , and
the output resistance as shown in Figure 4 by using the circuit in Figure 1.
In Figure 4, consider , and are the output resistance at output point, output resistance of each transistors and transconductance of the
transistors.
Step 5 Of 10
Consider the circuit transconductance is equal to the transconductance of transistor .
Write the formula of the output resistance which is a parallel equivalent of the cascaded output resistances and .
…… (1)
Step 6 Of 10
Consider the approximate output resistance at the point P due to the cascaded transistors and is,
The impedance seen by the transistor is , and the transistor has the lead source with the resistance of .
Therefore, the total output resistance at the cascaded transistor is,
Substitute for .
The impedance seen by the transistor is , and the transistor has the resistance in series of .
The impedance is the output resistance of the cascaded mirror of transistors and .

Step 7 Of 10
Write the formula of open loop gain at by considering the as the input.
…… (2)
Step 8 Of 10
Draw the circuit diagram of the error amplifier as shown in Figure 5 for the first stage of the circuit diagram to find the output resistance of an error
amplifier.
Step 9 Of 10
Consider the transconductance is equal to the transconductance of each of the two differential pair and .
or
From the circuit diagram of equivalent circuit of an error amplifier in Figure 5, an error amplifier gain is
…… (3)
In the equivalent circuit of an error amplifier in Figure 5 the output resistance is the parallel equivalent of the cascaded resistors and
.
Sunstitute for in equation (3).
…… (4)
Step 10 Of 10
Write the formula to find the total loop gain for the circuit of controlling output CM level.
…… (5)
Substitute equations (2) and (4) equation (5).
Thus, the loop gain of common mode feedback circuit is,
.
Question:
In the circuit of Fig. 9.73(a), assume that (W/L)1−4 = 100/0.5,C1 = C2 = 0.5 pF, and ISS = 1 mA.
(a) Calculate the small-signal time constant of the circuit.
(b) With a 1-V step at the input [Fig. 9.73(c)], how long does it take for ID2 to reach 0.1ISS?
Figure 9.73
Figure 9.73
Step 1 Of 19
(a)
Step 2 Of 19
Consider the expression for small-signal voltage gain for the circuit in Figure 1.
…… (1)
Here, is the transconductance of the MOSFET and is the output impedance in the circuit.
Here, is the output resistance of the MOSFET and is the output resistance of the MOSFET .
Consider the expression for input voltage in the circuit.
…… (2)
Step 3 Of 19
Consider the expression for output voltage in the circuit in Figure 1.

Step 4 Of 19
Substitute for .
Step 5 Of 19
…… (3)
Consider the expression for gain in terms of time constant.
…… (4)
Here, is the small-signal time constant.
Step 6 Of 19
Compare equations (3), (4), and write the small-signal time constant of the circuit.
Thus, the small-signal time constant of the circuit is .
Step 7 Of 19
(b)
Refer to Figure 9.56 (c) for the required circuit.
Consider the expression to find the required time.
As is a small current, consider the current through the capacitors and is equal to .
Consider the general expression to find the required time.
…… (5)
At , find the values of and .
Step 8 Of 19
Consider the expression for drain current for NMOS devices and in the circuit.
…… (6)
channel-length, is the gate-to-source voltage of the devices, is the channel-length modulation coefficient, and is the drain to source
voltage of the devices.
Step 9 Of 19
Consider the devices in saturation condition. Therefore, .

Step 10 Of 19
Modify the expression at .
…… (7)
The threshold voltage of the NMOS device is 0.7 V.
…… (8)
…… (9)
Step 11 Of 19
Substitute for .
Step 12 Of 19
…… (10)
Step 13 Of 19
Step 14 Of 19
At , and .
Divide with .
Modify equation (10) for the device at .
…… (11)
Modify equation (10) for the device .

…… (12)
Step 15 Of 19
Substitute 9 for .
…… (13)
Step 16 Of 19
As 1 V step at the input, write the expression as follows:
Step 17 Of 19
Modify equation (5) for the device .
Step 18 Of 19
Substitute 0.386 V for , 0.159 V for , for , and for .
Step 19 Of 19
Thus, the time take for to reach is .

Question:
It is possible to argue that the auxiliary amplifier in a gain-boosting stage reduces the output impedance.
Consider the circuit as drawn in Fig. 9.89, where the drain voltage of M2 is changed by ∆V to measure the
output impedance. It seems that, since the feedback provided by A1 attempts to hold VX constant, the
change in the current through rO2 is much greater than in the original circuit, suggesting that Rout ≈ rO2.
Explain the flaw in this argument.
Figure 9.89
Step 1 Of 3
(a)
Refer to Figure 9.24 (b), Figure 9.24 (c), and Figure 9.67 in the textbook for the required circuits.
Consider a test voltage as and redraw the circuit in Figure 9.67 as shown in Figure 1.
Step 2 Of 3
Consider the current driven by the voltage source as in Figure 1.
The consideration of current is the possible mistake in the argument. From the circuit in Figure 1, the current .is equal to .
…… (1)
From the circuit in Figure 1, write the expression of current through .
The current through is equal to when the current from the negative terminal of the amplifier is considered as negligible value.
Step 3 Of 3
From the circuit in Figure 1, write the expression of current through .
From equation (1), it is clear that, the current is equals to the current . In actual, the current is larger than the current as the
device provides some extra current. Therefore, the voltage across increases by a factor of and the current increases by a factor
of , which is .
Thus, the flaw in the argument is explained.
Question:
Calculate the CMRR of the circuit shown in Fig. 9.73(a).
Figure 9.73
Step 1 Of 7
Refer to Figure 9.56 (a)in the textbook.
Consider the expression to find the common mode rejection ratio (CMRR) of the circuit.
…… (1)
Here, is the differential mode gain and is the common mode gain.
Consider the expression to find the differential mode gain of the circuit.
Here, is the transconductance of the MOSFET , is the output resistance of the MOSFET , and is the output resistance of the
MOSFET .
Step 2 Of 7
Consider the resistance of the current source as and redraw the circuit as shown in Figure 1 to obtain the common mode gain of the circuit.
Step 3 Of 7
Simplify the circuit in Figure 1 as Figure 2.
Step 4 Of 7
Consider the expression to find the common mode gain of the circuit.
…… (2)
Here, is the output voltage of the circuit and sis the common mode voltage of the circuit.
From the circuit, write the expression for .
…… (3)
Step 5 Of 7
Consider the expression for from the circuit in Figure 2.
Step 6 Of 7
…… (4)

Step 7 Of 7
Thus, the CMRR of the circuit is .

Question:
Calculate the input-referred flicker noise of the op amp shown in Fig. 9.85(a).
Figure 9.85 Noise in a folded-cascode op amp.
Step 1 Of 5
As the devices , , , , and are in cascode configuration in the circuit, the input-referred flicker noise due to the devices is
neglected.
Therefore, the remaining devices , , , , , and are the potentially significant sources for the input-referred flicker noise
voltage in the circuit.
Step 2 Of 5
Consider the expression for input-referred flicker noise voltage due to the devices and .
…… (1)
Here, is the voltage gain, is the noise coefficient of NMOS device, is the capacitance per unit area, is the frequency, is the
transconductance of the devices and , and is the output resistance in the circuit.
Consider the expression for the voltage gain in the circuit.
Step 3 Of 5
…… (2)
Here, is the noise coefficient of PMOS device and is the transconductance of the devices and .
Step 4 Of 5
…… (3)
Here, is the transconductance of the devices and .
Step 5 Of 5
Consider the expression for total input-referred flicker noise voltage due to the devices , , , , , and .
Thus, the total input-referred flicker noise voltage of the op amp in circuit in Figure 9.64 (a) in the textbook is
.
Question:
In this problem, we design a two-stage op amp based on the topology shown in Fig. 9.90. Assume a power
budget of 6 mW, a required output swing of 2.5 V, and Lef f = 0.5 μm for all devices.
Figure 9.90
(a) Allocating a current of 1 mA to the output stage and roughly equal overdrive voltages to M5
and M6, determine (W/L)5 and (W/L)6. Note that the gate-source capacitance of M5 is in the signal
path, whereas that of M6 is not. Thus, M6 can be quite a lot larger than M5.
(b) Calculate the small-signal gain of the output stage.
(c) With the remaining 1 mA flowing through M7, determine the aspect ratio of M3 (and M4) such
that VGS3 = VGS5. This is to guarantee that if Vin = 0 and hence VX = VY, then M5 carries the
expected current.
(d) Calculate the aspect ratios of M1 and M2 such that the overall voltage gain of the op amp is
equal to 500.
Step 1 Of 11
(a)
Consider the NMOS transistor and the PMOS transistor has equal overdrive voltages (that is, ). The power is 6 mW, the
length is , and the output swing is 2.5 V. The drain current is or is 1 mA.
Consider the expression for the overdrive voltage.
Here, is the drain to drain voltage.
Substitute 3 V for and 2.5 V for output swing.
Step 2 Of 11
Consider the expression for the drain current for NMOS transistor when drain voltage is greater than threshold voltage.
channel-length modulation coefficient of NMOS, is the gate oxide capacitance per unit area, W is the width, and is the length, which is
.
Rearrange the equation to find .
…… (1)
Step 3 Of 11
…… (2)
Here,
…… (3)
Step 4 Of 11
Substitute for , for , for and for , and for in equation

(1).
Substitute the unit for .
Step 5 Of 11
Consider the general expression for the drain current for PMOS transistor when drain voltage is greater than threshold voltage.
Here, is the channel-length modulation coefficient of PMOS.
Substitute for , for , for and for , and for .
Thus, the for NMOS transistor is and the for PMOS transistor is .
Step 6 Of 11
(b)
Consider the expression for the voltage gain of the circuit in first stage.
Here, is the transconductance of the transistor , is the output resistance of transistor , and is the output resistance of transistor
.
Consider the expression for the voltage gain of the circuit in second stage.
Here, is the transconductance of the transistor , is the output resistance of transistor , and is the output resistance of transistor
.
Or
…… (4)
Here, is the drain current, is the gate to source voltage of the transistor , is the drain current of transistor , is the drain
current of transistor .
Substitute for , for , for , and for , , and in equation (4).
Thus, the small-signal gain of the output stage is .
Step 7 Of 11
(c)
Consider the drain current of the transistor is . Refer to Figure 9.68 in the textbook, consider the drain current for the transistor
and are and respectively (that is, ).

From Part (a),
Since, .Therefore, .
Consider the expression for for NMOS transistor when the gate voltage is greater than threshold voltage.
…… (5)
Step 8 Of 11
Substitute for , for , for and for , and for in

equation (5).
Thus, the aspect ratio of the transistors and is .
Step 9 Of 11
(d)
Consider the overall voltage gain of the operational amplifier is 500. Refer to Figure 9.68 in the textbook, consider the drain current for the
transistor and are and respectively (that is, ).

Refer to Figure 9.68 in the textbook; consider the expression for overall voltage gain.
…… (6)

Step 10 Of 11
Refer to Part (c).
Refer to Part (b).
Substitute 500 for , 26.67 for , for , and for .
Step 11 Of 11

Thus, the aspect ratio of the transistors and is .
Question:
Consider the op amp of Fig. 9.90, assuming that the second stage is to provide a voltage gain of 20 with a
bias current of 1 mA.
(a) Determine (W/L)5 and (W/L)6 such that M5 and M6 have equal overdrive voltages.
(b) What is the small-signal gain of this stage if M6 is driven into the triode region by 50 mV?
Figure 9.90
Step 1 Of 8
(a)
Consider the expression for the voltage gain of the circuit in second stage.
…… (1)
Here, is the transconductanceof the transistor , is the output resistance of transistor , and is the output resistance of transistor
.
or
…… (2)
Here, is the drain current, is the gate to source voltage of the transistor , is the threshold voltage, is the drain current of
transistor , is the drain current of transistor , is the channel-length modulation coefficient of NMOS, and is the channel-length
modulation coefficient of PMOS.
Step 2 Of 8
Consider the NMOS transistor and the PMOS transistor has equal overdrive voltages. The voltage gain of the circuit in second stage is
20 and the drain current or is 1 mA.
Substitute for , for , 20 for , and for , , and in equation (2)

Step 3 Of 8
…… (3)
Here,
…… (4)
Step 4 Of 8
Consider the expression for for NMOS transistor when the gate voltage is greater than threshold voltage.
…… (5)
Here,
is the drain current, is the mobility of electrons, is the gate oxide capacitance per unit area,W is the width, and is the length.
Substitute for , for , for , for ,and for in equation (5).

…… (6)
Step 5 Of 8
Step 6 Of 8
Consider the expression for for PMOS transistor when the gate voltage is greater than threshold voltage.
…… (7)
Here,
is the drain current, is the mobility of holes, is the gate oxide capacitance per unit area,W is the width, and is the length.
Thus, the for NMOS transistor is and the for PMOS transistor is .
Step 7 Of 8
(b)
Consider if the PMOS transistor is driven into the region of triode by 50 mV (that is, ), then the output resistance
of transistor is expressed as follows:
…… (8)
Here, is the drain-source voltage, is the threshold voltage of PMOS transistor, and is the gate to source voltage of the transistor
.
Compare equation (1) and (2).
Calculate the output resistance of transistor .
…… (9)
From equation (2), calculate the voltage gain of the circuit in second stage by using equation (8) and (9).
Substitute for , 449 for , for , for , for , for

, and for and .
…… (10)
Step 8 Of 8

Thus, the small-signal gain of the second stage is .
Question:
The op amp designed in Problem 9.9.18d is placed in unity-gain feedback. Assume that |VGS7 − VT H7| = 0.4
V.
(a) What is the allowable input voltage range?
(b) At what input voltage are the input and output voltages exactly equal?
Step 1 Of 14
(a)
Consider .Since, the overdrive voltage . Therefore, .

Refer to the reference problem 9.18 in the textbook.
Consider the overall voltage gain of the operational amplifier is 500.Refer to Figure 9.68 in the textbook, consider the drain current for the
transistors , , , is equal to (that is, ).

Refer to Figure 9.68 in the textbook; consider the expression for overall voltage gain.
…… (1)
Here, is the transconductance of the transistor , is the output resistance of transistor , is the output resistance of transistor
, is the transconductance of the transistor , is the output resistance of transistor , and is the output resistance of transistor
.
Step 2 Of 14
Step 3 Of 14

Step 4 Of 14
Refer to Figure 9.68 in the textbook; consider the expression for the voltage gain of the circuit in second stage.
or
…… (2)
Here, is the drain current, is the gate to source voltage of the transistor , is the drain current of transistor , is the channel-
length modulation coefficient of PMOS, is the channel-length modulation coefficient of NMOS, is the drain current of transistor .
Step 5 Of 14

Step 6 Of 14
The magnitude of overdrive voltage for the transistor is .
Step 7 Of 14
Refer to Figure 9.68 in the textbook; calculate the expression for the maximum input voltage.
Substitute 3 V for , 0.4 V for , 0.356 V for , and 0.8 Vfor .
Step 8 Of 14
Refer to the reference problem in the textbook; consider . Therefore,

Refer to Figure 9.68 in the textbook; calculate the expression for the minimum input voltage.
Substitute for .
Therefore, the input voltage range is expressed as .
Thus, the permissible input voltage range is .
Step 9 Of 14
(b)
Consider at , the input voltage . Since is connect to the output voltage .
Consider, if the input , then the drain current .Therefore, the voltage at node X and Y are equal.
Consider the expression for the drain current for PMOS transistor when drain voltage is greater than threshold voltage.
…… (3)
Here, is the mobility of holes, is the gate-source voltage of the transistor , is the drain-source voltage, is the threshold
voltage, is the gate oxide capacitance per unit area,W is the width, and is the length.
…… (4)
Step 10 Of 14
Step 11 Of 14
Consider expression for the overdrive voltage for the transistor .

Step 12 Of 14
Rearrange the equation (3) to find .
…… (5)
From Figure 9.68, consider the expression for the drain to source voltage of the transistor .
Substitute 3 V for , 0.4 V for , and 0.95 V for .
Step 13 Of 14
Substitute for , for , 1.65 V for , 206 for , for , and for in
equation (5).
Step 14 Of 14
From Figure 9.68, consider the expression for the input voltage.
Thus, the input voltage to the circuit is when the input and output voltages are exactly equal.
Question:
Calculate the input-referred noise of the op amp designed in Problem 9.9.18d.
Step 1 Of 12
Consider the input-referred noise due to the transistor is negligible. Since induce common mode gain is very small.
Consider the expression for the thermal noise due to transistors for the input referred noise of .
…… (1)
Here, is the transconductance of transistor ,k is the Boltzmann constant, which is , is the body effect
coefficient, and T is the temperature.
…… (2)
Here, is the transconductance of transistors .
Step 2 Of 12
From Figure 9.68, consider the expression for the first stage of the input-referred noise.
…… (3)
Substitute equation (1) and (2) in equation (3).
From Figure 9.68, consider the expression for the second stage of the output-referred noise.
Here, is the transconductance of transistor , is the transconductance of transistor , is the output resistance of transistor
and is the output resistance of transistor .
Step 3 Of 12
From Figure 9.68, consider the expression for the overall input-referred noise.
…… (4)
Here, is the output resistance of transistor and is the output resistance of transistor .
Consider the overall voltage gain of the operational amplifier is 500.Refer to Figure 9.68 in the textbook, consider the drain current for the
transistors , , , is equal to (that is, ).

Consider the expression for overall voltage gain.
…… (5)
Step 4 Of 12
Step 5 Of 12
Step 6 Of 12
Refer to Figure 9.68 in the textbook; consider the expression for the voltage gain of the circuit in second stage.
…… (6)
or
…… (7)
Here, is the drain current, is the gate to source voltage of the transistor , is the drain current of transistor , is the channel-
length modulation coefficient of PMOS, is the channel-length modulation coefficient of NMOS, is the drain current of transistor .
Step 7 Of 12
Step 8 Of 12
…… (8)
Similarly,the transconductance of the transistors and is expressed byusing equation (8).

…… (9)
Step 9 Of 12
Refer to Figure 9.68 in the textbook; consider the drain current for the transistor and are and respectively (that is,
).
Consider expression for the overdrive voltage for the transistor .
Step 10 Of 12
Step 11 Of 12
Substitute for , for k, 300 K for T, for and , for , for ,
for , and for in equation (4).

The input-referred noise voltage of the operational amplifier .
Step 12 Of 12
Square root on both sides.
Therefore, the value corresponds to an input noise voltage is .
Thus, the input-referred noise voltage of the operational amplifier is .

Question:
It is possible to use the bulk terminal of PMOS devices as an input [10]. Consider the amplifier shown in
Fig. 9.91 as an example.
Figure 9.91
(a) Calculate the voltage gain.
(b) What is the acceptable input common-mode range?
(c) How does the small-signal gain vary with the input common-mode level?
(d) Calculate the input-referred thermal noise voltage and compare the result with that of a
regular PMOS differential pair having NMOS current-source loads.
Step 1 Of 7
(a)
Refer to Figure 9.69 in the textbook. In this figure, the transistors and are connected in cascode configuration.
Assume the mirror configuration of cascode transistors and with and .

Consider the voltage gain as,
Here, is the transconductance and is the total output resistance.

For the mirror circuit, assume only one stage of the circuit (left); then, the total output resistance can be written as,
And the transconductance of the transistors
Step 2 Of 7
Substitute and in the expression of to find the voltage gain of the circuit.
Here, is the transconductance of the body of the transistor , is the output resistance of transistor , and is the output
resistance of transistor .
…… (1)
Thus, the differential voltage gain of the operational amplifier is
Step 3 Of 7
(b)
The input common mode voltage is always a bit greater than the difference between to keep the transistors in the forward operating
mode in the circuit configuration of Figure 9.69.
Consider the expression for the input commonmode voltage of the transistor .
Here, is the drain to drain voltage and is the diode junction voltage of the diode between the source and the bodyof transistor .
Thus, the range of the input common-mode is .
Step 4 Of 7
(c)
Consider the expression for the transconductance of body of the transistor.
…… (2)
Here, is the transconductance of the transistor, is the built-in-voltage of the transistor, and is the source to body voltage.
Consider that if the input common mode voltage decreases with the increase in source to body voltage , then the transconductance
of the body of the transistor decreases. That is, from equation (2), the transconductance of body of the transistor is inversely proportional to
.
Therefore, the voltage gain of the operational amplifier is decreased.

Thus, the small-signal gain decrease with the input common mode level is explained.
Step 5 Of 7
(d)
Consider the expression for the thermal noise due to transistors for the output referred noise of .
Here, is the transconductance of transistor , is the transconductance of transistor , k is the Boltzmann constant, T is the
temperature, and is the output resistance.
Step 6 Of 7
Step 7 Of 7
Refer to Figure 4.32(b) in the textbook for the voltage gain for NMOS current–source load, and it is expressed as,
Here, N and P denote NMOS and PMOS, respectively.

…… (3)
By comparing equations (2) and (3), the negative sign is only the difference for the differential voltage gain.
Thus, the input-referred thermal noise voltage is . The result is compared to the PMOS differential pair with NMOS
current-source loads.
Question:
The idea of the active current mirror can be applied to the output stage of a two-stage op amp as well. That
is, the load current source can become a function of the signal. Figure 9.92 shows an example [11]. Here,
the first stage consists of M1–M4, and the output is produced by M5–M8. Transistors M7 and M8 operate as
active current sources because their current varies with the signal voltage at nodes Y and X, respectively.
(a) Calculate the differential voltage gain of the op amp.
(b) Estimate the magnitude of the three major poles of the circuit.
Figure 9.92
Step 1 Of 5
(a)
Consider the circuit is a mirror amplifier. And assume the first stage to calculate the voltage gain
From Figure 9.70, consider the expression for the voltage gain of the first stage.
Here, is the transconductance of transistor , is the output resistance of transistor , and is the output resistance of transistor
.
…… (1)
From Figure 9.70, consider the expression for the voltage gain of the second stage.
Here, is the transconductance of transistor , is the output resistance of transistor , and is the output resistance of transistor
.
…… (2)
Step 2 Of 5
Calculate the total differential voltage gain.
…… (3)
Thus, the differential voltage gain of the operational amplifier is
Step 3 Of 5
(b)
Calculate the magnitude of three major poles of the circuit from Figure 9.70.
In Figure 9.70, find the first major pole in the circuit. In this Figure, the transistors and , and and are connected in parallel. Also,
the effects of capacitances included in the circuit are , , , , , and .Therefore, consider the expression for the first
major pole of the circuit.
Here,
is the transconductance of transistor , is the output resistance of transistor , is the output resistance of transistor , is
the drain to gate capacitance of transistor , is the drain to body capacitance of transistor , is the gate to source capacitance of
transistor , is the drain to body capacitance of the transistor , is the gate to source capacitance of transistor , and is
the gate to drain capacitance of transistor .
Step 4 Of 5
In Figure 9.70, find the second major pole at node X and Y in the circuit. In this Figure, the transistors and , and and are
connected in parallel. Also, the effects of capacitances included in the circuit are , , , , , , , .Therefore,
consider the expression for the second major pole of the circuit at node X and Y.
…… (4)
Here,
is the transconductance of transistor , is the transconductance of transistor , is the drain to gate capacitance of transistor
, is the drain to body capacitance of transistor , is the drain to gate capacitance of transistor , is the drain to base
capacitance of transistor , is the gate to source capacitance of transistor , is the gate to drain capacitance of transistor ,
is the gate to source capacitance of transistor , is the gate to drain capacitance of transistor .
Step 5 Of 5
In Figure 9.70, find the third major pole at output node in the circuit. In this Figure, the transistors and are connected in parallel at output
node . Also, the effects of capacitances included in the circuit.
Therefore, consider the expression for the third major pole of the circuit at output node.
Here, is the drain to body capacitance of transistor and is the drain to body capacitance of transistor .
Thus, the magnitudes of the three major poles of the circuit are
, .
Question:
The circuit of Fig. 9.93 employs a fast path in parallel with the slowpath. Calculate the differential
voltage gain of the circuit. Which ransistors typically limit the output swing?
Figure 9.93
Step 1 Of 4
Refer to Figure 9.71 in the textbook. The circuit is differential mirror amplifier.
From Figure 9.71, calculate the voltage gain of fastest path through .
Here, is the transconductance of transistor , is the output resistance of transistor , and is the output resistance of transistor .
…… (1)
Step 2 Of 4
From Figure 9.71, calculate the voltage gain of slowest path.
Here, is the transconductance of transistor , is the transconductance of transistor , is the output resistance of transistor ,
and is the output resistance of transistor .
…… (2)
Step 3 Of 4
Calculate the overall differential voltage gain.
…… (3)
Step 4 Of 4
Refer to Figure 9.71, the transistors is used usually for limiting the output swing. The condition of the output swing which depends on the
overdrive voltages of cascode transistors and is written as,
Here, is the supply power voltage, is the over drive voltages of and .
Thus, the overalldifferential voltage gain of the circuit is
and the output swing is limited by using the transistors .

Question:
Calculate the input-referred thermal noise of the op amp in Fig. 9.93.
Figure 9.93
Step 1 Of 3
…… (1)
Here, is the transconductance of transistor , k is the Boltzmann constant, and T is the temperature.
…… (2)
Here, is the transconductance of transistor .
…… (3)
Step 2 Of 3
Here, is the transconductance of transistor and is the output resistance.
…… (4)
Here, is the output resistance of transistor and is the output resistance of transistor .
Step 3 Of 3
Calculate the total input-referred thermal noise of the operational amplifier in Figure 9.71.
…… (5)
Substitute equation (1), (2), (3) and (4) in equation (5).
Thus, the input-referred thermal noise of the operational amplifier in Figure 9.71 is
.
Question:
Determine the slew rate of a fully-differential folded-cascode op amp.
Step 1 Of 0
Question:
Calculate the slew rate in Fig. 9.75 if ISS > IP.
Figure 9.75 Slewing in folded-cascode op amp.
Step 1 Of 0
Question:
An amplifier with a forward gain of A0 and two poles at 10 MHz and 500 MHz is placed in a unity-gain
feedback loop. Calculate A0 for a phase margin of 60°.
Step 1 Of 9
Write the formula to find the phase margin of an amplifier.
Here, is the phase angle at gain crossover frequency .
Substitute for PM.
The phase angle at gain cross over frequency is .
Step 2 Of 9
Write the formula to find the phase angle at gain crossover frequency by using the two poles of an amplifier.
…… (1)
Here, and are the pole frequencies of an amplifier system, which denotes the low frequency pole is at frequency , and high frequency
pole is at frequency .
Substitute for , for , for in Equation (1).
…… (2)
Step 3 Of 9
Perform an iteration process to find the gain crossover frequency .

Case 1:
Randomly choose the value of gain crossover frequency as .
Substitute for in Right Hand Side function of the Equation (2).
The choosing is not satisfying the function in Equation (2).
Step 4 Of 9
Case 2:
The choosing is not satisfying the function in Equation (2), and it is resulted in close value to .
Step 5 Of 9
Case 3:
Choosing gain crossover frequency as is not satisfying the function in Equation (2), and it is resulted very close value to .
Step 6 Of 9
Case 4:
Choosing gain crossover frequency as is resulted the value approximately equal to .
Step 7 Of 9
Case 5:
Randomly consider the value of gain crossover frequency as .
Step 8 Of 9
Choosing the gain crossover frequency as is resulted the value more than . Therefore, further selection of the value of gain
crossover frequency greater than will results in more than required value .
From the iteration process, the approximate value of gain crossover frequency is .
Step 9 Of 9
Write the formula to find the low frequency gain .
Substitute for , and for to find .
Thus, the low frequency gain is .

Question:
An amplifier with a forward gain of A0 has two coincident poles at ωp. Calculate the maximum value of A0
for a 60° phase margin with a closed-loop gain of (a) unity and (b) 4.
Step 1 Of 7
(a)
Consider the two poles of an amplifier at the lower frequency , and the higher frequency are coincident at .
Here, is the two poles coincident frequency.

Illustrate the criteria of bode plot of an amplifier for the magnitude plot and phase plot as in Figure 1.
Step 2 Of 7
In Figure 1, the two poles are coincident with unity gain, and the slope per decade of the magnitude line is . Generally in case of two pole
system, the phase margin begins to change at the frequency and reaches to at the pole frequency , and reaches to at
the pole frequency . From the Figure 1, the phase margin changes in steps of for the case of two poles coincident from to
.
When the closed loop system gain is unity its magnitude reaches so that the phase shift is reaches to at gain crossover point
as shown in Figure 1.
Step 3 Of 7
Write the formula to find the number of decades for phase margin as,
Substitute for phase margin, and for .
Thus, the two pole system has phase margin as .
Step 4 Of 7
The system has unity feedback gain that corresponds to magnitude as , where .
Write the formula to find the number of decades between two frequencies and on the log scale which must be equal to for
phase margin.
Re-write the equation to find .
The approximate possible value of in terms of is .
Step 5 Of 7
Write the formula to find the forward gain of the two pole system when two poles are coincident.
Substitute for .
Thus, the forward gain of the two pole system when two poles are coincident is with closed loop gain unity.
Step 6 Of 7
(b)
Consider the closed loop gain is 4.
The system has unity feedback gain that corresponds to magnitude as .
The forward gain increases as the magnitude of closed loop system increases by a factor 4 to maintain the phase margin as .
Step 7 Of 7
Write the formula to find the forward gain when closed loop gain is 4.
Here, is the magnitude of a two pole system with unity closed loop gain, and is the magnitude of a two pole system with the
closed loop gain 4.
Substitute H for , 4H for , and 13.2 dB for .
Thus, the forward gain of the two pole system when two poles are coincident is with closed loop gain 4.
Question:
An amplifier has a forward gain of A0 = 1000 and two poles at ωp1 and ωp2. For ωp1 = 1 MHz, calculate the
phase margin of a unity-gain feedback loop if (a) ωp2 = 2ωp1 and (b) ωp2 = ωp1.
Step 1 Of 13
(a)
Consider the two pole unity-gain feedback system.
Consider the feedback gain factor for a unity-gain feedback system is 1, and the higher pole frequency is equal to .
Write the formula to find the magnitude for the forward gain .
Here, is the forward gain.
Substitute 1000 for , and 1 for .
Step 2 Of 13
Draw the magnitude plot of the system as shown in Figure 1.
From the Figure 1, since the system is two pole system the slope of magnitude straight line between the frequencies and is
.
Step 3 Of 13
Write the formula to find the total gain with respect to the change in gain from to .
…… (1)
Here, is the lower pole frequency, and is the higher pole frequency.
The with respect to the change in gain from to in dB is .
Step 4 Of 13
Write the formula to find the number of decades for with respect to slope for two pole system.
…… (2)
Substitute for , and for slope in equation (2).
Thus, the two pole system has the gain .
Step 5 Of 13
Write the formula to find the number of decades between two frequencies and on the log scale.
Here, is the gain crossover frequency.
Substitute for .
Substitute 1 MHz for .
Step 6 Of 13
Reduce the equation to find .

The gain crossover frequency is is .
Step 7 Of 13
Write the formula to find the phase angle at gain crossover frequency by using the two poles of an amplifier.
…… (3)
Here, and are the pole frequencies of an amplifier system, which denote the low frequency pole is at frequency , and high frequency
pole is at frequency .
Substitute 1 MHz for , for .
Step 8 Of 13
…… (4)
Thus, the phase margin of an amplifier with a unity feedback loop is .
Step 9 Of 13
(b)
Consider the higher pole frequency is equal to .
From the Figure 1, since the system is two pole system the slope of magnitude straight line between the frequencies and is
.

The with respect to the change in gain from to in dB is .
Step 10 Of 13
Substitute for , and for slope in equation (2).
Thus, the two pole system has the gain .
Step 11 Of 13
Write the formula to find the number of decades between two frequencies and on the log scale.
Substitute for .
Substitute 1 MHz for .
Reduce the equation to find .
Step 12 Of 13
Substitute 1 MHz for , for .
Step 13 Of 13

Thus, the phase margin of an amplifier with a unity feedback loop is .
Question:
A unity-gain closed-loop amplifier exhibits a frequency peaking of 50% in the vicinity of the gain crossover.
What is the phase margin?
Step 1 Of 9
Consider the feedback gain factor for a unity-gain feedback system is 1 at gain crossover frequency.
Consider the transfer function of a unity-gain closed loop amplifier as,
Here, is the open loop transfer function, and is the feedback gain factor.
Substitute 1 for .
…… (1)
Here, is the gain crossover frequency.
Step 2 Of 9
Write the condition of a unity-gain closed loop transfer function at the frequency .
Consider the unity-gain open-loop amplifier frequency response exhibits a sharp peak in the vicinity , than the magnitude of a system
transfer function has the condition as,
Consider the unity-gain closed-loop amplifier frequency response exhibits a sharp peak in the vicinity , than the condition for magnitude of a
system is,
Step 3 Of 9
Write the formula to find the magnitude of a unity-gain closed loop system when closed-loop frequency response exhibits a sharp peak 50% in the
vicinity of .
Therefore, it is clear that when a unity-gain closed loop amplifier frequency response exhibits sharp peak in frequency at gain crossover frequency
the same results in increasing the gain.
Draw the magnitude plot of a closed loop frequency response as shown in Figure 1.
Step 4 Of 9
Consider the open loop transfer function at the point of gain crossover frequency (GX).
Here, is the phase angle.
Substitute 1 for .
Step 5 Of 9
Write the magnitude of a closed loop transfer function using equation (1).

Substitute for .
Step 6 Of 9
Simplify the value.
Substitute for .
…… (2)
Step 7 Of 9
Consider the function in the denominator of Left Hand side function in equation (2).
Substitute 1 for .
Take square on both sides.
Simplify further.
Rewrite the equation to find the phase angle .

Consider the phase angle is exists in the field between where the cosine value is negative. Therefore, consider that the phase
angle as .
Step 8 Of 9
…… (3)
Substitute for .
Step 9 Of 9
Thus, the phase margin of a unity-gain closed loop amplifier is .

Question:
Consider the transimpedance amplifier shown in Fig. 10.73, where RD = 1 kΩ, RF = 10 kΩ, gm1 = gm2 =
1/(100 Ω), and CA = CX = CY = 100 fF. Neglecting all other capacitances and assuming that λ = γ = 0,
compute the phase margin of the circuit. (Hint: break the loop at node X.)
Figure 10.73
Step 1 Of 12
Redraw the Figure 10.41 by considering breaking the loop in the circuit at node X as shown in Figure 1. That is, breaking the loop in the circuit
which is replaced by the impedance in both the ends and it is shown in Figure 2.
Figure 2 shows the modified circuit diagram when breaking the loop at node X.
Step 2 Of 12
In Figure 2, write the expression for the equivalent impedance .
Here, is the capacitance of the capacitor at node Y.

From Figure 2, consider the expression for the voltage gain of the circuit for first stage.
Substitute for .

Step 3 Of 12
Calculate the corner frequency from the voltage gain .
Step 4 Of 12
From Figure 2, consider the expression for the voltage gain of the circuit for second stage.
Here, is the capacitance of the capacitor at node A. and is the resistance of the resistor.

Step 5 Of 12
From Figure 2, consider the expression for the voltage gain of the circuit for third stage.
Here, is the transconductance of the transistor , is the drain resistance, and is the capacitance of the capacitor at node X.
Step 6 Of 12
Consider the expression for overall gain of the circuit.

Substitute for , , and , for , for , for and .
…… (1)
Step 7 Of 12
From Figure 2, calculate the expression for the loop gain.
Substitute for s.
…… (2)
Step 8 Of 12
Find the magnitude plot of the system.
The various terms of are tabulated in Table 1 in the increasing order of their corner frequencies.
Choose the low frequency less than and choose the high frequency greater than . Consider and .
For :
Step 9 Of 12
For :
For :
For :
For :
Step 10 Of 12
Step 11 Of 12
Consider the expression to find the phase margin.
…… (3)

From Figure 3, find the phase angle at gain crossover frequency by using equation (2).
Substitute for .
Step 12 Of 12
Substitute for .in equation (3).
Substitute for .
Thus, the phase margin of the circuit is .

Question:
In Problem 10.5, what is the phase margin if RD is increased to 2 kΩ?
Step 1 Of 13
Refer to mentioned problem in the textbook.
Refer to Figure 10.41 in the textbook; construct the Figure 10.41 by considering breaking the loop in the circuit at node X as shown in Figure 1.
That is, breaking the loop in the circuit which is replaced by the impedance in both the ends and it is shown in Figure 2.
Figure 2 shows the modified circuit diagram when breaking the loop at node X.
Step 2 Of 13

Substitute for .

Step 3 Of 13
Step 4 Of 13

Step 5 Of 13
Step 6 Of 13
Consider the expression for overall gain of the circuit.

Substitute for , , and , for , for , for and .
…… (1)
Step 7 Of 13
From Figure 2, calculate the expression for the loop gain.
Substitute for s.
…… (2)
Step 8 Of 13
Find the magnitude plot of the system.
The various terms of are tabulated in Table 1 in the increasing order of their corner frequencies.
Choose the low frequency less than and choose the high frequency greater than . Consider and .
For :
Step 9 Of 13
For :
For :
For :
For :
Step 10 Of 13
Step 11 Of 13
From Figure 3, the phase angle at gain crossover frequency is at . Hence, check by substituting in
magnitude of to find the phase angle at gain cross over frequency.
From equation (2), calculate the magnitude of .
Step 12 Of 13
At , the magnitude of is rewritten as follows:
Substitute for .
Since, . Therefore, the magnitude of the system at is approximately equal to zero.
Step 13 Of 13
…… (3)
Find the phase angle at gain crossover frequency by using equation (2).
Substitute for .
Substitute for .in equation (3).

Substitute for .
Thus, the phase margin of the circuit is .

Question:
If the phase margin required of the amplifier of Problem 10.5 is 45°, what is the maximum value of (a) CY,
(b) CA, and (c) CX while the other two capacitances remain constant?
Step 1 Of 10
(a)
Consider the phase margin of the amplifier is .

Figure 1 shows the modified circuit diagram of Figure 10.41 when breaking the loop at node X.
Step 2 Of 10

Substitute for .
Step 3 Of 10
…… (1)
Substitute for and for .in equation (1).
Step 4 Of 10
Step 5 Of 10
…… (2)
Step 6 Of 10
Step 7 Of 10
…… (3)
Step 8 Of 10
From equation (1), the corner frequency is inversely proportional to the capacitance of the capacitor at node Y .That is, .
Consider, if the capacitance of the capacitorat node Y is increased, then the corner frequency is decreased. That is, the frequency is
move towards the frequency and it shows less than 1 decade from the frequency . Since, the frequency moves towards results the
phase margin gets reduced. Therefore, the maximum capacitance of the capacitor is 100 fF to maintain the other two
capacitances remain constant.
Thus, the maximum value of capacitance of the capacitor at node Y is by keeping the other two capacitances remain constant.
Step 9 Of 10
(b)
Refer to Part (a),
From equation (2), the corner frequency is inversely proportional to the capacitance of the capacitor at node A .That is, .
Consider, if the capacitance of the capacitor at node A is increased, then the corner frequency is decreased and vice-versa. Thereby,
increasing results in increasing the phase margin of the amplifier. Therefore, the maximum value of the capacitance of the capacitor is 100 fF
by keeping the other two capacitances of the capacitor remains constant.
Thus,the maximum value of capacitance of the capacitor at node A is by maintaining the other two capacitances remain constant.
Step 10 Of 10
(c)
Refer to Part (a),
From equation (3), the corner frequency is inversely proportional to the capacitance of the capacitor at node X .That is, .
Consider, if the capacitance of the capacitorat node X is increased, then the corner frequency is decreased. That is, the corner
frequency is move towards the corner frequency and it shows less than 1 decade from the frequency . Since, the frequency moves
towards results the phase margin get reduced. Therefore, the maximum value of capacitance of the capacitor is 100 fF to
maintain the other two capacitances remain constant.
Thus, the maximum value of capacitance of the capacitor at node X is by keeping the other two capacitances remain constant.
Question:
Prove that the zero of the circuit shown in Fig. 10.32 is given by Eq. (10.30). Apply the technique illustrated
in Fig. 6.18.
Figure 10.32 Addition of Rz to move the right-half-plane zero.
Figure 6.18 Calculation of the zero in a CS stage.
Step 1 Of 3
The technique used to find the zero that needs to be eliminated or moved to the right half plan in the Figure 6.15 in the textbook is that the circuit
transfer function must drop to zero at the zero frequency . That is, for the finite input , the output is zero.
The technique says that the output is short to ground at with no current flow through short. The modified circuit is shown in Figure 1.
Step 2 Of 3
In Figure 1, input source resistance is neglected since it has a relatively larger value. Capacitance at node E is neglected since the
compensation capacitance is considered as large as enough to properly position the dominant pole. There is no requirement to add the
capacitance at node E before to establish the low frequency pole with moderate capacitor value.
From Figure 1, consider the current through a combination of series-added resistance and compensation capacitor is ,
where the impedance by the capacitance is , the current through is . Here, is the transconductance of the transistor
.
Consider that the current through the combination of and is equal to the current through . That is,
Simplify further.
…… (1)
Step 3 Of 3
Consider the zero is at zero frequency .

From the effect of zero, the numerator of the transfer function is . Equate the numerator of the transfer function to 0 to find the zero.
Here, s is a zero .
Substitute for in equation (1) to find the zero frequency .
Hence, the required zero frequency for the right-half plane zero of the circuit is proved.
Question:
Consider the amplifier of Fig. 10.74, where (W/L)1−4 = 50/0.5 and ISS = I1 = 0.5 mA.
(a) Estimate the poles at nodes X and Y by multiplying the small-signal resistance and capacitance
to ground. Assume that CX = CY = 0.5 pF. What is the phase margin for unity-gain feedback?
(b) If CX = 0.5 pF, what is the maximum tolerable value of CY that yields a phase margin of 60° for
unity-gain feedback?
Figure 10.74
Step 1 Of 15
(a)
From Figure 10.42, consider the expression for the corner frequency at node X by multiplying the small-signal resistance and capacitance to
ground.
Here, is the output resistance of transistor , is the output resistance of transistor , and is the capacitance of the capacitor at
node X.
…… (1)
Step 2 Of 15
From Figure 10.42, consider the expression for the corner frequency at node Y by multiplying the inverse transconductance of the transistor
and capacitance to ground.
Here, is the transconductance of the transistor and is the capacitance of the capacitor at node Y.
…… (2)
Step 3 Of 15
Write the formula to find the output resistance.
…… (3)
Here, is the channel-length modulation coefficient and is the drain current.
Refer to Figure 10.42 in the textbook, consider the drain current for the transistors , is equal to (that is, ).
Since, .
Rewrite the equation (3) to calculate the output resistance for PMOStransistor .
Step 4 Of 15
Rewrite the equation (3) to calculate the output resistance for NMOS transistor .
Consider the expression for the transconductance of the NMOS transistor .

…… (4)
Here, is the mobility of electron, is the drain current for the transistors , is the gate oxide capacitance per unit area, W is the width,
and is the length.
Refer to Figure 10.42 in the textbook, consider the drain current for the transistors is equal to . That is, .
Step 5 Of 15
Here,
Substitute for .
…… (5)
Step 6 Of 15
Step 7 Of 15

Step 8 Of 15
Step 9 Of 15
Write the expression for the transconductance of the NMOS transistor .

Step 10 Of 15
Refer to Figure 10.42, the transistors and are parallel. Consider the expression to find the magnitude of low frequency gain of the circuit
due to transistor and .

That is, the magnitude of low frequency gain obtained for the corner frequency is .
Step 11 Of 15
Draw the magnitude plot as shown in Figure 1.
Find the magnitude of when the corner frequency at .
Step 12 Of 15
Find the magnitude of when the corner frequency at .

Step 13 Of 15
…… (6)
Here, is the phase angle at gain crossover frequency.
From Figure 1, writethe expression for the phase angle at gain crossover frequency is at .
…… (7)
Substitute for .
Thus, the phase margin for unity-gain feedback of the amplifier is .
Step 14 Of 15
(b)
Refer to Part (a).
Substitute for , for , for in equation (7) to find .

Step 15 Of 15
Refer to Part (a).
Thus, the maximum tolerable value of the capacitance of the capacitor at node Y is .
Question:
Estimate the slew rate of the op amp of Problem 10.9 for both parts (a) and (b).
Step 1 Of 4
Assume the input signal is a step input.
Find the slew rate for large positive step input voltage .
Refer to Figure 10.42 in the textbook; consider the drain current for the transistors and is equal to (that is,
). Since, .
In Figure 10.42, when supplying the large positive step input voltage, the transistor gets turns off and the transistor is turned on and
provide to charges the capacitor . Also, the transistor is turned on and provide to charges the capacitor due to the current .
Figure 1 shows the node voltage at X and Y.
In Figure 1, the node voltage is increased from to and the node voltage increased from to . Therefore, the slew
rates of and (or ) are exactly the same irrespective of the capacitors and .
Step 2 Of 4
Consider the expression for the slew rate due to positive step input voltage for both parts (a) and (b) of the mentioned problem in the textbook.

Step 3 Of 4
Find the slew rate for large negative step input voltage .
In Figure 10.42, consider the circuit issupplied with the large negative step input voltage.Whenthe voltage at node X drops then the output voltage
is also drops at the same time, because the output voltage tracks the voltage at node X.
Consider the expression for the slew rate due to negative step input voltage for both parts (a) and (b) of the mentioned problem in the textbook.
…… (1)
Step 4 Of 4
From Figure 10.42, consider the expression for the current through the capacitor .
Thus, the slew rate of the operational amplifier for large positive step input voltage is and the slew rate of the operational amplifier for
large negative step input voltage is .

Question:
In the two-stage op amp of Fig. 10.75, W/L = 50/0.5 for all transistors except for M5,6, for which W/L =
60/0.5. Also, ISS = 0.25 mA and each output branch is biased at 1 mA.
(a) Determine the CM level at nodes X and Y.
(b) Calculate the maximum output voltage swing.
(c) If each output is loaded by a 1-pF capacitor, compensate the op amp by Miller multiplication
for a phase margin of 60° in unity-gain feedback. Calculate the pole and zero positions after
compensation.
(d) Calculate the resistance that must be placed in series with the compensation capacitors to
position the zero atop the nondominant pole.
(e) Determine the slew rate.
Figure 10.75
Step 1 Of 0
Question:
In Problem 10.11, the pole-zero cancellation resistor is implemented with a PMOS device as in Fig. 10.34.
Calculate the dimensions of M13–M15 if I1 = 100 μA.
Figure 10.34 Generation of Vb for proper temperature and process tracking.
Step 1 Of 11
Consider the expression for the drain current for the PMOS transistor when the input voltage is greater than threshold voltage.
…… (1)
Here,
is the mobility of hole, is the gate-source voltage for transistor , is the threshold voltage for PMOS transistor, is the gate
oxide capacitance per unit area,W is the width, and is the length.
…… (2)
Step 2 Of 11
…… (3)
Here,

…… (4)
Step 3 Of 11
Step 4 Of 11
Step 5 Of 11
Refer to Figure 10.31 and Figure 10.43 in the textbook;consider the magnitude of the voltage is equal to the magnitude of voltage .
Therefore, .
In this figure, consider the expression for common mode level.
Step 6 Of 11
Rewrite the equation (1) for PMOS transistor .

Step 7 Of 11
In Figure 10.31, consider that allowing 0.5 V across the current and the maximizing voltage at . Therefore, the magnitude of gate
to source voltage for transistor is expressed as,
Substitute for .
Step 8 Of 11
Refer to the mentioned problem in the textbook in Part (d); consider the expression for theresistance when pole-zero cancellation resistor is
implemented with a PMOS transistor .
Here, is the transconductance of the transistor , is the coupling capacitor, and is the output frequency after compensation.
Step 9 Of 11
Consider the expression for the transconductance of the transistor .
…… (5)
Step 10 Of 11
Step 11 Of 11
Rewrite the equation (1) for PMOS transistor .

Thus, the dimensions of the transistors , , and are , , and respectively.

Question:
Calculate the input-referred thermal noise voltage of the op amp shown in Fig. 10.75.
Figure 10.75
Step 1 Of 16
Consider the expression for the drain current for the PMOS transistor when the input voltage is greater than threshold voltage.
…… (1)
Here,
is the mobility of hole, is the gate-source voltage for transistor , is the threshold voltage for PMOS transistor, is the gate
oxide capacitance per unit area, W is the width, and is the length.
…… (2)
Step 2 Of 16
…… (3)
Here,

…… (4)
Step 3 Of 16
Step 4 Of 16
Refer to Figure 10.43 in the textbook, consider the drain current for the transistor and is equal to (that is, ).
Here, is the channel-length modulation coefficient of NMOS and is the drain current of transistor .
Step 5 Of 16

Here, is the channel-length modulation coefficient of PMOS and is the drain current of transistor .
Since, the output resistance of NMOS transistor and the output resistance of PMOS transistor are connected in parallel. Therefore,
Step 6 Of 16
Refer to Figure 10.43 in the textbook, consider the drain current for the transistor and is equal to (that is, ).
Step 7 Of 16

Here, is the channel-length modulation coefficient of PMOS and is the drain current of transistor .
Since, the output resistance of PMOS transistor and the output resistance of NMOS transistor are connected in parallel. Therefore,
Step 8 Of 16
Consider the expression for the transconductance of the NMOS transistors and .
Step 9 Of 16
Consider the expression for the transconductance of the PMOS transistors and .
Since, and .
Substitute for .
Substitute for , for , for , for , 1.46 V for , and for .
Step 10 Of 16
Refer to Figure 10.43 in the textbook; consider the expression for voltage gain for second stage of operational amplifier .
Step 11 Of 16
Refer to Figure 10.43 in the textbook; consider the expression for voltage gain for first stage of operational amplifier .

Refer to Figure 10.43 in the textbook, consider the drain current for the PMOS transistor and is equal to (that is,
).
Consider the expression for the transconductance of the PMOS transistors and .
Step 12 Of 16
Refer to Figure 10.43 in the textbook, consider the drain current for the NMOS transistor and is equal to (that is,
).
Consider the expression for the transconductance of the NMOS transistors and .
Step 13 Of 16
The modified circuit of Figure 10.43 is redrawn as shown in Figure 1.
Step 14 Of 16
Refer to Figure 1, consider the expression for the output voltage .
…… (5)
From equation (5), write the expression for the thermal noise for the output referred noise of .
Refer to Figure 1, write the expression for the thermal noise for the output referred noise of .
Consider the expression for the total thermal noise for the output referred noise of .
Substitute for and
for .
Refer to Figure 1, consider the expression for the voltage gain in terms of input-referred and output-referred thermal noise voltage.
Substitute for .
…… (6)
Step 15 Of 16
Consider the general expression for the referred current .
Here, is the transconductance of transistor,k is the Boltzmann constant, which is , and T is the temperature.
Substitute for k and 300 K for T.
…… (7)
Step 16 Of 16
Using equation (7), rewrite equation (6) as follows:
Substitute for , for , for , for , for , for ,

for , and for .
Thus, the input-referred thermal noise voltage of the operational amplifier is .

Question:
Figure 10.76 depicts a transimpedance amplifier employing voltage-current feedback. Note that the
feedback factor may exceed unity because of M3. Assume that I1–I3 are ideal, I1 = I2 = 1 mA, I3 = 10 μA,
(W/L)1,2 = 50/0.5, and (W/L)3 = 5/0.5.
(a) Breaking the loop at the gate of M3, estimate the poles of the open-loop transfer function.
(b) If the circuit is compensated by adding a capacitor CC between the gate and the drain of M1,
what value of CC achieves a phase margin of 60°? Determine the poles after compensation.
(c) What resistance must be placed in series with CC to position the zero of the output stage atop
the first nondominant pole?
Figure 10.76
Step 1 Of 0
Question:
Repeat Problem 10.14 if the output node is loaded by a 0.5-pF capacitor.
Step 1 Of 0
Question:
Suppose that in the circuit of Fig. 10.76, a large negative input current is applied such that M1 turns off
momentarily. What is the slew rate at the output?
Figure 10.76
Step 1 Of 0
Question:
Explain why, in the circuit of Fig. 10.76, the compensation capacitor should not be placed between the gate
and the drain of M2 or M3.
Figure 10.76
Step 1 Of 2
Figure 10.44 in the textbook is redrawn as shown in Figure 1.
Step 2 Of 2
Refer to Figure 1:
Consider that compensation capacitor is not placed across transistor or because of the location of the poles. In this figure, if the
dominant pole is at node B, the second pole is at node A, and the third pole is at node Y, then split the first two poles by placing compensation
capacitor across transistor .
Consider that if compensation capacitor is placed across transistor , then it splits the second pole and third pole by keeping the dominant
pole without any change. That is, it moves the second pole at node A towards the dominant pole at node B and the third pole away. Hence, the
placement of across should not be provided to give a phase margin 60 .
Consider that if compensation capacitor is placed across transistor , then it only affects the dominant pole. Hence, the placement of
across should not be provided to take the advantage of pole-splitting to extend the bandwidth.
Thus, compensation capacitor is not placed between the gate and the drain of transistor or and it is explained.
Question:
Determine the input-referred noise current of the circuit shown in Fig. 10.76 and described in Problem
10.14.
Figure 10.76
Step 1 Of 16
Substitute for .
…… (1)
Step 2 Of 16
Refer to Figure 10.44, calculate the output resistance of PMOS transistor .
Here, is the channel-length modulation coefficient of PMOSand is the drain current of transistor .

Step 3 Of 16
Refer to Figure 10.44, calculate the output resistance of NMOS transistor .
Step 4 Of 16
Refer to Figure 10.44, calculate the output resistance of NMOS transistor .
Here, is the drain current of transistor .
Step 5 Of 16
Here, is the mobility of electron, is the gate oxide capacitance per unit area,W is the width, and is the length.
Step 6 Of 16
Here, is the mobility of hole.
Step 7 Of 16

Step 8 Of 16
The modified circuit of Figure 10.44 is redrawn as shown in Figure 1.
Step 9 Of 16
Refer to Figure 1, find the expression for the voltage at node B using Kirchhoff’s current law.
Step 10 Of 16
Refer to Figure 1, find the expression for the voltage at node A using Kirchhoff’s current law.
Substitute for .
Step 11 Of 16
Refer to Figure 1, find the expression for the output voltage using Kirchhoff’s current law.
Substitute for .
Step 12 Of 16
…… (2)
Step 13 Of 16
From equation (2), write the expression for the thermal noise for the output referred noise of .
…… (3)
Consider the general expression for the referred current .

Here, is the transconductance of transistor,k is the Boltzmann constant, which is , and T is the temperature.
Substitute for k and 300 K for T.
…… (4)
Step 14 Of 16
Using equation (4), rewrite the equation (3) as follows:
Step 15 Of 16
Figure 2 shows the transresistance of the circuit.
Refer to Figure 2, consider the expression for the trans-resistance.
Step 16 Of 16
Refer to Figure 1, consider the expression for the input-referred noise current of the circuit.
Thus, the input-referred noise current of the circuit is .

Question:
The cancellation of a pole by a zero, e.g., in a two-stage op amp, entails an issue called the “doublet
problem” [5, 6]. If the pole and the zero do not exactly coincide, we say that they constitute a doublet. The
step response of feedback circuits in the presence of doublets is of great interest. Suppose the open-loop
transfer function of a two-stage op amp is expressed as
Ideally, ωz = ωp2 and the feedback circuit exhibits a first-order behavior, i.e., its step response contains a
single time constant and no overshoot.
(a) Prove that the transfer function of the amplifier in a unity-gain feedback loop is given by
(b) Determine the two poles of Hclosed (s), assuming they are widely spaced.
(c) Assuming ωz ≈ ωp2 and ωp2 (1 + A0)ωp1, write Hclosed (s) in the form
and determine the small-signal step response of the closed-loop amplifier.

(d) Prove that the step response contains an exponential term of the form (1 − ωz/ωp2) exp(−ωp2t).
This is an important result, indicating that if the zero does not exactly cancel the pole, the step
response exhibits an exponential with an amplitude proportional to 1−ωz/ωp2 (which depends on
the mismatch between ωz and ωp2) and a time constant of 1/ωz.
Step 1 Of 16
(a)
Consider the expression for the open-loop transfer function of a two-stage operational amplifier.
Step 2 Of 16
Consider the expression for the closed-loop transfer function of a unity-feedback system.
Substitute for .
Thus, the closed-loop transfer function of the operational amplifier in unity-gain feedback is
and it is proved.
Step 3 Of 16
(b)
Refer to Part (a);
Consider the expression for the closed-loop transfer function of the operational amplifier in a unity-feedback system.
From closed-loop transfer function, consider the poles of the system using the denominator part.
…… (1)
Step 4 Of 16
Consider the expression for denominator part of the second order of the system.
…… (2)
Step 5 Of 16
Find the two poles of the closed-loop transfer function of a system by comparing equation (1) and (2).
Find by equating the equation (1) and (2) for the coefficient of s term.
Find by equating the equation (1) and (2) for the coefficient of term.
Substitute for .
Thus, the two poles of the closed-loop transfer function of a system are
and .
Step 6 Of 16
(c)
Assume and .
Rearrange the expression of .
Refer to Part (b); consider one of the pole of closed-loop transfer function of a system.
Substitute for .
Step 7 Of 16
Refer to Part (b); consider the other pole of closed-loop transfer function of a system.
Substitute for .
Step 8 Of 16
Using the new poles of and , consider the new closed-loop transfer function of a system.
…… (3)
Here, consider .
Step 9 Of 16
Consider expression for the transfer of the system.
…… (4)
Consider the Laplace transform function of step response, .
Here, , , and .
Step 10 Of 16
Expand using partial fraction method.

…… (5)
Substitute for .
…… (6)
Equating the coefficient of constant in equation (6).
Step 11 Of 16
Equating the coefficient of s term in equation (6).
Substitute Afor .
…… (7)
Step 12 Of 16
Equating the coefficient of term in equation (6).
Substitute Afor .
…… (8)
Multiply equation (7) by and add with equation (8).
Step 13 Of 16

…… (9)
Step 14 Of 16
Step 15 Of 16
Substitute Afor , for , and for in equation (5).

Find inverse Laplace transform of .
Thus, the small-signal step response of the closed-loop amplifier is
Step 16 Of 16
(d)
Refer to Part (c); consider the expression for the small-signal step response of the closed-loop amplifier.
Since, .Therefore, rewrite the equation of .
Here, is the time constant, which is equal to .

Consider if and do not exactly cancel, then the exponential term with a time constant or .
Thus, the response contains an exponential term of the form with time constant and it is proved.
Question:
Using the results of the previous problem, determine the step response of the amplifier described in Problem
10.11 with (a) perfect pole-zero cancellation and (b) 10% mismatch between the pole and the zero
magnitudes.
Step 1 Of 3
(a)
For a perfect pole-zero cancellation:
Refer to the referenced problem in the textbook.
Consider the expression of the result obtained in the reference problem for the small-signal step response of the closed-loop amplifier.
…… (1)
Using equation (1), find the expression of for pole-zero cancellation.
At , rewrite the equation of .
Figure 1 shows the response of for a perfect pole-zero cancellation.

Thus, the step response of the amplifier for a perfect pole-zero cancellation is shown in Figure 1.
Step 2 Of 3
(b)
For 10% mismatch between the pole and the zero magnitudes:
Since, .Therefore, rewrite the equation of for 10 % mismatch between the pole and the zero in equation (1).
…… (2)
From equation (2), consider the expression for the step response of the amplifier .
…… (3)
Substitute 0 for t.
Likewise, substitute the various values of t in equation (3) to obtain the respective which are tabulated in Table 1.
Step 3 Of 3
Figure 2 shows the plot for versus for 10% mismatch between the pole and the zero magnitudes.
Thus, the step response of the amplifier for a 10% mismatch between the pole and the zero magnitudes is shown in Figure 2.
Question:
It is possible to raise the voltage gain of a folded-cascode op amp by adding a secondary path. As shown in
Fig. 10.77 by the gray section, the input signal can also travel through a differential pair with current-source
loads, I1 and I2, and drive the current sources in the original op amp. Of course, nodes X and Y exhibit a
relatively high impedance, thus contributing a pole that significantly degrades the phase margin.
(a) Neglecting channel-length modulation in I1 and I2, determine the low-frequency gain of the op
amp.
(b) Considering only the capacitances at X, Y, P, Q, and the output nodes, compute the overall
transfer function. Is it possible for the zero to cancel one of the poles?
Figure 10.77
Step 1 Of 0
Question:
Consider the circuit of Fig. 10.37(b) and assume that Iin = ISSu(t). Also, assume that a load capacitance of
CL is tied from the drain to ground. Write a KCL at the output node and derive a differential equation in
terms of Vout. Taking the Laplace transform and using partial fractions, prove that
where τ = CL/gm. Plot these three terms as a function of time and determine the time at which Vout (t)
reaches a minimum. This result indicates that the output initially falls and then assumes a ramp behavior.
Figure 10.37 (a) Simplified circuit for slew study, (b) realization of (a), and (c) output waveform during
slewing.
Step 1 Of 0
Question:
A two-stage op amp is compensated for a phase margin of 60° with β = 1. If β is reduced to β1 < 1,
determine the new phase margin.
Step 1 Of 0
Question:
Consider the characteristics shown in Fig. 11.2. Estimate a λ value for VGS − VTH = 350 mV based on the
slope from VDS = 0.2 V to 1 V. [Hint: express the ratio of two currents at VDS1 and VDS2 as 1 + λVDS1)/(1 +
λVDS2)]. Repeat this calculation for VGS − VTH = 200 mV, 250 mV, and 300 mV. What trend do you
observe?
Figure 11.2 I-V characteristics of a 5-μm/40-nm device for VGS − VTH = 50, · · ·, 350 mV.
Step 1 Of 0
Question:
Explain why gm falls in Fig. 11.6 as VGS − VTH exceeds 0.5 V.
Figure 11.6 Transconductance as a function of overdrive voltage.
Step 1 Of 0
Question:
Suppose a hypothetical transistor exhibits a transconductance given by gm = β(VGS − VTH)2.

(a) Find an expression for ID as a function of VGS − VTH.
(b) Find two other expressions for gm.
Step 1 Of 0
Question:
Sketch the plots in Fig. 11.7 for the device introduced in the previous problem.
Figure 11.7 Dependence of (a) gm and ID upon W/L, (b) gm and ID upon VGS − VTH, (c) gm and VGS − VTH
upon W/L, (d) gm and VGS − VTH upon ID, (e) gm and W/L upon ID, and (f) gm and W/L upon VGS − VTH.
Step 1 Of 0
Question:
We wish to bias a transistor with L = 40 nm at ID = 0.25 mA. Referring to Fig. 11.13, determine which case
yields a higher output impedance: W = 5 μm or W = 10 μm.
Figure 11.13 Output resistance of a 5-μm/40-nm NMOS device as a function of drain current.
Step 1 Of 0
Question:
Explain what happens to the unachievable region in Fig. 11.15 if ξ falls from 1.5 to 1.0. Assume that the
behavior in strong inversion does not change.
Figure 11.15 Unachievable gm region.
Step 1 Of 0
Question:
Modeling the thermal noise of M6 in Fig. 11.21 by a voltage source in series with its gate, determine the gain
that it sees as it reaches node Y. Use the exact expression for the gain of a degenerated CS stage. Compare
this result with the thermal noise contributed by M8.
Figure 11.21 First design of telescopiccascode op amp.
Step 1 Of 0
Question:
Consider the arrangement shown in Fig. 11.24(b). How high can the input CM level be for M13 and M14 to
remain in saturation? Does ID11/ID12 increase or deacrease beyond this point?
Figure 11.24 (a) Simple and (b) more accurate biasing for tail current source.
Step 1 Of 0
Question:
Suppose a closed-loop amplifier exhibits ringing at a frequency f1 in its step response [as in Fig. 11.46(b)].
Does this provide any information about the phase response of the open-loop circuit?
Figure 11.46 (a) Closed-loop amplifier and (b) its step response.
Step 1 Of 0
Question:
A two-stage op amp contains a nondominant pole, ωp2, at the output and is compensated for PM = 45° so
that |βH| drops to unity at ωp2. Assume that the dominant pole is much lower than ωp2.
(a) Estimate the degradation in PM if the load capacitance seen at the output is doubled.
(b) How should the compensation be modified to ensure that PM = 45° again?
Step 1 Of 0
Question:
Estimate the closed-loop time constant in Fig. 11.57 and see if it agrees with the open-loop dominant
frequency of 1.7 MHz.
Figure 11.57 (a) Closed-loop step response and (b) close-up showing settling to 1% accuracy.
Step 1 Of 0
Question:
Suppose that in Fig. 11.60, we scale an op amp up by a factor of α. If the load capacitance is constant, how
much bandwidth improvement can be achieved?
Figure 11.60 (a) Original op amp reponse and frequency compensation, (b) scaled op amp response, and (c)
compensation of scaled op amp.
Step 1 Of 0
Question:
Modeling the op amp in Fig. 11.51(a) by a voltage-dependent current source equal to GmVXY and an output
resistance equal to Rout, calculate the zero of the closed-loop transfer function. (Hint: the output voltage is
equal to zero at the zero frequency.)
Figure 11.51 (a) Closed-loop amplifier using capacitive feedback, and (b) its simplified equivalent for loop
gain calculation.
Step 1 Of 0
Question:
Consider the situation illustrated in Fig. 11.47(a). Suppose we place a capacitor, CF, in parallel with the
feedback resistor. Prove that CF introduces a zero in the loop transmission and determine its value so as to
cancel the pole reated by Cin.
Figure 11.47 (a) Equivalent circuit of closed-loop amplifier and (b) step response with Rz = 1500 Ω.
Step 1 Of 0
Question:
Derive an expression for Iout in Fig. 12.42.
Figure 12.42
Step 1 Of 6
Refer to Figure 11.36 in the textbook for the MOSFET circuit.
Modify the Figure as shown in Figure 1.
Step 2 Of 6
Consider PMOS devices and have identical dimensions.
Since the differential transistors and have identical, the reference current is same as the output current .
Apply Kirchhoff’s Voltage Law (KVL) to write the following expression.
…… (1)
Here, is the gate-source voltage of , is the gate-source voltage of , is the resistance, and is the source resistance.
Consider the formula for .

…… (2)
Here, is the drain current, is mobility of charge carriers in NMOS device, is the gate oxide capacitance per unit area, W is the channel
width, is the threshold voltage, and L is the channel length.
Step 3 Of 6
Step 4 Of 6
From Figure 1, the branch currents of through the transistors , and are , and respectively.
Substitute for .
…… (3)
Step 5 Of 6
Consider the transistors and are identical has the same threshold voltage.

Square the equation on both sides.
…… (4)
Step 6 Of 6
Re-arrange the equation (4).
Thus, the expression for is .

Question:
Explain how the start-up circuit shown in Fig. 12.43 operates. Derive a relationship that guarantees that VX
< VTH after the circuit turns on.
Figure 12.43
Step 1 Of 5
Modify circuit as shown in Figure 1.
Step 2 Of 5
Initially, both MOSFET’s and are in “OFF” state. When circuit turns “ON”, the voltage at point X and Y are
increases together. When the voltage reaches , the voltage is approximately equal to . At this point, MOSFET’s and
are turns “ON” simultaneously. When MOSFET turns “ON”, the surge in the drain current of MOSFET turns the remaining circuit
“ON”.
Further increase in voltage , the MOSFET turned “ON” sufficiently because the voltage gainsof and resistor exceeds unity. As
voltage increases, the voltage drop at resistor is also increases results in decreases the value of voltage compare to .
Step 3 Of 5
Consider the path , , MOSFET , and ground in Figure 1.

Write the expression for drain current.
Step 4 Of 5
Consider the path , , , and in Figure 1.
Consider the relation between and .
Substitute for .
Step 5 Of 5
Substitute for .
Thus, a relationship that guarantees after the circuit turns on is .

Question:
Consider the circuit of Fig. 12.15.
(a) If M1 and M2 suffer from channel-length modulation, what is the error in the output voltage?
(b) Repeat part (a) for M3 and M4.
(c) If M1 and M2 have a threshold mismatch of ΔV, i.e., VTH1 = VTH and VTH2 = VTH + ΔV, what
is the error in the output voltage?
(d) Repeat part (c) for M3 and M4.
Figure 12.43
Figure 12.15 Reference generator incorporating two series base-emitter voltages.
Step 1 Of 9
(a)
Consider the voltage at node X.
Here, is the base emitter voltage.
The output voltage is approximately equal to 2.5 V.

Consider the expression of drain current of .
Here, is the drain voltage, and is the channel-length modulation coefficient.
Substitute for .
…… (1)
Step 2 Of 9
Here, is the drain voltage, and is the channel-length modulation coefficient.
…… (2)
As the value of , neglect higher order terms in the equation.
Step 3 Of 9
Consider the expression of difference in base voltage between two transistors and to obtain the error voltage.
…… (3)
Here, is the thermal voltage.
Substitute for .
Find the error in the output voltage.

Thus, the error in output voltage is .
Step 4 Of 9
(b)
…… (4)
Here, is the base emitter voltage of .
Consider the expression of drain current of
…… (5)
Step 5 Of 9
As the value of , neglect higher order terms in the equation.
…… (6)
Substitute for .

Step 6 Of 9
(c)
Consider the expression of transconductance of MOSFET.
Here, is the gate source voltage and is the threshold voltage of and is the drain current of .
Consider the expression of drain current with threshold voltage.
Here, is the meantransconductance of and and is the change in threshold voltage.

Divide the expression by .
Substitute for .
Step 7 Of 9
Step 8 Of 9
(d)
Consider the expression of transconductance of MOSFET.
Here, is the gate source voltage and is the threshold voltage of and and is the drain current of .
Consider the expression of drain current with threshold voltage.
Here, is the meantransconductance of and and is the change in threshold voltage.

Divide the expression by .
Substitute for .
Step 9 Of 9

Question:
In Fig. 12.15, if the open-loop gain of the op amp A1 is not sufficiently large, then |VX − VY | exceeds Ve,
where Ve is the maximum tolerable error. Calculate the minimum value of A1 in terms of Ve such that the
condition |VX − VY | < Ve is satisfied.
Step 1 Of 5
Refer to Figure 11.15 in the textbook for the reference generator incorporating two series base-emitter voltages.
Consider PMOS devices have identical dimensions.
Consider the circuit is a current source mirror amplifier circuit, and consider the second stage of the circuit to calculate the output voltage.
Write the expression for output of the amplifier.
…… (1)
Here, is the voltage at Y terminal of the op-amp, is the voltage at X terminal of the op-amp, is the positive voltage applied to the
circuit, and is the gate-source voltage of .
Step 2 Of 5
…… (2)
Here, is the drain current, is mobility of charge carriers MOS device, is the gate oxide capacitance per unit area, W is the width, is
the threshold voltage, and L is the channel length.
Step 3 Of 5
…… (3)
In Figure, the drain current of is approximately same as emitter current of .
…… (4)
Write the expression for emitter current of .
Here, n is the emitter multiplication factor, is thermal voltage which has the value of 26mV, and is the resistance.
Step 4 Of 5
…… (5)
Consider the relation to be satisfied between and .
Here, is the tolerable error voltage.
Step 5 Of 5
…… (6)
The value of open-loop gain is resulted as in equation (6). Here, satisfy the condition , the minimum value of open-loop gain
should equal or greater than the value in stated in equation (6).
Thus, the minimum value of in terms of is .

Question:
In the circuit of Fig. 12.15, assume that Q2 and Q4 have a finite current gain β. Calculate the error in the
output voltage.
Step 1 Of 3
Refer to Figure 11.15 in the textbook for the reference generator incorporating two series base-emitter voltages.
Consider the expression for collector current.
…… (1)
Here,
is the collector current, is the emitter current.
Consider the relation between and .
Substitute for .
…… (2)
Step 2 Of 3
Modify equation (2) for transistor .

…… (3)
Write the expression for collector current of transistor .
The emitter current is flows through resistor and .

Write the expression for output voltage.
Substitute for .
…… (4)
In equation (4), the term is the error occurs due to finite current gain .
Step 3 Of 3
In Figure, the base of the transistor’s and are connected toMOSFET’s and respectively. Therefore, a small amount of
error is introduced in the circuit due to the flow of base current of transistor’s and . Due to this the emitter-base voltage of transistor’s
and that is and are slightly less than the predicted value.
Thus, the error in the output voltage is .

Question:
Calculate the output noise voltage of the circuit shown in Fig. 12.30 due to the thermal and flicker noise of
M1 and M2.
Figure 12.30 Circuit for calculation of noise in a reference generator.
Step 1 Of 7
Figure 11.29 is redrawn as shown in Figure 1.
Step 2 Of 7
Case 1:
Refer to Figure 1, calculate the output noise voltage of the circuit due to thermal and flicker noise of the PFET device .
From Figure 1, consider the expression for the node voltage at P due to the PFET device .
Here, and are the bipolar transistor resistance and is the transconductance.
Consider the expression for the drain current of PFET device .
Here, is the gain of operational amplifier.

Take magnitude on both sides of the equation.
…… (1)
Step 3 Of 7
Apply Kirchhoff’s voltage law in Figure 1 by considering the voltage of the circuit.
…… (2)
Step 4 Of 7
Simplify the equation (2) to find .

Step 5 Of 7
Case 2:
Refer to Figure 1, calculate the output noise voltage of the circuit due to thermal and flicker noise of the PFET device .
From Figure 1, consider the expression for the node voltage at P due to the PFET device .
Step 6 Of 7
Apply Kirchhoff’s voltage law in Figure 1 by considering the voltage of the circuit.

Step 7 Of 7
Thus, the output noise voltage of the circuit due to the thermal and flicker noise of the PFET devices and are
and respectively.
Question:
Consider the self-biased cascode shown in Fig. 12.44. Determine the minimum and maximum values of
RIREF such that both M1 and M2 remain in saturation.
Figure 12.44
Step 1 Of 5
Refer to Figure 11.38 in the textbook for the self-biased cascade circuit. Assume the transistors are in saturation.
Modify Figure 11.38 as shown in Figure 1.
Step 2 Of 5
Consider the relation between gate-to-source voltage and threshold voltage of PMOS device.
…… (1)
Here, is the gate-to-source voltage, and is the threshold voltage.
In Figure 1, the voltage is equal to the gate-to-source voltage of MOSFET .
…… (2)
Here, is the voltage at point N, and is the gate-to-source voltage of MOSFET .
Write the expression for voltage at point N .
Here, is the reference current, and R is the resistance.
Substitute for .
…… (3)
Step 3 Of 5
In Figure 1, the gate-to-source voltage of MOSFET is equal to sum of voltage and gate-to-source voltage of MOSFET .
Here, is the gate-to-source voltage of MOSFET .
Write the expression for required threshold voltage to operate MOSFET in saturation region.
Here, is the threshold voltage of MOSFET , is the positive voltage applied to the circuit, and is the gate-source voltage of
.
…… (4)
Step 4 Of 5
From Figure 1, the voltage at point Y is equal to .
…… (5)

…… (6)
Step 5 Of 5
From equation (3) the minimum and maximum values of are written as . From equation (6) the minimum and maximum values
of are also written as .
Thus, the minimum and maximum values of is .

Question:
The circuit of Fig. 12.3(a) sometimes turns on even with no explicit start-up mechanism. Identify the
capacitive path(s) that couple the transition on VDD to the internal nodes and hence provide the start-up
current.
Figure 12.3 (a) Addition of RS to define the currents; (b) alternative implementation eliminating body effect.
Step 1 Of 2
Refer to Figure 11.3(a) in the textbook for simple circuit to establish supply-independent currents with addition of .
Step 2 Of 2
The following steps are used to turn on the circuit without using explicit start-up mechanism.
• The rise in voltage , turns on the MOSFET . Due to this, the gate-drain capacitance of MOSFET is charged.
• Increase in flow of current through increases the gate voltage of MOSFET sufficiently, that turn on MOSFET .
• Due to the connectivity of gate terminals of both transistors, MOSFET turns on and MOSFET also turns on.
Thus, the gate-drain capacitance of MOSFET turns on the circuit without using explicit start-up mechanism.
Question:
Sketch the temperature coefficient of VBE [Eq. (12.13)] versus temperature. Some iteration may be
necessary.
Step 1 Of 8
Consider the expression for temperature coefficient of the base-emitter voltage as a function of temperature T.
…… (1)
Here, is base-emitter voltage, is thermal voltage, is the bandgap energy of silicon and has the value of , q is the charge of
electron, which has the value of , T is the temperature, and m is the fraction number has the value of .
Consider the formula for thermal voltage .
Here, k is the Boltzmann constant, which has the value of , T is the temperature, and q is the charge on an electron.
Step 2 Of 8
Substitute for .
…… (2)
Step 3 Of 8
Consider an initial value of as .
Consider the range of temperature varies from to with the interval of .

Modify equation (2) for initial temperature.
Substitute for , for k, for , for q, for m, and for .
Step 4 Of 8
Find the value of at point of .
Modify equation (2) for temperature.
Step 5 Of 8
Step 6 Of 8
Step 7 Of 8

Step 8 Of 8
Draw the plot of the temperature coefficient of versus temperature as shown in Figure 1.
Thus, the plot of the temperature coefficient of versus temperature is shown in Figure 1.
Question:
Determine the derivative of Eq. (12.13) with respect to temperature and sketch the result versus T. This
quantity reveals the curvature of the voltage.
Step 1 Of 11
Consider the expression for temperature coefficient of the base-emitter voltage as a function of temperature T.
…… (1)
Here, is base-emitter voltage, is thermal voltage, is the bandgap energy of silicon and has the value of , q is the charge of
electron, which has the value of , T is the temperature, and m is the fraction number has the value of .
Consider the formula for thermal voltage .
Here, k is the Boltzmann constant, which has the value of , T is the temperature, and q is the charge on an electron.
Step 2 Of 11
Substitute for .
…… (2)
Step 3 Of 11
Differentiate equation (2) with respect to T.
Substitute for .
…… (3)
Step 4 Of 11
Consider the range of temperature varies from to with the interval of .
Modify equation (3) for initial temperature.
Substitute for k, for q, for m, and for .
Step 5 Of 11
Step 6 Of 11
Step 7 Of 11
Step 8 Of 11
Step 9 Of 11

Step 10 Of 11
Step 11 Of 11
Draw the plot of versus temperature as shown in Figure 1.
Thus, the plot of versus temperature is shown in Figure 1.

Question:
Suppose that in Fig. 12.9, the amplifier has an output resistance Rout. Calculate the error in Vout.
Figure 12.9 Actual implementation of the concept shown in Fig. 12.8.
Figure 12.8 Conceptual generation of temperature-independent voltage.
Step 1 Of 4
Modify circuit as shown in Figure 1.
Step 2 Of 4
Write the expression for output voltage.
…… (1)
Consider the value of is approximately equal to .
…… (2)

…… (3)
Step 3 Of 4
Divide numerator and denominator of equation (3) by .
…… (4)
Assume .
Step 4 Of 4
…… (5)
Neglect the and collect the terms with in equation (5) to find the error in output voltage.
Thus, error in output voltage is .

Question:
The circuit of Fig. 12.9 is designed with R3 = 1 kΩ and a current of 50 μA through it. Calculate R1 = R2 and
n for a zero TC.
Figure 12.9 Actual implementation of the concept shown in Fig. 12.8.
Step 1 Of 4
…… (1)
Here, is base-emitter voltage of , and are the resistances, n is the emitter multiplication factor, and is thermal voltage which has
the value of 26mV.
Step 2 Of 4
Consider the value of for all transistor is .
For a zero TC, the value of must be equal to 17.2.
…… (2)
Step 3 Of 4
Substitute for .
Substitute 17.2 for , for , for , and 26mV for .
Step 4 Of 4
The value of is equal to .
Substitute for .

Thus, the obtained value for and is , and the value of n is .
Question:
In the circuit of Fig. 12.15, Q1 and Q2 are biased at 100 μA and Q3 and Q4 at 50 μA. If R1 = 1 kΩ, calculate
R2 and (W/L)1−4 such that the circuit operates with VDD = 3 V. Which op amp topology can be used here?
Step 1 Of 10
Refer to Figure 11.15 in the textbook for reference generator incorporating two series base-emitter voltages.
Consider the output voltage is .
To obtain, as a output, the MOSFET and must be sized such that they operate in saturation region.
…… (1)
Here,
is the base-emitter voltage of , is the base-emitter voltage of , and are the resistor, and is the collector current.
Step 2 Of 10
Here,
is thermal voltage and has the constant value of , m is ratioed factor of resistor, and n is the ratioed factor of transistor.
Write the expression for m.

…… (2)
Step 3 Of 10
…… (3)
Consider base-emitter voltage of all transistor is .
Step 4 Of 10
Substitute for , for , for , for , 2 for m, for and for in equation (2).

Step 5 Of 10
Step 6 Of 10
…… (4)
Here,
is the drain current, is the gate oxide capacitance per unit area, is the mobility of MOS device, is the drain-to-source voltage, and
is the width to length ratio.
…… (5)
Step 7 Of 10
Substitute for .

Step 8 Of 10
The current flows through MOSFET is same as collector current of .
Substitute for
Step 9 Of 10
To obtain the exact output voltage, the current of and must be 2 times and is same as .
Therefore, and are 2 times and is same as .
Step 10 Of 10
Substitute for .
Substitute for .
Substitute for .
In this circuit, temperature-independent voltage with grounded collector biased by PMOS current source topology is used.
Thus, the obtained value of is , and .

Question:
Since the bandgap of silicon exhibits a small temperature coefficient, Eq. (12.48) suggests that ∂VREF/∂T ∝
(4 + m)k/q, a relatively large value, whereas we derived VREF such that it has a zero TC. Explain the flaw in
this argument.
Step 1 Of 4
Consider the expression for reference voltage .
…… (1)
Here,
is the base emitter voltage, is thermal voltage.

…… (2)
In equation (2), depends upon only single temperature.
Step 2 Of 4
Differentiate equation (1) with respect to t.
Substitute 0 for .
…… (3)
In equation (3), is valid at only one temperature.
Step 3 Of 4

…… (4)
Re-arrange the equation.
Substitute for .
…… (5)
In equation (5), depends upon only single temperature.
Step 4 Of 4
Substitute for .
…… (6)
In equation (6), reaches to when temperature T tends to zero. So, for zero temperature coefficients (TC) the value of extrapolated
and reaches to .
Thus, the flaw in argument is explained.

Question:
A differential pair with resistive loads is designed such that its voltage gain, gm RD, has a zero TC at room
temperature. If only the temperature dependence of the mobility is considered, determine the required
temperature behavior of the tail current. Design a circuit that roughly approximates this behavior.
Step 1 Of 7
Consider the relation of temperature dependence of quantity .
…… (1)
Here, is permeability of free space, which has the value of , T is the temperature, and m is the fraction number has the value of
Substitute for m in equation (1).
…… (2)
…… (3)
channel length.
Step 2 Of 7
Square the equation (2) on both sides.
…… (4)
In equation (4), drain current is inversely proportional to and in equation (2), is proportional to . So, is proportional to .
Step 3 Of 7
…… (5)
Substitute for .
…… (6)
…… (7)
Differentiate equation (6) with respect to T.
…… (8)
Consider the standard temperature (that is ).
Substitute for T in equation (7).
…… (9)
Substitute for T in equation (8).
…… (10)
Subtract equation (9) from equation (10).
Step 4 Of 7
Substitute for and for T in equation (7).
…… (11)
Step 5 Of 7
Draw the simple circuit in which the drain current is proportional to temperature as shown in Figure 1.
Step 6 Of 7
In Figure 1, voltage across the resistor is proportional to temperature T.
…… (12)
…… (13)
…… (14)
Here, is the drain current, is mobility of charge carriers in NMOS device, is the gate oxide capacitance per unit area, W is the channel
width, is the threshold voltage, and L is the channel length.
Substitute for .
…… (15)
Step 7 Of 7
In equation (12), voltage across resistor is proportional to T and in equation (15), is proportional to . So that the current is
proportional to .
…… (16)
Compare equations (11) and (16) as:
In both equations, the value of is proportional to . Therefore, designed circuit meets the desired requirements.
Thus, the circuit is designed and shown in Figure 1 and the behavior of the tail current is explained.
Question:
In Problem 12.15, assume that the tail current is constant, but the load resistors exhibit a finite TC. What
resistor temperature coefficient cancels the variation of the mobility at room temperature?
Step 1 Of 6
Consider the relation between temperature dependence of quantity and temperature.
…… (1)
Here, is permeability of free space, which has the value of , T is the temperature, and m is the fraction number has the value of
Substitute for m in equation (1).
…… (2)
…… (3)
channel length.
Step 2 Of 6
Substitute for .
…… (4)
In equation (4), transconductance is proportional to .
Step 3 Of 6
Refer to Figure 11.3 in the textbook for simple circuit to establish supply-independent currents with the addition of .
Consider the formula for the transconductance of .
…… (5)
Here, is the source resistance connected to MOSFET , and K is the multiplication factor for ratio.
In equation (5), transconductance of MOSFET is inversely proportional to resistance and the value of resistance varies with
temperature and process technology.
…… (6)
Step 4 Of 6
…… (7)
Step 5 Of 6
Consider the expression for resistor temperature coefficient.
…… (8)
Here, is the change in resistor value, is the change in temperature, is the temperature coefficient of resistor, and is the initial value
of resistor.
…… (9)
Consider the source resistance as an initial value of the resistor .
…… (10)
Step 6 Of 6
From equations (7) and (10), resistor temperature coefficient cancels the variation of the mobility at room temperature. The parameters and
are constants. Therefore, the relation is written as,
Thus, the resistor temperature coefficient that cancels the variation of the mobility at room temperature is .
Question:
In the circuit of Fig. 12.32(b), how should R1–R3 be chosen so that the negative-feedback loop is stronger
than the positive-feedback loop?
Figure 12.32 (a) Attempt to make drain current of M4 temperature-independent, (b) circuit modification
resulting in a zero-TC current, and (c) generation of arbitrarily small voltage with zero TC.
Step 1 Of 0
Question:
Does the five-transistor OTA in Fig. 12.34(a) impose additional supply voltage constraints?
Figure 12.34 (a) Implementation of low-voltage BG circuit using a five-transistor OTA, and (b) addition of
start-up device.
Step 1 Of 0
Question:
Figure 12.45 illustrates a “single-junction” bandgap design [11]. Here, switches S1 and S2 are driven by
complementary clocks.
(a) What is Vout when S1 is on and S2 is off?
(b) What is the change in Vout when S1 turns off and S2 turns on?
(c) How are I1, I2, C1, and C2 chosen to produce a zero-TC output when S1 is off?
Figure 12.45
Step 1 Of 4
(a)
Refer to Figure 11.40 in the textbook for single junction bandgap design circuit.
Consider the condition when, switch is “on” and switch is “off”.
In this case, current is connected to X terminal and direct feedback path occurred between and inverting terminal of the op-amp circuit.
Write the expression for voltage at point X.
…… (1)
Since, voltage is applied to non-inverting terminal of the op-amp with closed feedback path, the output voltage is same as .
Thus, the obtained value of when is “on” and switch is “off” .
Step 2 Of 4
(b)
Consider the condition when, switch is “off” and switch is “on”.
In this case, currents and is connected to X terminal and capacitors and are connected in feedback path of the op-amp circuit.
The voltage applied to the non-inverting terminal of the op-amp is the sum of and voltage applied due to the feedback path of op-amp
. The voltage applied to the inverting terminal of the op-amp is a previously obtained output voltage at the output
terminal of the circuit with the feedback factor . Therefore, total output obtained at the output terminal of the op-
amp is sum of voltage applied at non-inverting terminal and inverting terminal.
Step 3 Of 4
Write the expression for voltage at the output terminal of the op-amp.
Substitute for .
…… (2)
Assume and modify the equation.
Thus, the changed value of when is “off” and switch is “on” .
Step 4 Of 4
(c)
Refer to Figure 11.6 in the textbook for generation of PTAT voltage.
For zero temperature coefficient (TC), is approximately equal to .
In equation (2), the natural logarithm (ln) term is approximately equal to .
Thus, the required relation to produce a zero-TC output when turns off is .
Question:
Suppose that in Fig. 12.45, I2/I1 deviates from its nominal value by a small error ϵ. Calculate Vout when S1 is
off.
Figure 12.45
Step 1 Of 3
Refer to Figure 11.40 in the textbook for single junction bandgap design circuit.
Consider the condition when, switch is “off” and switch is “on”.
In this case, currents and is connected to X terminal and capacitors and are connected in feedback path of the op-amp circuit.
The voltage applied to the non-inverting terminal of the op-amp is the sum of and voltage applied due to the feedback path
.The inverting terminal is connected to ground. Therefore, total output obtained at the output terminal of the op-amp
is voltage applied at non-inverting terminal.
Substitute for .
…… (1)
Step 2 Of 3
Consider is the current flow in the transistor is same as .

…… (2)
Consider deviates from its nominal value by a small error .
Step 3 Of 3
Assume , and according to natural logarithm rules, for small value relatively about zero values of the value of is true.
Therefore, modify the equation as follows by considering very small error.
Now, write separately the error function that is resulting in output voltage.
Thus, the obtained expression with error for is .

Question:
The circuit of Fig. 12.20 is designed with (W/L)1−4 = 50/0.5, ID1 = ID2 = 50 μA, R1 = 1 kΩ, and R2 = 2 kΩ.
Assume that λ = γ = 0 and Q3 is identical to Q1.
(a) Determine n and (W/L)5 such that Vout has a zero TC at room temperature.
(b) Neglecting the noise contribution of Q1–Q3, calculate the output thermal noise.
Figure 12.20 Generation of a temperature-independent voltage.
Step 1 Of 0
Question:
Consider the circuit of Fig. 12.21. Assume K = 4, fCK = 50 MHz, and a power budget of 1mW. Determine
the aspect ratio of M1–M4 and the value of CS such that gm1 = 1/(500 Ω).
Figure 12.21 Constant-Gm biasing by means of a switched-capacitor “resistor.”
Step 1 Of 10
Refer to Figure 11.21 in the textbook for the circuit of constant-Gm biasing by means of a switched-capacitor.
In circuit, the current flows through MOSFET and is same. Similarly, the current flows through MOSFET and is same.
…… (1)
Assume the power budget of the circuit as 1 mW.

Since, the current flows in the circuit takes two different paths, the total power budget is equally divided in between two paths. So, the power
budget of and is 0.5 mW.
Consider the expression average for resistance.
…… (2)
Here, is the clock frequency and is switched capacitor.
Step 2 Of 10
Consider the formula for the transconductance of .
…… (3)
Here, is the source resistance connected to MOSFET , and K is the multiplication factor for ratio.
Consider the formula for output current .

…… (4)
Here, is the output current, is mobility of charge carriers in NMOS device, is the gate oxide capacitance per unit area, W is the
channel width, and L is the channel length.
Step 3 Of 10
Find the value of .
Find the value of .
Step 4 Of 10
Take square on both sides.
Consider the drain current of is .
Substitute for .
Step 5 Of 10
…… (5)
Step 6 Of 10
…… (6)
Substitute for .
Step 7 Of 10

Substitute for F, and for .
Step 8 Of 10
Substitute 4 for K, and for .
Step 9 Of 10
Refer to Figure 11.3(a) in the textbook for simple circuit to establish supply-independent currents with an addition of .
Compare the Figure 11.21 and Figure 11.3(a) in the textbook.
The value of ratio of MOSFET is equal to .
Substitute for .
The value of ratio of MOSFET is equal to .
Substitute for , and 4 for K.
The value of ratio of MOSFET’s and is equal to .
…… (7)
…… (8)
Step 10 Of 10
Consider the expression for drain current of PMOS in saturation region for .
…… (9)
Here, is the drain current of PMOS device, is mobility of charge carriers of PMOS device, is the source to gate voltage applied to
PMOS device, is the threshold voltage of PMOS device, is the gate oxide capacitance per unit area, W is the width, and L is the channel
length.
Since, the value of for both NMOS and PMOS device is same, the value of for devices is same.
Consider is the gate to source applied voltage to PMOS device to operate in a saturation region.

Substitute for F.
Thus, the obtained value of is and the aspect ratio of , , and is , , and
respectively.
Question:
Suppose (W/L)3 = K(W/L)4 in Fig. 12.32(c). How should R2 and R3 be chosen?
Step 1 Of 0
Question:
Determine the output noise voltage of the circuit in Fig. 12.32(c).
Step 1 Of 0
Question:
Analyze the circuit of Fig. 12.3(a) if RS is placed in series with the source of M1.
Figure 12.3 (a) Addition of RS to define the currents; (b) alternative implementation eliminating body effect.
Step 1 Of 0
Question:
The circuit of Fig. 13.2(b) is designed with C1 = 2 pF and C2 = 0.5 pF.
Figure 13.2 (a) Continuous-time feedback amplifier using capacitors; (b) use of resistor to define bias point.
Step 1 Of 0
Question:
Assuming that RF = ∞, but the op amp has an output resistance Rout, derive the transfer function
Vout(s)/Vin(s).
Step 1 Of 0
Question:
If the op amp is ideal, determine the minimum value of RF that guarantees a gain error of 1% for an input
frequency of 1 MHz.
Step 1 Of 0
Question:
Suppose that in Fig. 13.6(a), the op amp is characterized by a transconductance Gm and an output
resistance Rout.
Figure 13.6 Circuit of Fig. 13.5 in (a) sampling mode, (b) amplification mode (c) input and output waveforms
in the two modes.
Figure 13.5 Switched-capacitor amplifier.
Step 1 Of 0
Question:
Determine the transfer function Vout/Vin in this mode.
Step 1 Of 0
Question:
Plot the waveform at node B if Vin is a 100-MHz sinusoid with a peak amplitude of 1 V, C1 = 1 pF, Gm =
1/(100 Ω), and Rout = 20 k Ω.
Step 1 Of 0
Question:
In Fig. 13.6(b), node A is in fact connected to ground through a switch (Fig. 13.5). If the switch introduces a
series resistance Ron and the op amp is ideal, calculate the time constant of the circuit in this mode. What is
the total energy dissipated in the switch as the circuit enters the amplification mode and Vout settles to its
final value?
Figure 13.6 Circuit of Fig. 13.5 in (a) sampling mode, (b) amplification mode (c) input and output waveforms
in the two modes.
Figure 13.5 Switched-capacitor amplifier.
Step 1 Of 5
Replace the switch with the series resistance and modify the circuit diagram as shown in Figure 1.
Step 2 Of 5
The node B is at virtually grounded. That is the voltage across inverting and non-inverting terminals must be same. So, the value of is,
Modify the circuit diagram as shown in Figure 2.
Step 3 Of 5
Since the voltage across the node B is zero, modify the circuit diagram as shown in Figure 3.
Step 4 Of 5
Find the time constant from Figure 3.
Consider the expression of time constant of RC circuit.
Here, R is the resistance and C is the capacitance.
Substitute for C, and for R.
Step 5 Of 5
The total energy stored in is same as the energy dissipated in the switch.
Consider the expression of energy stored in a capacitor.
Here, C is the capacitance and V is the voltage.
Substitute for C and for V.

Here, is the voltage across the capacitor and is the capacitance.
Thus, the time constant of the circuit and the total energy dissipated in the switch are , and , respectively.
Question:
The circuit of Fig. 13.10(a) is designed with (W/L)1 = 20/0.5 and CH = 1 pF.
Figure 13.10 Response of a sampling circuit to different input levels and initial conditions.
Step 1 Of 0
Question:
Using Eqs. (13.9) and (13.16), calculate the time required for Vout to drop to +1 mV.
Step 1 Of 0
Question:
Approximating M1 by a linear resistor equal to [μnCox (W/L)1(VDD −VTH)]−1, calculate the time required for
Vout to drop to +1 mV and compare the result with that obtained in part (a).
Step 1 Of 0
Question:
The circuit of Fig. 13.12 cannot be characterized by a single time constant because the resistance charging
CH (equal to 1/gm1 if γ = 0) varies with the output level. Assume that (W/L)1 = 20/0.5 and CH = 1 pF.
Figure 13.12 Maximum output level in an NMOS sampler.
Step 1 Of 0
Question:
Using Eq. (13.21), calculate the time required for Vout to reach 2.1 V.
Step 1 Of 0
Question:
Sketch the transconductance of M1 versus time.
Step 1 Of 0
Question:
In the circuit of Fig. 12.8(b), (W/L)1 = 20/0.5 and CH = 1 pF. Assume that λ = γ = 0 and Vin = V0 sin ωint +
Vm, where ωin = 2π × (100 MHz).
Step 1 Of 0
Question:
Calculate Ron1 and the phase shift from the input to the output if V0 = Vm = 10 mV.
Step 1 Of 0
Question:
Repeat part (a) if V0 = 10 mV but Vm = 1 V. The variation of the phase shift translates to distortion.
Step 1 Of 0
Question:
Describe an efficient SPICE simulation that yields the plot of Ron,eq for the circuit of Fig. 13.17.
Figure 13.17 (a) Complementary switch; (b) on-resistance of the complementary switch.
Step 1 Of 4
Consider the expression of equivalent on-resistance.
Here,
is the input voltage, is the width-length ratio of PMOS, is the width-length ratioof NMOS, is the threshold voltage of
NMOS, is the threshold voltage of PMOS, is the oxide capacitance, is the mobility of electrons, which has standard value as
, is the mobility of holes, which has standard value as and is the voltage that is applied to drain terminal.
Step 2 Of 4
Consider the capacitor supplies the voltage (voltage dependent voltage source).
Step 3 Of 4
Procedure to construct and simulate the circuit in SPICE simulation:
• Consider that is the dependent voltage source with a voltage difference of 20 mV.
• Construct this modified circuit in SPICE simulation.
• Use DC sweep in the simulation settings to vary the input voltage, vary the input voltage and obtain the values of current drawn by the source.
• Enter the valid expression to obtain the resistance value, that is,
Here,
is the input voltage and is the current drawn from source.

• Then plot the graph between on-resistance and input voltage.
The approximate plot of equivalent on resistance of the circuit from the SPICE simulation is drawn as shown in Figure 2.
Step 4 Of 4
The computation of equivalent on resistance of the modified circuit using SPICE simulation is more efficient than computation using theoretical
expression of on-resistance of the original circuit.
Thus, the efficient of SPICE simulation to plot for the circuit is described.
Question:
The sampling network of Fig. 13.17 is designed with (W/L)1 = 20/0.5, (W/L)2 = 60/0.5, and CH = 1 pF. If Vin
= 0 and the initial value of Vout is +3 V, estimate the time required for Vout to drop to +1 mV.
Figure 13.17 (a) Complementary switch; (b) on-resistance of the complementary switch.
Step 1 Of 7
Refer to Figure 12.9 (a) and Table 2.1 in the textbook.
…… (1)
So, the effective value of is .
Step 2 Of 7
Here,
is the permittivity of the oxide, which is and is the gate oxide thickness, which has the value as .
…… (2)

Step 3 Of 7
Consider the expression of on-resistance for NMOS.
…… (3)
Here,
is the input voltage, is the width-length ratio, is the threshold voltage of NMOS, is the oxide capacitance, is the mobility of
electrons, which has standard value as , and is the voltage that is applied to drain terminal.
Substitute 3 V for , for , 1 pF for , 0.7 V for , for , 0 for , and for in equation
(3).
Step 4 Of 7
So, the effective value of is .

Consider the expression of on-resistance for PMOS.
…… (4)
Here,
is the threshold voltage of PMOS, is the oxide capacitance, t is the time, is the mobility.
For PMOS, the value of input voltage is same .
Step 5 Of 7
Substitute for , 1 pF for , –0.8 V for , for , and for in equation (4).
Step 6 Of 7
Draw the modified circuit diagram as shown in Figure 1.
Step 7 Of 7
Consider the expression of time constant.
Here,
are the turn on resistances and is the capacitance.
Substitute for , for , and 1 pF for .
Here,
t is the time and is the time constant.
Substitute 29.4psfor , 3 V for , and 1 mV for .

Take ln on both sides.
Thus, the time required to drop the from 3 V to 1 mV is .

Question:
In the circuit of Fig. 13.20, (W/L)1 = 20/0.5 and CH = 1 pF. Calculate the maximum error at the output due
to charge injection. Compare this error with that resulting from clock feedthrough.
Figure 13.20 Charge injection when a switch turns off.
Step 1 Of 3
…… (1)
Here,
…… (2)
Refer to Table 2.1 in the textbook for the value of .
Consider the source drain side diffusion in the MOSFET, so that the channel length of the device (L) is equal to .
Step 2 Of 3
Consider the expression of maximum error.
…… (3)
Here,
is the input voltage, W is the width and L is the length, is the threshold voltage, is the oxide capacitance, is the voltage that is
applied to drain terminal, and is the capacitance.
Substitute for W, for L, 3 V for , 0 V for , 0.7 V for , for ,and 1 pF for in
equation (3).
Step 3 Of 3
Consider the clock voltage as 3 V.
Find the error voltage for clock feedthrough.
Here,
is the overlap capacitance per unit width.
The overlap capacitance of the NMOS is .

Modify the expression as follows.
Substitute 0.4 nF for , 1 pF for , and for W, and 3 V for .
Maximum error at the output is higher than the error that is obtained from clock feedthrough.
Thus, the maximum error at the output due to charge injection is and the error is compared with the error that is obtained from clock
feedthrough.
Question:
The circuit of Fig. 13.63 samples the input on C1 when CK is high and connects C1 and C2 when CK is low.
Assume that (W/L)1 = (W/L)2 and C1 = C2.
Figure 13.63
Step 1 Of 0
Question:
If the initial voltages across C1 and C2 are zero and Vin = 2 V, plot Vout versus time for many clock cycles.
Neglect charge injection and clock feedthrough.
Step 1 Of 0
Question:
What is the maximum error in Vout due to charge injection and clock feedthrough of M1 and M2? Assume
that the channel charge of M2 splits equally between C1 and C2.
Step 1 Of 0
Question:
Determine the sampled kT/C noise at the output after M2 turns off.
Step 1 Of 0
Question:
For Vin = V0 sin ω0t + V0, where V0 = 0.5 V and ω0 = 2π × (10 MHz), plot the output waveforms of the
circuits shown in Fig. 13.30(b) and 13.31(a). Assume a clock frequency of 50 MHz.
Figure 13.30 (a) Unity-gain buffer; (b) sampling circuit followed by unity-gain buffer.
Figure 13.31 (a) Unity-gain sampler; (b) circuit of (a) in sampling mode; (c) circuit of (a) in amplification
mode.
Step 1 Of 3
Refer to Figures 12.29 (b) and 12.30 (a) in the textbook.
Consider the expression of input voltage.
Here,
is the initial voltage, t is the time, and is the frequency.
Step 2 Of 3
Find the time period of the input sinusoidal voltage.
Here,
f is the frequency.
Substitute 10 MHz for f.
Find the time period of the sampler circuit.
Here,
f is the clock frequency.
Substitute 50 MHz for f.
Calculate the number of samples.
Step 3 Of 3
Both gain buffer with sampling circuit and unit gain sampler are using in discrete-time applications.
In unity gain buffer, the time-dependent charge is injected by and the resultant waveform is shown in Figure 1.
In unity gain sampler, switches and are in ON condition and the switch is in
OFF condition during sampling mode. The output voltage raises to a value that is approximately equal to and the resultant output waveform of
both the circuits are drawn as shown in Figure 1.
Thus, the output waveforms of unity gain buffer with sampling circuit and unity gain sampler are drawn and shown in Figure 1.
Question:
In Fig. 13.47, S1 turns off Δt seconds after S2, and S3 turns on Δt seconds after S1 turns off. Plot the output
waveform, taking into account the charge injection and clock feedthough of S1–S3. Assume that all of the
switches are NMOS devices.
Figure 13.47 Effect of input change after S2 turns off.
Step 1 Of 2
Switch is connected in series with the parallel connected switch and the switch is connected across the capacitor .
When the switch is turn off, current flows through the feedback capacitor and the output voltage is increased during this time. So, the
change in input voltage is amplified during the time period .
When the switch is turn off, the capacitor starts to discharge and the discharging effect increases the output voltage as shown in Figure 1.
When the switch is turn on, the expression of increase in output voltage is,
Here,
are the capacitors and
is the input voltage.
Step 2 Of 2
Draw the output waveform as shown in Figure 1.
Thus, the output waveform is drawn.
Question:
The circuit of Fig. 13.50 is designed with C1 = 2 pF, Cin = 0.2 pF, and Av = 1000. What is the maximum
nominal gain, C1/C2, that the circuit can provide with a gain error of 1%?
Figure 13.50 Equivalent circuit of noninverting amplifier during amplification.
Step 1 Of 2
Consider the expression of gain error of the noninverting amplifier during amplification.
Here,
is the finite open-loop gain and are the capacitances.
Substitute 1% for Gain error and 1000 for .
Step 2 Of 2
Find the maximum nominal gain.
Thus, the maximum nominal gain is .

Question:
In Problem 13.26, what is the maximum nominal gain if Gm = 1/(100 Ω) and the circuit must achieve a time
constant of 2 ns in the amplification mode? Assume that Cin = 0.2 pF, and calculate C1 and C2.
Step 1 Of 4
Consider the expression of time constant.
Here,
is the transconductance, and are the capacitances.
Consider the value of as zero.
Substitute 0 for .
Substitute 2 ns for , for .
Step 2 Of 4
Consider the expression of gain error of the noninverting amplifier during amplification.
Here,
is the finite open-loop gain and are the capacitances.
Substitute 1% for Gain error and 1000 for .

…… (1)
Step 3 Of 4
Substitute for .
Step 4 Of 4
Find the maximum nominal gain.
Thus, the maximum nominal gain is .

Question:
The integrator of Fig. 13.57 is designed with C1 = C2 = 1 pF and a clock frequency of 100 MHz. Neglecting
charge injection and clock feedthrough, sketch the output if the input is a 10-MHz sinusoid with a peak
amplitude of 0.5 V. Approximating C1, S1, and S2 by a resistor, estimate the output amplitude.
Figure 13.57 (a) Discrete-time integrator; (b) response of circuit to a constant input voltage.
Step 1 Of 3
Write the expression of input voltage from the specifications.
Consider output voltage equation of integrator circuit.
...... (1)
Here, is the feedback capacitance and R is the resistance.

Consider the expression to find R.
Here, is the clock frequency.
Substitute 100 MHz for and 1 pF for .
Step 2 Of 3
Substitute for , 1 pF for , and for R in equation (1).

...... (2)
Substitute 0 for t.
Thus, the output amplitude is .
Step 3 Of 3
Sketch the output waveform of the integrator with clock frequency as shown in Figure 1.
Thus, the output voltage waveform is sketched and shown in Figure 1.

Question:
Consider the switched-capacitor amplifier depicted in Fig. 13.64, where the common-mode feedback is not
shown. Assume that (W/L)1−4 = 50/0.5, ISS = 1 mA, C1 = C2 = 2 pF, C3 = C4 = 0.5 pF, and the output CM
level is 1.5 V. Neglect the transistor capacitances.
Figure 13.64
Step 1 Of 0
Question:
What is the maximum allowable output voltage swing in the amplification mode?
Step 1 Of 0
Question:
Determine the gain error of the amplifier.
Step 1 Of 0
Question:
What is the small-signal time constant in the amplification mode?
Step 1 Of 0
Question:
Repeat Problem 13.32 if the gate-source capacitance of M1 and M2 is not neglected.
Step 1 Of 0
Question:
A differential circuit incorporating a well-designed common-mode feedback network exhibits the open-loop
input-output characteristic shown in Fig. 13.65(a). In some circuits, however, the characteristic appears as
in Fig. 13.65(b). Explain how this effect occurs.
Figure 13.65
Step 1 Of 3
Figure 12.62 (a) and Figure 12.62 (b) are represent the open-loop input-output characteristics.
The expression of common mode (CM) voltage of a common-mode feedback network is written as follows:
Here,
are the single-ended outputs.
Step 2 Of 3
Draw the input-output characteristics with CM level voltage as shown in Figure 1.
Step 3 Of 3
The common-mode level voltage is always depends on the sensing elements, that are connected with the circuit.
The commonly using sensing elements are,
• Resistors and
• MOSFET, etc.
If the characteristics of sensing element that is used in CM level network is linear, the characteristic curve of input-output of CM level network is
also linear as shown in Figure 12.62 (a) in the question.
Similarly, if the characteristics of sensing element that is used in CM level network is non-linear, the characteristic curve of input-output of CM
level network is also non-linear as shown in Figure 12.62 (b) in the question.
Thus, the reason why the characteristic curve of CM level networks are different is explained.
Question:
In the common-mode feedback network of Fig. 13.61, assume that W/L = 50/0.5 for all transistors, ID5 = 1
mA, and ID6,7 = 50 μA. Determine the allowable range of the input common-mode level.
Figure 13.61 Definition of the voltage across C1 and C2.
Step 1 Of 10
Step 2 Of 10
Substitute for .
Substitute for .
Step 3 Of 10
Write the formula to find the drain current of NMOS model transistor .
Here, is the oxide capacitance, is the threshold voltage, is the drain to source voltage, is the mobility, is the gate source
voltage of a MOSFET , and is the channel length of a MOSFET .
…… (1)
Refer to Table 2.1 in the textbook, mobility of electrons in NMOS is .
Step 4 Of 10
Substitute for .
Consider the conversion factor.
Substitute for .
Step 5 Of 10
Consider the formula to find .
Here,
is the gate source voltage of a MOSFET , and is the channel length of a MOSFET .
From the circuit diagram, the value of the drain current is half of the drain current that is flowing through .
Substitute for and modify the expression.
…… (2)
Step 6 Of 10
Substitute for .
Step 7 Of 10
Substitute for .
Consider the expression to find minimum range of input common-mode voltage level.
Step 8 Of 10
Consider the expression of drain current .
…… (3)
Here,
Substitute for .
Step 9 Of 10
Substitute for .
Step 10 Of 10
Consider the formula to find output voltage of the Common mode level.
Here,
is the gate source voltage of MOSFET , is the gate source voltage of MOSFET , and are the threshold voltage
levels.
Substitute for , for , 0.7 V for .
Consider the expression to find maximum range of input common-mode voltage level.
Here,
is the output of CM amplifier and is the threshold voltage.
Thus, the allowable range of input common-mode level is .

Question:
Repeat Problem 13.35 if (W/L)6,7 = 10/0.5.
Step 1 Of 9
Substitute for .
Substitute for .
Step 2 Of 9
Write the formula to find the drain current of NMOS model transistor .
Here, is the oxide capacitance, is the threshold voltage, is the drain to source voltage, is the mobility, is the gate source
voltage of a MOSFET , and is the channel length of a MOSFET .
…… (1)
Refer to Table 2.1 in the textbook, mobility of electrons in NMOS is .
Step 3 Of 9
Substitute for .
Substitute for .
Step 4 Of 9
Consider the formula to find .
Here,
From the circuit diagram, the value of the drain current is half of the drain current that is flowing through .
Substitute for and modify the expression.
…… (2)
Step 5 Of 9
Substitute for .
Substitute for .
Consider the expression to find minimum range of input common-mode voltage level.
Step 6 Of 9
Consider the expression of drain current .

…… (3)
Here,
Substitute for .
Step 7 Of 9
Substitute for .
Step 8 Of 9
Consider the formula to find output voltage of the Common mode level.
Here,
is the gate source voltage of MOSFET , is the gate source voltage of MOSFET , and are the threshold voltage
levels.
Substitute for , for , 0.7 V for .

Step 9 Of 9
Consider the expression to find maximum range of input common-mode voltage level.
Here,
is the output of CM amplifier and is the threshold voltage.
Thus, the allowable range of input common-mode level is .

Question:
Suppose that in the common-mode feedback network of Fig. 13.61, S1 injects a charge of Δq onto the gate
of M5. How much do the gate voltage of M5 and the output common-mode level change due to this error?
Figure 13.61 Definition of the voltage across C1 and C2.
Step 1 Of 6
As the charge is injected onto the gate of , draw the modified circuit diagram as shown in Figure 1.
Step 2 Of 6
Small signal circuit components of each MOSFET are provided as follows:
Transconductance and output resistance of MOSFET is and .
Find the equivalent capacitance of two parallel connected capacitances and .
Step 3 Of 6
Draw the simplified circuit diagram as shown in Figure 2.
Step 4 Of 6
Consider the formulae to find the small signal parameters of a MOSFET.
Write the formula to find the transconductance of a MOSFET.
Here, is an effective channel length, is the drain current, is the oxide capacitance, is the mobility, and is width of the channel.
Write the formula to find the output resistance of a MOSFET.
Here, is the channel length modulation coefficient of MOSFET.

Step 5 Of 6
Draw the equivalent op-amp model of the circuit in Figure 2 as shown in Figure 3. Consider that the open loop gain of the amplifier as .
Step 6 Of 6
From Figure 3, The injected charge have the path through the capacitance to the output node. The output of Common Mode (CM)
level changes by the variation of charge injected . That is,
The rate of change in voltage at node X is depends on the open-loop gain of the op amp.
Therefore, the expression for the rate of change in voltage at node X (Change in gate voltage of due to the injected charge ).
Here, is the small signal open loop gain of the circuit, and the expression for the open loop voltage gain as follows by considering Figure 2.
The op-amp output voltage is equal to the input voltage multiplied by the open-loop gain, in reverse pattern to find the gate input voltage of the
, the ratio divides by the open-loop gain as shown in equation (1).
Thus, the change in gate voltage of and output of common-mode level due to injection of the charge are and ,
respectively.
Question:
In the circuit of Fig. 13.66, each op amp is represented by a Norton equivalent and characterized by Gm and
Rout. The output currents of two op amps are summed at node Y [7]. (The circuit is shown in the
amplification mode.) Note that the main amplifier and the auxiliary amplifier are identical and that the error
amplifier senses the voltage variation at node X and injects a proportional current into node Y. The output
impedance of the error amplifier is much greater than Rout. Assume that Gm Rout 1.
Figure 13.66
Step 1 Of 0
Question:
Calculate the gain error of the circuit.
Step 1 Of 0
Question:
Repeat part (a) if the auxiliary and error amplifiers are eliminated and compare the results.
Step 1 Of 0
Question:
The input-output characteristic of an amplifier is approximated as y(t) = α1x(t) + α2x2(t) in the range x = [0 =
xmax].
(a) What is the maximum nonlinearity?
(b) What is the THD for x(t) = (xmax cos ωt + xmax)/2.

Step 1 Of 6
(a)
Consider the input-output characteristic equation of an amplifier.
…… (1)
Consider the range of xis .

Draw the input-output relation over a range of x as shown in Figure 1.
Step 2 Of 6
Write the expression for the straight line passing through the end points.
Find the difference between yand .

Substitute for y, and for .
…… (2)
Maximum error occurs when the derivative of with respect to xequals to zero.
Differentiate equation (2) with respect to x.
Substitute 0 for .
Step 3 Of 6
Substitute for x.
Thus, the maximum nonlinearity output is .
Step 4 Of 6
(b)
Substitute for .
Step 5 Of 6
…… (3)
Step 6 Of 6
In equation (3), is fundamental term, is second harmonic term and is constant term.
Find the total harmonic distortion.
Substitute for second harmonic term, and for fundamental term.
Thus, the THD is .

Question:
In the circuits of Fig. 14.6, W/L = 20/0.5 and I = 0.5 mA. Calculate the harmonic distortion in each circuit if
the input signal has a peak amplitude of 100 mV. How do the results change if we double W/L or I?
Figure 14.6 Single-ended and differential amplifiers providing the same voltage gain.
Step 1 Of 10
Refer to Figure 13.6 in the textbook for single-ended and differential amplifiers providing the same voltage gain.
Case 1:
Consider the first circuit of single-ended amplifier in Figure 13.6.
Consider the formula for drain current of MOSFET .
Here, is the drain current of MOSFET , is the mobility of charge carriers of NMOS device, is the gate oxide capacitance per
unit area, W is the channel width, L is the channel length, is the gate-to-source voltage, is the threshold voltage, and is the
signal applied to the circuit.
Consider the expression for I when .
…… (1)
Step 2 Of 10
…… (2)

Substitute for .
Step 3 Of 10
Consider that NMOS device is in saturation region and the length of the device (L) is equal to the effective length due to the source/drain side
diffusion.
…… (3)
The value of width and length of the MOSFET is very small. Therefore, consider that the unit of width and length is in .
Substitute for L in equation (1).
Modify the expression for MOSFET .
…… (4)
Step 4 Of 10
Substitute for , for , for , for , and for I in equation (4).

Step 5 Of 10
Step 6 Of 10
Consider the expression for harmonic distortion of single-ended amplifier circuit.
…… (5)
Here, is the amplitude of the second harmonic, is the fundamental amplitude, and is the peak amplitude of the input signal.
Substitute 100 mV for and 356 mV for .
Find the percentage of harmonic distortion.
Find the harmonic distortion in decibel value of .
Step 7 Of 10
…… (6)
From equation (6), the value of is divided by when the factor of is doubled.
Use equation (5) to write the relation between and .
…… (7)
Substitute for .
Substitute for .
…… (8)
From equation (8), the harmonic distortion is increased by the factor of when is doubled.
Consider that the value of I is doubled.
From equation (6), the value of is increased by when the value of I is doubled.
Modify (7) for .
Substitute for .
Substitute for .
…… (9)
From (9), the harmonic distortion is decreased by the factor of or 3dB when current (I) is doubled.
Thus, the harmonic distortion of a single-ended amplifier circuit is ; the obtained result is increased by the factor of or 3dB when
is doubled and decreased by the factor of or 3dB when current (I) is doubled.
Step 8 Of 10
Case 2:
Consider the second circuit of differential amplifier in Figure 13.6.
As the voltage gain of two circuits is the same, the value of for differential amplifier circuit is equal to the value of single-
ended circuit.
Consider the expression for harmonic distortion of differential amplifier circuit.
…… (10)
Here, is the amplitude of the harmonic, is the fundamental amplitude, and is the peak amplitude of the input signal.
Substitute 100 mV for and 356 mV for equation (10).
Find the percentage of harmonic distortion.
Find the decibel value of .
Step 9 Of 10
Consider that the value of is doubled.
Use (10) to write the relation between and .

…… (11)
Substitute for .
Substitute for .
…… (12)
From (12), the harmonic distortion increases by the factor of 2 or 6dB when is doubled.
Step 10 Of 10
Consider that the value of I is doubled.
Substitute for .
Substitute for .
…… (13)
From equation (13), the harmonic distortion is divided by the factor of 2 or 6dB when current (I) is doubled.
Thus, the harmonic distortion of differential amplifier circuit is ; the obtained result is increased by factor 2 or 6dB when is
doubled and decreased by factor of 2 or 6dB when current (I) is doubled.
Question:
For the circuits of Fig. 14.6, plot the THD and the input-referred thermal noise as a function of (a) W/L, (b)
I. Identify the trade-offs among noise, linearity, and power dissipation.
Step 1 Of 11
(a)
Refer to Figure 13.6 (a) in the textbook for a single-ended amplifier.
Consider the expression for I.
…… (1)
Step 2 Of 11
Consider the expression for harmonic distortion of a single-ended amplifier circuit.
Here, is the amplitude of the second harmonic, is the fundamental amplitude, is the peak amplitude of the input signal, is the
gate-to-source voltage, and is the threshold voltage.
Re-arrange expression.
…… (2)
…… (3)
From equation (3), the value of is decreased by the factor of .
Use equation (2) and write the relation between and .
…… (4)
Substitute for .
Substitute for .
…… (5)
From equation (5), the amplitude of harmonic distortion is increased by the factor of .
Step 3 Of 11
Step 4 Of 11
Here, is the transconductance of MOSFET and is the drain resistance.
…… (6)
Step 5 Of 11

Substitute for .
Write the expression for thermal noise due to MOSFET.
Substitute for .
Square equation (6) on both sides.

Modify the expression for thermal noise.
…… (7)
Step 6 Of 11
Here, is the drain current, and is mobility of charge carriers.
…… (8)
…… (9)
Step 7 Of 11
Use equations (5) and (9) to plot the total harmonic distortion (THD) and input-referred thermal noise voltage as shown in Figure 2.
Step 8 Of 11
The value of THD is obtained by the ratios of voltages. Since the power is related to square of the voltage value, the value of THD varies as a
square of the quantity with respect to power dissipation.
From Figure 2, an increase in the value of degrades the linearity by reducing the noise voltage.
Thus, the plot of total harmonic distortion (THD) and input-referred thermal noise voltage as a function of is shown in Figure 2.
Step 9 Of 11
(b)
From equation (3), the value of is increased by .
Substitute for .
Substitute for .
…… (10)
From equation (10), the amplitude of harmonic distortion is decreased by the factor of .
Step 10 Of 11
Consider that the value of I is the same as .
Substitute I for in equation (8).

…… (11)
…… (12)
Use equations (10) and (12) to plot the total harmonic distortion (THD) and input-referred thermal noise voltage as shown in Figure 3.
Step 11 Of 11
From Figure 3, an increase in the value of I decreases both noise and nonlinearity. The power dissipation varies as the changes in input-referred
thermal noise voltage .
Thus, the plot of total harmonic distortion (THD) and input-referred thermal noise voltage as a function of current is shown in Figure 3.
Question:
In Fig. 14.6, two effects lead to a trade-off between nonlinearity and voltage gain. Describe these effects.
Step 1 Of 2
Refer to Figure 13.6 (first circuit) and Figure 3.3 (a) in the textbook for single-ended amplifier circuit and common-source stage respectively.
Consider the formula for voltage gain.
…… (1)
Here, is the drain current, is the gate oxide capacitance per unit area, is the mobility of NMOS device, is the width to length ratio,
is the voltage drop across resistor .
Case 1:
Consider the drain current has constant value.
From equation (1), as ratio increased to increase the voltage gain, the linearity of the circuit degrades. From the properties of linear functions,
the square root functions are nonlinear functions. So that, even though is in proportional relation with , it degrades the linearity.
Case 2:
Consider the drain current value increases.
If the drain current increased to linearize the circuit, then the value of drain resistance decreased into balanced range to maintain the same voltage
level.
Step 2 Of 2
Refer to Figure 13.6 (second circuit) and Figure 4.11 in the textbook for differential amplifier circuit and common-source stage respectively.
…… (2)
Here is the bias current and is equal to , is the gate oxide capacitance per unit area, is the mobility of NMOS device, is
the width to length ratio, is the drain resistance.
Case 1:
Consider the drain current has constant value.
From equation (2), as ratio increased to increase the voltage gain, the linearity of the circuit degrades.
Case 2:
Refer to Figure 4.13 in the textbook for input-output characteristic of differential pair.
…… (3)
From equation (3), increase in ratio decreases the value of , which results in narrowing the input range across and .
Refer to Figure 4.13 (c) in the textbook for input-output characteristic of differential pair as increase in value of .
In this case, both the input voltage range and the output current swing increases due to increase in the value of .
Thus, the trade-offs between nonlinearity and voltage gain is described.
Question:
The circuit of Fig. 14.6(a) is designed with W/L = 50/0.5, I = 1 mA, and RD = 2 kΩ. The circuit is placed in a
feedback loop similar to that of Fig. 14.7 with β = 0.2 and senses an input sinusoid with a peak amplitude of
10 mV. Calculate the THD at the output.
Figure 14.7 Feedback system incorporating a nonlinear feedforward amplifier.
Step 1 Of 9
Refer to Figure 13.6 (a) and Figure 13.7 in the textbook for single-ended amplifier and feedback system incorporating a nonlinear feedforward
amplifier circuit respectively.
…… (1)
area, W is the channel width, L is the channel length, is the gate-to-source voltage, is the threshold voltage, and is the signal
applied to the circuit.
Consider the expression for normalized amplitude of the second harmonic to that of the fundamental.
…… (2)
Here, and are the small signal gain, is the feedback factor, and is the peak amplitude of the input signal.
The total harmonic distortion (THD) is same as the normalized amplitude of the second harmonic to that of the fundamental.
…… (3)
Step 2 Of 9
…… (4)
…… (5)
Substitute for .
Step 3 Of 9
diffusion.
…… (6)
…… (7)
Step 4 Of 9

Step 5 Of 9
Substitute for , for , for , for ,and for I in equation (7).
Step 6 Of 9
Consider as a single term in equation (1).

…… (8)
Consider the expression for harmonic content present in the nonlinearity circuit.
…… (9)
Here, is the signal applied to the circuit, , are the small signal gain.
Modify equation (9) for applied signal .
…… (10)
Use equation (8) and (10) to write the values of small signal gain.
Find the value of .
Substitute for .
Step 7 Of 9
Consider the expression for small signal voltage gain including drain resistor.
…… (11)

Write the expression for Taylor expansion.
Consider the expression for when x has smaller value.
…… (12)
Step 8 Of 9
From equation (12), the overall gain of the circuit is nearly equal to for smaller value of x.
Substitute for L.
…… (13)
Substitute for , for , for , for , for ,and for .
Step 9 Of 9
Substitute for , 0.2 for , for , and for .
Thus, the obtained value of THD is .

Question:
Suppose that in Fig. 14.16, A1 and A2 have an input-referred noise voltage Vn. Neglecting other sources of
noise, calculate the input-referred noise voltage of the overall circuit.
Step 1 Of 6
Refer to Figure 13.14 in the textbook for differential pair using input devices operating in the triode region.
Modify the Figure as shown Figure 1.
Step 2 Of 6
Replace MOSFET by resistor and modify the Figure 1 as shown Figure 2.

Step 3 Of 6
From Figure 2, write the expression for .
…… (1)
Step 4 Of 6
Consider the value of .
…… (2)
Step 5 Of 6
Consider the value of gain of the amplifier is greater than 1 .

…… (3)
Here,
is the output current, and is the input voltage.
Modify equation (3) for input-referred noise voltage applied to MOSFET .
Step 6 Of 6
Substitute for .
Thus, the input-referred noise voltage of the overall circuit is .

Question:
Equation 14.36 suggests that if the open-loop gain, α1, increases while other parameters remain constant,
then the harmonic distortion drops sharply. Repeat Problem 14.14.5 with W/L = 200/0.5 to achieve a higher
open-loop gain and explain the results.
Step 1 Of 13
Refer to Figure 13.6 (a) and Figure 13.7 in the textbook for a single-ended amplifier and feedback system incorporating a nonlinear feedforward
…… (1)
…… (2)
Here, and are the small signal gain, is the feedback factor, and is the peak amplitude of the input signal.
The total harmonic distortion (THD) is the same as the normalized amplitude of the second harmonic to that of the fundamental.
…… (3)
Step 2 Of 13
…… (4)
…… (5)
Here, is the permittivity of silicon oxide, and is the thickness of the oxide layer.

Substitute for .
Step 3 Of 13
Consider that the NMOS device is in saturation region and the length of the device (L) is equal to the effective length due to the source/drain
side diffusion.
…… (6)
…… (7)
Step 4 Of 13
Step 5 Of 13
Modify equation (7) for the initial width of MOSFET .

Substitute for , for , for , for , and for I.
Step 6 Of 13

…… (8)
…… (9)
Here, is the signal applied to the circuit , which are the small signal gain.
…… (10)
…… (11)
…… (12)
Find the value of .
Substitute for .
…… (13)
Step 7 Of 13
…… (14)

Consider the expression for when x has the smaller value.
…… (15)
…… (16)

Substitute for .
Substitute for L.
…… (17)
Substitute for , for , for , for , for , and for

.
…… (18)
Step 8 Of 13
…… (19)

Step 9 Of 13
…… (20)
Consider that the width of the MOSFET is changed from to .
Modify equation (7) for the increased width of MOSFET .
Substitute for , for , for , for , and for I.
Step 10 Of 13

Find the value of .
Substitute for .
…… (21)
Step 11 Of 13
Substitute for .
Substitute for L.
…… (22)
Substitute for , for , for , for , for , and

for .
…… (23)
Step 12 Of 13
Step 13 Of 13
Modify equation (3) for increased width of MOSFET .
Substitute for .
…… (24)
Compare equations (13) and (21); the value of doubles as ratio of the MOSFET increases by 4 times.
Compare equations (18) and (23); the value of doubles as ratio of the MOSFET increases by 4 times.
Compare equations (20) and (24); the value of total harmonic distortion decreases as ratio of the MOSFET increases by 4 times.
Thus, the obtained value of THD with is . The values of and get doubled and harmonic distortion drops
sharply as ratio of the MOSFET increased by 4 times.

Question:
Equation 14.36 suggests that if βα1 1, then b/a ∝ β−2. Repeat Problem 14.14.5 with β = 0.4.
Step 1 Of 13
Refer to Figure 13.6 (a) and Figure 13.7 in the textbook for single-ended amplifier and feedback system incorporating a nonlinear feedforward
…… (1)
area, W is the channel width, L is the channel length, is the gate-to-source voltage, is the threshold voltage, and is the signal
applied to the circuit.
Step 2 Of 13
…… (2)
Here, and are the small signal gains, is the feedback factor, and is the peak amplitude of the input signal.
The total harmonic distortion (THD) is same as the normalized amplitude of the second harmonic to that of the fundamental.
…… (3)
Step 3 Of 13
…… (4)
…… (5)

Step 4 Of 13
Substitute for .
Step 5 Of 13
diffusion.
…… (6)
…… (7)
Step 6 Of 13
Step 7 Of 13
Substitute for , for , for , for ,and for I in equation (7).
Step 8 Of 13

…… (8)
…… (9)
Here, is the signal applied to the circuit, , are the small signal gain.
…… (10)
Step 9 Of 13
Find the value of .
Substitute for .
Step 10 Of 13
…… (11)

Consider the expression for when x has the smaller value.
…… (12)
Step 11 Of 13
Substitute for L.
…… (13)
Step 12 Of 13
Substitute for , for , for , for , for ,and for .
Step 13 Of 13
Find the value of .
The obtained value of is greater than 1. Therefore, .

Substitute for .
Thus, the obtained value of THD is .

Question:
Suppose the nonlinear feedforward amplifier in Fig. 14.7 is characterized by y(t) = α1x(t) + α3x3(t). Estimate
the magnitude of the third harmonic at the output of the overall system.
Figure 14.7 Feedback system incorporating a nonlinear feedforward amplifier.
Step 1 Of 6
Refer to Figure 13.7 in the textbook for feedback system incorporating a nonlinear feedforward amplifier circuit.
Modify figure as shown in Figure 1.
Step 2 Of 6
Consider the sinusoidal input applied is and the approximated output is .
…… (1)
Step 3 Of 6
Write the expression for output.
Substitute for .
Use the formula to simplify the expression.
Use the formula to simplify the expression.
Neglect the higher-order terms in the expression.
…… (2)
Step 4 Of 6
Compare equations (1) and (2).
Equate the coefficients of .
…… (3)
Step 5 Of 6
Equate the coefficients of .
Step 6 Of 6
Find the magnitude of the third harmonic at the output of overall system .
Substitute for .
Substitute for a.
Thus, the magnitude of the third harmonic at the output of overall system is .
Question:
As mentioned in Chapter 2, MOSdevices operating in the subthreshold region exhibit an exponential
behavior: ID = I0 exp[VGS/(ζ VT)]. Suppose both of the circuits shown in Fig. 14.6 operate in the
subthreshold region. Derive expressions for the harmonic amplitudes if the input signal is much less than ζ
VT. For the differential pair, first prove that ID1 − ID2 ∝ tanh[Vin/(2ζ VT)] and then write the Taylor
expansion of the hyperbolic tangent.
Step 1 Of 7
Refer to Figure 13.6 in the textbook for single-ended and differential amplifier.
…… (1)
Here,
is the gate-to-source voltage, is the thermal voltage, is a nonideality factor, and is the reverse saturation current.
Consider is applied to the circuit. So, the value of is equal to .

…… (2)
Consider the input signal is much less than .
In equation (2), only second harmonic is significant, that is .
Thus, the harmonic amplitudes if the input signal is much less than is
Step 2 Of 7
Consider the differential pair circuit.
…… (3)
Here,
is the drain current in MOSFET , and is the drain current in MOSFET .

Consider the expression for applied voltage.
…… (4)
…… (5)
Step 3 Of 7

Step 4 Of 7
…… (6)
…… (7)
Step 5 Of 7

Step 6 Of 7
Find the expression for .
…… (8)
Use to solve equation (8).
…… (9)
Step 7 Of 7
Consider is applied to the circuit. So, the value of is equal to .
Use formula to simplify the expression.
Use formula to simplify the expression.

The third harmonic is equal to .
Thus, the expression of is proved and Taylor expansion of the hyperbolic tangent
.
Question:
The mobility of MOSFETs is in fact a function of the gate-source voltage and expressed as μ = μ0/[1 +θ(VGS
− VTH)], where θ is an empirical factor (Chapter 17). Assuming that θ (VGS − VTH) 1 and using the
relationship (1 + ϵ)−1 ≈ 1 − ϵ for ϵ 1, calculate the third harmonic in the circuit of Fig. 14.6(a).
Step 1 Of 2
Refer to Figure 13.6 (a) in the textbook for single-ended voltage gain.
Here, is the drain current, is the mobility, is the width to length ratio, is the gate-to-source voltage, and is the threshold
voltage.
Substitute for .
…… (1)
Step 2 Of 2
Consider a signal is applied to the circuit.
In this case, the value of equals to .

Substitute for
…… (2)
In equation (2), the third harmonic is .
Thus, the third harmonic in Figure 13.6 (a) is .

Question:
The input devices of a differential pair have an effective length of 0.5 μm.
(a) Assuming that and neglecting other mismatches, determine the minimum width of
the transistors such that VOS ≤ 5 mV.
(b) If the tail current is 1 mA, what is the maximum input swing that gives a THD of 1%?
Step 1 Of 6
(a)
…… (1)
Here,
is the oxide thickness, is the threshold voltage mismatch,W is the width of the transistor, and L is the length of the transistor.
The normal allowable mismatch in transistor quantity is of original quantity.
The is the voltage applied at the gate terminal of the transistor and which is approximately equal to .Therefore, the value of is same
as .
Substitute for .
Step 2 Of 6
Refer to Table 2.1 in the textbook for level 1 spice models for NMOS and PMOS devices.
Substitute for , for , for L in equation (1).
Square the expression on both sides.
Thus, the minimum width of the transistors is

Step 3 Of 6
(b)
Consider the formula for amplitude of the third harmonic.
…… (2)
Here, is the amplitude of the third harmonic, is the amplitude of the signal, is the gate to source voltage , and is the threshold
voltage.
…… (3)
Here, is the drain current, is the gate oxide capacitance per unit area, is the mobility, is the width to length ratio, is the gate-to-
source voltage, and is the threshold voltage.
Step 4 Of 6
…… (4)
Substitute for .
Step 5 Of 6
Consider the drain current is tail current.
Substitute for .
Substitute for , for , for , for W, and for L.
Square root on both side.
Step 6 Of 6
Substitute for , and for in equation (2)
Thus, the maximum output swing is .

Question:
Repeat Problem 14.14.12 if the tolerable input offset is 2 mV and compare the results.
Step 1 Of 11
…… (1)
Here, is the oxide thickness, is the threshold voltage mismatch,W is the width of the transistor, and L is the length of the transistor.
The normal allowable mismatch in transistor quantity is of original quantity.
The is the voltage applied at the gate terminal of the transistor and which is approximately equal to .Therefore, the value of is same
as .
Substitute for .
Step 2 Of 11
Refer to Table 2.1 in the textbook for level 1 spice models for NMOS and PMOS devices.
Substitute for , for , for L.
Square the expression on both sides.
Step 3 Of 11
Consider the formula for amplitude of the third harmonic.
…… (2)
Here, is the amplitude of the third harmonic, is the amplitude of the signal, is the gate to source voltage , and is the threshold
voltage.
…… (3)
Here,
is the drain current, is the gate oxide capacitance per unit area, is the mobility, is the width to length ratio, is the gate-to-source
voltage, and is the threshold voltage.
Step 4 Of 11
…… (4)
Substitute for .
Step 5 Of 11
Consider the drain current is tail current.
Substitute for .
Step 6 Of 11
Substitute for , for , for , for W, and for L.
Square root on both side.
Step 7 Of 11
Substitute for , and for in equation (2)
Step 8 Of 11
Refer to Figure 4.11 in the textbook for differential pair circuit.
Consider the formula for voltage gain of differential pair.
…… (5)
Here,
is the gate oxide capacitance per unit area, is the mobility of electron, is the width to length ratio, is the transistor biased current,
and is the drain resistor.

…… (6)
Step 9 Of 11
…… (7)
Substitute for and for W.
…… (8)
Modify equation (7) for changed value of input offset.
Substitute for .
…… (9)
Thus, the value of width (W) increased by decrease in input offset voltage.
Step 10 Of 11
…… (10)
Use equation (10) and write the relation between and W.
…… (11)
…… (12)
Modify equation (12) for changed value of width (W).
…… (13)
Substitute for , for W, and for .
Thus, the value of decreased by decrease in input offset voltage.
Step 11 Of 11
…… (14)
…… (15)
Use equations (11) and (15) to write the relation between and W.
…… (16)
Modify equation (16) for changed value of width (W).
…… (17)
Substitute for , for W, and for .
Thus, the value of decreased from 0.61 V to 0.242 V by the decrease in the input offset voltage.
Question:
Determine the dimensions of M1 and M2 in Fig. 14.28 such that ID1 ≈ ID2 = 0.5 mA, Δ ID/ID = 2%, and VGS
− VTH = 0.5 V. Assume that and neglect other mismatches.
Figure 14.28 Mismatch between two current sources.
Step 1 Of 7
Refer to Figure 13.25 in the textbook for the MOSFET circuit that shows the mismatch between two current sources.
Consider the formula for current mismatch.
…… (1)
Here, is the channel width, L is the channel length, is the gate-to-source voltage, is the threshold voltage, is the drain current,
is the drain current mismatch, and is the threshold voltage mismatch.
Consider the mismatch occurs due to the threshold voltage only and neglect all other mismatches. Then,
Modify equation (1) for threshold voltage mismatch.
…… (2)
Substitute for .
Substitute for .
Step 2 Of 7
…… (3)
Here, and is the thickness of the oxide layer, W is the channel width, and L is the channel length.
Step 3 Of 7
…… (4)
Here, is the drain current of MOSFET, is mobility of charge carriers of NMOS device, is the gate oxide capacitance per unit area, W
is the channel width, L is the channel length, is the gate-to-source voltage, and is the threshold voltage.
…… (5)
Step 4 Of 7

Substitute for .
Step 5 Of 7
…… (6)
…… (7)
Substitute for .

Step 6 Of 7
Step 7 Of 7
Consider MOSFET’s and are identical to each other.
Thus, the width of and is and length of and is .

Question:
Source degeneration can improve the matching between current sources if resistor mismatches are small.
Prove that in the circuit of Fig. 14.41,
where ΔRS denotes the mismatch between RS1 and RS2. Note that for an appreciable reduction of ΔI /ID, RS
must be greater than 1/gm.
Figure 14.41
Step 1 Of 0
Question:
In the circuit of Fig. 14.29, assume that αj = βj but x1(t) = A cos ωt and x2(t) = A cos(ωt + θ), where θ denotes
a small phase mismatch. Calculate the magnitude of the second harmonic at the output.
Figure 14.29 Effect of mismatch on second-order distortion.
Step 1 Of 4
Refer to Figure 13.26 in the text book for effect of mismatch on second-order distortion.
Consider the formula of differential output.
…… (1)
Here, , , and are the magnitude of the first, second and third harmonic at the output respectively.
Modify equation (1) in terms of and .
Consider the condition between and .
…… (2)
Substitute 1 for j.
Substitute 2 for j in equation (2).
Substitute 3 for j in equation (2).
Step 2 Of 4

Step 3 Of 4
Consider the second harmonic term in expression .
Step 4 Of 4
Use formula and simplify the expression.
Thus, the magnitude of second harmonic at the output is .

Question:
In the circuit of Fig. 14.42, M3 and M4 suffer from a threshold mismatch of Δ VTH and the circuit is
otherwise symmetric. Assuming that λ ≠ 0 but γ = 0, calculate the input-referred offset voltage. What
happens as RD →∞?
Figure 14.42
Step 1 Of 5
In this circuit MOSFET and suffer from a threshold mismatch of .

Modify the circuit as shown in Figure 1.
Step 2 Of 5
Write the expression for voltage gain of the circuit.
…… (1)
Consider the value of is moderate and greater than the value of and the value of is very small.
Step 3 Of 5
Write the expression for voltage gain with moderate value of .
Here,
is the transconductance of MOSFET , and is the drain resistor.

…… (2)
Modify equation (2) for input offset voltage.
Thus, input-referred offset voltage is .
Step 4 Of 5
Consider the value of is equal to infinity.


Step 5 Of 5
Modify equation (2) for input offset voltage when .
Since, the value of is negligible, the offset contributed by cascade devices can be neglected.
Thus, offset contributed by cascade devices can be neglected when .

Question:
In the circuit of Fig. 14.32, the amplifier has an input capacitance (between X and Y) equal to Cin. Calculate
the input offset voltage after offset compensation.
Figure 14.32 (a) Input offset storage; (b) circuit of (a) in the offset cancellation mode.
Step 1 Of 6
Step 2 Of 6
Consider the capacitors and are unequal and is equal to .
Consider at the virtual ground, the capacitor and are parallel to each other.
Draw the arrangements of capacitors at input virtual ground as shown in Figure 2.
Step 3 Of 6
Modify Figure 2 as shown in Figure 3.
Step 4 Of 6
In Figure 3, capacitor is in series with .

Find the total capacitance of the circuit.
Write the expression for output voltage in terms of voltage gain of the amplifier.
Substitute for .
Step 5 Of 6
Substitute for
Consider the expression for total voltage gain of the circuit.
Substitute for .
Step 6 Of 6
Substitute for .
Thus, the expression for input offset voltage is .

Question:
The circuit of Fig. 14.32 is designed for an input offset voltage of 1 mV. If the width of the transistors in the
input differential pair of the amplifier is doubled, what is the overall input offset voltage? (Neglect the input
capacitance of the amplifier.)
Figure 14.32 (a) Input offset storage; (b) circuit of (a) in the offset cancellation mode.
Step 1 Of 3
Refer to Figure 4.6 in the textbook for basic differential pair circuit.
…… (1)
Here,
is the drain current, is the gate oxide capacitance per unit area, is the mobility of NMOS device, is the width to length ratio, is
the bias current and is equal to , and is the drain resistor.
From equation (1), write the relation between voltage gain and ratio.
…… (2)
Substitute for W.
…… (3)
As width (W) is doubled, the gain of the differential pair is approximately increased by factor .
Step 2 Of 3

…… (4)
From equation (4), for same value , write the relation between and .
…… (5)
Substitute for W.
…… (6)
As width (W) is doubled, the threshold voltage of the differential pair is approximately decreased by factor .
Step 3 Of 3
As the value of width (one of the basic parameter) changes, the input device exhibits a smaller mismatch.
Refer to Figure 13.21 (a) and (b) in the textbook for differential pair with offset measured at the output circuit and with its offset referred to the
input respectively.
Consider the expression for input-referred offset voltage.
…… (7)
Substitute for .
As width (W) is doubled, input-referred offset voltage of the differential pair is decreased by factor 2 which in turns drops the input-referred offset
voltage of input offset storage circuit approximately by factor .
Thus, overall input offset voltage is drops by factor .

Question:
Explain why the circuit of Fig. 14.27 suffers from a trade-off between the input offset and the output voltage
swing (for a given tail current).
Figure 14.27
Step 1 Of 3
Consider the expression for input offset voltage of the circuit.
…… (1)
Here,
is the width to length ratio, is the change in width to length ratio, is the overdrive voltage of PMOS transistor,
is the overdrive voltage of NMOS transistor, is the threshold voltage of PMOS transistor, is the threshold voltage of
NMOS transistor, is the transconductance of PMOS transistor, and is the NMOS transistor.
Consider that the tail current in the circuit is related to PMOS transistor.
…… (2)
Step 2 Of 3
…… (3)
Here,
…… (4)
Modify equation (4) for PMOS transistor.
Modify equation (3) for PMOS transistor.
Substitute for .
Step 3 Of 3
The input offset voltage decreases as the overdrive voltage of PMOS transistors increases.
The tail current source suppresses the effect of the input common mode level variations on the output swing. Therefore,
maximizing the overdrive voltage of PMOS transistors decreases the input offset voltage but limits the high-level output voltage swing.
Thus, the trade-off between the input offset voltage and output voltage swing is explained.
Question:
For the circuit of Fig. 15.6, determine the open-loop tranfer function and calculate the phase margin.
Assume that gm1 = gm2 = gm and neglect other capacitances.
Figure 15.6 Two-pole feedback system with additional signal inversion.
Step 1 Of 3
Refer to Figure 14.6 in the textbook for two-pole feedback system with additional signal inversion.
Consider that the open-loop transfer function is the product of two stages. Each stage has the transfer function of .
Then, the expression for the open-loop transfer function is,
…… (1)
Step 2 Of 3
Write the expression for the 3-dB bandwidth .
Re-arrange the equation.
Consider the expression for the factor.
…… (2)
The gain falls to unity at , which for the condition . This provides the frequencies and .
Substitute for .
Step 3 Of 3
The phase changes from at frequency to at frequency that is the change in phase at is
.
Consider the expression for the phase margin.
Substitute for .
Thus, the open-loop transfer function is and the phase margin is .

Question:
In the circuit of Fig. 15.8, assume that gm1 = gm2 = gm3 = (200 Ω)−1.
(a) What is the minimum value of RD that ensures oscillation?
(b) Determine the value of CL for an oscillation frequency of 1 GHz and a total low-frequency loop
gain of 16.
Figure 15.8 Three-stage ring oscillator.
Step 1 Of 3
(a)
Refer to Figure 14.8 in the textbook for the circuit of three-stage ring oscillator.
Consider the transconductance when all three MOSFETs transconductances are equal is .
Consider the condition of low frequency gain for ensuring the oscillation.
Substitute for .
The minimum value of reistance to ensure oscillation .
Thus, the minimum value of for oscillation is .
Step 2 Of 3
(b)
Write the expression for the oscillation frequency when low-frequencygain is considered as minimum value 2 per stage.
…… (1)
Consider the expression for the 3-dB bandwidth .

…… (2)
Step 3 Of 3
Write the expression for the total low frequency loop gain for a three stage ring oscilator.
Substitute 16 for total gain.
Substitute for .
Substitute for and 1 GHz for in equation (2).
Thus, the value of capacitance is .

Question:
For the circuit of Fig. 15.12, determine the minimum value of ISS that guarantees oscillation. (Hint: if the
circuit is at the edge of oscillation, the swings are quite small.)
Figure 15.12
Step 1 Of 2
Refer to Figure 14.12 in the textbook for differential implementation of the oscillator.
Consider that each stage of the oscillator requires the minimum small-signal gain of 2. Then the oscilator low-frequency gain considtion is,
…… (1)
Here, is transconductance and is resistance.

Each transistor (MOSFET) carries a half of the tail current.
For square-low devices, consider the expression in equation (1) for oscillation.
Step 2 Of 2
…… (2)
Square on both sides of the equation.

The current is requiredminimum equal or greater than the value of .
Thus, the minimum value of that guarantees oscillation of the oscillator is .

Question:
Prove that the small-signal resistance of the composite load in Fig. 15.18(c) is roughly equal to 1/gm3.
Figure 15.18 Differential stages using PMOS loads.
Step 1 Of 2
Refer to Figure 14.18(c) in the textbook
The circuit is modified as shown in Figure 1.
By neglecting the body effect of mosfet the circuit has . As a result, the drain and gate of mosfet experience voltage variations
equally. That is, the mosfet operates as a diode-connected device. The impedance mosfet is equal to .
Step 2 Of 2
Refer to Figure 14.18(c) in the textbook
In the circuit, the NMOS source follower is placed between the drain and gate of PMOS transistors. If , mosfet will operates at
the edge of the triode region and the small-signal resistance of the load is approximately equal to , by assuming . That is,
The small-signal resistance of mosfet is approximately equal to the small-signal resistance of composite load.
Thus, the small-signal resistance of the composite load is approximately equal to .

Question:
Including only the gate-source capacitance of M3 in Fig. 15.18(c), explain under what condition the
impedance of the composite load (seen at the drain of M3) becomes inductive.
Figure 15.18 Differential stages using PMOS loads.
Step 1 Of 3
Figure 1 shows a gate-source capacitance of .

In Figure 1, if approximately equal to , then the mosfet will operates at the edge of the triode region and small-signal resistance of
the load is approximately equal to , by considering .
In Figure 1, consider the relationship between the voltages and .

Step 2 Of 3
In Figure 1, consider the relationship between the current and voltage .
Therefore, the impedance is always inductive
Step 3 Of 3
In Figure 1, as gate source capacitance of mosfet is driven by the source follower, the time constant associated with the composite load
will be lesser than that of a diode-connected transistor. Likewise, the finite output resistance of the follower will lead to an inductive behavior of the
composite load.
Thus, at finite output resistance of the follower the impedance of the composite load will be inductive.
Question:
If each inductor in Fig. 15.25 exhibits a series resistance of RS, how low must RS be to ensure that the low-
frequency loop gain is less than unity? (This condition is necessary to avoid latch-up.)
Figure 15.25 Two tuned stages in a feedback loop.
Step 1 Of 2
Refer Figure 14.25 in the textbook for two tuned stages in a feedback loop.
In this circuit, the configuration in Figure 14.25 does not latch up when the low frequency gain is very small.
Consider that each inductor in the circuit exhibits the series resistance . Then, neglect the resistance in the circuit.
Step 2 Of 2
The condition to avoid latch up, which is alsothe condition for ensuring the low-frequency loop gain to beless than unity is as follows:
…… (1)
The product of transconductance and series resistance should be greater than unity to avoid latch up.
Thus, the condition for series resistance to ensure the low-frequency loop gain to be less than unity is .
Question:
Explain why the VX and VY waveforms in Fig. 15.28 are closer to sinusoids (i.e., they contain smaller
harmonics) than are the ID1 and ID2 waveforms do.
Figure 15.28
Step 1 Of 3
Consider if the circuit starts with zero difference between and , then it means that the voltages are reached at that is nearly equal to
the drain-drain voltage . At this instant X, Y and acts as a single node.
Consider if , then at the resonant frequency, the noise components are amplified by the mosfets and , thereby resulting in
increasing oscillations. The tail current trough each of the transistors is .
Step 2 Of 3
The amplitude of oscillation rises till the loop gain falls at the peaks. When is a large level that causes the voltage difference between
, then it will attain a level that directs the total tail current toward one transistor and the other transistors are turned off. As a result, in a
steady state, the drain currents and vary between 0 and , and the addition of both the currents is equal to the total tail current .
Step 3 Of 3
For a short duration, currents and will saturate near 0 and as the waveform in a square manner. The output voltages and drain
the currents into RLC tanks. As RLC tanks are suppressed at high harmonics in the current changing, the voltages and are applied at the
nodes like a filtered manner of the drain currents and . Therefore, the waveforms of and look as sinusoid with less harmonics,
where and look in the shape of a square waveform
From Figure 14.28 in the textbook, the voltages and are shown as filtered versions of drain currents and , and the amplitude of
oscillations increases up to the point where the loop gain drops at the peak.
Thus, the reason for waveforms and to be nearer to sinusoids is explained.

Question:
Determine the minimum value of ISS in Fig. 15.47(c) that guarantees oscillation. Estimate the maximum
value of ISS that guarantees that M1 and M2 do not enter the triode region.
Figure 15.47 (a) Current folding topology; (b) application of current folding to current steering.
Step 1 Of 2
Refer Figure 14.27 (c) in the textbook.
For oscillation of the circuit, the loop gain should exceed unity. That is,
…… (1)
Here, is the transconductance and is the equivalent parallel resistance.
Modify equation (1) for transcondutance as shown.
Consider the condition for square-law devices,
…… (2)
Here, W is the gate width, L is the gate length, is the gate oxide capacitance per unit area, is the tail current and is the mobility of
electrons.
Square on both sides in equation (2) to obtain the following:
Step 2 Of 2
To constrain the mosfets and entering into the triode region, the minimum and maximum voltages at nodes and should not differ by
exceeding the threshold voltage . That is, the peak-to-peak voltage swing at nodes and should not go beyond . As the peak-to-peak
voltage swing is nearly equal to , the threshold voltage should be greater than . That is, . Hence, the maximum value
of tail current that limits the mosfets from entering into the triode region should not exceed the threshold voltage. That is, the relation is written
as follows:
Thus, the minimum value of is and the maximum value of should be less than .
Question:
Repeat Example 15.7 by applying a current stimulus to the drain of M1.
Example 15.7
Figure 15.30
Step 1 Of 2
Refer to Example 14.7 in the textbook
Figure 1 shows the input current is connected to the drain of mosfet .

In Figure 1, the total current from the source flowing through the mosfet and capacitor is equal to the base current . The input source
current is injecting in to the RLC tank.
Step 2 Of 2
The closed-loop gain for the circuit by ignoring the mosfet parasitics is as follows,
Further modify the equation.

Thus, the closed loop gain for the circuit is , and the simplified function is .
Question:
Prove that if a capacitor CP is placed in parallel with LP in Fig. 15.31(a), then Eq. (15.47) results.
Figure 15.31 (a) Colpitts oscillator; (b) equivalent circuit of (a) with input stimulus
Step 1 Of 2
Refer to Figure 14.31(a) in the textbook for Colpitts oscillator.
Consider the expression for for the Colpitts oscillator.
…… (1)
Here, is power drive resistance, is power drive inductance, and is transconductance.
Consider that the capacitor is placed in parallel with the inductor .
Replace with in equation (1).
…… (2)
Step 2 Of 2
The denominator of equation (2) is reduces to the expression of characteristic equation as,
Re-arrange the equation as follows:
Equate the imaginary part to zero.
…… (3)
Consider that . Neglect in equation (3).
Thus, the required expression of is verified.

Question:
The Colpitts oscillator of Fig. 15.31(a) was analyzed and its oscillation conditions were derived by applying
a current stimulus to the source. Repeat the analysis by applying a voltage stimulus to the gate of M1.
Figure 15.31 (a) Colpitts oscillator; (b) equivalent circuit of (a) with input stimulus
Step 1 Of 4
Refer to Figure 14.31(a) in the textbook shows Colpitts oscillator.
In the circuit, add a voltage stimulus to the gate of mosfet and the modified circuit is shown in Figure1.
By approximating with a voltage source, the equivalent circuit of Figure 1 is redrawn as shown in Figure 2.
Step 2 Of 4
The current flowing through and (parallel combination) is,
The negative of this current is flowing through the capacitor and producing a voltage across is,
Consider the expression for voltage .
Consider the expression for current flowing through capacitor .
Step 3 Of 4
Summing and the current flowing through capacitor , and equating the relation with as shown.

Step 4 Of 4
Thus, the closed-loop gain of the circuit is

Question:
Repeat the analysis of the Colpitts oscillator for the topologies in Figs. 15.38(a) and (c). Determine the
oscillation condition and the frequency of oscillation.
Figure 15.38 Oscillator topologies derived from the circuit of Fig. 15.37(c).
Figure 15.38 Oscillator topologies derived from the circuit of Fig. 15.37(c).
Figure 15.37 (a) Circuit topology providing negative resistance; (b) equivalent circuit of (a); (c) oscillator
using (a).
Step 1 Of 6
Figure 2 shows the equivalent circuit of Figure 1.
In Figure 1, consider the expression for voltage .

Step 2 Of 6
In Figure 2, apply Kirchhoff’s voltage law as shown.
Substitute for .
Step 3 Of 6

…… (1)
Refer to Figure 14.31 in the textbook shows a colpitts oscillator.
Consider the expression for of a colpitts oscillator.
…… (2)
On comparing equation (1) and (2), the denominator of equation (1) is same the denominator of equation (2). Therefore, the oscillation conditions
are same as that of the colpitts oscillator.
Step 4 Of 6
Figure 4 shows the equivalent circuit of Figure 3.

In Figure 4, consider the output voltage as because for the oscillations to begin the gain from the input current to output voltage and
should be infinity.
Consider the parallel resistance of the circuit as infinity. That is, .
Step 5 Of 6
In Figure 4, apply Kirchhoff’s current law as shown.
…… (3)
In Figure 4, consider the expression for current in the circuit.
Step 6 Of 6
Now, include the parallel resistance and modify the equation as shown.
…… (4)
On comparing equation (2) and (4), the denominator of equation (2) is same the denominator of equation (4). Therefore, the frequency of
oscillation is same as that of the colpitts oscillator.
Thus, the oscillation condition and the frequency of oscillation are determined and are same as of the colpitts oscillator.
Question:
The stage of Fig. 15.45 is designed with IT = 1 mA and (W/L)1,2 = 50/0.5. Assume that IH I1.
(a) Determine the minimum value of R1 = R2 = R to ensure oscillation in a three-stage ring.
(b) Determine (W/L)3,4 such that gm3,4 R = 0.5 when each of M3 and M4 carries IT/2.
(c) Calculate the minimum value of IH to guarantee oscillation.
(d) If the common-mode level of Vcont1 and Vcont2 is 1.5 V, calculate (W/L)5,6 such that IT sustains
0.5 V when Vcont1 = Vcont2.
Figure 15.45 Use of a differential pair to steer current between M1–M2 and M3–M4.
Step 1 Of 8
(a)
For oscillation in a three-stage ring, the minimum gain value per stage at low frequencies should be 2. Therefore,
…… (1)
Since no current flows through the mosfets and .

…… (2)
…… (3)
Here, is the tail current, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width and L is the gate
length.
…… (4)
…… (5)
Thus, the minimum value of resistance for the oscillation in a three-stage ring is .
Step 2 Of 8
(b)
…… (6)
Divide equation (6) and equation (3) as shown.
Step 3 Of 8
Squaring on both sides.
Thus, the value of is 6.25.
Step 4 Of 8
(c)
Figure 14.45 is modified as shown in Figure 1.
Figure 2 shows the modified equivalent circuit of Figure 1.
Step 5 Of 8
The voltage gain of the circuit should be equal to 2 with a differential pair of tail current where the mosfets and carries all of current
.
In Figure 2, consider the expression for voltage gain.
Step 6 Of 8
Consider if (to avoid latch up), therefore
…… (7)
Consider the expression for transcondutance .
Consider the expression for transcondutance .

Substitute for , 6.25 for , for , for , for and for .
Thus, the minimum value of tail current to guarantee oscillation is .
Step 7 Of 8
(d)
Figure 14.45 is modified as shown in Figure 3 by neglecting the body effect.
In Figure 3, consider the expression for tail current .

Find the value of .
Step 8 Of 8
Substitute 1 V for , 0.7 V for , for , for and for .
Thus, the value of is 100.

Question:
Repeat Example 15.14 if each inductor in the circuit contributes a constant capacitance equal to C1.
Example 15.14
Step 1 Of 3
Consider that the built-in potential of junction as 0.7 V. The reverse bias voltage vary from 0 to 2 V.
Consider the expression for capacitance of varactor.
…… (1)
Here, is the zerobias value.
Calculate the varactor capacitance when .
Substitute 0 for , 0.35 for m, and 0.7 V for in equation (1).
Calculate the varactor capacitance when .
Substitute 2 V for , 0.35 for m, and 0.7 V for in equation (1).
Step 2 Of 3
When each inductor contributes the capacitance of , then the expression for minimum oscillation frequency when is,
…… (2)
The expression for maximum oscillation frequency when is,

…… (3)
Step 3 Of 3
Consider the expression for the turning range.
…… (4)
Substitute equations (2) and (3) in (4).
…… (5)
This is less than 27%.
In Example 14.14 in the textbook, the turning range is approximately 27%. Since the constant capacitance is added, the turning ratio is less
than 27%.
For example, when , calculate the turning range.
Substitute for in Equation (5).
Thus, the achieved turning range is .

Question:
The VCO of Fig. 15.53 is designed for operation at 1 GHz.
(a) If LP = 5 nH and the total (fixed) parasitic capacitance seen at X (and Y) to ground is 500 fF,
determine the maximum capacitance that D1 and D2 can add to the circuit.
(b) If the tail current is equal to 1 mA and the Q of each inductor at 1 GHz is equal to 4, estimate
the output voltage swing.
Figure 15.53 LC oscillator using varactor diodes.
Step 1 Of 4
(a)
Refer to Figure 14.53 in the textbook for LC oscillator by using varactor diodes.
Consider the value of inductor is 5 nH. The value of parasitic capacitance is 500 fF.
Consider the expression for the oscillation frequency.
Substitute 1 GHz for , 5 nH for , and 500 fF for .
Thus, the maximum capacitance is .
Step 2 Of 4
(b)
Consider the expression for the Q-factor.
Substitute 5 nH for and 4 for Q.

Substitute for f.
Step 3 Of 4
Consider the formula to calculate the value of .
Substitute 4 for Q and for .
Step 4 Of 4
When the tail current is 1 mA, calculate the peak-to-peak voltage swing on each side.
Substitute 1 mA for and for .
Thus, the output voltage swing is .

Question:
The Gilbert cell (Chapter 4) operates as an XOR gate with large input swings and as an analog multiplier
with small input swings. Prove that an analog multiplier can be used to detect the phase difference between
two sinusoids. Is the input-output characteristic of such a phase detector linear?
Step 1 Of 3
Refer to Chapter 4 for Gilbert cell in the textbook.
In this, an analog multiplier output voltage is equal to product of two voltage signals.
Step 2 Of 3
Consider the two signals and . Calculate an analog multiplier voltage using the two signals.
…… (1)
Step 3 Of 3
In equation (1), consider if the high frequency component is filtered out, then output voltage is directly proportional to cosine of angle .
That is,
…… (2)
Consider that is unity at , and zero at .
From equation 2, draw the waveform for as shown in Figure 1.

From Figure 1, it is analyzed that the phase detector is linear only for a small regionaround .
Thus, an analog multiplier is used to detect the phase difference between two sinusoids and it is proved. Yes, the input-output characteristic of a
phase detector is linear.
Question:
Redraw the waveforms of Fig. 16.4(b) if the VCO frequency is lowered at t = t1. If the phase error between
VCK and VVCO before t = t1 is equal to and fVCO is lowered from fH to fL, determine the minimum t2 − t1
that is sufficient for phase alignment.
Figure 16.4 (a) Two waveforms with a skew; (b) change of VCO frequency to eliminate the skew.
Step 1 Of 2
The waveforms of Figure 15.4 (b) are redrawn to align the output phase of a voltage-controlled oscillator with the phase of a reference
clock , which is shown in Figure 1.
Figure 1 shows the waveforms for clock voltage, voltage-controlled oscillator voltage, and control voltage versus time.
Step 2 Of 2
Refer to Figure 1; consider that the voltage-controlled frequency is stepped to a lower value at . The phase detector in the circuit then
accumulates the phase faster and slowly decreases the phase error . At time , the phase error falls to zero and yields the control
voltage to its normal value.
Write the expression for the phase angle .
…… (1)
Here, is the angular frequency and t is the time.
Consider the expression for the angular frequency.
Here, f is the frequency.
…… (2)
Refer to Figure 1; consider that the change in time is and the frequency is lowered from to . That is, .
Thus, the minimum time change required for phase alignment is .

Question:
Explain why the low-pass filter in Fig. 16.5(b) cannot be replaced by a high-pass filter.
Figure 16.5 (a) Feedback loop comparing input and output phases; (b) simple PLL.
Step 1 Of 2
The voltage controlled oscillator (VCO) needs a quiet steady-state control voltage as an input.The low-pass filter (LPF) is mainly used to suppress
the high-frequency components from the phase detector (PD) output,thereby presenting the dc component control voltage to the voltage controlled
oscillator.
Step 2 Of 2
A high-pass filter cannot provide the desirable dc componentsince the output results at high frequencies and is not saturated to the desired level.
Therefore, the low-pass filters (LPF) are mostpreferred to use in a simple phase-locked loop (PLL) circuit.
Thus, the low-pass filter (LPF) is not replaced by a high-pass filter (HPF).
Question:
A PLL using an XOR gate as a phase detector locks with if KPDKVCO is large. Explain why.
Step 1 Of 2
Refer to Figure 15.6 in the textbook for a simple phase-locked loop (PLL) using an exclusive OR gate as phase detector.
In Figure 15.6 (b) the calculation of phase error the phase detector (PD) gain drops to zero at .
Consider the PLL waveforms characteristics shown in Figure 1.
Step 2 Of 2
Consider the expression for the phase in a phase-locked loop (PLL) in locked condition.
That is, with a large loop gain, the phase detector output settles around half of its full scale.
Therefore, from Figure 1 the control voltage is very small and hence, the phase error is .
Thus, a phase-locked loop using exclusive OR gate as a phase detector locks with the phase difference , and it is explained.
Question:
Using the characteristic of Fig. 16.3 as an example, explain why the polarity of feedback in a PLL (without
frequency detection) is unimportant. (Hint: prove that the loop locks regardless of whether the initial phase
difference falls in the positive-slope region or the negative-slope region.)
Figure 16.3
Step 1 Of 2
Modified figure is shown in Figure 1 when the phase difference falls in the positive-slope region.
In Figure 1, the positive-slope region is drawn with a maximum magnitude of voltage for the plot versus .
Step 2 Of 2
Consider the loop that initiates with . When the feedback is considered as positive, the loop accumulates so much of the phase to drive the
phase detector (PD) toward the phase , where as when the feedback is considered as negative, the loop is settled down.
Thus, the polarity of feedback in a phase-locked loop is unimportantand it isexplained.
Question:
Assuming a first-order LPF in Fig. 16.14, determine the transfer function Φout/Φex, where Φout denotes the
excess phase of Vout.
Figure 16.14
Step 1 Of 2
Refer to Figure 15.14 in the textbook; consider a first order low-pass filter (LPF) is shown in Figure 1.
In Figure 1, denotes the excess phase of .
Step 2 Of 2
In Figure 1, apply block diagram reduction technique to determine the value of .
…… (1)
Here, is the angular frequency of low pass filter, is gain of phase detector, is gain or sensitivity of the filter circuit.
Consider the excess phase denotes the external voltage .
Thus the transfer function of is .

Question:
A VCO used in a type I PLL exhibits nonlinearity in its input-output characteristic, i.e., KVCO varies across
the tuning range. If the damping ratio must remain between 1 and 1.5, how much variation can be tolerated
in KVCO?
Step 1 Of 2
Consider the voltage-controlled oscillator (VCO) used in a type I phase-locked loop (PLL), which shows nonlinearity in the input-output
characteristics.
Figure 1 shows the nonlinear characteristic for across the tuning range .
In Figure 1, the terms and are the gains of voltage-controlled oscillator, which are determined by providing slope in the curve across
the tuning range .
Step 2 Of 2
Write the expression for the damping ratio .
…… (1)
Here, is the frequency of low-pass filter, is the gain of phase detector, and is the gain of voltage-controlled oscillator.
As the damping ratio varies from 1 to 1.5, consider the two cases as and .
Use equation (1) to consider the expression for damping ratio when the gain is .
Substitute 1 for .
…… (2)
Use equation (1) to consider the expression for damping ratio when the gain is .
…… (3)
Thus, the slope in the curve across the tuning range varies by a factor of .
Question:
Prove that in the root locus of Fig. 16.20, cos θ = ζ.
Figure 16.20 Root locus of type I PLL.
Step 1 Of 3
Redraw the Figure 15.20 in the textbook as Figure 1 which shows the root locus of type I phase-locked loop (PLL).
Step 2 Of 3
Consider the expression for the two poles of the closed-loop system.
…… (1)
Here, is the natural frequency and is the damping ratio.
From equation (1), the real part of pole is and the imaginary part of pole is .
Refer to Figure 1; consider the expression to find the angle .
…… (2)
Step 3 Of 3
Consider the expression for trigonometry formula.
…… (3)
From equation (3), the term is equal to . That is, .
Thus, the root locus of Figure 1 is .

Question:
A type I PLL incorporates a VCO with KVCO = 100 MHz/V, a PD with KPD = 1 V/rad, and an LPF with
ωLPF = 2π(1 MHz). Determine the step response of the PLL.
Step 1 Of 3
Write the expression for the damping ratio .
Here, is the angular frequency of low-pass filter in Hz, is the gain of phase detector, and is the gain of voltage-controlled
oscillator.
Hence, the system is underdamped for a type I phase-locked loop (PLL).
Step 2 Of 3
Consider the relationship between the natural frequency and angular frequency of low-pass filter.
Consider the expression for the natural frequency.
Here, is the frequency.

Substitute for .
Consider the expression for the time constant.
Here, is the natural frequency.
Step 3 Of 3
Write the expression for the step response of the phase-locked loop (PLL).
…… (4)
Here, t is the time, is the time constant, is the phase angle and is the unit step response.
Consider the maximum value of phase angle is .
Thus, the step response of the PLL is .

Question:
Explain why in the charge-pump PLL of Fig. 16.35, the control voltage of the VCO cannot be connected to
the top plate of CP.
Figure 16.35 Addition of zero to charge-pump PLL.
Step 1 Of 2
Refer to Figure 15.35 in the textbook, which shows the addition of zero to a charge-pump phase-locked loop (PLL).
Consider if the control voltage of the voltage control oscillator (VCO) is sensed at node X, then the resistor seems to be in series with the
current in the sources charge pump, thereby failing to give zero .
Figure 1 shows the control voltage that is connected to the top plate of the capacitor .
Step 2 Of 2
The control voltage must be connected as shown in Figure 15.35 in the textbook with the series connection and for the charge-pump
phase-locked loop. The series combination of and can add a zero to increase the stability of the system.
Thus, the control voltage of the voltage control oscillator (VCO) is not connected to the top plate of capacitor and it is explained.
Question:
Prove that the transfer function of the PFD/CP/LPF circuit in Fig. 16.35 is given by Eq. (16.43).
Step 1 Of 3
Refer to Figure 15.35 in the textbook shows that addition of zero to charge-pump phase-locked loop (PLL).
In this Figure, a resistor is connected in series with the loop filter capacitor. Therefore, a Laplace transform for a series connection of resistor
and capacitor is .
Step 2 Of 3
Refer to Example 15.10 in the textbook, the transfer function from phase error to the current is expressed as follows:
Step 3 Of 3
Using Ohm’s law, the voltage is calculated by the current multiplied by the series combination of resistor and capacitor. That is,
Thus, the transfer function of the PFD/CP/LPF circuit is and it is proved.

Question:
As illustrated in Fig. 16.45, mismatches between the UP and DOWN currents translate to phase offset at the
input of a CPPLL.With the aid of the waveforms in Fig. 16.45, calculate the phase offset in terms of current
mismatch.
Figure 16.45 Effect of UP and DOWN current mismatch.
Step 1 Of 2
Figure 15.45 is redrawn as shown in Figure 1 for the effect of UP and DOWN current pulse mismatch.
Step 2 Of 2
Consider if the phase-locked loop generates a phase error among the input and the output, then the net current injected by a charge pump in each
cycle is zero. That is, the phase error is determined when the net current is zero.
Refer to Figure 1; the net current due to the current pulses and is mismatched, which is equal to and the width of the magnitude of
current pulse is equal to . Therefore, the phase error is expressed as
Here, is the finite period and is the current due to the charge pump.
Thus, the phase offset in terms of current is .

Question:
For a VCO, we have ωout = ω0 + KVCOVcont. The control line experiences a small sinusoidal ripple, Vcont =
Vm cos ωmt. If the VCO is followed by a ÷M circuit, determine the output spectrum of the divider. Consider
two cases: ω0/M > ωm and ω0/M < ωm.
Step 1 Of 6
Consider the expression for the output frequency of voltage control oscillator (VCO).
Here, is the gain of voltage control oscillator, is the control voltage, and is the angular frequency.
Consider the expression for the control voltage with a small sinusoidal ripple.
Here, is the maximum voltage.
Step 2 Of 6
Consider the expression for the voltage control oscillator (VCO) output.
Substitute for .
…… (1)
Rewrite the output voltage when is small.

…… (2)
Using equation (2), draw output voltage of the spectrum as shown in Figure 1.
Step 3 Of 6
Similarly using equation (1), consider the expression for the output spectrum of the divider.
Simplify the equation for small value of .
…… (3)
Step 4 Of 6
Reduce the equation (3).
…… (4)
Step 5 Of 6
Case 1:
For :
Using equation (4), draw the spectrum of divider output as shown in Figure 2.
Step 6 Of 6
Case 2:
For :
Using equation (4), draw the spectrum of divider output as shown in Figure 3.
Thus, the output spectrum of the divider is
. The output spectrum is drawn for the two cases as shown in Figure 2 and Figure
3.
Question:
Prove that the root locus of a type II PLL is as shown in Fig. 16.37.
Figure 16.37 Root locus of type II PLL.
Step 1 Of 6
Consider the expression for the characteristics roots of type II PLL.
…… (1)
…… (2)
Step 2 Of 6
Consider the expression for the natural frequency.
…… (3)
Here, is the gain of voltage control oscillator, is the capacitor of charge-pump, and is the current due to charge pump.
Consider the expression for the damping ratio.
…… (4)
Here, is the resistor of charge-pump.
Step 3 Of 6
From equation (3) and (4), the damping ratio and the natural frequency is directly proportional to . That is, and
.
Since, the values of starts from small values, the roots of are complex. Therefore, from equation (2) and
.
Substitute for .
…… (5)
Step 4 Of 6
Adding to both sides, and subtracting and adding .
……. (6)
Therefore, equation (5) isa circle centered at with a radius equal to .
Step 5 Of 6
Using equation (6), draw the root locus diagram as shown in Figure 1.
Step 6 Of 6
Consider the damping ratio means the pulses become real and move away from each other’s and .
Consider if , then to find .
Therefore, Figure 1 is same as Figure 15.37 in the textbook shows root locus of type II phase-locked loop (PLL).
Thus, the root locus of a type II phase-locked loop shown in Figure 15.37 is proved.
Question:
Determine the transfer function Φout/Φex for the circuit of Fig. 16.14 if the PLL is modified to the
architecture of Fig. 16.35.
Figure 16.14
Step 1 Of 2
Refer to Figure 15.14 in the textbook; consider a block diagram shown in Figure 1 when phase-locked loop is modified to the architecture of
Figure 15.35 in the textbook.
In Figure 1, denotes the excess phase of .
Step 2 Of 2
In Figure 1, apply block diagram reduction technique to determine the value of .
…… (1)
Here, is gain or sensitivity of the filter circuit, is the charge pump driving capacitor. is the charge pump driving resistor, and is the
current provided by charge pump.
Consider the excess phase denotes the external voltage .
Thus the transfer function of is .

Question:
When a charge-pump PLL incorporating a PFD is turned on, the VCO frequency may be far from the input
frequency. Explain why the order of the PLL transfer function is lower by one while the PFD operates as a
frequency detector.
Step 1 Of 2
Consider a charge-pump phase-locked loop including a phase/frequency detector is turned on. If the voltage control oscillator (VCO) frequency is
far from the input frequency, then the phase/frequency detector (PFD) works as a frequency detector, and this compares the voltage control
oscillator frequency and input frequency. Hence, the transfer function of voltage control oscillator (VCO) relates the output frequency to
the control voltage .
…… (1)
Step 2 Of 2
From equation (1), the order of the system falls by one from the voltage control oscillator (VCO) phase as the factor becomes .
Thus, the order of the phase-locked loop is lower by one when the phase/frequency detector operates as a frequency detector, and it isexplained.
Question:
Silicon dioxide breaks down at high electric fields. Explain what happens if ideal scaling is performed while
keeping the gate oxide thickness constant.
Step 1 Of 3
Consider ideal scaling is performed by keeping the gate-oxide thickness constant. Therefore, W, L, and scale down by .
Consider the expression for drain current of a square-law device after scaling.
Here, is the gate-source voltage, is the threshold voltage, is the scaling factor, is the mobility of electrons and is the gate oxide
capacitance per unit area.
Consider the expression for total channel capacitance of a square-law device after scaling.
Step 2 Of 3
Consider that the junction capacitances of source/drain are neglected. Therefore,
Consider the expression for gate delay of a square-law device after scaling.
Step 3 Of 3
Consider the expression for transconductance of a square-law device after scaling.
Thus, the scaling of with constant is same as ideal scaling, and the scaling of , is times of the ideal scaling. The
channel capacitance is is times of the ideal scaling.

Question:
The maximum doping level that can be established in the source and drain regions is limited by the “solid
solubility” of silicon. Explain what happens to the S/D junction capacitance and series resistance as ideal
scaling occurs, but the S/D doping level remains constant. Does DIBL become more or less significant?
Step 1 Of 2
Consider that ideal scaling is performed by keeping the doping level constant.
Consider the expression for total width of the depletion region of a square-law device after scaling.
Modify the equation as shown.
Here, is the reverse bias voltage, , are the doping levels of the junction, is the scaling factor and q is the charge.
Step 2 Of 2
As the depletion region width scales down by , there is an increase in the depletion region capacitance per unit area by the same factor.
Therefore, the depletion region capacitance per unit area increases by instead of and the series resistance increases.
The drain-induced barrier lowering (DIBL) arises mainly from the depletion region in the substrate instead of the drain. As a result, the DIBL will
remain relatively constant.
Thus, the S/D junction capacitance increases by , the series resistance increases, and the DIBL remains constant.
Question:
Suppose the supply voltage of a switched-capacitor amplifier is reduced by a factor of two and so is the
maximum allowable output voltage swing. In order to maintain the dynamic range constant, the noise
voltage must scale down by the same factor.
(a) If the noise is only of kT/C type, how should the capacitors in the circuit be scaled?
(b) If the time constant is given by Gm/C, where Gm denotes the transconductance of a one-stage
op amp, how should Gm be scaled to maintain the same small-signal time constant?
(c) How should the dimensions and tail current of the input differential pair of the op amp be
scaled?
(d) Repeat parts (b) and (c) where the slew rate must remain constant.
Step 1 Of 5
Figure 1 shows a switched-capacitor amplifier circuit.
Through ideal scaling, the maximum permissible output voltage swing will reduce by and decrease the dynamic range. Consider the supply
voltage of the switched-capacitor amplifier circuit is decreased by 2.
Step 2 Of 5
(a)
Consider the expression for noise rms voltage.
Consider the maximum allowable voltage swing is reduced by factor 2, that is, . Therefore, to make constant swing the capacitor should be
increased by factor 4. It is shown as follows,
As the noise is only , the capacitor must increase by a factor 4 to maintain constant swing.
Thus, the capacitors scaled by a factor of .
Step 3 Of 5
(b)
Consider the expression for time constant.
In order to retain the dynamic range, of the transistors should be raised by since noise voltages and current scale down with
Therefore, the transconductance should increase by a factor 4.
Thus, should be scaled by a factor 4.
Step 4 Of 5
(c)
For square-law devices, the bias current and dimensions should raise by a factor 4. Therefore, the power rises by a factor 2.
Thus, and are scaled by a factor 4.
Step 5 Of 5
(d)
Consider if the dynamic range lower end is determined by noise, therefore to retain a constant slew rate in switched-capacitor amplifier,
have to be scaled by a factor . Therefore, it leads to rise in power dissipation. Hence, should rise by a factor 4.
Thus, is scaled by a factor 4.

Question:
Explain how each parameter in Eq. (17.16) scales in an ideal constant-field scaling scenario. What happens
to the subthreshold slope?
Step 1 Of 3
Consider the expression for subthreshold drain current of a MOSFET.
…… (1)
Here, is the capacitance of the depletion region, is the gate source voltage, is the threshold voltage, is nonideality factor, is
the drain source voltage, is the thermal voltage, W is the gate width, and L is the gate length.
Consider the expression for capacitance of the depletion region.
Here, q is the charge, is the substrate doping density and is the built-in potential.
Consider the expression for nonideality factor.
Here, is the gate oxide capacitance per unit area.
…… (2)
Step 2 Of 3
Consider the effect of ideal constant-field scaling the parametersin equation (2) as shown.
Step 3 Of 3
Equation (1) has two important properties. As drain-source voltage goes beyond a small thermal voltage , the drain current will be
independent of and the relationship reduces as follows,
Under this condition, on a logarithmic scale the slope of drain current equals
The inverse of this quantity is called as the subthreshold slope, S. Hence, the scaled subthreshold slope is,
Therefore, the subthreshold slope decreases. That is, the subthreshod behavior increases.
Thus, the ideal constant-field scaling scenario on each parameter is explained.
Question:
A common-gate stage designed for an input impedance of 50 Ω undergoes ideal scaling. If λ = γ = 0, what is
the input impedance?
Step 1 Of 2
Figure 1 shows a common-gate designed circuit.
In Figure 1, consider the expression for input impedance.
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, is the gate

Step 2 Of 2
Consider the input impedance undergoes ideal scaling. Assume, an oxide capacitance scaled by , voltage scale down by ,
dimensions of W and L of the transistor are scaled down by in the ideal scaling.
Write the total input impedance of square-law device after scaling as,
Substitute for .
Hence, there is no impact on the input impedance before and after scaling for the Figure 1.
Thus, the scaled input impedance is .

Question:
Repeat Problem 17.5 if λ ≠ 0, γ ≠ 0, and the load is a MOS current source that is also scaled.
Step 1 Of 3
Figure 1 shows a common-drain designed circuit .
In Figure 1, consider the expression for input impedance of the circuit.
Here, is the transconductance, is the backgate transconductance and is the output resistance.
Consider if , then the equation is modified as shown.
…… (1)
Consider the expression for total input impedance of square-law device after scaling.
…… (2)
Step 2 Of 3
Consider the expression for backgate transconductance.
…… (3)
Consider the expression for backgate transconductance of square-law device after scaling.
…… (4)
In equation (4), if , then the equation is modified as shown.
Step 3 Of 3
When , then the scaled backgate transconductance is approximately equal to the backgate transconductance . That is,
Thus, the scaled input impedance is .

Question:
For power-conscious applications, a figure of merit is defined as the transconductance of devices normalized
to their bias current. Determine this quantity for long-channel devices operating in strong inversion or the
subthreshold region. At what drain current are these two equal?
Step 1 Of 3
Consider the transconductance of a device is normalized to their bias current.
Consider the transistor are in saturation region.
Write the formula of transconductance of MOSFET under saturation.
Write the expression of the transconductance is normalized to bias current for the long-channel devices operating in saturation region.
Here, is the bias current, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width and L is the gate
length.
…… (1)
Step 2 Of 3
Write the relationship between transconductance and bias current for long-channel devices operating in subthreshold region.
Here, is the thermal voltage.

…… (2)
Step 3 Of 3
Assume two drain currents in both regions are same.
Square on the both sides of the equation.
Thus, the drain current at which the two quantities are equal is,
Thus, the quantity for long-channel devices operating in saturation region is and subthreshold region is . The two quantities
are equal at .
Question:
Explain why the mobile charge density cannot drop to exactly zero at any point along the channel. What
happens beyond the pinch-off point?
Step 1 Of 2
Consider the expression for the drain current of a MOSFET.
Here, is the drain charge and is the saturation velocity.

Consider the formula for current through the channel.
…… (1)
Here, is the charge and is the velocity.

Consider if charge drops to zero. Therefore, the equation becomes as follows:
Therefore, when drops to zero the velocity tend to infinity, but the velocity is restricted to saturation velocity. Therefore, at the pinch-off point,
the mobile charge density is not exactly zero.
Step 2 Of 2
The mobility of charge carriers experience saturation velocity in long channel devices when drain-source voltage is sufficientto a pinch off
along the channel. The mobile charge density at pinch-off point is near to zero and experience a large electric field. Hence, the carriers attain their
saturated velocity beyond the pinch-off point and shoot through the depletion region nearby the drain.
Thus, the reason for mobile charge density does notfall to zero exactly along the channel and it is explained.
Question:
Using Eq. (17.21), calculate the transconductance of a MOSFET. What happens if the overdrive voltage is
very small or very large?
Step 1 Of 5
…… (1)
Here, is the gate source voltage, is the threshold voltage, is the low field mobility, is the gate oxide capacitance per unit area, W
is the gate width, L is the gate length and is a fitting parameter.
…… (2)
Step 2 Of 5
…… (3)
Step 3 Of 5
…… (4)
Step 4 Of 5
Consider for very small over-drive voltages , and is negligible, therefore, the equation (4) will become as:
Consider for large over-drive voltages is very large, so that , therefore, the equation (4) will become as:
Step 5 Of 5
Thus, the transconductance of a MOSFET is . The transconductances for very small overdrive voltage
and very large overdrive voltage are and respectively. Hence, the transconductance with a very small overdrive voltage is
approximately double then the transconductance with very large overdrive voltage.
Question:
Using Eq. (17.30), calculate the transconductance of a MOSFET. Prove that
Step 1 Of 5
Consider the expression of drain current for degradation of the mobility.
…… (1)
Here, is the gate source voltage, is the threshold voltage, is the low field mobility, is the gate oxide capacitance per unit area, W
is the gate width, L is the gate length and is a fitting parameter.
Consider the expression for drain current in the saturation region.
…… (2)
Here, is the velocity saturation.

Equation (2) is similar to equation (1), inferring that the mobility degradation with both lateral and vertical fields can be denoted by addition of the
terms and .
Step 2 Of 5

…… (3)
Step 3 Of 5
Step 4 Of 5

…… (4)
Step 5 Of 5
Consider the expression for transcondutcance of a MOSFET.
Thus, the transcondutcance of a MOSFET is
and is proved.
Question:
Suppose the channel-length modulation coefficient λ is modified as λ/(1 + κVDS), where κ is a constant, to
represent the dependence of the output impedance upon VDS. Calculate rO. Explain how a current source
with such behavior introduces distortion in the voltage across it.
Step 1 Of 3
Consider the expression for drain current of a MOSFET in saturation region.
…… (1)
Here, is the mobility of electrons, is the gate source voltage, is the gate oxide capacitance per unit area, W is the gate width, is the
drain-source voltage, L is the gate length and is the modulation coefficient.
Consider the channel-length modulation coefficient is modified as . Therefore, equation (1) becomes,
…… (2)
Consider the expression for drain current of a MOSFET.
Consider the expression for output impedance.
Step 2 Of 3
Differentiate equation (2) with respect to . Therefore,
Substitute for .
Modify the equation as shown for output impedance.

Consider if , equation (2) is modified as shown.
Step 3 Of 3
Consider a MOSFET circuit shown in Figure 1
Consider the expression to find the voltage across the drain resistance .
Substitute for .
Therefore, if the gate-source voltage is varied by a small value, the nonlinear dependence on drain-source voltage will leads to
nonlinearity in the voltage across the drain resistance.
Thus, the value of output impedance is .

Question:
Assuming that the devices in Fig. 17.19 experience complete velocity saturation, derive expressions for the
voltage gain of each circuit in terms of W and vsat. Assume that λ = γ = 0.
Figure 17.19
Step 1 Of 2
Case I:
Consider the device experience complete velocity saturation.
Consider the formula for drain current of a MOSFET.
…… (1)
…… (2)
Here, is the gate oxide capacitance per unit area, W is the gate width, is the gate source voltage, is the drain charge, is the
threshold voltage and is the velocity saturation.
…… (3)
Substitute for .
Thus, the expression for voltage gain of the circuit is .
Step 2 Of 2
Case II:
Consider the device experience complete velocity saturation.
…… (4)
Consider the expression for transconductance and of a MOSFET.
Thus, the expression for voltage gain of the circuit is .

Question:
Using Eq. (17.37), calculate gmb and compare the result with that derived in Chapter 2.
Step 1 Of 2
Consider the expression for drain current with a varying threshold voltage.
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, is the drain-
source voltage, is the body-source voltage, is the gate-source voltage and is the threshold voltage.
Consider the expression for backgate transconductance for a varying threshold voltage.
Differentiate equation (1) with respect to as shown.
…… (2)
Step 2 Of 2
Consider the expression for backgate transconductance in saturation region.
…... (3)
Consider the expression for static feedback.
By comparing equation (2) and (3), in both the equations the backgate transconductance is proportional to . Equation (3) also proposes
that the incremental body effect will be less prominent as increases.
Thus, the value of is .
Question:
From Eq. (17.51), determine ∂Eg/∂T at room temperature and explain how it affects bandgap reference
voltages.
Step 1 Of 6
Consider the expression for bandgap energy of a MOSFET.
Here, T is the temperature.

Differentiate the equation with respect to T using quotient rule.
Consider the room temperature at .
Substitute for T in equation.
Step 2 Of 6
Consider the expression for saturation current of a bipolar device.
Here, b is a proportionality factor, is the bandgap energy, T is the temperature and k is the Boltzmann constant.
Differentiate the equation with respect to T.
…… (1)
Consider the expression for thermal voltage.
…… (2)
Here, q is the charge.
Step 3 Of 6
Consider the expression for base-emitter voltage.
Here, is the thermal voltage, is the collector current and is the saturation current.
Differentiate the equation with respect to T.
…… (3)
Step 4 Of 6
For bandgap references, equation (1) is modified as shown.
Simplify the equation and multiply the equation with on both sides.
…… (4)
Step 5 Of 6
From equations (3) and (4), the equation can be rewritten as,
…… (5)
Step 6 Of 6
Substitute for and q for in equation (5).
…… (6)
In equation (6), at room temperature consider the term is adding with , so that the temperature coefficient of is slightly more
positive, and affects the bandgap reference voltages.
Thus, the bandgap energy at room temperature is .

Question:
Suppose the fast corners of a process result from a higher μCox. Explain what happens to the voltage gain
and the input thermal noise of the circuits shown in Fig. 17.20 at the four corners of the process if the
transistors are biased at a constant current in saturation.
Figure 17.20
Step 1 Of 6
The circuit shown in 16.19(a) has a diode connected PMOS, where the drain currents and are same since both devices are in cascode
configuration. That is,
Consider the formula for transconductance of MOSFET under saturation.
Substitute for .
Consider the formula for transconductance of MOSFET under saturation.
Substitute for .
Step 2 Of 6
Consider the expression for voltage gain of the circuit.

…… (1)
From equation (1), if the fast corners of a process of result with a higher than , the voltage gain results in
, else the voltage gain will result in low value.
Step 3 Of 6
Consider the expression for input thermal noise voltage.
The relationship can be written as,
…… (2)
From equation (2), if the fast corners of a process of result with a higher and slow then the input thermal noise result with a .
Step 4 Of 6
……. (3)
Write the expression for the output resistance relationship with as follows:
The output resistances of NMOS and PMOS are in relationship as shown in equation (1), there is not much effect on the gain from the
output resistances of the two transistor, wheras plays vital role.
Step 5 Of 6
Write the expression for relationship with as follows:
Then,
Here, if the fast corners of a process of result with a higher and slow corners of a process of , the voltage gain results in
.
Step 6 Of 6
Since, the two transistors are connected in cascaded configuration, the input noise voltage is consider as same in Figure 16.19 (a). Therefore, the
input thermal noise has the relationship with as follows:
If the fast corners of a process of result with a higher and slow then the input thermal noise result with a .
Thus, the effect of fast corners of a process resulting higher on the voltage gain and the input thermal noise voltage is explained.
Question:
Repeat Problem 17.15 if each transistor is biased with a fixed VGS.
Step 1 Of 7
Consider the circuit shown in Figure 16.19(a), the transistors are biased with a constant and .
Consider the formula for transconductance of MOSFET .
Consider the formula for transconductance of MOSFET .
Step 2 Of 7
...... (1)
From equation (1), if the fast corners of a process of mosfet result with a higher than mosfet , the voltage gain
results in higher value, else the voltage gain will result in low value.
Step 3 Of 7
Consider the expression for input thermal noise voltage.
The relationship can be written as,

…… (2)
From equation (2), if the fast corners of a process of result with a higher and slow then the input thermal noise result with a .
Step 4 Of 7
……. (3)
Consider the expression for output resistance of mosfet .
…… (4)
Consider the expression for output resistance of mosfet .
…… (5)
Step 5 Of 7
Substitute for , for and for in equation (3)

…… (6)
Step 6 Of 7
Write the expression for the output resistance relationship with as follows:
The output resistances of NMOS and PMOS are in relationship as shown in equation (1), there is not much effect on the gain from the
output resistances of the two transistor, wheras plays vital role.
Write the expression for relationship with as follows:
Then,
Here, if the fast corners of a process of result with a higher and slow corners of a process of , the voltage gain results in
.
Step 7 Of 7
Since, the two transistors are connected in cascaded configuration, the input noise voltage is considered as same in Figure 16.19 (a). Therefore,
the input thermal noise has the relationship with as follows:
If the fast corners of a process of result with a higher and slow then the input thermal noise result with a .
Thus, the effect of fast corners of a process resulting higher on the voltage gain and the input thermal noise voltage is explained.
Question:
A MOS technology is designed to provide only n-type transistors and two metal layers. Sketch the
fabrication steps and determine the minimum number of masks required in this technology.
Step 1 Of 7
The transistor fabrication steps are shown in Figure 1.
Step 2 Of 7
In Figure 1, the fabrication process starts with a p-type silicon wafer, having a thickness of nearly 1 mm. Followed by cleaning and polishing, a thin
layer of silicon dioxide is createdas a protective coating on the top of the wafer (Figure 1(a)).The growth of a field implant and field oxide is
required in the regions between the transistors. At this point, a stack consisting of a silicon oxide layer, silicon nitride and a positive
photoresist layeris formed. Then, the ‘active’ mask is used for lithography, due to that only the regions between the transistors only are exposed
(Figure 1(b)).
Next, the channel-stop implant is performed, followed by removal of photoresist and a thick layer of oxide is created in the exposed silicon areas,
fabricating the field oxide. Then, the oxide layers and protective nitride are removed (Figure 1(c)) and in the exposed areas, the transistors are
formed. Next, it involves the creation of gate oxide and a critical process necessitating slow, low-pressure chemical vapor deposition (Figure 1(d)).
Step 3 Of 7
The transistors ‘native’ threshold voltage is normally far from the preferred value, therefore requiring a threshold-adjust implant. The threshold
implant is accomplished followed by the development of gate oxide, and near to the surface develops a thin sheet of dopants. Therefore, it makes
the threshold of NMOSFET and PMOSFET more positive. Along the gate oxide in place, deposition of the polysilicon layer and followed by
‘poly mask’ lithography, it leads to a structure shown in Figure 1(e). Next, the substrate and the S/D junctions of the transistors are created by ion
implantation (Figure 1(f)).
Step 4 Of 7
After the fabrication of basic transistors, the wafer should undertake the ‘back-end’ processing, which is the primary sequence that provides
various electrical connections on the chip through wires and contacts.
In back-end processing,the first step is ‘silicidation’. It reduces the sheet resistance of doped polysilicon and source/drain regions by covering the
polysilicon layers, source/drain regions, and substrate by means of a thin layer of conductive material (tungsten or titanium silicide). Figure 2(a)
shows a formation of ‘oxide spacer’ at the polysilicon gate edges, so that the silicide deposition will be a self-aligned process.
Step 5 Of 7
Figure 2 shows oxide spacer and silicide layer.
Step 6 Of 7
Figure 3 shows contact and metal fabrication.
Step 7 Of 7
In back-end processing, the next process is to construct a contact window on the top of polysilicon and active regions. The wafer is protectedby
an oxide layer of thickness , and followed by a lithographic sequence with the ‘contact mask’,then formation of contact holes by
means of plasma etching [Figure 3(a)]. The first interconnect metal layer using copper or aluminum called ‘metal 1’ is deposited over the full region
of wafer. Using ‘metal 1 mask’ a lithographicarrangement is carried out and the metal layer is etched [Figure 3(b)]. Using the same process, higher
levels of interconnect are fabricated [Figure 3(c)]. Therefore, a CMOS process requiresat least one mask for the back end.
Thus, the fabrication steps are sketched, and the minimum number of masks required is .
Question:
During a threshold-adjust implant, the wafer was not tilted, leading to severe channeling. Explain whether
the resulting threshold voltage is higher or lower than the target value.
Step 1 Of 2
The native threshold voltage of the NMOS and PMOS transistors is normally far from the desired value, therefore imposing a threshold-adjust
implant. During the process of threshold-adjust implant, the concentrations of dopants are not close to the surface, and due to this reason the
dopant effect is less than expected.
Step 2 Of 2
Example: Consider the aim of the threshold implant to raise the threshold voltage of an NFET from 0 to 0.7 V, but the actual value will be less than
0.7 V.
Thus, during the threshold-adjust implant, the resulting threshold voltage will be lesser than the target value, and it is explained.
Question:
The circuits of Fig. 18.27 have been fabricated with a longer-than-expected gate oxidation cycle. If the
threshold voltages are still equal to the desirable value, sketch Vout versus Vin and compare the results to
the target case.
Figure 18.27
Step 1 Of 11
The circuit shown in Figure 17.31 (a) is a cascode configuration, the drain currents and is same.
…… (1)
Consider for mosfets , operates in the saturation region.
In Figure 17.31(a), since gate and source of mosfet isshorted, the output voltage is equal to the gate-source voltage of . And as
the source of mosfet is grounded, the voltage is equal to .
Step 2 Of 11
Consider the expression for drain current in the saturation region where the NMOSFET does not depend on .
Substitute for . .
Consider the expression for drain current in the saturation region where the PMOSFET does not depend on .
Substitute for .
Step 3 Of 11
…… (2)
Modify the equation by eliminating .
…… (3)
From equation (3), the current operation is independent of in the saturation region.
Step 4 Of 11
Consider for mosfet enters the triode region by further increasing in .
Consider the expression for drain current in triode region.
From Figure 17.31 (a) the voltage is equal to .
Substitute for , and for . .
Step 5 Of 11
Consider the expression for drain current in the saturation region.
Substitute for and
…… (4)
From equation (4), the current operation is independent of in in triode region, is in the saturation region.
Step 6 Of 11

Refer to figure 17.31 (a), the value of exists at when . Here, device opened is called a cut off region. remain
constant till reaches the threshold voltage . Here, device enters in to the saturation region for .Thereafter starts to
connect so that the output voltage drops from and settles at the minimum value in the triode region. Device enters in to the triode
region where the output gets equal to . When the mosfet enter into the triode region, the output voltage gradually decreases and
remains constant at the level of .
Step 7 Of 11
The circuit shown in Figure 17.31 (b) is a CMOS current inverter, the drain currents and is related since the devices are connected in
cascade configuration.
…… (5)
Consider that mosfet operates in the saturation region, and mosfet operates in the triode region.
For saturation region: Here .
For triode region: Here and .
Step 8 Of 11
Substitute for , and

…… (6)
From equation (6), the current operation is independent of in operate in the saturation region, and operate in the triode region.
Similarly, current operation is independent of when operates in the saturation region, and operates in the triode region.
Step 9 Of 11
Consider that mosfet and are in the saturation region. Then, the current relation can be written from equation (3) for the CMOS inverter.
Hence, the current operation is independent of when and are in the saturation region.
Step 10 Of 11
From the circuit of Figure 17.31(b), the values , the device is off. The value of exists at and remains constant till
reaches the threshold voltage . At the point when , the device enters into the saturation region, and is in the triode region.
Thereafter, the voltage starts drop to the minimum value.
Step 11 Of 11
When mosfets enter into the triode region, is in the saturation region, the output is settled at the minimum voltage value of . The
further increase in causes to keep in cut off region and then the output voltage gets zero.
Thus, the sketch for versus for Figure 17.31(a) and (b) are drawn as shown in Figure 1 and Figure 2.
Question:
The circuits of Fig. 18.27 have been fabricated without a threshold-adjust implant. Sketch Vout versus Vin
and compare the results to the target case.
Figure 18.27
Step 1 Of 4
Consider the circuit in Figure 17.31 is fabricated without a threshold-adjust implant.
The native threshold voltage of NMOS and PMOS transistors is normally far from the desired value, therefore imposing a threshold-adjust
implant. The native thresholds of both the transistors are generally with more negative value than the desired value.
Example:
The threshold voltage for NMOS is approximately 0 V and for PMOS is approximately . That is, without threshold-adjust implant
and .
During the threshold-adjust implant, performs the growth of the gate oxide and forms a thin sheet of dopants close to the surface, and allows the
threshold voltages of PMOS transistor and NMOS transistor are more positive.
Step 2 Of 4
Consider the drain-drain voltage .
Consider the expression of for without threshold-adjust implant.
Consider as a different values.
Step 3 Of 4
Assume the target values as shown.
Consider the expression of for target case.

Step 4 Of 4
From Figure 1, for the input voltage is , and for the target value of the input voltage is . For the low
threshold voltage high output voltage results. Low threshold voltage is an optimal requirement, so that output in increases. In adjusting the threshold
voltage value of the transistors threshold-adjust implant is used.
Thus, plot for versus is sketched and the results were compared with the target values.
Question:
Due to a layout error, the circuit shown in Fig. 18.28 suffers from contact spiking in one of the junctions.
Identify the faulty junction if (a) the voltage gain is higher than expected, (b) the output voltage is near VDD.
Figure 18.28
Step 1 Of 2
(a)
Redraw the Figure 17.32 in the textbook as shown in Figure 1.
In Figure 1, consider if the voltage gain value is larger than the expected value, then the source of mosfet is spiked to the substrate and the
source resistance is shorted.
Thus, for the higher voltage gain, the faulty junction is .
Step 2 Of 2
(b)
In Figure 1, consider if the output voltage is close to the drain-drain voltage value, then the drain of mosfet is spiked to its n-well. As
the output voltage varies, so the width of the depletion region changes and hence the value of the resistor changes.
Thus, for the output voltage close to the drain-drain voltage, the faulty junction is .
Question:
An NMOS cascode current source used in a large circuit exhibits a substantially lower output impedance
than expected. Determine which fabrication error may have led to this effect: (a) channeling during S/D
implant, (b) omission of the channel-stop implant, or (c) insufficient gate-oxide growth.
Step 1 Of 3
Figure 1 shows a NMOS cascode current source.
(a)
Channeling during source/drain implant will leads to formation of deep junctions and intensifying DIBL (drain-induced barrier lowering). However,
this effect is significant as far the output impedance is concerned, which is slightly lower than the expected value.
Step 2 Of 3
(b)
By considering no channel-stop implant, it may cause to an unrelated high-voltage line passing over the field oxide between the transistors and
produces a channel between the transistors.
Figure 2 shows a parasitic channel between the transistors.
Step 3 Of 3
(c)
Insufficient gate oxide growth normally does not lower the output impedance of the circuit.
Hence, from the explanation, during channeling of S/D implant, the output impedance will be slightly lower.
Thus, the NMOS cascode current source exhibits lower impedance value than the expected value while the process of (a) channeling during S/D
implant.
Question:
An NMOS cascode current source has a zero output current. If a single (small) lithography misalignment
has caused this error, determine in which fabrication step(s) this may have occurred.
Step 1 Of 2
Figure 1 shows a NMOS cascode currrent source circuit.
In a cascade current source, the zero output current is primarily due to the contact misalignment, and a small lithography misalignment will simply
create one junction slightly narrower than the other junction.
Step 2 Of 2
Figure 2 shows a junction narrower than the other junction.
Even if misalignment occurs only of a minor fraction of the minimum channel length, it can lead to an appearance in gap between the source or drain
and the gate area, and it forbids the formation of continuous channel in the MOS transistors.
Thus, the zero output current is due to the contact misalignment.
Question:
A differential pair using an active current mirror as load suffers from a low small-signal voltage gain. If the
bias current is equal to the target value, determine which fabrication error may have led to this effect: (a)
heavy n-well implantation, (b) heavy threshold-adjust implantation, or (c) long gate oxidation cycle.
Step 1 Of 2
Figure 1 shows a MOSFET differential pair with an active current mirror as the load.
Step 2 Of 2
Consider the circuit with a low small-signal voltage gain. During the process of long gate oxidation cycle of the circuit, the bias current value will be
equal to the target value, due to the fabrication error.
Consider the expression for small-signal voltage gain of the circuit.
Here, is the transconductance and are the output resistances.
In the circuit, the transconductance is lesser than the expected value, and the output resistances decrease or remain constant, as the oxide
thickness increases . The oxide thickness determines the current handling and reliability of the MOS transistors. The others,
heavy n-well implementation and heavy threshold-adjust implantation are mainly used to adjust the threshold voltage.
Thus, the bias current is equal to the target value during the process of (c) long gate oxidation cycle.
Question:
The switched-capacitor amplifier of Fig. 18.29 exhibits a large gain error. If the bias current of the op amp
is equal to the desired value, which fabrication error is likely to have happened: (a) heavy threshold-adjust
implantation, (b) very heavy doping in the bottom plate of C1 (placed at node P), or (c) channeling during the
S/D implantation?
Figure 18.29
Step 1 Of 2
Refer to Figure 17. 33 in the textbook shows a switched-capacitor amplifier.
The circuit in Figure 17.33 exhibits a large gain error.
Consider if the bottom plate of the capacitor is heavily doped, then the oxide growth will be faster in capacitor . As a result, it leads to a
smaller value of . If the op-amp input capacitance is taken into account, then a smaller value of capacitance will lead to a high gain error.
Step 2 Of 2
Heavy threshold adjust implantation and channeling during S/D implantation are used in adjusting the channel resistance and thereby junction
capacitance and threshold voltages.
Thus, the bias current of the op amp is equal to the desired value when (b) very heavy doping occurs in the bottom plate of the capacitor .
Question:
In Fig. 18.30, the digital circuit draws large transient currents from VDD. Without M1, the inductor Lb
would sustain a large transient voltage Lbd IDD/dt. Transistor M1 with W/L = 100/0.5 is added to suppress
this effect.
Figure 18.30
(a) Calculate the equivalent series resistance of M1.
(b) Calculate the maximum value of Lb that results in a critically-damped response at node X.
Model the digital circuit by a transient current source.
Step 1 Of 8
(a)
The modified circuit of Figure 17.34 as shown in Figure 1.
Step 2 Of 8
Substitute for .
…… (1)
Step 3 Of 8
Consider the expression for the transconductance of NMOS transistor .
…… (2)
Here, is the mobility of electron, is the gate-source voltage, is the threshold voltage, is the gate oxide capacitance per unit area,W
is the width, and is the length.
Refer to Figure 1, consider the expression for the transconductance.
Here, is the equivalent series resistance of the transistor in ON state. In the ON state of , the gate to source voltage is equal to supply
voltage .
Step 4 Of 8
…… (3)
Substitute for , 0.7 V for , for , for , and for in equation (3).
Thus, the equivalent series resistance of the NMOS transistor is .
Step 5 Of 8
(b)
Refer to Figure 1, consider the expression for the capacitance of the capacitor of the NMOS transistor .
…… (4)
Here, is the overlap capacitance.

Refer to Figure 1, consider the expression for the overlap capacitance.
Here, is the gate-drain overlap capacitance per unit width.
Step 6 Of 8
Step 7 Of 8
Refer to Figure 1, consider the expression for critically-damped response of the circuit at node Xwith relationship of , , and .
Here, is the inductance of the inductor and is the capacitance of the capacitor of the NMOS transistor .
Step 8 Of 8
Therefore, the maximum value of inductor in a critically damped response of the circuit at node X is less than or equal to .
Thus, the maximum value of the inductor is and the digital circuit is modelled by a transient current source as shown in Figure 1.
Question:
In the circuit of Fig. 18.23, Vb = 1.2 V, N = 32, and (W/L)1−N = 20/0.5. Determine the maximum value of r
for a maximum current mismatch of 1%.
Figure 18.23 Effect of ground resistance in a D/A converter.
Step 1 Of 4
Consider the expression for a maximum current mismatch.
…… (1)
Here, is the transconductance, N is the number of current sources and r is the resistance, and is the mismatch.
…… (2)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the gate width, L is the gate length, is the gate
In Figure 17.27 (a), the base voltage is the gate source voltage , which is 1.2 V. That is, .
Step 2 Of 4
Refer to Table 2.1 in the textbook for the term , which is , for the term , which is and for the term , which is
0.7 V.
…… (3)
…… (4)

Step 3 Of 4
Substitute for , for , for , 1.2 V for and 0.7 V for in equation (2).
Step 4 Of 4
Substitute for , 0.01 for and 32 for N in equation (1.)
Thus, for a maximum current mismatch of 1% the maximum value of ris .

Question:
Suppose that in Eq. (18.11), t = 1 μm and h = 3 μm. For what value of W are the parallel-plate and fringe
capacitances equal? What if h = 5 μm?
Step 1 Of 3
Consider the expression for total wire capacitance per unit length of a substrate.
…… (1)
Here, W, t and h are the dimensions.
In equation (1), consider the parallel-plate capacitance is proportional to and the rest of the terms determine the fringe capacitance.
Consider the expression to determine when the parallel-plate capacitance and fringe capacitance are equal.
…… (2)
Step 2 Of 3
Consider when .
Substitute 3 for h and 1 for t in equation (2).
On solving the equation,

Here, consider the maximum value .
Thus, for , the parallel-plate and fringe capacitance are equal for the value of .
Step 3 Of 3
Consider when .
Substitute 5 for h and 1 for t in equation (2).
On solving the equation,
Here, consider the maximum value .
Thus, for , the parallel-plate and fringe capacitance are equal for the value of .
Question:
In Fig. 19.3, polysilicon has a sheet resistance of 30 Ω/□ (before silicidation) and metal 1 a sheet resistance
of 80 m Ω/□. What is the ratio of the resistivities of the two materials?
Figure 19.3 Widths and thicknesses of poly and metal lines.
Step 1 Of 3
Consider the expression to calculate the sheet resistance of the material.
Here, is the resistivity of the material and is the thickness of the material.
…… (1)
Step 2 Of 3
Rearrange the equation (1) for the resistivity of the polysilicon.
Rearrange the equation (1) for the resistivity of the metal.
Step 3 Of 3
Consider the expression to calculate the ratio of the resistivities of the polysilicon and metal.

Thus, the value of ratio of the resistivities of two materials is .
Question:
A MOSFET with W/L = 100 μm/0.5 μm undergoes ideal scaling by a factor of two. What happens to the
sheet resistivity and the total resistance of the gate?
Step 1 Of 3
A MOSFET with the aspect ratio is and the layout of the MOSFET is drawn as Figure 1.
Step 2 Of 3
Consider the expression of the aspect ratio when it undergoes a scaling factor.
Here, is the width, is the length and is the scaling factor.
The scaled MOSFET layout is drawn as Figure 2.

Refer to Figure 2, since the length and width of the layout is scaled by a factor , therefore the thickness is also scaled by the factor that is,
Step 3 Of 3
Consider the expression to calculate the resistance of the wire.
Here, is the sheet resistance of the wire.

From the expression, the sheet resistance is directly proportional to the aspect ratio of the MOSFET and the number of squares used to represent
the layout before and after scaling is also constant. Therefore, both the sheet resistance and total gate resistance increases by the factor of 2.
Thus, the sheet resistivity and the total resistance of the gate .
Question:
A cascode structure uses W/L = 100 μm/0.5 μm for both the input device and the cascode device. If the sheet
resistance of polysilicon is 5 Ω/□ and the maximum tolerable gate resistance 10 Ω, draw the layout of the
structure while minimizing the drain junction capacitances.
Step 1 Of 3
The cascode structure includes the input device and the cascode device, both with the width of and the length of .
For the gate resistance, it is considered that each device consists of number of fingers therefore, the width for each device is .
Step 2 Of 3
Consider the expression to calculate the total resistance of the gate.
Here, is the sheet resistance of the polysilicon, is the width, is the length and is the number of fingers in the layout.
Step 3 Of 3
Now, using the Figure 18.13 (c) in the textbook, the layout obtained while minimizing the drain junction capacitance is drawn as Figure 1.
Thus, the layout of the structure while minimizing the drain junction capacitance is drawn.
Question:
In Fig. 19.7, explain what happens to the differential amplifier if each of the design rules A1–A8 is violated.
Figure 19.7 Layout of a differential pair with PMOS current-source loads.
Step 1 Of 1
Refer to Figure 18.7 in the textbook for the layout of the differential pair with the PMOS current source loads.
A small subset of design rules governs the layout of the NMOS differential pair with the current source loads. The changes occur to the differential
amplifier if the used devices violate the designed rules.
(i) If Active-Active spacing violates the designed rule, then a finite resistance appears between the drains and degrades the voltage
gain.
(ii) If Metal width violates the designed rule, then a large resistance may be generated in the source in series form and introduces unwanted
degeneration or the input-referred offset.
(iii) If Metal-Metal spacing violates the designed rule, then the gate terminal of the NMOS current source that is located in the bottom is
shortened with its respective source.
(iv) If Enclosure of contact by active violates the designed rule, then a certain part of the contact hole falls on FOX and increases the contact
resistance, which tends to cause referred offsets or the source degeneration.
(v) If Poly-Active spacing violates the designed rule, that is, if the poly is contacted too close with the active area, then the active area is
damaged during the etching process of the poly contact area and therefore, the transistor operation becomes poor.
(vi) If Active-Well spacing violates the designed rule, then the latch up process may occur for the differential amplifier.
(vii) If Enclosure of active by well violates the designed rule, then the latch up process may occur for the differential amplifier.
(viii) If Poly-Poly spacing violates the designed rule, then a finite resistance appears between the gates of the input transistors.
Thus, the changes occur in the differential amplifier when the rules violation is explained.
Question:
The input differential pair of an amplifier is to be laid out as in Fig. 19.19, but with each half device (e.g.,
1/2M1) using four gate fingers. What is the minimum number of interconnect layers required here?
Figure 19.19 Common-centroid layout.
Step 1 Of 1
Refer to Figure 18.19 in the textbook for the layout of the common centroid.
A small subset of design rules governs the layout of the NMOS differential pair with the current source loads. Interconnects are used for routing
purposes and as per the principle, two layers of interconnects are highly sufficient for routing purpose.
However, for a reasonable symmetry, inter-connect resistance and area, four layers of interconnects are used and the layout of the differential pair
is drawn as shown below in Figure 1.
Thus, the minimum number of interconnect layers required is .
Question:
Large integrated circuits may suffer from significant temperature gradients. Compare the performance of
the circuits shown in Figs. 19.23 and 19.24 in such an environment.
Figure 19.23 Distribution of a reference voltage for current mirror biasing.
Figure 19.24 Distribution of current to reduce the effect of interconnect resistance.
Step 1 Of 2
Temperature gradients in a large circuit lead to rise appreciable mismatches and cause errors or mismatch in the output of the differential amplifier.
Refer to Figure 18.21 in the textbook for the distribution of a reference voltage for a current mirror biasing.
If the Figure 18.21 suffers from temperature gradients, it leads to produce a threshold and mobility mismatch between device and each of
the device . Due to these mismatches, the output current suffers from additional mismatches.
Step 2 Of 2
Refer to Figure 18.22 in the textbook for the distribution of current to reduce the effect of the interconnect resistance. The circuit illustrates that it is
used to route the reference current to the vicinity of the building blocks in order to perform the current mirror operation.
If the Figure 18.22 suffers from temperature gradients, it leads to cause much less effects because devices and are quite close to
their mirrors.
Thus, the performance of the circuits in Figure 18.21 and Figure 18.22 under temperature gradients is explained.
Question:
Suppose polysilicon with silicide block has a sheet resistance of 60 Ω/□ and a parallel-plate capacitance of
100 aF/μm2 to the substrate. Also, assume that these parameters are respectively equal to 2 k Ω/□ and 1,000
aF/μm2 for the n-well. Determine which material should be used to construct a 500- Ωresistor if matching
considerations require a minimum poly width of 3 μm and a minimum n-well length of 6 μm. Neglect fringe
capacitances.
Step 1 Of 4
For polysilicon:
Consider the expression to calculate the resistance of the polysilicon.
Here, is the length, is the width and is the sheet resistance of the wire.
Step 2 Of 4
For n-well:
Consider the expression to calculate the resistance.

Step 3 Of 4
Consider the expression to calculate the area capacitance of the polysilicon.
Here, is the parallel-plate capacitance.
Step 4 Of 4
Consider the expression to calculate the area capacitance of the n-well.
Therefore, for the polysilicon, the capacitance is and for the n-well, the capacitance is .
From the calculated values, the polysilicon has the minimum capacitance.
Thus, the polysilicon structure must be used to construct a resistor.

Question:
Using the data in Table 18.1, calculate C and CP for each structure in Fig. 19.35 and identify the one with
minimum CP /C. Neglect fringe capacitances.
Figure 19.35 Capacitor structures using various conductive layers.
Table 18.1 Minimum widths and capacitances of interconnects in a 0.25-μm technology.
Step 1 Of 9
The value for the capacitances between the consecutive metal layers is considered on the order of and the value of the capacitance
between the metal 1 and the polysilicon is .
Refer to Figure 18.33 (a), (b) and (c) in the textbook, the capacitances , and is located between the metal layers, therefore the value is
considered as . That is,
Refer to Figure 18.33 (d) in the textbook, the capacitance is located between the metal 1 and the polysilicon, therefore the value is considered
as . That is,
Step 2 Of 9
Consider the expression to calculate the interplate capacitance.
Substitute for .
The bottom plate parasitic capacitance is placed in the metal 3.

Refer to Table 17.1 in the textbook for the bottom place capacitance value in metal 3. Therefore,
Step 3 Of 9
Substitute for and for to calculate the ratio .
Step 4 Of 9

Step 5 Of 9
Step 6 Of 9

Step 7 Of 9

Step 8 Of 9
The bottom plate parasitic capacitance is placed in the polysilicon.

Refer to Table 17.1 in the textbook for the bottom place capacitance value in Poly. Therefore,
Step 9 Of 9
Therefore, the ratio value from Figure 18.33 (a) is , from Figure 18.33 (b) is , from Figure 18.33 (c) is and from Figure
18.33 (d) is .
From the calculated values, the Figure 18.33 (b) has the minimum ratio value.
Thus, the value of the interplate capacitance and bottom plate parasitic capacitance for Figure 18.33 (a) is , for
Figure 18.33 (b) is , for Figure 18.33 (c) is , for Figure 18.33 (d) is
respectively and the Figure 18.33 (b) is the one with minimum value.
Question:
A metal 4 wire with a length of 1,000 μm and width of 1 μm is driven by a source impedance of 500 Ω. Using
the data in Table 18.1 and assuming a sheet resistance of 40 m Ω/□, calculate the delay through the wire
and compare the result with the lumped time constant obtained by multiplying the source impedance by the
total wire capacitance.
Table 18.1 Minimum widths and capacitances of interconnects in a 0.25-μm technology.
Step 1 Of 6
Consider the expression to calculate the total resistance of the wire.
Here, is the sheet resistance of the wire, is the length of the wire and is the width of the wire.
Step 2 Of 6
Consider the expression to calculate the area capacitance.
Here, is the bottom-plate capacitance.

Refer to Table 17.1 in the textbook for the value of the bottom-plate capacitance in metal 4.

Step 3 Of 6
Consider the expression to calculate the fringing capacitance.
Here, is the fringe capacitance.

Refer to Table 17.1 in the textbook for the value of the fringe capacitance in metal 4.
Step 4 Of 6
Consider the expression to calculate the total capacitance.
Step 5 Of 6
Consider the expression to calculate the wire propagation delay.
Step 6 Of 6
Consider the expression to calculate the lumped time constant.
Here, is the source impedance.

Thus, the value of the delay through the wire is , the value of the lumped time constant is and from the comparison
of the results, the propagation delay through the wire is very less, therefore it is negligible.
Question:
Repeat Problem 19.9 if the width of the wire is increased to 2 μm.
Step 1 Of 6
Here, is the sheet resistance of the wire, is the length of the wire and is the width of the wire.
Step 2 Of 6
Here, is the bottom-plate capacitance.

Refer to Table 17.1 in the textbook for the value of the bottom-plate capacitance in metal 4.
Step 3 Of 6

Refer to Table 17.1 in the textbook for the value of the fringe capacitance in metal 4.

Step 4 Of 6
Step 5 Of 6
Step 6 Of 6
Consider the expression to calculate the lumped time constant.
Here, is the source impedance.
Thus, the value of the delay through the wire is , the value of the lumped time constant is and from the comparison
of the results, the propagation delay through the wire is very less, therefore it is negligible.
Question:
An interconnect having a length of 1,000 μm is required in a circuit. Using the data in Table 15.1 and
assuming that the sheet resistance of metals 1–3 is 80 m Ω/□ and that of metal 4 is 40 m Ω/□, determine
which metal layer must be used to obtain the minimum delay.
Step 1 Of 17
Metal 1:
…… (1)
Here, is the length of the wire, is the width of the wire and is the bottom-plate capacitance.
Refer to Table 17.1 in the textbook for the minimum width , bottom-plate capacitance and fringe capacitance in metal 1.
Step 2 Of 17
…… (2)
Step 3 Of 17
…… (3)

Step 4 Of 17
…… (4)
Step 5 Of 17
…… (5)
Step 6 Of 17
Metal 2:
Refer to Table 17.1 in the textbook for the values of , and in metal 2.
Step 7 Of 17

Step 8 Of 17
Step 9 Of 17
Step 10 Of 17
Metal 3:
Step 11 Of 17

Step 12 Of 17
Step 13 Of 17
Step 14 Of 17
Metal 4:
Step 15 Of 17

Step 16 Of 17
Step 17 Of 17
Therefore,
For the metal 1, the delay through the wire is .
For the metal 2, the delay through the wire is .
For the metal 3, the delay through the wire is and, for the metal 4, the delay through the wire is .
From the calculated values, the metal 4 has the minimum propagation delay.
Thus, the metal 4 must be used to obtain the minimum delay value.
Question:
Some new technologies use copper for interconnects because its resistivity is about half that of aluminum.
Repeat Problem 19.11 with copper interconnects.
Step 1 Of 18
Metal 1:
…… (1)
Here, is the length of the wire, is the width of the wire and is the bottom-plate capacitance.
Refer to Table 17.1 in the textbook for the minimum width , bottom-plate capacitance and fringe capacitance in metal 1.
Step 2 Of 18
…… (2)
Step 3 Of 18
…… (3)

Step 4 Of 18
Consider the expression to calculate the sheet resistance of the material.
Here, is the resistivity of the material and is the thickness of the material.
From the expression of , the sheet resistance of the material is directly proportional to the resistivity of the material.
The resistivity of the copper is about half of the resistivity of aluminum .

Therefore, the sheet resistance used for the copper interconnect is also half of the sheet resistance used in aluminum. Hence, for metal 1-3, the
sheet resistance is and for metal 4, the sheet resistance is .
Step 5 Of 18
…… (4)
Step 6 Of 18
…… (5)
Step 7 Of 18
Metal 2:

Step 8 Of 18
Step 9 Of 18
Step 10 Of 18
Step 11 Of 18
Metal 3:

Step 12 Of 18
Step 13 Of 18
Step 14 Of 18
Step 15 Of 18
Metal 4:

Step 16 Of 18
Step 17 Of 18
Step 18 Of 18
Therefore, for the metal 1, the delay through the wire is , for the metal 2, the delay through the wire is , for the metal 3, the delay
through the wire is and for the metal 4, the delay through the wire is .
From the calculated values, the metal 4 has the minimum propagation delay.
Thus, the metal 4 must be used to obtain the minimum delay value.
Question:
In the circuit of Fig. 19.53(a), (W/L)1 = 100/0.5 and ID1 = 1 mA. If the substrate noise, Vsub, has a peak-to-
peak amplitude of 50 mV, what is the effect referred to the gate of M1?
Figure 19.53 (a) Mixed-signal circuit including the effect of substrate coupling; (b) side view of device layout;
(c) signal waveforms.
Step 1 Of 5
Refer to Figure 18.50 (a) in the textbook, the device is NMOS.
Consider the expression to calculate transconductance for the NMOS device .
…… (1)
Here, is the mobility of electrons, is the gate oxide capacitance per unit area, W is the channel width,L is the channel length and is the
drain current.
Substitute for .

Step 2 Of 5
Step 3 Of 5
Consider the expression to calculate bulk transconductance for the NMOS device .
…… (2)
Refer to Table 2.1 in the textbook for the values of and in NMOS model. For device , .

Step 4 Of 5
Refer to Figure 18.50 (a), the voltage produces the drain current of . Therefore, the effect of the gate for device can be
calculated as follows,
Step 5 Of 5
Consider the expression to calculate the input referred noise.
Here, is the peak to peak amplitude.
Thus, the effect of the gate for device is and the value of the input referred noise is .
Question:
Suppose two bond wires are placed 5 mm above ground with a center-to-center spacing of 1 mm.
(a) What is the total mutual inductance if each wire is 4 mm long?
(b) If one wire carries a 100-MHz sinusoidal current with a peak amplitude of 1 mA, what is the
voltage induced across the other wire?
Step 1 Of 2
(a)
Two bond wires are placed above the ground and the center to center spacing of the two wires is . This geometry setup of wires is
drawn as Figure 1.
Consider the expression to calculate the mutual inductance of the two wires.
…… (1)
Here, is the distance of the wires from the ground and is the center-to-center spacing of two wires.
From Figure 1, each wire is long, therefore rewrite the equation (1) with the length of wire.
Here, is the length of the wire.

Thus, the value of the mutual inductance of the wires is .
Step 2 Of 2
(b)
Consider the expression to calculate the voltage across the mutual inductance of wires.
…… (2)
Rearrange the equation (2) for one wire with sinusoidal current and peak amplitude.
Thus, the value of the voltage induced across the other wire is .
Question:
In Problem 14, what center-to-center spacing is required to decrease the induced voltage by a factor of
four?
Step 1 Of 4
From the Problem 18.14 in the textbook, two bond wires are placed above the ground and the center to center spacing of the two wires is
. This geometry setup of wires is drawn as Figure 1.
Consider the expression to calculate the mutual inductance of the two wires.
…… (1)
Here, is the distance of the wires from the ground and is the center-to-center spacing of two wires.
From Figure 1, each wire is long, therefore rewrite the equation (1) with the length of wire.
…… (2)
Here, is the length of the wire.

Step 2 Of 4
Consider the expression to calculate the voltage across the mutual inductance of wires.
…… (3)
It is required to decrease the induced voltage by a factor of four.
Refer to equation (3), the induced voltage is directly proportional to the mutual inductance. If the induced voltage is decreased by the factor 4 then,
the mutual inductance must be decreased by a factor of 4.
The mutual inductance is , if the value is decreased by a factor 4, then the value becomes,
Step 3 Of 4
Take exponential on both sides of the equation.
Step 4 Of 4
Thus, the required value of the center-to-center spacing to decrease the induced voltage by a factor of four is .
Question:
In order to reduce the total bond wire inductance, a package uses 4 supply pads and 4 ground pads.
Suppose the self-inductance of each wire is 4 nH and the mutual inductance between adjacent lines is 2 nH.
Neglecting mutual inductance between nonadjacent lines, calculate the equivalent inductance of the supply
and ground connections if (a) all of the supply wires are placed next to each other and so are the ground
wires, and (b) every supply wire is placed next to a ground wire.
Step 1 Of 5
The self-inductance of each wire is and the mutual inductance between the adjacent lines is .
The setup for the inductance in which all the supply wires are placed next to each other and the ground wires is drawn as Figure 1.
Step 2 Of 5
Refer to Figure 1, the symmetry conditions of the current is expressed as,
…… (1)
…… (2)
…… (3)
…… (4)
…… (5)
Step 3 Of 5
Solving the equations (1), (2), (3), (4) and (5) provides the following values.
and
Step 4 Of 5
Consider the expression to calculate the total current .
Rewrite the equation using the symmetry conditions.

Step 5 Of 5
Consider the expression to calculate the equivalent inductance.
Substitute for .
The equivalent inductance is also same for the condition if every wire is placed next to a ground wire.
Thus, the value of the equivalent inductance for both the cases (a) and (b) is .
Question:
The input bandwidth of high-speed circuits may be limited by the bond wire inductance and the pad
capacitance. Consider two cases: (a) the bond wire diameter is 50 μm and the pad size 100 μm × 100 μm; (b)
the bond wire diameter is 25 μm and the pad size 50 μm × 50 μm. If all other dimensions are constant, which
case is preferable?
Step 1 Of 7
Case (a):
The bond wire diameter is .

Consider the expression to calculate the radius of the wire.
…… (1)
Step 2 Of 7
Consider the expression to calculate the inductance for a round wore above a ground plane.
…… (2)
Here, is the height of the wire from the ground in and is the radius of the wire.
Step 3 Of 7
Consider the expression to calculate the total capacitance for the pad with the size .
Here, is the bottom parallel plate capacitance in .
Step 4 Of 7
Case (b):
The bond wire diameter is .
Step 5 Of 7
Consider the expression to calculate the total capacitance for the pad with the size .
Here, is the bottom parallel plate capacitance.
Step 6 Of 7
Consider the expression to compare the cases (a) and (b) to compute the height of the wire from ground.
Step 7 Of 7

Take exponential on both sides of the equation.
Therefore, the height of the wire from the ground is represented in , hence, the value is,
Thus, for the height value , the case (b) is certainly preferable and for the height value , the case (a) is preferable to
limit the input bandwidth of the high-speed circuits.

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Design of Analog CMOS Integrated Circuits

Solution for Chapter 2 Problem 1P

Consider the general expression for the drain current when .

Substitute for and for in equation (1).

Substitute for in equation (3).

Refer to Table 2.1 in the textbook for the term .

Substitute for and for in equation (4).

Refer to Table 2.1 in the textbook for the terms , , and .

Substitute the unit for in equation (5).

Consider if , then equation (6) becomes .

Substitute 0.8 V for in equation (6).

Draw the plot between and as shown in Figure 2.

Consider the expression for the drain current when or .

Refer to Table 2.1 in the textbook for the terms , , and .

Substitute the unit for in equation (8).

Consider if , then equation (9) becomes .

Substitute 0.9 V for in equation (9).

Figure 4 shows the plot drawn between and .

Consider the general expression for the transconductance .

Substitute for in equation (2).

Refer to Table 2.1 in the textbook for the term .

Substitute for and for in equation (3).

Refer to Table 2.1 in the textbook for the term .

Substitute the unit for in equation (4).

Thus, the transconductance is .

Consider the general expression for the output resistance .

Here, is the channel-length modulation coefficient.

Refer to Table 2.1 in the textbook for the term .

Substitute the unit for in equation (6).

Thus, the output resistance or output impedance is .

Substitute for and for in equation (7).

Refer to Table 2.1 in the textbook for the term .

Substitute the unit for in equation (8).

Thus, the transconductance is .

Substitute the unit for in equation (9).

Substitute for and for in equation (7).

Thus, the intrinsic gain is .

Consider the expression for the transconductance .

Consider the general expression for the output resistance .

is the channel-length modulation coefficient.

Substitute for in equation (2).

Consider for length and modify the equation (6).

Consider the parameter .

Substitute 1 for in equation (7).

Consider for length and modify equation (6).

Consider the parameter .

Substitute 2 for in equation (9).

Consider for length and modify equation (6).

Substitute 3 for in equation (11).

Consider the drain current is .

Substitute 2 for in equation (8).

Substitute 2 for in equation (10).

Figure 1 shows the plot between and with L as a parameter.

Consider the expression for the drain current when .

Consider the expression for the drain current when .

Here, is the drain-source voltage.

Write the expression for threshold voltage with body effect.

Substitute for , for , and for in equation (1).

Equation (2) is valid for .

Simplify the condition to find .

Simplify the condition.

Reduce the condition.

Substitute 0.1 for in equation (2).