Lecture Topic Sub Topic Reference Material

1 Intro to COAL Orientation in CS Slide01-No15-16

Motivation
-Hardware-Agnostic Programming
Intro to Assembly Irv: Ch.1.1 Slide01-No18-27
Course Policies, Grading, Practical Info
2 Number System Data and Instruction representation Irv: Ch. 1.3
Binary, Hexadecimal, Decimal
-Conversion: Integer and FP (dec to bin)
3 Number System Signed Integers irv: Ch.1.3
-Sign Magnitude
-Two's complement
-Bias-N
Binary Addition
4 Number System Binary Arithmetic Irv: Ch.1.3 Slide02
-Subtraction
-Carry and Overflow
Hexadecimal Arithmetic
Character Representation
5 Assembly Basics Assembly as a tool for Learning CO
Intel x86 Architecture Irv: Ch.3.3
x86 Assembly Program Format
-Segments, Directives
-Instruction Format: Label, Mnemoincs, Operands, ComIrv: Ch.3.1 Slide03
6 Assembly Basics Operands
-x86 Address Space/Registers Irv: Ch.2.2
-Data Types Irv: Ch.3.4
-Data Declaration (Direct Addressing)
MOV, ADD, SUB Instructions Irv: Ch.4.1-4.2 Registers: AX, BX, CX, DX
7 Assembly Basics Memory Management Irv: 3.4 Slide06 (can follow all)
 -Little-Endian
-Filling Up Memory
-Operators: PTR, OFFSET, SIZEOF, LENGTHOF, TYPEIrv: Ch.4.3 Registers: DS, CS, EIP
8 Assembly Basics Indirect Addressing / Arrays Irv: Ch.4.4 Slide06 (can follow all)
-Base-Index Registers: SI, DI
-Base-Index-Displacement
-Examples/2D Array Irv: Ch.9.4
9 Assembly Advance Conditional Structures: JMP, LOOP, Jcond, Status FlagsIrv: Ch.4.5, 6.3 Slide05, Registers: EFLAGS
-Example: WHILE Loop Irv: Ch.6.5
10 Assembly Advance Stack and Procedures Irv: Ch.5.1-5.2 Slide08
-PUSH, POP, RET, PUSHA, PULLA, USES Operator Registers: SS, ESP
11 Assembly Advance Parameter Passing Irv: Ch.5.2 Slide08, Register: EBP
Local Variables Irv: Ch. 8.2.5
12 Assembly Advance Sum Up Assembly
13 Intro to Comp Org Introduction to Computer Organization Stl: Ch.1 Slide04-No3-8
Von Neumann Machine Stl: Pg17-21 Slide07
14 Intro to Comp Org Instruction Execution Cycle Stl: Ch.3.2 (full) Slide07 (can follow all)
15 Intro to Comp Org Interrupts Stl: Ch.3.2 (full) Slide07 (can follow all)
16 Computer Arithmet Shift and Rotate (all eight) Irv: Ch.7.1 slide15 (can follow all)
17 Computer Arithmet Shift and Rotate Applications Irv: Ch.7.2 slide15 (can follow all)
18 Computer Arithmet Hardware for Addition and Subtraction Stl: Ch.10.3 (8th Ed: 9.3) Slide16 (can folllow all)
Unsigned Multiplication
19 Computer Arithmet Booths Algorithm Stl: Ch.10.3 (8th Ed: 9.3) Slide16 (can folllow all)
Unsigned Division
20 Computer Arithmet Floating Point Representation Stl: Ch.10.4 (8th Ed.: 9.4), Irv: C Slide17 (can follow all)
-Single Precision
-Double Precision
21 Computer Arithmet FP Arithmetic: Add, Sub, Mul, Div Stl: Ch.10.5
22 FPU FPU: FP Instruction Set, FP Arithmetic Irv: Ch.12.2.4, 12.2.5
23 Instruction Set Addressing Modes Stl: Ch.13.1 (8th Ed.: 11.1) Slide18
24 Instruction Set Instruction Format Stl: Ch.13.3 (8th Ed.: 11.3)
 -General Instruction Elements
-Number of Addresses
-x86 Instruction Format Stl: Ch.13.4 (8th Ed.: 11.4) Slide19
25 Instruction PipelininPipeline Strategy Stl: Ch.14.4: Pg.495-504 (8th Ed.: 12.4)
6 stage Pipeline
Pipeline Hazards
26 Cache Principles of Locality Stl: Ch.4.1-4.3 Slide10, Pattison & Hennessy book
Cache Performance: Hit Rate and Miss Rate
Cache Components: Block, index, Set, Capacity, Tag
Cache Design: Direct Mapped Cache, Valid bit
27 Cache Associative Cache Slide11
-LRU Bits
28 Cache Write Policies Slide12
-Write Back, Write Through, Write Allocate, Write Around
-Dirty bit
29 Cache Cache Examples Slide13
30 Revision Revision