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Memory Hierarchy, Fetch-Execute Cycle. Technology Lab 1/2: Introduction to MIPS Assembly Language Programming (MARS)
Improvements. Introduction to assembly language programming,
Information about the lab
instructions, registers, assembly language statements, directives,
2 MARS tutorial: Editor, Assembler, Debugger
text, data, and stack segments. Defining data, arrays, and strings.
Register and Memory
Memory alignment, byte ordering, and symbol table. System calls,
console input, and output. Introduction to system calls. Hello world program
Lab 3: Integer Arithmetic
Integer storage sizes, review of binary addition and subtraction,
carry and overflow. Integer addition & subtraction
MIPS instruction set architecture, instruction formats, R-type Shift and rotate
3 integer arithmetic, logic, and shift instructions, immediate Bitwise logic instructions
operands, I-type arithmetic and logic instructions, pseudo- Convert character to integer
instructions. Simple loop: e.g. count the number of 1’s in a register.
Tracing program execution and breakpoints
Lab 4: Flow Control and 1D arrays (Quiz 1)
MIPS Integer multiply and divide instructions. Defining data, strings, and arrays
Control flow, branch and jump instructions, translating if-else Viewing variables in memory
4 statements and logical expressions. Compare instructions and 1D-Array traversal
conditional-move instructions. Searching an array
Finding min and max
Generate a sequence of random numbers and save in an array.
Arrays, allocating arrays statically in the data segment and
Lab 5: 2D Arrays and Files
dynamically on the heap, computing the memory addresses of
5 array elements. Indexing 2D arrays
Load and store instructions. Pointers versus indexing
Loops and use of pointers to traverse arrays. Reading a text file
Addressing modes, jump, and branch limits. Application: reading an image from a file and dealing with images
Main memory organization, SRAM vs DRAM storage cells, Lab 15: Project Submission
DRAM refresh cycles, latency and bandwidth, trends in DRAMs,
memory hierarchy, cache memory, and locality of reference. Completing project
14 Cache memory organization: direct-mapped, fully-associative, and Submitting report + presentation
set-associative caches, handling cache miss, write policy, write Presenting work + Demo
buffer, and replacement policy. Questions & answers
Cache performance, memory stall cycles, and average memory Lab 15: Project Submission
15 access time. Introduction to multi-level caches, and multi-level
cache performance. Final Quiz (Quiz 6)