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NAP00 Power On Sequence

XDP_DBRESET#

(From Power Button)

ON/OFFBTN#
(to EC)

D PBTN_OUT# 1.03s D
(From EC to ICH)

SLP_S5# (From ICH to EC) 1.01s

SLP_S3# (From ICH to EC) 90.8us

SYSON (From EC to control +1.5V) 156ms

+1.5V 984us

47.2ms
+V_DDR3_DIMM_REF

SUSP# (From EC to control VS Power) 186ms

DGPU Power Sequence
+3VS_DELAY +5VS 2.6ms
+VGA_CORE
+1.8VSDGPU +3VS 2.87ms

C +1.5VS_DGPU C

DGPU_PWR_EN (From ICH to control DGPU Power) 108ms

+3VS_DELAY 4.52us

+VGA_CORE 940us

ONLY FOR DGPU +1.8VSDGPU 6.9ms

+1.5VS_DGPU 6.98ms

+1.05VSDGPU 980us
(can ramp up anytime)

PEG_RST# 1.2ms

+1.8V 1.33ms

+1.5VS 768us
B B

+0.75VS 15.8us

+VCCP 980us

EN_WOL# 5.26ms

+3V_LAN 500us

VR_ON (From EC to IMVP) 58.8ms

568us
+VCC_CORE

VGATE (From IMVP to ICH & EC) 7.6ms

PM_PWROK (From EC to ICH) 40.7ms

A A
PLT_RST#_BUFF (From ICH to CPU) 1.18ms

H_RESET# (Output from CPU) 1ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2010/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5811P
Date: Tuesday, December 29, 2009 Sheet 58 of 58
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