Scribd Logo
Upload

Welcome to Scribd!

  • Quanta DA0QU8MB6G1 Lenovo ThinkCentre A70z 5

    Uploaded by

    ougeyf
    15 views1 page
    1. The document outlines the power on sequence for a device, showing the order that various voltage rails and control signals are activated. 2. It begins with always-on rails being powered from the battery, followed by activation of the RTC voltage and reset signal. 3. Subsequent stages involve powering additional rails from the EC or other modules, with minimum timing delays between steps. 4. A table also shows which voltage rails are powered during different system sleep states from S0 to S5.

    Original Description:

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    1. The document outlines the power on sequence for a device, showing the order that various voltage rails and control signals are activated. 2. It begins with always-on rails being powered from the battery, followed by activation of the RTC voltage and reset signal. 3. Subsequent stages involve powering additional rails from the EC or other modules, with minimum timing delays between steps. 4. A table also shows which voltage rails are powered during different system sleep states from S0 to S5.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    15 views1 page

    Quanta DA0QU8MB6G1 Lenovo ThinkCentre A70z 5

    Uploaded by

    ougeyf
    1. The document outlines the power on sequence for a device, showing the order that various voltage rails and control signals are activated. 2. It begins with always-on rails being powered from the battery, followed by activation of the RTC voltage and reset signal. 3. Subsequent stages involve powering additional rails from the EC or other modules, with minimum timing delays between steps. 4. A table also shows which voltage rails are powered during different system sleep states from S0 to S5.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    8 7 6 5 4 3 2 1

    power on Sequence
    SLP_M#, M3 ON
    D D

    +P5V_ALWAYS/+P3V3_ALWAYS
    From battery
    9ms
    RTC_VDD
    SLP_S4_N 30us,min
    From battery
    FM_RTCRST_N
    SLP_S3_N

    SLP_M# could come up as early as before SLP_S4#/SLP_S5#


    +P5V_ALWAYS ICH_SLP_M# or as late as SLP_S3#,but no later.

    +P1P05V_ME(VccME,VccLAN)
    +P3V3_ALWAYS
    From EC to Power Bottom
    +VCC3_ME
    PWRBTSW#
    From EC PCH_MEPWROK_R/LAN_PWROK
    500us,min
    S5_PWRON
    SPI FLASH
    +P5V_S5/+P3V3_S5
    From EC to PCH
    10ms
    PCH_REMRST_N
    From PCH to EC
    C

    SLP_S4_N
    VGA_IN C

    From PCH to EC
    30us,min
    SLP_S3_N
    From PCH VGA_PRESENT
    30us,min
    ICH_SLP_M
    From EC
    EC_Panel_ON
    +VCC3_ME/+P1P05V_ME
    From EC to DDR power module +P12V_monitor
    SUSON
    +P5V_monitor
    P5V_DDR_S3/+DDR1V5_S3 30us,min

    From EC +P3V_monitor
    MAINON

    +P12V_S0/+P5V_S0/+P3V3_S0
    +P1V05_PCH_S0/CPU_VTT_S0+
    +VCC1_8_PCH_S0 From NCP5380 Voltage Rails
    Power Voltage S0~S2 S3 S4 S5 Ctl Signal
    V_AXG_S0 5V
    +P5V_ALWAYS V V V V
    B
    From VTT power module to CPU B
    3.3V V V V V
    +P3V3_ALWAYS
    H_VTTPWRGD
    +P5V_S5 5V V V V V S5_PWRON
    3.3V V V S5_PWRON
    From Vcore power module to CPU +P3V3_S5
    VCORE_S0 +VCC3_ME 3V V V ME_G
    +P1P05V_ME 1.05V V V ICH_SLP_M
    P5V_DDR_S3 5V V SUSD/MAINON
    From Vcore power module to CLK,PCH
    VRMPWRGD(PCH_SYSPWROK/CKPWRGD) +DDR1V5_S3 1.5V V SUSD/MAINON
    +P12V_S0 12V V MAINON
    99ms From EC to PCH +P5V_S0 5V V MAINON
    SIO_PWRGD_3V/PWRGD_3V +P3V3_S0 3.3V V MAINON
    +VCC1_8_PCH_S0 1.8V V MAINON
    From PCH P15V 15V V MAINON
    1ms
    +P1V05_PCH_S0 1.05V V MAINON
    PCH_MEPWROK_R/LAN_PWROK CPU_VTT_S0+ 1.1V MAIN0N
    V
    V_AXG_S0
    1ms From PCH to CPU 1.1 V CPU_VTT_S0+
    VCORE_S0 1.1 H_VTTPWRGD
    H_DRAMPWRGD
    V
    +P12V_monitor 12V EC_Panel_ON
    V
    +P5V_monitor EC_Panel_ON
    5V V
    From PCH to CPU
    100ms +P3V_monitor EC_Panel_ON
    3V V
    H_PWRGD
    From PCH to TPM
    SUS_TAT_N 1ms

    A
    From PCH A

    60us
    PLTRST_N

    Quanta Computer Inc.


    PROJECT : QU8
    Size Document Number Rev
    D
    Power Diagram
    Date: Monday, January 25, 2010 Sheet 5 of 37
    8 7 6 5 4 3 2 1

    You might also like