Scribd Logo
Upload

Welcome to Scribd!

  • Quanta Y01 Shark Bay Power Sequence

    Uploaded by

    Joselo López
    24 views1 page
    This document outlines the power on sequence from G3 to S0 for an Intel Shark Bay ULT system. It shows the order of events, including enabling various power rails through ICs, asserting signals between the EC, PCH and CPU, and establishing the CPU SVID bus. Key steps include the EC enabling the 3V/5V and SUS rails, the PCH asserting reset and power good signals to the EC and CPU, and the CPU powering on and driving its SVID bus. The full power on sequence takes between 5-99 milliseconds to complete.

    Original Description:

    Original Title

    Quanta Y01 shark bay power sequence

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document outlines the power on sequence from G3 to S0 for an Intel Shark Bay ULT system. It shows the order of events, including enabling various power rails through ICs, asserting signals between the EC, PCH and CPU, and establishing the CPU SVID bus. Key steps include the EC enabling the 3V/5V and SUS rails, the PCH asserting reset and power good signals to the EC and CPU, and the CPU powering on and driving its SVID bus. The full power on sequence takes between 5-99 milliseconds to complete.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    24 views1 page

    Quanta Y01 Shark Bay Power Sequence

    Uploaded by

    Joselo López
    This document outlines the power on sequence from G3 to S0 for an Intel Shark Bay ULT system. It shows the order of events, including enabling various power rails through ICs, asserting signals between the EC, PCH and CPU, and establishing the CPU SVID bus. Key steps include the EC enabling the 3V/5V and SUS rails, the PCH asserting reset and power good signals to the EC and CPU, and the CPU powering on and driving its SVID bus. The full power on sequence takes between 5-99 milliseconds to complete.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    5 4 3 2 1

    A23 - Intel Shark Bay ULT mainly Power On Sequence(G3 to S0) 01


    From Coin Cell BAT PP3300_RTC
    D D
    From AC,BATT VIN
    3V/5V (TPS51225RUKR) PP3300_DSW EC assert PP3300_DSW_EN to 3V/5V (TPS51225RUKR)

    EC to PCH PCH_DPWROK 10ms

    EC to PCH For a non-DeepSx system DPWROK and RSMRST# go


    PCH_RSMRST_L high at the same time (connected on board)
    PCH to EC PCH_SLP_SUS_L

    From PW On Button to EC PWR_BTN_L


    EC to PCH PCH_PWRBTN_L Minimum duration of PCH_PWRBTN_L assertion = 16 mS.
    PCH_PWRBTN_L can assert before or after PCH_RSMRST_L
    C PCH to EC PCH_SLP_S5_L C

    PCH to EC PCH_SLP_S3_L 60uS

    SUSON Power Rail PP3300_PCH_SUS PCH_SLP_S5_L enable TPS22930

    SUSON Power Rail PP1050_PCH_SUS EC assert SUSP_VR_EN to AOZ1237QI

    VDDQ PP1350 EC assert PP1350_EN to TPS51216RUKR

    VDDQ Power GOOD PP1350_PGOOD 100nS Power IC to EC

    MainOn Power Rail PP1050_PCH PCH_SLP_S3_L enable TPS22964

    MainOn Power Rail PP3300_PCH PCH_SLP_S3_L enable TPS22930


    B
    MainOn Power Rail PP1500_PCH_TS PCH_SLP_S3_L enable APW8824CTI B

    EC to PCH PCH_PWROK 1mS PCH_PWROK and APWROK are strapped together

    EC to CPU VCCST_PWRGD PCH_PWROK to CPU via power buffer

    CPU to Power IC VRON_CPU


    CPU Core Power +VCCIN
    Power IC to CPU VCORE_PGOOD
    EC to PCH SYS_PWROK 5~99mS

    CPU SVID BUS CPU SVID BUS CPU drives SVID


    A A
    PCH Assert PLTRST# PLTRST#
    Quanta Computer Inc.
    PROJECT : A23
    Size Document Number Rev
    1A
    Power Sequence
    Date: Monday, April 29, 2013 Sheet 1 of 1
    5 4 3 2 1

    You might also like