EE6P051: Power Electronics System Simulation Laboratory Instructor:

Autumn 2022-23 Dr. Olive Ray

olive@iitbbs.ac.in

Experiment #08
Aim: Generating Pulse Width Modulation signal using Verilog.
Prerequisite: Install Icarus (iverilog-v11-20200824-x64_setup) from
the following link: http://bleyer.org/icarus/ and GTKWave viewer
from the link: http://gtkwave.sourceforge.net/
Problem Statement:
Implement
(a) Step-up and step-down counters using verilog.
(b) Developing pulse width modulated signal using carrier
comparison scheme
Lab objectives:
The following activities will be tested in the laboratory:
1. Design the logic diagram for step-up and step-down counter using
digital circuits.
2. Design the verilog code for implementation of both the counters.
3. Implement PWM control using carrier comparison method and
observe the behavior.
The specifications of the counter are: frequency = 100 kHz,
number of bits: 4, PWM output should be capable to modulating
duty ration between 0.2 to 0.7.
Observations:
1. How do you set the value of carrier frequency with respect to the
clock signal?
2. Show the change in PWM output with respect to the change in
duty cycle reference.
 EE6P051: Power Electronics System Simulation Laboratory Instructor:
Autumn 2022-23 Dr. Olive Ray
olive@iitbbs.ac.in

Report:
1. Show the truth table and logic diagram for both the step-up and step-
down counters.
2. What changes you need to do in order to increase the number of bits
of counter to 5.
3. Provide the simuation output waveforms for all the digital circuits.

Further information: Schematic of four-bit ripple counter using D-

flip flops
 EE6P051: Power Electronics System Simulation Laboratory Instructor:
Autumn 2022-23 Dr. Olive Ray
olive@iitbbs.ac.in

Verilog code for implementation of ripple counter