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A B C D E F G H

PG301 A02
Comanche 192b GDDR5, <150W, 2-way SLI
1 1

Tall DVI-I + DP + DP + DP/HDMI + DP


TABLE OF CONTENTS
Page Description Page Description

1 Table of Contents 26 PS: NVVDD Phase 1,2


2 Block Diagram 27 PS: NVVDD Phase 3,4
3 PCI Express 28 [RESERVED]
4 MEMORY: GPU Partition A/B 29 PS: NVVDD OVR2+1 option
5 MEMORY: FBA[31:0] 30 PS: Inputs, Filtering, and Monitoring
2 2

6 MEMORY: FBA[63:32] 31 PS: Sequence and Shutdown


7 MEMORY: FBB[31:0] 32 LEDs
8 MEMORY: FBB[63:32] 33 PS: IOVDD Regulator
9 MEMORY: GPU Partition C 34 MECH: Bracket/Thermal
10 MEMORY: FBC[31:0]
11 MEMORY: FBC[63:32] V320-2.0 change item:
12 GPU PWR and GND Page15:DVI add esd

13 GPU Decoupling Page18:remove DP colay

14 DACA Interface Page20:HDMI add esd

15 IFPAB DVI-I-DL Page21:4pin housing colay 6pin housing


3 3

16 IFPEF with IFPE DP Page25:NVVDD enable phase4

17 IFPF DP Page27:Add phase4

18 IFPC HDMI/DP Page29:remove colay NVVDD power solution

19 IFPD DP Page30: 12V input bead change to choke


6pin power con colay 8pin con
20 MIOA remove 0603 MLCC colay

21 MISC1: Fan, Thermal, JTAG, GPIO Page32:stuff logo LED

22 MISC2: ROM, XTAL, Straps


23 PS: 5V, PEX_VDD, VID_PLL
24 PS: FBVDD/Q
25 PS: NVVDD Controller OVR4 option
4 4

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
Custom 01_Table of Contents 2.0
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. Date: Tuesday, November 18, 2014 Sheet 1 of 34

A B C D E F G H
A B C D E F G H

Block Diagram

1 Power Supply 1
EXT_12V 2x3 PWR 1
NVVDD-PH4
(NORTH)
Power Supply
NVVDD-PH3

Power Supply
NVVDD-PH2

SLI/ Power Supply


NVVDD-PH1
DP

2
QD:FRAME LOCK 2

MEM C MEM C MEM B


LO HI LO
HDMI/

MEM B
DP

HI Power Supply
5V Linear
3 3

Power Supply
MEM A
DP

FBVDD/FBVDDQ
LO
PEX_12V Finger

MEM A
DVI-I

HI
DP

4
QD:STEREO PEX_VDD
4

LDO

QUADRO OPTIONS SHOWN IN YELLOW


and prefix "QD:"

VID_PLL
PEX_3V3 Finger
LDO

5 5

Fan

MICRO-STAR INT'L CO.,LTD


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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
Custom 01_Table of Contents 2.0
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. Date: Monday, November 17, 2014 Sheet 2 of 34

A B C D E F G H
A B C D E F G H

PCI Express NV3V3


3V3_F
12V @logic.u_buf_3_state(sym_10):page3_i876
NONPHY-X16 1R688 0ohm
2 JTAG_TRST*
21 SC70_5

5
OUT
0402 COMMON COMMON
CN2

1
1R724 0ohm
2 JTAG_TCLK
21
VCC 12V NET VOLTAGE MAX_CURRENT MIN_WIDTH
CON_X16 OUT OE
0402 COMMON
COMMON
1R118 0ohm
2 1R704 0ohm
2 JTAG_TDI
3 21
PEX_RST* 2 A Y 4 PEX_RST_BUF* 3V3
3,20,32
12V 12V 5.5A 0.500
@electro_mechanic.con_pci_express(sym_1):page3_i662 OUT IN OUT
0402 0402 COMMON
COMMON 1R705 0ohm
2 JTAG_TDO
21
3V3 3.3V 3.0A 0.500
OUT GND
B1 B9 PEX_TRST* 0402 COMMON
+12V TRST* JTAG1
B2 +12V TCLK JTAG2 A5 PEX_TCLK 1R706 0ohm
2 JTAG_TMS
21
GND 0V 8.5A 0.400

3
OUT
1 A2 A6 PEX_TDI 0402 COMMON 1
+12V TDI JTAG3
3V3 A3 A7 PEX_TDO NV3V3
+12V TDO JTAG4
B3 A8 PEX_TMS GND
+12V/RSVD TMS JTAG5
GND
B8 +3V3

G
1

5
C817 C822 A9 1 0ohm
2
4.7uF 0.1uF +3V3
A10 Q518A Q518B 0402 COMMON

D
+3V3

S
6.3V 16V R1642 R1643
@discrete.q_fet_n_enh(sym_2):page3_i897 @discrete.q_fet_n_enh(sym_2):page3_i898
20% 10% 100k 100k
X5R X7R B10 +3V3AUX COMMON COMMON
2

2
5% 5% 5%
0603 0402 SOT363 SOT363

4
0402 0402 0402
COMMON COMMON U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
COMMON COMMON DNI
PEX_PRSNT* A1 PRSNT1 SMCLK B5 PEX_SMCLK 1R162 0ohm
2 I2CS_SCL
21BGA1428
OUT
B17 B6 PEX_SMDAT 0402 DNI 1 0ohm
2 I2CS_SDA
PRSNT2 SMDAT OUT 21G1A
0402 DNI
@digital.u_gpu_gb2b_192(sym_1):page3_i864
GND BGA1428 GND
COMMON
B12 RSVD
1/18 PCI_EXPRESS
PEX_VDD
B4 GND WAKE B11
A4 GND BA15 PEX_WAKE
B7 GND PEX_IOVDD AP29
A12 A11 PEX_RST* PEX_RST_BUF* BB19 AP30
GND PERST 3 3,20,32 PEX_RST PEX_IOVDD

1
OUT IN C762 C743 C741 C751 C132
B13 GND PEX_IOVDD AR27
1uF 4.7uF 22uF 22uF 22uF nv_res nv_res
A15 GND BB18 PEX_CLKREQ PEX_IOVDD AR28
6.3V 6.3V 6.3V 6.3V 6.3V
B16 GND PEX_IOVDD AR29
10% 20% 20% 20% 20%
B18 A13 PEX_REFCLK AW17 R1668 R1670
GND REFCLK PEX_REFCLK PEXGEN3_SIGNALS PEX_REFCLK X5R X5R X5R X5R X5R

2
A18 A14 PEX_REFCLK* AY17 0402 0603 0805 0805 0805 0ohm 0ohm
GND REFCLK PEX_REFCLK PEXGEN3_SIGNALS PEX_REFCLK
COMMON COMMON COMMON COMMON COMMON 0.05 ohm
0.05 ohm
A16 PEX_TXX0 C804
1 0.22uF
2 PEX_TX0 AU19 0805 0805
PERP0 PEX_TXX0 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX0
A17 PEX_TXX0* 0402 6.3V C801
1 0.22uF
2 PEX_TX0* AV19 AP17 COMMON COMMON
PERN0 PEX_TXX0 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX0 PEX_IOVDDQ
2 10% 0402 6.3V 10% AP18 2
GND COMMON COMMON PEX_IOVDDQ
PEX_RX0 X5R X5R
PETP0 B14 PEX_RX0 PEXGEN3_SIGNALS BA19 PEX_RX0 PEX_IOVDDQ AP19 GND
B15 PEX_RX0* AY19 AP20
END OF X1 PETN0 PEX_RX0 PEXGEN3_SIGNALS PEX_RX0 PEX_IOVDDQ
PEX_IOVDDQ AP21
B31 PRSNT2 PERP1 A21 PEX_TXX1 PEXGEN3_SIGNALS
C795
1 0.22uF
2 PEX_TX1 PEXGEN3_SIGNALS AW20 PEX_TX1 PEX_IOVDDQ AP22 GPU_PEX_IOVDDQ 0.400
A19 A22 PEX_TXX1* 0402 6.3V C790
1 0.22uF
2 PEX_TX1* AV20 AP23
RSVD PERN1 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX1 PEX_IOVDDQ
B30 10% 0402 6.3V 10% AP24
RSVD COMMON COMMON PEX_IOVDDQ

1
A32 B19 PEX_RX1 X5R X5R
AY21 AP25 C723 C724 C722 C732 nv_res

1
RSVD PETP1 PEX_RX1 PEXGEN3_SIGNALS PEX_RX1 PEX_IOVDDQ 1uF 1uF 0.1uF 0.1uF C721
B20 PEX_RX1* BA21 AP26 1uF
PETN1 PEX_RX1 PEXGEN3_SIGNALS PEX_RX1 PEX_IOVDDQ 6.3V 6.3V 16V 16V
A20 GND PEX_IOVDDQ AP27 6.3V R1669
C787 0.22uF 10% 10% 10% 10%
B21 A25 PEX_TXX2 1 2 PEX_TX2 AV21 AP28 10% 0ohm
GND PERP2 PEX_TXX2 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX2 PEX_IOVDDQ X5R X5R X7R X7R

2
B22 A26 PEX_TXX2* C783
1 0.22uF
2 PEX_TX2* AU21 AR19 X5R

2
GND PERN2 PEX_TXX2 PEXGEN3_SIGNALS 0402 6.3V PEXGEN3_SIGNALS PEX_TX2 PEX_IOVDDQ 0402 0402 0402 0402 0.05 ohm
0402
A23 GND COMMON
10% 0402 6.3V 10%
COMMON PEX_IOVDDQ AR20 COMMON COMMON COMMON COMMON
COMMON
0805
PEX_RX2 X5R X5R COMMON
A24 GND PETP2 B23 PEX_RX2 PEXGEN3_SIGNALS BB21 PEX_RX2 PEX_IOVDDQ AR21
B25 B24 PEX_RX2* BB22 AR22
GND PETN2 PEX_RX2 PEXGEN3_SIGNALS PEX_RX2 PEX_IOVDDQ
B26 GND PEX_IOVDDQ AR23
A27 A29 PEX_TXX3 C779
1 0.22uF
2 PEX_TX3 AU22 AR24 IOVDD
GND PERP3 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX3 PEX_IOVDDQ
A28 A30 PEX_TXX3* 0402 6.3V C777
1 0.22uF
2 PEX_TX3* AV22 AR25
GND PERN3 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX3 PEX_IOVDDQ GND
B29 GND COMMON
10% 0402 6.3V 10%
COMMON PEX_IOVDDQ AR26
PEX_RX3 X5R X5R
A31 GND PETP3 B27 PEX_RX3 PEXGEN3_SIGNALS BA22 PEX_RX3
B32 B28 PEX_RX3* AY22
GND END OF X4 PETN3 PEX_RX3 PEXGEN3_SIGNALS PEX_RX3

A35 PEX_TXX4 C769


1 0.22uF
2 PEX_TX4 AV23
PERP4 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX4
A36 PEX_TXX4* 0402 6.3V C767
1 0.22uF
2 PEX_TX4* AW23
PERN4 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX4
B48 10% 0402 6.3V 10%
GND PRSNT2 COMMON COMMON
PEX_RX4 X5R X5R
A33 RSVD PETP4 B33 PEX_RX4 PEXGEN3_SIGNALS AY24 PEX_RX4
PEX_RX4* PEX_VDD
PETN4 B34 PEX_RX4 PEXGEN3_SIGNALS BA24 PEX_RX4
A34 GND
B35 A39 PEX_TXX5 C782
1 0.22uF
2 PEX_TX5 AV24 IOVDD
GND PERP5 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX5
B36 A40 PEX_TXX5* 0402 6.3V C781
1 0.22uF
2 PEX_TX5* AU24
GND PERN5 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX5

1
3 A37 10% 0402 6.3V 10% AT22 C137 C133 C136 C750 3
GND COMMON X5R X5R COMMON PEX_PLL_HVDD 4.7uF 22uF 22uF 22uF
A38 B37 PEX_RX5 BB24
GND PETP5 PEX_RX5 PEXGEN3_SIGNALS PEX_RX5 6.3V 6.3V 6.3V 6.3V
B39 B38 PEX_RX5* BB25 AT28
GND PETN5 PEX_RX5 PEXGEN3_SIGNALS PEX_RX5 PEX_SVDD_3V3 20% 20% 20% 20%
B40 GND X5R X5R X5R X5R

2
A41 A43 PEX_TXX6 C780
1 0.22uF
2 PEX_TX6 AU25 0603 0805 0805 0805
GND PERP6 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX6

1
A42 A44 PEX_TXX6* 0402 6.3V C778
1 0.22uF
2 PEX_TX6* AV25 C672 C729 C679 COMMON COMMON COMMON COMMON
GND PERN6 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX6 0.1uF 4.7uF 4.7uF
B43 10% 0402 6.3V 10%
GND COMMON X5R X5R COMMON 16V 6.3V 6.3V
B44 B41 PEX_RX6 BA25
GND PETP6 PEX_RX6 PEXGEN3_SIGNALS PEX_RX6 10% 20% 20%
A45 B42 PEX_RX6* AY25
GND PETN6 PEX_RX6 PEXGEN3_SIGNALS PEX_RX6 X7R X5R X5R

2
A46 GND 0402 0603 0603
PEX_TXX7 C776 0.22uF PEX_TX7 GND
B47 GND PERP7 A47 PEX_TXX7 PEXGEN3_SIGNALS 1 2 PEXGEN3_SIGNALS AW26 PEX_TX7 COMMON COMMON COMMON
B49 A48 PEX_TXX7* 0402 6.3V C771
1 0.22uF
2 PEX_TX7* AV26
GND PERN7 PEX_TXX7 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX7
A49 GND COMMON
10% 0402 6.3V 10%
COMMON
PEX_RX7 X5R X5R
PETP7 B45 PEX_RX7 PEXGEN3_SIGNALS AY27 PEX_RX7
B46 PEX_RX7* BA27
PETN7 PEX_RX7 PEXGEN3_SIGNALS PEX_RX7
END OF X8
GND
A52 PEX_TXX8 C770
1 0.22uF
2 PEX_TX8 AV27
GND PERP8 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX8
A53 PEX_TXX8* 0402 6.3V C768
1 0.22uF
2 PEX_TX8* AU27
PERN8 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX8
B81 PRSNT2 COMMON
10% 0402 6.3V 10%
COMMON
PEX_RX8 X5R X5R NVVDD_SENSE
A50 RSVD PETP8 B50 PEX_RX8 PEXGEN3_SIGNALS BB27 PEX_RX8 NVVDD_SENSE AT42 25
OUT
B82 B51 PEX_RX8* BB28
RSVD PETN8 PEX_RX8 PEXGEN3_SIGNALS PEX_RX8
AT41 GND_SENSE
GND_SENSE OUT 25
A56 PEX_TXX9 C766
1 0.22uF
2 PEX_TX9 AU28
PERP9 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX9
A57 PEX_TXX9* 0402 6.3V C765
1 0.22uF
2 PEX_TX9* AV28
PERN9 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX9
A51 10% 0402 6.3V 10%
GND COMMON X5R X5R COMMON
B52 B54 PEX_RX9 BA28
GND PETP9 PEX_RX9 PEXGEN3_SIGNALS PEX_RX9
B53 B55 PEX_RX9* AY28
GND PETN9 PEX_RX9 PEXGEN3_SIGNALS PEX_RX9
A54 GND
A55 A60 PEX_TXX10 C684
1 0.22uF
2 PEX_TX10 AW29
GND PERP10 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX10
B56 A61 PEX_TXX10* 0402 6.3V C678
1 0.22uF
2 PEX_TX10* AV29
GND PERN10 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX10
4 B57 GND COMMON
10% 0402 6.3V 10%
COMMON
4
PEX_RX10 X5R X5R
A58 GND PETP10 B58 PEX_RX10 PEXGEN3_SIGNALS AY30 PEX_RX10
A59 B59 PEX_RX10* BA30
GND PETN10 PEX_RX10 PEXGEN3_SIGNALS PEX_RX10
B60 GND
B61 A64 PEX_TXX11 C659
1 0.22uF
2 PEX_TX11 AV30
GND PERP11 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX11
A62 A65 PEX_TXX11* 0402 6.3V C652
1 0.22uF
2 PEX_TX11* AU30
GND PERN11 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX11
A63 10% 0402 6.3V 10%
GND COMMON X5R X5R COMMON
B64 B62 PEX_RX11 BB30 PEX_VDD IOVDD
GND PETP11 PEX_RX11 PEXGEN3_SIGNALS PEX_RX11 R635
B65 B63 PEX_RX11* BB31
GND PETN11 PEX_RX11 PEXGEN3_SIGNALS PEX_RX11 200ohm
A66 BB36 PEX_PLL_CLK_OUT
GND PEX_TSTCLK_OUT PEX_PLL_CLK PEXGEN3_SIGNALS
A67 A68 PEX_TXX12 C639
1 0.22uF
2 PEX_TX12 AU31 BA36 PEX_PLL_CLK_OUT* 5% R664 R663
GND PERP12 PEX_TXX12 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX12 PEX_TSTCLK_OUT PEX_PLL_CLK PEXGEN3_SIGNALS 0402 0ohm 0ohm
B68 A69 PEX_TXX12* 0402 6.3V C632
1 0.22uF
2 PEX_TX12* AV31
GND PERN12 PEX_TXX12 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX12 COMMON
B69 GND COMMON
10% 0402 6.3V 10%
COMMON 0402 0402
PEX_RX12 X5R X5R
A70 GND PETP12 B66 PEX_RX12 PEXGEN3_SIGNALS BA31 PEX_RX12 COMMON COMMON
A71 B67 PEX_RX12* AY31
GND PETN12 PEX_RX12 PEXGEN3_SIGNALS PEX_RX12
B72 GND
B73 GND PERP13 A72 PEX_TXX13
PEX_TXX13 PEXGEN3_SIGNALS
C609
1 0.22uF
2 PEX_TX13
PEXGEN3_SIGNALS AW32 PEX_TX13 PEX_PLLVDD AT25 PEX_PLLVDD
A74 A73 PEX_TXX13* 0402 6.3V C601
1 0.22uF
2 PEX_TX13* AV32
GND PERN13 PEX_TXX13 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX13

1
A75 10% 0402 6.3V 10% C759 C731 C761
GND COMMON X5R X5R COMMON 0.1uF 1uF 4.7uF
B76 B70 PEX_RX13 AY33
GND PETP13 PEX_RX13 PEXGEN3_SIGNALS PEX_RX13 16V 6.3V 6.3V
B77 B71 PEX_RX13* BA33
GND PETN13 PEX_RX13 PEXGEN3_SIGNALS PEX_RX13 10% 10% 20%
A78 GND X7R X5R X5R

2
A79 A76 PEX_TXX14 C584
1 0.22uF
2 PEX_TX14 AV33 0402 0402 0603
GND PERP14 PEX_TXX14 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX14
B80 A77 PEX_TXX14* 0402 6.3V C581
1 0.22uF
2 PEX_TX14* AU33 AT21 GPU_TESTMODE 1R637 10k 2 COMMON COMMON COMMON
GND PERN14 PEX_TXX14 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX14 TESTMODE
A82 10% 0402 6.3V 10% 0402 COMMON
GND 5%
COMMON X5R X5R COMMON
B74 PEX_RX14 BB33
PETP14 PEX_RX14 PEXGEN3_SIGNALS PEX_RX14
B75 PEX_RX14* BB34
PETN14 PEX_RX14 PEXGEN3_SIGNALS PEX_RX14
GND
A80 PEX_TXX15 C574
1 0.22uF
2 PEX_TX15 AU34
GND PERP15 PEX_TXX15 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX15 GND
A81 PEX_TXX15* 0402 6.3V C570
1 0.22uF
2 PEX_TX15* AV34
PERN15 PEX_TXX15 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TX15
5 10% 0402 6.3V 10% 5
COMMON X5R X5R COMMON
PETP15 B78 PEX_RX15
PEX_RX15 PEXGEN3_SIGNALS BA34 PEX_RX15 PEX_TERMP AW35 PEX_TERMP 1R629 2.49k
2
B79 PEX_RX15* AY34 0402 1% COMMON
PETN15 PEX_RX15 PEXGEN3_SIGNALS PEX_RX15
END OF X16
GM206-300-A1

GND

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 3 of 34
A B C D E F G H
A B C D E F G H

MEMORY: GPU Partition A/B

1 U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 1
G1B G1C
@digital.u_gpu_gb2b_192(sym_2):page4_i1905 @digital.u_gpu_gb2b_192(sym_3):page4_i1906
BGA1428 BGA1428
COMMON COMMON

2/18 FBA 3/18 FBB

FBA_D<0> H38 W38 FBA_CMD<0> FBB_D<0> F15 D24 FBB_CMD<0>


Fba_D<0> 0 FBA_D0 FBA_CMD0 0 FBA_CMD<0> Fbb_D<0> 0 FBB_D0 FBB_CMD0 0 Fbb_Cmd<0>
FBA_D<1> J39 W37 FBA_CMD<1> FBB_D<1> D15 E24 FBB_CMD<1>
FBA_D1 FBA_CMD1 FBB_D1 FBB_CMD1
Fba_D<1>
Fba_D<2>
1
2
FBA_D<2> J38 FBA_D2 FBA_CMD2 Y40 FBA_CMD<2>
1
2
FBA_CMD<1>
FBA_CMD<2>
GDDR5_BGA170_MIRROR Fbb_D<1>
Fbb_D<2>
1
2
FBB_D<2> E15 FBB_D2 FBB_CMD2 F24 FBB_CMD<2>
1
2
Fbb_Cmd<1>
Fbb_Cmd<2>
FBA_D<3> J37 Y38 FBA_CMD<3> FBB_D<3> G15 H24 FBB_CMD<3>
Fba_D<3> 3 FBA_D3 FBA_CMD3 3 FBA_CMD<3> Fbb_D<3> 3 FBB_D3 FBB_CMD3 3 Fbb_Cmd<3>
FBA_D<4> L36 AC40 FBA_CMD<4> FBB_D<4> E16 C24 FBB_CMD<4>
Fba_D<4> 4 FBA_D4 FBA_CMD4 4 FBA_CMD<4> Fbb_D<4> 4 FBB_D4 FBB_CMD4 4 Fbb_Cmd<4>
FBA_D<5> 0..31 32..63 FBB_D<5>
K38 FBA_D5 FBA_CMD5 Y36 FBA_CMD<5> D16 FBB_D5 FBB_CMD5 A25 FBB_CMD<5>
Fba_D<5> 5
FBA_D<6>
5 FBA_CMD<5> Fbb_D<5> 5
FBB_D<6> 5 Fbb_Cmd<5>
M39 FBA_D6 FBA_CMD6 V36 FBA_CMD<6> CMD0 CS* D18 FBB_D6 FBB_CMD6 B25 FBB_CMD<6>
Fba_D<6> 6
FBA_D<7>
6 FBA_CMD<6> Fbb_D<6> 6
FBB_D<7>
6 Fbb_Cmd<6>
K39 FBA_D7 FBA_CMD7 W42 FBA_CMD<7> E18 FBB_D7 FBB_CMD7 C25 FBB_CMD<7>
Fba_D<7> 7
FBA_D<8>
7 FBA_CMD<7> CMD1 A3_BA3 Fbb_D<7> 7
FBB_D<8> 7 Fbb_Cmd<7>
M42 FBA_D8 FBA_CMD8 W41 FBA_CMD<8> C18 FBB_D8 FBB_CMD8 D25 FBB_CMD<8>
Fba_D<8> 8
FBA_D<9>
8 FBA_CMD<8> Fbb_D<8> 8
FBB_D<9> 8 Fbb_Cmd<8>
L40 FBA_D9 FBA_CMD9 W40 FBA_CMD<9> CMD2 A2_BA0 C17 FBB_D9 FBB_CMD9 G24 FBB_CMD<9>
Fba_D<9> 9
FBA_D<10>
9 FBA_CMD<9> Fbb_D<9> 9
FBB_D<10> 9 Fbb_Cmd<9>
M41 FBA_D10 FBA_CMD10 V35 FBA_CMD<10>
CMD3 A4_BA2 A18 FBB_D10 FBB_CMD10 F25 FBB_CMD<10>
Fba_D<10> 10
FBA_D<11>
10 FBA_CMD<10> Fbb_D<10> 10
FBB_D<11> 10 Fbb_Cmd<10>
M40 FBA_D11 FBA_CMD11 W39 FBA_CMD<11> B18 FBB_D11 FBB_CMD11 E25 FBB_CMD<11>
Fba_D<11> 11
FBA_D<12>
11 FBA_CMD<11> CMD4 A5_BA1 Fbb_D<11> 11
FBB_D<12>
11 Fbb_Cmd<11>
J42 FBA_D12 FBA_CMD12 V40 FBA_CMD<12> C15 FBB_D12 FBB_CMD12 C26 FBB_CMD<12>
Fba_D<12> 12
FBA_D<13>
12 FBA_CMD<12> Fbb_D<12> 12
FBB_D<13> 12 Fbb_Cmd<12>
J41 FBA_D13 FBA_CMD13 V39 FBA_CMD<13>
CMD5 WE* A15 FBB_D13 FBB_CMD13 C29 FBB_CMD<13>
Fba_D<13> 13
FBA_D<14>
13 FBA_CMD<13> Fbb_D<13> 13
FBB_D<14> 13 Fbb_Cmd<13>
H40 FBA_D14 FBA_CMD14 V38 FBA_CMD<14> C14 FBB_D14 FBB_CMD14 C30 FBB_CMD<14>
Fba_D<14> 14
FBA_D<15>
14 FBA_CMD<14> CMD6 A7_A8 Fbb_D<14> 14
FBB_D<15> 14 Fbb_Cmd<14>
J40 FBA_D15 FBA_CMD15 V37 FBA_CMD<15> B15 FBB_D15 FBB_CMD15 B30 FBB_CMD<15>
Fba_D<15> 15
FBA_D<16>
15 FBA_CMD<15> Fbb_D<15> 15
FBB_D<16> 15 Fbb_Cmd<15>
N40 FBA_D16 FBA_CMD16 AE38 FBA_CMD<16>
CMD7 A6_A11 D19 FBB_D16 FBB_CMD16 B31 FBB_CMD<16>
Fba_D<16> 16
FBA_D<17>
16 FBA_CMD<16> Fbb_D<16> 16
FBB_D<17>
16 Fbb_Cmd<16>
N41 FBA_D17 FBA_CMD17 AE37 FBA_CMD<17> E19 FBB_D17 FBB_CMD17 G26 FBB_CMD<17>
Fba_D<17> 17
FBA_D<18>
17 FBA_CMD<17> CMD8 ABI* Fbb_D<17> 17
FBB_D<18> 17 Fbb_Cmd<17>
N42 FBA_D18 FBA_CMD18 AE36 FBA_CMD<18> F19 FBB_D18 FBB_CMD18 E26 FBB_CMD<18>
Fba_D<18> 18
FBA_D<19>
18 FBA_CMD<18> Fbb_D<18> 18
FBB_D<19> 18 Fbb_Cmd<18>
P40 FBA_D19 FBA_CMD19 AD39 FBA_CMD<19> CMD9 A12_RFU D21 FBB_D19 FBB_CMD19 C31 FBB_CMD<19>
Fba_D<19> 19
FBA_D<20>
19 FBA_CMD<19> Fbb_D<19> 19
FBB_D<20> 19 Fbb_Cmd<19>
T40 FBA_D20 FBA_CMD20 AE35 FBA_CMD<20> G23 FBB_D20 FBB_CMD20 A31 FBB_CMD<20>
Fba_D<20> 20
FBA_D<21>
20 FBA_CMD<20> CMD10 A0_A10 Fbb_D<20> 20
FBB_D<21> 20 Fbb_Cmd<20>
T42 FBA_D21 FBA_CMD21 AD38 FBA_CMD<21> F22 FBB_D21 FBB_CMD21 A30 FBB_CMD<21>
Fba_D<21> 21
FBA_D<22>
21 FBA_CMD<21> CMD11 A1_A9 Fbb_D<21> 21
FBB_D<22>
21 Fbb_Cmd<21>
U40 FBA_D22 FBA_CMD22 AE41 FBA_CMD<22> E22 FBB_D22 FBB_CMD22 G31 FBB_CMD<22>
Fba_D<22> 22
FBA_D<23>
22 FBA_CMD<22> Fbb_D<22> 22
FBB_D<23> 22 Fbb_Cmd<22>
2 T41 FBA_D23 FBA_CMD23 AE42 FBA_CMD<23>
CMD12 RAS* D22 FBB_D23 FBB_CMD23 D30 FBB_CMD<23> 2
Fba_D<23> 23
FBA_D<24>
23 FBA_CMD<23> Fbb_D<23> 23
FBB_D<24> 23 Fbb_Cmd<23>
T38 FBA_D24 FBA_CMD24 AD37 FBA_CMD<24> C23 FBB_D24 FBB_CMD24 F30 FBB_CMD<24>
Fba_D<24> 24
FBA_D<25>
24 FBA_CMD<24> CMD13 RST* Fbb_D<24> 24
FBB_D<25> 24 Fbb_Cmd<24>
T37 FBA_D25 FBA_CMD25 AC38 FBA_CMD<25> B22 FBB_D25 FBB_CMD25 E30 FBB_CMD<25>
Fba_D<25> 25
FBA_D<26>
25 FBA_CMD<25> Fbb_D<25> 25
FBB_D<26> 25 Fbb_Cmd<25>
T39 FBA_D26 FBA_CMD26 AC36 FBA_CMD<26>
CMD14 CKE* C22 FBB_D26 FBB_CMD26 E29 FBB_CMD<26>
Fba_D<26> 26
FBA_D<27>
26 FBA_CMD<26> Fbb_D<26> 26
FBB_D<27>
26 Fbb_Cmd<26>
U36 FBA_D27 FBA_CMD27 W35 FBA_CMD<27> A22 FBB_D27 FBB_CMD27 H25 FBB_CMD<27>
Fba_D<27> 27
FBA_D<28>
27 FBA_CMD<27> CMD15 CAS* Fbb_D<27> 27
FBB_D<28> 27 Fbb_Cmd<27>
P36 FBA_D28 FBA_CMD28 AE40 FBA_CMD<28> B21 FBB_D28 FBB_CMD28 G29 FBB_CMD<28>
Fba_D<28> 28
FBA_D<29>
28 FBA_CMD<28> Fbb_D<28> 28
FBB_D<29> 28 Fbb_Cmd<28>
R39 FBA_D29 FBA_CMD29 AD42 FBA_CMD<29> CMD32 C19 FBB_D29 FBB_CMD29 D31 FBB_CMD<29>
Fba_D<29> 29
FBA_D<30>
29 FBA_CMD<29> Fbb_D<29> 29
FBB_D<30> 29 Fbb_Cmd<29>
R38 FBA_D30 FBA_CMD30 AD41 FBA_CMD<30> A19 FBB_D30 FBB_CMD30 E31 FBB_CMD<30>
Fba_D<30> 30
FBA_D<31>
30 FBA_CMD<30> CMD34 DBG0 DBG0 Fbb_D<30> 30
FBB_D<31> 30 Fbb_Cmd<30>
N39 FBA_D31 FBA_CMD31 AD40 FBA_CMD<31> FBVDDQ B19 FBB_D31 FBB_CMD31 F31 FBB_CMD<31> FBVDDQ
Fba_D<31> 31
FBA_D<32>
31 FBA_CMD<31> Fbb_D<31> 31
FBB_D<32>
31 Fbb_Cmd<31>
AT40 FBA_D32 FBA_CMD32 AE34 CMD16 CS* G41 FBB_D32 FBB_CMD32 H29
Fba_D<32> 32 Fbb_D<32> 32
FBB_D<33>
FBA_D<33> AP39 FBA_D33 FBA_CMD33 AF34 CMD17 A3_BA3 F42 FBB_D33 FBB_CMD33 H26
Fba_D<33> 33 Fbb_D<33> 33
FBA_D<34> AR38 FBA_D34 FBA_CMD34 AC35 FBA_DEBUG0 1R580 60.4ohm
2 FBB_D<34> G42 FBB_D34 FBB_CMD34 H30 FBB_DEBUG0 1R562 60.4ohm
2
Fba_D<34> 34 CMD18 A2_BA0 Fbb_D<34> 34
FBA_D<35> AP38 FBA_D35 FBA_CMD35 AD35 FBA_DEBUG1 0402 1% DNI 1R583 60.4ohm
2 FBB_D<35> F41 FBB_D35 FBB_CMD35 H31 FBB_DEBUG1 0402 1% DNI 1R566 60.4ohm
2
Fba_D<35> 35
FBA_D<36> Fbb_D<35> 35
FBB_D<36>
AN37 FBA_D36 0402 1% DNI CMD19 A4_BA2 C41 FBB_D36 0402 1% DNI
Fba_D<36> 36
FBA_D<37> Fbb_D<36> 36
FBB_D<37>
AL37 FBA_D37 D42 FBB_D37
Fba_D<37> 37
FBA_D<38> CMD20 A5_BA1 Fbb_D<37> 37
FBB_D<38>
AN39 FBA_D38 C39 FBB_D38
Fba_D<38> 38
FBA_D<39> Fbb_D<38> 38
FBB_D<39>
AN38 FBA_D39 CMD21 WE* C40 FBB_D39
Fba_D<39> 39
FBA_D<40> Fbb_D<39> 39
FBB_D<40>
AL40 FBA_D40 G35 FBB_D40
Fba_D<40> 40
FBA_D<41>
CMD22 A7_A8 Fbb_D<40> 40
FBB_D<41>
AL41 FBA_D41 F37 FBB_D41
Fba_D<41> 41
FBA_D<42> CMD23 A6_A11 Fbb_D<41> 41
FBB_D<42>
AL42 FBA_D42 D36 FBB_D42
Fba_D<42> 42
FBA_D<43> Fbb_D<42> 42
FBB_D<43>
AM40 FBA_D43 CMD24 ABI* D37 FBB_D43
Fba_D<43> 43
FBA_D<44> FBA_CLK0 Fbb_D<43> 43
FBB_D<44> FBB_CLK0
AP40 FBA_D44 FBA_CLK0 V41 FB_CLK E37 FBB_D44 FBB_CLK0 B24 FB_CLK
Fba_D<44> 44
FBA_D<45> FBA_CLK0*
OUT CMD25 A12_RFU Fbb_D<44> 44
FBB_D<45> FBB_CLK0*
OUT
AP42 FBA_D45 FBA_CLK0 V42 FB_CLK E39 FBB_D45 FBB_CLK0 A24 FB_CLK
Fba_D<45> 45
FBA_D<46> FBA_CLK1
OUT Fbb_D<45> 45
FBB_D<46> FBB_CLK1
OUT
AR40 FBA_D46 FBA_CLK1 AF40 FB_CLK CMD26 A0_A10 G37 FBB_D46 FBB_CLK1 D32 FB_CLK
Fba_D<46> 46
FBA_D<47> FBA_CLK1*
OUT Fbb_D<46> 46
FBB_D<47> FBB_CLK1*
OUT
AP41 FBA_D47 FBA_CLK1 AF39 FB_CLK F38 FBB_D47 FBB_CLK1 C32 FB_CLK
Fba_D<47> 47
FBA_D<48>
OUT CMD27 A1_A9 Fbb_D<47> 47
FBB_D<48>
OUT
AK37 FBA_D48 A36 FBB_D48
Fba_D<48> 48
FBA_D<49> Fbb_D<48> 48
FBB_D<49>
AK39 FBA_D49 CMD28 RAS* C35 FBB_D49
Fba_D<49> 49
FBA_D<50> Fbb_D<49> 49
FBB_D<50>
AK38 FBA_D50 CMD29 RST* C36 FBB_D50
Fba_D<50> 50
FBA_D<51> Fbb_D<50> 50
FBB_D<51>
AH39 FBA_D51 B36 FBB_D51
Fba_D<51> 51
FBA_D<52> CMD30 CKE* Fbb_D<51> 51
FBB_D<52>
AF36 FBA_D52 A34 FBB_D52
Fba_D<52> 52
FBA_D<53> Fbb_D<52> 52
FBB_D<53>
3 AG37 FBA_D53 CMD31 CAS* A33 FBB_D53 3
Fba_D<53> 53
FBA_D<54> Fbb_D<53> 53
FBB_D<54>
AG39 FBA_D54 C33 FBB_D54
Fba_D<54> 54
FBA_D<55> CMD33 Fbb_D<54> 54
FBB_D<55>
AG38 FBA_D55 B33 FBB_D55
Fba_D<55> 55
FBA_D<56> FBA_WCK01 Fbb_D<55> 55
FBB_D<56> FBB_WCK01
AF38 FBA_D56 FBA_WCK01 M37 FB_WCK CMD35 DBG1 DBG1 F35 FBB_D56 FBB_WCK01 H20 FB_WCK
Fba_D<56> 56
FBA_D<57> FBA_WCK01*
OUT Fbb_D<56> 56
FBB_D<57> FBB_WCK01*
OUT
AG41 FBA_D57 FBA_WCK01 M38 FB_WCK G34 FBB_D57 FBB_WCK01 G19 FB_WCK
Fba_D<57> 57
FBA_D<58>
OUT Fbb_D<57> 57
FBB_D<58>
OUT
AG40 FBA_D58 FBA_WCKB01 M36 E36 FBB_D58 FBB_WCKB01 G18
Fba_D<58> 58
FBA_D<59> Fbb_D<58> 58
FBB_D<59>
AG42 FBA_D59 FBA_WCKB01 L35 A37 FBB_D59 FBB_WCKB01 H17
Fba_D<59> 59
FBA_D<60> FBA_WCK23 Fbb_D<59> 59
FBB_D<60> FBB_WCK23
AJ40 FBA_D60 FBA_WCK23 N37 FB_WCK F34 FBB_D60 FBB_WCK23 G17 FB_WCK
Fba_D<60> 60
FBA_D<61> FBA_WCK23*
OUT Fbb_D<60> 60
FBB_D<61> FBB_WCK23*
OUT
AK40 FBA_D61 FBA_WCK23 N38 FB_WCK E33 FBB_D61 FBB_WCK23 F18 FB_WCK
Fba_D<61> 61
FBA_D<62>
OUT Fbb_D<61> 61
FBB_D<62>
OUT
AK42 FBA_D62 FBA_WCKB23 P35 F33 FBB_D62 FBB_WCKB23 G20
Fba_D<62> 62
FBA_D<63> Fbb_D<62> 62
FBB_D<63>
AK41 FBA_D63 FBA_WCKB23 N36 G32 FBB_D63 FBB_WCKB23 G21
Fba_D<63> 63
FBA_WCK45 Fbb_D<63> 63
FBB_WCK45
FBA_WCK45 AK36 FB_WCK FBB_WCK45 C38 FB_WCK
OUT OUT
AJ35 FBA_WCK45* B39 FBB_WCK45*
FBA_WCK45 FB_WCK
OUT FBB_WCK45 FB_WCK
OUT
FBA_DBI<0> K36 AH36 FBB_DBI<0> F16 G36
BI FBA_DQM0 FBA_WCKB45 BI FBB_DQM0 FBB_WCKB45
FBA_DBI<1> K42 AG35 FBB_DBI<1> A16 H35
BI FBA_DQM1 FBA_WCKB45 BI FBB_DQM1 FBB_WCKB45
FBA_DBI<2> R42 AL38 FBA_WCK67 FBB_DBI<2> H22 A39 FBB_WCK67
BI FBA_DQM2 FBA_WCK67 FB_WCK
OUT BI FBB_DQM2 FBB_WCK67 FB_WCK
OUT
FBA_DBI<3> R37 AL39 FBA_WCK67* FBB_DBI<3> A21 B40 FBB_WCK67*
BI FBA_DQM3 FBA_WCK67 FB_WCK
OUT BI FBB_DQM3 FBB_WCK67 FB_WCK
OUT
FBA_DBI<4> AP37 AM35 FBB_DBI<4> D40 H36
BI FBA_DQM4 FBA_WCKB67 BI FBB_DQM4 FBB_WCKB67
FBA_DBI<5> AN42 AL36 FBB_DBI<5> D41 H37
BI FBA_DQM5 FBA_WCKB67 BI FBB_DQM5 FBB_WCKB67
FBA_DBI<6> AJ36 FBB_DBI<6> E34
BI FBA_DQM6 BI FBB_DQM6
FBA_DBI<7> AH42 IOVDD FBB_DBI<7> D34
BI FBA_DQM7 BI FBB_DQM7

FBA_EDC<0> J36 FBB_EDC<0> G16


IN FBA_DQS_WP0 IN FBB_DQS_WP0
FBA_EDC<1> K41 LB501 FBB_EDC<1> B16
IN FBA_DQS_WP1 IN FBB_DQS_WP1
FBA_EDC<2> R41 30ohm FBB_EDC<2> E21
IN FBA_DQS_WP2 IN FBB_DQS_WP2
FBA_EDC<3> T35 FBB_EDC<3> C21
IN FBA_DQS_WP3 COMMON
IN FBB_DQS_WP3
FBA_EDC<4> AN36 FBB_EDC<4> F40
IN FBA_DQS_WP4 BEAD_0603
IN FBB_DQS_WP4
FBA_EDC<5> AN41 FBB_EDC<5> D38
IN FBA_DQS_WP5 IN FBB_DQS_WP5
FBA_EDC<6> AH38 FBB_EDC<6> C34
IN FBA_DQS_WP6 IN FBB_DQS_WP6
4 FBA_EDC<7> AH41 AG34 FB_PLLVDD FBB_EDC<7> B37 H23 FB_PLLVDD 4
IN FBA_DQS_WP7 FBA_PLL_AVDD OUT IN FBB_DQS_WP7 FBB_PLL_AVDD IN
1

1
J35 C593 C633 H15 C704
FBA_DQS_RN0 0.1uF 22uF FBB_DQS_RN0 0.1uF
K40 FBA_DQS_RN1 C16 FBB_DQS_RN1
16V 6.3V 16V
R40 FBA_DQS_RN2 F21 FBB_DQS_RN2
10% 20% 10%
R36 FBA_DQS_RN3 X7R X5R C20 FBB_DQS_RN3 X7R
2

2
AM36 FBA_DQS_RN4 0402 0805 E40 FBB_DQS_RN4 0402
AN40 FBA_DQS_RN5 COMMON COMMON D39 FBB_DQS_RN5 COMMON
AH37 FBA_DQS_RN6 B34 FBB_DQS_RN6
AH40 FBA_DQS_RN7 C37 FBB_DQS_RN7
FBVDDQ FBVDDQ GND
GND

R614 R561 R552 R550


CKE*
10k 10k 10k 10k
CKE*
5% 5% 5% 5%
0402 0402 0402 0402
COMMON COMMON COMMON COMMON
FBA_CMD<30> FBB_CMD<30>
FBA_CMD<14> FBB_CMD<14>

FBA_CMD<29> FBB_CMD<29>
FBA_CMD<13> FBB_CMD<13>

R564 R621 R551 R553


10k 10k 10k 10k
RST* RST*
5% 5% 5% 5%
0402 0402 0402 0402
COMMON COMMON COMMON COMMON

5 5

GND GND

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 4 of 34
A B C D E F G H
A B C D E F G H

MEMORY: FBA Partition 31..0


M2C
@memory.u_mem_sd_ddr5_x32(sym_6):page5_i558
BGA170
COMMON
M2B
@memory.u_mem_sd_ddr5_x32(sym_5):page5_i556
BGA170
Normal FBVDDQ
COMMON J1 MF_VSS/SOE*
add 1k to VSS
FBA_CMD<3> FBA_CMD<12> G3 B10 C10
FBA_CMD<3> 3 RAS VSS VDD
1 FBA_CMD<0> FBA_CMD<15> L3 B5 C5 1
FBA_CMD<0> 0 CAS VSS VDD
FBA_CMD<10> FBA_CMD<5> L12 D10 D11
FBA_CMD<10> 10 WE VSS VDD
FBA_CMD<15> FBA_CMD<0> G12 G10 G1
M2D M2A FBA_CMD<15> 15 CS VSS VDD
G5 VSS VDD G11
@memory.u_mem_sd_ddr5_x32(sym_1):page5_i468 @memory.u_mem_sd_ddr5_x32(sym_3):page5_i507 FBA_CMD<8>
BGA170 BGA170 FBA_CMD<7> J4 ABI H1 VSS VDD G14
FBA_CMD<7> 7
COMMON COMMON H14 VSS VDD G4
FBA_CMD<5> FBA_CMD<10> H4 K1 L1
NORMAL NORMAL FBA_CMD<5> 5 A0_A10 VSS VDD
FBA_CMD<4> FBA_CMD<11> H5 K14 L11
FBA_CMD<4> 4 A1_A9 VSS VDD
FBA_D<0> A4 FBA_D<16> V11 FBA_CMD<13> FBA_CMD<2> H11 L10 L14
4 Fba_D<0> 0 DQ0 4 Fba_D<16> 16 DQ16 FBA_CMD<13> 13 A2_BA0 VSS VDD
FBA_D<1> A2 FBA_D<17> V13 FBA_CMD<14> FBA_CMD<1> H10 L5 L4
4 Fba_D<1> 1 DQ1 4 Fba_D<17> 17 DQ17 FBA_CMD<14> 14 A3_BA3 VSS VDD
FBA_D<2> B4 FBA_D<18> T11 FBA_CMD<12> FBA_CMD<3> K11 P10 P11
4 Fba_D<2> 2 DQ2 4 Fba_D<18> 18 DQ18 FBA_CMD<12> 12 A4_BA2 VSS VDD
FBA_D<3> B2 FBA_D<19> T13 FBA_CMD<11> FBA_CMD<4> K10 T10 R10
4 Fba_D<3> 3 DQ3 4 Fba_D<19> 19 DQ19 FBA_CMD<11> 11 A5_BA1 VSS VDD
FBA_D<4> E4 FBA_D<20> N11 FBA_CMD<8> FBA_CMD<7> K5 T5 R5
4 Fba_D<4> 4 DQ4 4 Fba_D<20> 20 DQ20 FBA_CMD<8> 8 A6_A11 VSS VDD
FBA_D<5> E2 FBA_D<21> N13 FBA_CMD<9> FBA_CMD<6> K4
4 Fba_D<5> 5 DQ5 4 Fba_D<21> 21 DQ21 FBA_CMD<9> 9 A7_A8
FBA_D<6> F4 FBA_D<22> M11 FBA_CMD<6> FBA_CMD<9> J5 A1 B1
4 Fba_D<6> 6 DQ6 4 Fba_D<22> 22 DQ22 FBA_CMD<6> 6 RFU_A12 VSSQ VDDQ
FBA_D<7> F2 FBA_D<23> M13 A12 B12
4 Fba_D<7> 7 DQ7 4 Fba_D<23> 23 DQ23 VSSQ VDDQ
FBA_CMD<2> A14 VSSQ VDDQ B14
FBA_EDC<0> FBA_EDC<2> FBA_CMD<2> 2
4 C2 EDC0 4 R13 EDC2 FBA_CMD<1> A3 VSSQ VDDQ B3
OUT
FBA_DBI<0>
OUT
FBA_DBI<2> FBA_CMD<1> 1
4 D2 DBI0 4 P13 DBI2 C1 VSSQ VDDQ D1
OUT OUT
VREFD A10 VREFD V10 C11 VSSQ VDDQ D12
FBA_CMD<13> J2 C12 D14
RESET VSSQ VDDQ
x32 x16 x32 x16 FBA_CMD<14> J3 C14 D3
CKE VSSQ VDDQ
FBA_D<8> A11 FBA_D<24> V4 C3 E10
4 Fba_D<8> 8 DQ8 NC 4 Fba_D<24> 24 DQ24 NC VSSQ VDDQ
FBA_D<9> A13 FBA_D<25> V2 FBA_CLK0 J12 C4 E5
4 Fba_D<9> 9 DQ9 NC 4 Fba_D<25> 25 DQ25 NC 4 IN CLK VSSQ VDDQ
FBA_D<10> B11 FBA_D<26> T4 FBA_CLK0* J11 E1 F1
4 Fba_D<10> 10 DQ10 NC 4 Fba_D<26> 26 DQ26 NC 4 IN CLK VSSQ VDDQ
FBA_D<11> B13 FBA_D<27> T2 E12 F12
4 Fba_D<11> 11 DQ11 NC 4 Fba_D<27> 27 DQ27 NC VSSQ VDDQ
FBA_D<12> E11 FBA_D<28> N4 E14 F14
4 Fba_D<12> 12 DQ12 NC 4 Fba_D<28> 28 DQ28 NC R563 R565 VSSQ VDDQ
FBA_D<13> E13 FBA_D<29> N2 E3 F3
4 Fba_D<13> 13 DQ13 NC 4 Fba_D<29> 29 DQ29 NC 40.2ohm 40.2ohm VSSQ VDDQ
FBA_D<14> F11 FBA_D<30> M4 F10 G13
4 Fba_D<14> 14 DQ14 NC 4 Fba_D<30> 30 DQ30 NC 1% 1%
VSSQ VDDQ
2 FBA_D<15> F13 FBA_D<31> M2 F5 G2 2
4 Fba_D<15> 15 DQ15 NC 4 Fba_D<31> 31 DQ31 NC 0402 0402 VSSQ VDDQ
COMMON COMMON H13 VSSQ VDDQ H12
FBA_EDC<1> C13 FBA_EDC<3> R2 FBA_CLK0_CM H2 H3
4 OUT EDC1 GND 4 OUT EDC3 NC VSSQ VDDQ
FBA_DBI<1> D13 FBA_DBI<3> P2 K13 K12
4 DBI1 NC 4 DBI3 NC VSSQ VDDQ

1
OUT OUT C578 A5 NC_RFU_A5 K2 VSSQ VDDQ K3
FBA_WCK01 FBA_WCK23 10nF
4 D4 WCK01 4 P4 WCK23 V5 NC_RFU_V5 M10 VSSQ VDDQ L13
IN IN 16V
FBA_WCK01* D5 FBA_WCK23* P5 M5 L2
4 IN WCK01 4 IN WCK23 10% VSSQ VDDQ
X7R N1 VSSQ VDDQ M1

2
0402 N12 VSSQ VDDQ M12
FBVDDQ COMMON N14 VSSQ VDDQ M14
N3 VSSQ VDDQ M3
GND R1 VSSQ VDDQ N10
R659 R11 N5
549ohm VSSQ VDDQ
6 R12 VSSQ VDDQ P1
1% OUT
0402
R14 VSSQ VDDQ P12
COMMON R3 VSSQ VDDQ P14
Use low VGSth part for Pascal FBA_VREFC J14 R4 P3
VREFC VSSQ VDDQ
AO3420 0.350 1.05V 0.140A V1 VSSQ VDDQ T1

1
R181 R658 C573 1R204 121ohm
2 FBA_ZQ_1 J13 V12 T12
1.33k 931ohm 10nF ZQ VSSQ VDDQ
0402 1% COMMON V14 VSSQ VDDQ T14
1% 1% 6.3V
1G1D1S 3 0402 0402
J10 SEN V3 VSSQ VDDQ T3
D 10%
Q515 COMMON COMMON X5R

2
@discrete.q_fet_n_enh(sym_2):page5_i506 0402
SOT23_1G1D1S
7,10,21
GPIO10_FBVREF_SEL 1G COMMON
COMMON
IN
S 2
60V GND GND GND
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W GND
20V

3 GND 3

FBA_VREF_Q
0.350 1.05V

4 4

FBVDDQ
1

C147 C140 C742 C694 C738 C693 C181 C739 C703 C712
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
2

0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
1

C621 C159 C554 C158 C162 C550


1

C176 C173
4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF
47uF 47uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20%
4V 4V GND
20% 20%
X5R X5R X5R X5R X5R X5R
2

X5R X5R
2

0603 0603 0603 0603 0805 0805


0805 0805
COMMON COMMON COMMON COMMON COMMON COMMON
COMMON COMMON

5 5

GND

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 5 of 34
A B C D E F G H
A B C D E F G H

MEMORY: FBA Partition 63..32

1 1

2 2

M503C
M503B @memory.u_mem_sd_ddr5_x32(sym_6):page6_i479
@memory.u_mem_sd_ddr5_x32(sym_5):page6_i477 BGA170
FBA_CMD<19> BGA170
COMMON
FBA_CMD<19> 19
FBA_CMD<16> COMMON FBVDDQ
3 FBA_CMD<16> 16
FBA_CMD<26>
Normal 3
FBA_CMD<26> 26
FBA_CMD<28>
FBA_CMD<31> G3 RAS J1 MF_VSS/SOE*
FBA_CMD<31> 31
FBA_CMD<31> L3 CAS add 1k to VSS
FBA_CMD<23> FBA_CMD<21> L12 B10 C10
M503D M503A FBA_CMD<23> 23 WE VSS VDD
FBA_CMD<16> G12 B5 C5
@memory.u_mem_sd_ddr5_x32(sym_1):page6_i380 @memory.u_mem_sd_ddr5_x32(sym_3):page6_i420
CS VSS VDD
BGA170 BGA170 FBA_CMD<21> D10 VSS VDD D11
FBA_CMD<21> 21
FBA_CMD<24>
COMMON COMMON FBA_CMD<20> J4 ABI G10 VSS VDD G1
FBA_CMD<20> 20
FBA_CMD<29> G5 VSS VDD G11
NORMAL NORMAL FBA_CMD<29> 29
FBA_CMD<30> FBA_CMD<26> H4 H1 G14
FBA_CMD<30> 30 A0_A10 VSS VDD
FBA_D<32> A4 FBA_D<48> V11 FBA_CMD<28> FBA_CMD<27> H5 H14 G4
4 Fba_D<32> 32 DQ0 4 Fba_D<48> 48 DQ16 FBA_CMD<28> 28 A1_A9 VSS VDD
FBA_D<33> A2 FBA_D<49> V13 FBA_CMD<27> FBA_CMD<18> H11 K1 L1
4 Fba_D<33> 33 DQ1 4 Fba_D<49> 49 DQ17 FBA_CMD<27> 27 A2_BA0 VSS VDD
FBA_D<34> B4 FBA_D<50> T11 FBA_CMD<24> FBA_CMD<17> H10 K14 L11
4 Fba_D<34> 34 DQ2 4 Fba_D<50> 50 DQ18 FBA_CMD<24> 24 A3_BA3 VSS VDD
FBA_D<35> B2 FBA_D<51> T13 FBA_CMD<25> FBA_CMD<19> K11 L10 L14
4 Fba_D<35> 35 DQ3 4 Fba_D<51> 51 DQ19 FBA_CMD<25> 25 A4_BA2 VSS VDD
FBA_D<36> E4 FBA_D<52> N11 FBA_CMD<22> FBA_CMD<20> K10 L5 L4
4 Fba_D<36> 36 DQ4 4 Fba_D<52> 52 DQ20 FBA_CMD<22> 22 A5_BA1 VSS VDD
FBA_D<37> E2 FBA_D<53> N13 FBA_CMD<23> K5 P10 P11
4 Fba_D<37> 37 DQ5 4 Fba_D<53> 53 DQ21 A6_A11 VSS VDD
FBA_D<38> F4 FBA_D<54> M11 FBA_CMD<18> FBA_CMD<22> K4 T10 R10
4 Fba_D<38> 38 DQ6 4 Fba_D<54> 54 DQ22 FBA_CMD<18> 18 A7_A8 VSS VDD
FBA_D<39> F2 FBA_D<55> M13 FBA_CMD<17> FBA_CMD<25> J5 T5 R5
4 Fba_D<39> 39 DQ7 4 Fba_D<55> 55 DQ23 FBA_CMD<17> 17 RFU_A12 VSS VDD
FBA_EDC<4> C2 FBA_EDC<6> R13 A1 B1
4 OUT EDC0 4 OUT EDC2 VSSQ VDDQ
FBA_DBI<4> D2 FBA_DBI<6> P13 A12 B12
4 OUT DBI0 4 OUT DBI2 VSSQ VDDQ
VREFD A10 VREFD V10 A14 VSSQ VDDQ B14
A3 VSSQ VDDQ B3
x32 x16 x32 x16 FBA_CMD<29> J2 C1 D1
RESET VSSQ VDDQ
FBA_D<40> A11 FBA_D<56> V4 FBA_CMD<30> J3 C11 D12
4 Fba_D<40> 40 DQ8 NC 4 Fba_D<56> 56 DQ24 NC CKE VSSQ VDDQ
FBA_D<41> A13 FBA_D<57> V2 C12 D14
4 Fba_D<41> 41 DQ9 NC 4 Fba_D<57> 57 DQ25 NC VSSQ VDDQ
FBA_D<42> B11 FBA_D<58> T4 FBA_CLK1 J12 C14 D3
4 Fba_D<42> 42 DQ10 NC 4 Fba_D<58> 58 DQ26 NC 4 IN CLK VSSQ VDDQ
FBA_D<43> B13 FBA_D<59> T2 FBA_CLK1* J11 C3 E10
4 Fba_D<43> 43 DQ11 NC 4 Fba_D<59> 59 DQ27 NC 4 IN CLK VSSQ VDDQ
FBA_D<44> E11 FBA_D<60> N4 C4 E5
4 Fba_D<44> 44 DQ12 NC 4 Fba_D<60> 60 DQ28 NC VSSQ VDDQ
FBA_D<45> E13 FBA_D<61> N2 E1 F1
4 Fba_D<45> 45 DQ13 NC 4 Fba_D<61> 61 DQ29 NC R609 R600 VSSQ VDDQ
FBA_D<46> F11 FBA_D<62> M4 E12 F12
4 4 Fba_D<46> 46 DQ14 NC 4 Fba_D<62> 62 DQ30 NC 40.2ohm 40.2ohm VSSQ VDDQ 4
FBA_D<47> F13 FBA_D<63> M2 E14 F14
4 Fba_D<47> 47 DQ15 NC 4 Fba_D<63> 63 DQ31 NC 1% 1%
VSSQ VDDQ
0402 0402
E3 VSSQ VDDQ F3
FBA_EDC<5> C13 FBA_EDC<7> R2 F10 G13
4 OUT EDC1 GND 4 OUT EDC3 NC COMMON COMMON VSSQ VDDQ
FBA_DBI<5> D13 FBA_DBI<7> P2 FBA_CLK1_CM F5 G2
4 OUT DBI1 NC 4 OUT DBI3 NC VSSQ VDDQ
H13 VSSQ VDDQ H12

1
FBA_WCK45 D4 FBA_WCK67 P4 C726 A5 H2 H3
4 IN WCK01 4 IN WCK23 10nF NC_RFU_A5 VSSQ VDDQ
FBA_WCK45* D5 FBA_WCK67* P5 V5 K13 K12
4 IN WCK01 4 IN WCK23 16V
NC_RFU_V5 VSSQ VDDQ
K2 VSSQ VDDQ K3
10%
X7R M10 VSSQ VDDQ L13

2
0402 M5 VSSQ VDDQ L2
COMMON N1 VSSQ VDDQ M1
N12 VSSQ VDDQ M12
GND N14 VSSQ VDDQ M14
FBVDDQ N3 VSSQ VDDQ M3
R1 VSSQ VDDQ N10
R11 VSSQ VDDQ N5
R12 P1
1

C566 C646 C567 C182 C595 C619 C154 C620 C151 C150 VSSQ VDDQ
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF FBA_VREFC J14 R14 P12
5 IN VREFC VSSQ VDDQ
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V R3 VSSQ VDDQ P14

1
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
C713 1R619 121ohm
2 FBA_ZQ_2_B J13 R4 P3
10nF ZQ VSSQ VDDQ
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R V1 T1
2

0402 1% COMMON VSSQ VDDQ


0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 6.3V
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
J10 SEN V12 VSSQ VDDQ T12
10%
X5R V14 VSSQ VDDQ T14

2
0402 V3 VSSQ VDDQ T3
COMMON
1

C665 C130 C754 C674 C129 C653 C145 C569


4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF 47uF 47uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V GND GND
20% 20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R X5R
2

0603 0603 0603 0603 0805 0805 0805 0805


5 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON 5
GND

GND
MICRO-STAR INT'L CO.,LTD
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
Custom 01_Table of Contents 2.0
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. Date: Monday, November 17, 2014 Sheet 6 of 34

A B C D E F G H
A B C D E F G H
M3C
@memory.u_mem_sd_ddr5_x32(sym_6):page7_i570
BGA170

MEMORY: FBB Partition 31..0 M3B


@memory.u_mem_sd_ddr5_x32(sym_5):page7_i567
COMMON

Normal
BGA170 FBVDDQ
COMMON J1 MF_VSS/SOE*
add 1k to VSS
FBB_CMD<3> FBB_CMD<12> G3 B10 C10
Fbb_Cmd<3> 3 RAS VSS VDD
FBB_CMD<0> FBB_CMD<15> L3 B5 C5
Fbb_Cmd<0> 0 CAS VSS VDD
FBB_CMD<10> FBB_CMD<5> L12 D10 D11
Fbb_Cmd<10> 10 WE VSS VDD
FBB_CMD<15> FBB_CMD<0> G12 G10 G1
M3D M3A Fbb_Cmd<15> 15 CS VSS VDD
G5 VSS VDD G11
@memory.u_mem_sd_ddr5_x32(sym_1):page7_i480 @memory.u_mem_sd_ddr5_x32(sym_3):page7_i519 FBB_CMD<8>
BGA170 BGA170 FBB_CMD<7> J4 ABI H1 VSS VDD G14
Fbb_Cmd<7> 7
COMMON COMMON H14 VSS VDD G4
FBB_CMD<5> FBB_CMD<10> H4 K1 L1
NORMAL NORMAL Fbb_Cmd<5> 5 A0_A10 VSS VDD
1 FBB_CMD<4> FBB_CMD<11> H5 K14 L11 1
Fbb_Cmd<4> 4 A1_A9 VSS VDD
FBB_D<0> A4 FBB_D<16> V11 FBB_CMD<13> FBB_CMD<2> H11 L10 L14
4 Fbb_D<0> DQ0 4 Fbb_D<16> 16 DQ16 Fbb_Cmd<13> 13 A2_BA0 VSS VDD
FBB_D<1> A2 FBB_D<17> V13 FBB_CMD<14> FBB_CMD<1> H10 L5 L4
4 Fbb_D<1> DQ1 4 Fbb_D<17> 17 DQ17 Fbb_Cmd<14> 14 A3_BA3 VSS VDD
FBB_D<2> B4 FBB_D<18> T11 FBB_CMD<12> FBB_CMD<3> K11 P10 P11
4 Fbb_D<2> DQ2 4 Fbb_D<18> 18 DQ18 Fbb_Cmd<12> 12 A4_BA2 VSS VDD
FBB_D<3> B2 FBB_D<19> T13 FBB_CMD<11> FBB_CMD<4> K10 T10 R10
4 Fbb_D<3> DQ3 4 Fbb_D<19> 19 DQ19 Fbb_Cmd<11> 11 A5_BA1 VSS VDD
FBB_D<4> E4 FBB_D<20> N11 FBB_CMD<8> FBB_CMD<7> K5 T5 R5
4 Fbb_D<4> DQ4 4 Fbb_D<20> 20 DQ20 Fbb_Cmd<8> 8 A6_A11 VSS VDD
FBB_D<5> E2 FBB_D<21> N13 FBB_CMD<9> FBB_CMD<6> K4
4 Fbb_D<5> DQ5 4 Fbb_D<21> 21 DQ21 Fbb_Cmd<9> 9 A7_A8
FBB_D<6> F4 FBB_D<22> M11 FBB_CMD<6> FBB_CMD<9> J5 A1 B1
4 Fbb_D<6> DQ6 4 Fbb_D<22> 22 DQ22 Fbb_Cmd<6> 6 RFU_A12 VSSQ VDDQ
FBB_D<7> F2 FBB_D<23> M13 FBB_CMD<2> A12 B12
4 Fbb_D<7> DQ7 4 Fbb_D<23> 23 DQ23 Fbb_Cmd<2> VSSQ VDDQ
FBB_CMD<1> A14 VSSQ VDDQ B14
FBB_EDC<0> FBB_EDC<2> Fbb_Cmd<1>
4 C2 EDC0 4 R13 EDC2 A3 VSSQ VDDQ B3
OUT OUT
FBB_DBI<0> D2 FBB_DBI<2> P13 C1 D1
4 OUT DBI0 4 OUT DBI2 VSSQ VDDQ
VREFD A10 VREFD V10 C11 VSSQ VDDQ D12
FBB_CMD<13> J2 C12 D14
RESET VSSQ VDDQ
x32 x16 x32 x16 FBB_CMD<14> J3 C14 D3
CKE VSSQ VDDQ
FBB_D<8> A11 FBB_D<24> V4 C3 E10
4 Fbb_D<8> DQ8 NC 4 Fbb_D<24> DQ24 NC VSSQ VDDQ
FBB_D<9> A13 FBB_D<25> V2 FBB_CLK0 J12 C4 E5
4 Fbb_D<9> DQ9 NC 4 Fbb_D<25> DQ25 NC 4 IN CLK VSSQ VDDQ
FBB_D<10> B11 FBB_D<26> T4 FBB_CLK0* J11 E1 F1
4 Fbb_D<10> DQ10 NC 4 Fbb_D<26> DQ26 NC 4 IN CLK VSSQ VDDQ
FBB_D<11> B13 FBB_D<27> T2 E12 F12
4 Fbb_D<11> DQ11 NC 4 Fbb_D<27> DQ27 NC VSSQ VDDQ
FBB_D<12> E11 FBB_D<28> N4 E14 F14
4 Fbb_D<12> DQ12 NC 4 Fbb_D<28> DQ28 NC R532 R533 VSSQ VDDQ
FBB_D<13> E13 FBB_D<29> N2 E3 F3
4 Fbb_D<13> DQ13 NC 4 Fbb_D<29> DQ29 NC 40.2ohm 40.2ohm VSSQ VDDQ
FBB_D<14> F11 FBB_D<30> M4 F10 G13
4 Fbb_D<14> DQ14 NC 4 Fbb_D<30> DQ30 NC 1% 1%
VSSQ VDDQ
FBB_D<15> F13 FBB_D<31> M2 F5 G2
4 Fbb_D<15> DQ15 NC 4 Fbb_D<31> DQ31 NC 0402 0402 VSSQ VDDQ
COMMON COMMON H13 VSSQ VDDQ H12
FBB_EDC<1> C13 FBB_EDC<3> R2 FBB_CLK0_CM H2 H3
4 OUT EDC1 GND 4 OUT EDC3 NC VSSQ VDDQ
FBB_DBI<1> D13 FBB_DBI<3> P2 K13 K12
4 DBI1 NC 4 DBI3 NC VSSQ VDDQ

1
OUT OUT C510 A5 NC_RFU_A5 K2 VSSQ VDDQ K3
FBB_WCK01 FBB_WCK23 10nF
4 D4 WCK01 4 P4 WCK23 V5 NC_RFU_V5 M10 VSSQ VDDQ L13
IN IN 16V
FBB_WCK01* D5 FBB_WCK23* P5 M5 L2
4 IN WCK01 4 IN WCK23 10% VSSQ VDDQ
2 X7R N1 VSSQ VDDQ M1 2

2
0402 N12 VSSQ VDDQ M12
FBVDDQ COMMON N14 VSSQ VDDQ M14
N3 VSSQ VDDQ M3
GND R1 VSSQ VDDQ N10
R543 R11 N5
549ohm VSSQ VDDQ
8 R12 VSSQ VDDQ P1
1% OUT
0402
R14 VSSQ VDDQ P12
COMMON R3 VSSQ VDDQ P14
Use low VGSth part for Pascal FBB_VREFC J14 R4 P3
VREFC VSSQ VDDQ
AO3420 0.350 1.05V 0.140A V1 VSSQ VDDQ T1

1
R212 R214 C509 1R216 121ohm
2 FBB_ZQ_1 J13 V12 T12
1.33k 931ohm 10nF ZQ VSSQ VDDQ
0402 1% COMMON V14 VSSQ VDDQ T14
1% 1% 6.3V
1G1D1S 3 0402 0402
J10 SEN V3 VSSQ VDDQ T3
D 10%
Q34 COMMON COMMON X5R

2
@discrete.q_fet_n_enh(sym_2):page7_i518 0402
SOT23_1G1D1S
5,10,21
GPIO10_FBVREF_SEL 1G COMMON
COMMON
IN
S 2
60V GND GND GND
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
FBB_VREF_Q
0.31A
0.3W 0.350 1.05V GND
20V

GND

3 3

4 4

FBVDDQ
1

C572 C185 C184 C539 C602 C538 C523 C524 C522 C540
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
2

0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
1

C514 C513 C177 C525 C518 C571 C533 C174


4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF 47uF 47uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
20% 20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R X5R
2

5 0603 0603 0603 0603 0805 0805 0805 0805 5


COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

GND
MICRO-STAR INT'L CO.,LTD
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 7 of 34
A B C D E F G H
A B C D E F G H

MEMORY: FBB Partition 63..32

1 1

2 2

M502C
M502B @memory.u_mem_sd_ddr5_x32(sym_6):page8_i500
@memory.u_mem_sd_ddr5_x32(sym_5):page8_i498 BGA170
COMMON
BGA170
3 COMMON FBVDDQ 3
Normal
FBB_CMD<19> FBB_CMD<28> G3 J1
Fbb_Cmd<19> 19 RAS MF_VSS/SOE*
FBB_CMD<16> FBB_CMD<31> L3
Fbb_Cmd<16> 16 CAS add 1k to VSS
FBB_CMD<26> FBB_CMD<21> L12 B10 C10
M502D M502A Fbb_Cmd<26> 26 WE VSS VDD
FBB_CMD<31> FBB_CMD<16> G12 B5 C5
@memory.u_mem_sd_ddr5_x32(sym_1):page8_i401 @memory.u_mem_sd_ddr5_x32(sym_3):page8_i441 Fbb_Cmd<31> 31 CS VSS VDD
BGA170 BGA170 D10 VSS VDD D11
COMMON COMMON FBB_CMD<23> FBB_CMD<24> J4 G10 G1
Fbb_Cmd<23> 23 ABI VSS VDD
G5 VSS VDD G11
NORMAL NORMAL FBB_CMD<21> FBB_CMD<26> H4 H1 G14
Fbb_Cmd<21> 21 A0_A10 VSS VDD
FBB_D<32> A4 FBB_D<48> V11 FBB_CMD<20> FBB_CMD<27> H5 H14 G4
4 Fbb_D<32> 32 DQ0 4 Fbb_D<48> 48 DQ16 Fbb_Cmd<20> 20 A1_A9 VSS VDD
FBB_D<33> A2 FBB_D<49> V13 FBB_CMD<29> FBB_CMD<18> H11 K1 L1
4 Fbb_D<33> 33 DQ1 4 Fbb_D<49> 49 DQ17 Fbb_Cmd<29> 29 A2_BA0 VSS VDD
FBB_D<34> B4 FBB_D<50> T11 FBB_CMD<30> FBB_CMD<17> H10 K14 L11
4 Fbb_D<34> 34 DQ2 4 Fbb_D<50> 50 DQ18 Fbb_Cmd<30> 30 A3_BA3 VSS VDD
FBB_D<35> B2 FBB_D<51> T13 FBB_CMD<28> FBB_CMD<19> K11 L10 L14
4 Fbb_D<35> 35 DQ3 4 Fbb_D<51> 51 DQ19 Fbb_Cmd<28> 28 A4_BA2 VSS VDD
FBB_D<36> E4 FBB_D<52> N11 FBB_CMD<27> FBB_CMD<20> K10 L5 L4
4 Fbb_D<36> 36 DQ4 4 Fbb_D<52> 52 DQ20 Fbb_Cmd<27> 27 A5_BA1 VSS VDD
FBB_D<37> E2 FBB_D<53> N13 FBB_CMD<24> FBB_CMD<23> K5 P10 P11
4 Fbb_D<37> 37 DQ5 4 Fbb_D<53> 53 DQ21 Fbb_Cmd<24> 24 A6_A11 VSS VDD
FBB_D<38> F4 FBB_D<54> M11 FBB_CMD<25> FBB_CMD<22> K4 T10 R10
4 Fbb_D<38> 38 DQ6 4 Fbb_D<54> 54 DQ22 Fbb_Cmd<25> 25 A7_A8 VSS VDD
FBB_D<39> F2 FBB_D<55> M13 FBB_CMD<22> FBB_CMD<25> J5 T5 R5
4 Fbb_D<39> 39 DQ7 4 Fbb_D<55> 55 DQ23 Fbb_Cmd<22> 22 RFU_A12 VSS VDD
FBB_CMD<18>
FBB_EDC<4> FBB_EDC<6> Fbb_Cmd<18> 18
4 C2 EDC0 4 R13 EDC2 FBB_CMD<17> A1 VSSQ VDDQ B1
OUT
FBB_DBI<4>
OUT
FBB_DBI<6> Fbb_Cmd<17> 17
4 D2 DBI0 4 P13 DBI2 A12 VSSQ VDDQ B12
OUT OUT
VREFD A10 VREFD V10 A14 VSSQ VDDQ B14
A3 VSSQ VDDQ B3
x32 x16 x32 x16 FBB_CMD<29> J2 C1 D1
RESET VSSQ VDDQ
FBB_D<40> A11 FBB_D<56> V4 FBB_CMD<30> J3 C11 D12
4 Fbb_D<40> 40 DQ8 NC 4 Fbb_D<56> 56 DQ24 NC CKE VSSQ VDDQ
FBB_D<41> A13 FBB_D<57> V2 C12 D14
4 Fbb_D<41> 41 DQ9 NC 4 Fbb_D<57> 57 DQ25 NC VSSQ VDDQ
FBB_D<42> B11 FBB_D<58> T4 FBB_CLK1 J12 C14 D3
4 Fbb_D<42> 42 DQ10 NC 4 Fbb_D<58> 58 DQ26 NC 4 IN CLK VSSQ VDDQ
FBB_D<43> B13 FBB_D<59> T2 FBB_CLK1* J11 C3 E10
4 Fbb_D<43> 43 DQ11 NC 4 Fbb_D<59> 59 DQ27 NC 4 IN CLK VSSQ VDDQ
FBB_D<44> E11 FBB_D<60> N4 C4 E5
4 Fbb_D<44> 44 DQ12 NC 4 Fbb_D<60> 60 DQ28 NC VSSQ VDDQ
FBB_D<45> E13 FBB_D<61> N2 E1 F1
4 Fbb_D<45> 45 DQ13 NC 4 Fbb_D<61> 61 DQ29 NC VSSQ VDDQ
4 FBB_D<46> F11 FBB_D<62> M4 R534 R535 E12 F12 4
4 Fbb_D<46> 46 DQ14 NC 4 Fbb_D<62> 62 DQ30 NC 40.2ohm 40.2ohm VSSQ VDDQ
FBB_D<47> F13 FBB_D<63> M2 E14 F14
4 Fbb_D<47> 47 DQ15 NC 4 Fbb_D<63> 63 DQ31 NC 1% 1%
VSSQ VDDQ
0402 0402
E3 VSSQ VDDQ F3
FBB_EDC<5> C13 FBB_EDC<7> R2 F10 G13
4,8 OUT EDC1 GND 4,8 OUT EDC3 NC COMMON COMMON VSSQ VDDQ
FBB_DBI<5> FBB_DBI<7> FBB_CLK1_CM
4,8 OUT 4,8 D13 DBI1 NC 4,8 OUT 4,8 P2 DBI3 NC
F5 VSSQ VDDQ G2
4,8 4,8 H13 VSSQ VDDQ H12

1
FBB_WCK45 D4 FBB_WCK67 P4 C512 A5 H2 H3
4 IN WCK01 4 IN WCK23 10nF NC_RFU_A5 VSSQ VDDQ
FBB_WCK45* D5 FBB_WCK67* P5 V5 K13 K12
4 IN WCK01 4 IN WCK23 16V
NC_RFU_V5 VSSQ VDDQ
K2 VSSQ VDDQ K3
10%
X7R M10 VSSQ VDDQ L13

2
0402 M5 VSSQ VDDQ L2
COMMON N1 VSSQ VDDQ M1
N12 VSSQ VDDQ M12
GND N14 VSSQ VDDQ M14
FBVDDQ
N3 VSSQ VDDQ M3
R1 VSSQ VDDQ N10
R11 VSSQ VDDQ N5
1

C548 C547 C166 C169 C541 C521 C519 C155 C179 C520 R12 P1
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF VSSQ VDDQ
FBB_VREFC J14 R14 P12
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 7 IN VREFC VSSQ VDDQ
R3 VSSQ VDDQ P14

1
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% C511
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R 1R536 121ohm
2 FBB_ZQ_2_B J13 ZQ R4 VSSQ VDDQ P3
2

10nF
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 1% COMMON V1 VSSQ VDDQ T1
6.3V
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON J10 SEN V12 VSSQ VDDQ T12
10%
X5R V14 VSSQ VDDQ T14

2
0402 V3 VSSQ VDDQ T3
1

C171 C172 C534 C535 C537 C170 C175 C141 COMMON


4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF 47uF 47uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
20% 20% 20% 20% 20% 20% 20% 20%
GND GND
X5R X5R X5R X5R X5R X5R X5R X5R
2

0603 0603 0603 0603 0805 0805 0805 0805


5 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON 5
GND

GND
MICRO-STAR INT'L CO.,LTD
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 8 of 34
A B C D E F G H
A B C D E F G H

MEMORY: GPU Partition C/D

1 U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 1
G1D
@digital.u_gpu_gb2b_192(sym_4):page9_i2034
BGA1428
COMMON

4/18 FBC

FBC_D<0> AB5 N6 FBC_CMD<0>


10 Fbc_D<0> 0 FBC_D0 FBC_CMD0 0 Fbc_Cmd<0>
FBC_D<1> AB6 N5 FBC_CMD<1>
10 Fbc_D<1> 1 FBC_D1 FBC_CMD1 1 Fbc_Cmd<1>

F
FBC_D<2> AC7 N4 FBC_CMD<2>
10 Fbc_D<2> 2 FBC_D2 FBC_CMD2 2 Fbc_Cmd<2>
FBC_D<3> AB4 N7 FBC_CMD<3>
10 Fbc_D<3> 3 FBC_D3 FBC_CMD3 3 Fbc_Cmd<3>
FBC_D<4> AA5 N8 FBC_CMD<4>
10 Fbc_D<4> 4 FBC_D4 FBC_CMD4 4 Fbc_Cmd<4>
FBC_D<5> AA4
B M4 FBC_CMD<5>
10 FBC_D5 FBC_CMD5
10
Fbc_D<5>
Fbc_D<6>
5
6
FBC_D<6> W4 FBC_D6 FBC_CMD6 M5 FBC_CMD<6>
5
6
Fbc_Cmd<5>
Fbc_Cmd<6>
GDDR5_BGA170_MIRROR
FBC_D<7> W5 M6 FBC_CMD<7>
10 Fbc_D<7> 7 FBC_D7 FBC_CMD7 7 Fbc_Cmd<7>
FBC_D<8> W1 L5 FBC_CMD<8>
10 FBC_D8 FBC_CMD8
10
10
Fbc_D<8>
Fbc_D<9>
Fbc_D<10>
8
9
10
FBC_D<9>
FBC_D<10>
FBC_D<11>
Y3
W2
W3
FBC_D9
FBC_D10
FBC_D11
C FBC_CMD9
FBC_CMD10
FBC_CMD11
L7
M8
G3
FBC_CMD<9>
FBC_CMD<10>
FBC_CMD<11>
8
9
10
Fbc_Cmd<8>
Fbc_Cmd<9>
Fbc_Cmd<10>
CMD0
0..31

CS*
32..63

10 Fbc_D<11> 11
FBC_D<12>
11 Fbc_Cmd<11>
10 AB1 FBC_D12 FBC_CMD12 F3 FBC_CMD<12>
Fbc_D<12> 12
FBC_D<13>
12 Fbc_Cmd<12> CMD1 A3_BA3
10 AB2 FBC_D13 FBC_CMD13 F1 FBC_CMD<13>
Fbc_D<13> 13
FBC_D<14>
13 Fbc_Cmd<13>
AC3
N F2 FBC_CMD<14> CMD2 A2_BA0
10 Fbc_D<14> 14 FBC_D14 FBC_CMD14 14 Fbc_Cmd<14>
FBC_D<15> AB3 G2 FBC_CMD<15>
10 Fbc_D<15> 15 FBC_D15 FBC_CMD15 15 Fbc_Cmd<15> CMD3 A4_BA2
FBC_D<16> V5 D4 FBC_CMD<16>
10 Fbc_D<16> 16 FBC_D16 FBC_CMD16 16 Fbc_Cmd<16>
FBC_D<17> V6 E4 FBC_CMD<17> CMD4 A5_BA1
10 FBC_D17 FBC_CMD17
10
10
Fbc_D<17>
Fbc_D<18>
Fbc_D<19>
17
18
19
FBC_D<18>
FBC_D<19>
FBC_D<20>
V4
T4
P7
FBC_D18
FBC_D19
FBC_D20
O FBC_CMD18
FBC_CMD19
FBC_CMD20
F4
G4
H4
FBC_CMD<18>
FBC_CMD<19>
FBC_CMD<20>
17
18
19
Fbc_Cmd<17>
Fbc_Cmd<18>
Fbc_Cmd<19>
CMD5

CMD6
WE*

A7_A8
10 Fbc_D<20> 20
FBC_D<21>
20 Fbc_Cmd<20>
10 R5 FBC_D21 FBC_CMD21 D3 FBC_CMD<21>
CMD7 A6_A11
Fbc_D<21>
T Fbc_Cmd<21>
21 21
FBC_D<22> R6 D1 FBC_CMD<22>
10 Fbc_D<22> 22 FBC_D22 FBC_CMD22 22 Fbc_Cmd<22> CMD8 ABI*
2 FBC_D<23> R4 B3 FBC_CMD<23> 2
10 Fbc_D<23> 23 FBC_D23 FBC_CMD23 23 Fbc_Cmd<23>
FBC_D<24> P3 C2 FBC_CMD<24> CMD9 A12_RFU
10 Fbc_D<24> 24 FBC_D24 FBC_CMD24 24 Fbc_Cmd<24>
FBC_D<25> R1 L3 FBC_CMD<25>
10 Fbc_D<25> 25 FBC_D25 FBC_CMD25 25 Fbc_Cmd<25> CMD10 A0_A10
FBC_D<26> R2 N3 FBC_CMD<26>
10 Fbc_D<26> 26 FBC_D26 FBC_CMD26 26 Fbc_Cmd<26>

A
FBC_D<27> R3 M3 FBC_CMD<27> CMD11 A1_A9
10 Fbc_D<27> 27 FBC_D27 FBC_CMD27 27 Fbc_Cmd<27>
FBC_D<28> U3 M1 FBC_CMD<28>
10 Fbc_D<28> 28 FBC_D28 FBC_CMD28 28 Fbc_Cmd<28> CMD12 RAS*
FBC_D<29> V2 E3 FBC_CMD<29>
10 Fbc_D<29> 29 FBC_D29 FBC_CMD29 29 Fbc_Cmd<29>
FBC_D<30> V3 D2 FBC_CMD<30> CMD13 RST*
10 Fbc_D<30> 30 FBC_D30 FBC_CMD30 30 Fbc_Cmd<30>

V
FBC_D<31> V1 M2 FBC_CMD<31> FBVDDQ
10 Fbc_D<31> 31 FBC_D31 FBC_CMD31 31 Fbc_Cmd<31> CMD14 CKE*
FBC_D<32> D13 K8
11 Fbc_D<32> 32 FBC_D32 FBC_CMD32
FBC_D<33> CMD15 CAS*
11 G14 FBC_D33 FBC_CMD33 K9
Fbc_D<33> 33
11
FBC_D<34> E13 FBC_D34 FBC_CMD34 K7 FBC_DEBUG0 1R568 60.4ohm
2 CMD32

11
11
Fbc_D<34>
Fbc_D<35>
Fbc_D<36>
34
35
36
FBC_D<35>
FBC_D<36>
FBC_D<37>
F13
D12
E12
FBC_D35
FBC_D36
FBC_D37
A FBC_CMD35 L8 FBC_DEBUG1 0402 1% DNI 1R570
0402 1%
60.4ohm
DNI
2
CMD34

CMD16
DBG0 DBG0

CS*
11 Fbc_D<37> 37
FBC_D<38>
11 E10 FBC_D38

I
Fbc_D<38> 38 CMD17 A3_BA3
FBC_D<39> D10
11 Fbc_D<39> 39 FBC_D39
FBC_D<40> B10 CMD18 A2_BA0
11 Fbc_D<40> 40 FBC_D40
FBC_D<41> C10 CMD19 A4_BA2
11 Fbc_D<41> 41 FBC_D41
FBC_D<42> A10
11 FBC_D42
11
11
Fbc_D<42>
Fbc_D<43>
Fbc_D<44>
42
43
44
FBC_D<43>
FBC_D<44>
FBC_D<45>
C11
C13
A13
FBC_D43
FBC_D44
FBC_D45
L FBC_CLK0
FBC_CLK0
N2
N1
FBC_CLK0
FBC_CLK0*
FB_CLK
FB_CLK
OUT 10
CMD20

CMD21
A5_BA1

WE*

11 Fbc_D<45> 45 OUT 10 CMD22 A7_A8

A
FBC_D<46> D14 A4 FBC_CLK1
11 Fbc_D<46> 46 FBC_D46 FBC_CLK1 FB_CLK OUT 11
FBC_D<47> B13 B4 FBC_CLK1* CMD23 A6_A11
11 Fbc_D<47> 47 FBC_D47 FBC_CLK1 FB_CLK
OUT 11
FBC_D<48> D9
11 Fbc_D<48> 48 FBC_D48 CMD24 ABI*
FBC_D<49> D7
11 Fbc_D<49> 49 FBC_D49
FBC_D<50> CMD25 A12_RFU
11
11
11
Fbc_D<50>
Fbc_D<51>
Fbc_D<52>
50
51
52
FBC_D<51>
FBC_D<52>
FBC_D<53>
G8
E7
G5
FBC_D50
FBC_D51
FBC_D52
B CMD26

CMD27
A0_A10

A1_A9
3
11 F6 FBC_D53 3
Fbc_D<53> 53
FBC_D<54> E6
L
FBC_D54 CMD28 RAS*
11 Fbc_D<54> 54
FBC_D<55>
11 D6 FBC_D55 CMD29 RST*
Fbc_D<55> 55
FBC_D<56> FBC_WCK01
11 C5 FBC_D56 FBC_WCK01 V7 FB_WCK 10
Fbc_D<56> 56
FBC_D<57> FBC_WCK01*
OUT
CMD30 CKE*
11 B6 FBC_D57 FBC_WCK01 U8 FB_WCK 10
Fbc_D<57> 57
FBC_D<58>
OUT
11
11
11
Fbc_D<58>
Fbc_D<59>
Fbc_D<60>
58
59
60
FBC_D<59>
FBC_D<60>
FBC_D<61>
C6
A6
C8
FBC_D58
FBC_D59
FBC_D60
E FBC_WCKB01
FBC_WCKB01
FBC_WCK23
Y8
W7
Y7 FBC_WCK23
FBC_WCK23*
FB_WCK
OUT 10
CMD31

CMD33
CAS*

11 C9 FBC_D61 FBC_WCK23 W6 FB_WCK 10 CMD35 DBG1 DBG1


Fbc_D<61> 61
FBC_D<62>
OUT
11 A9 FBC_D62 FBC_WCKB23 R8
Fbc_D<62> 62
FBC_D<63>
11 B9 FBC_D63 FBC_WCKB23 T7
Fbc_D<63> 63
FBC_WCK45

10 BI
FBC_DBI<0>
FBC_DBI<1>
AA6 FBC_DQM0
W FBC_WCK45
FBC_WCK45
FBC_WCKB45
E9
F9
H8
FBC_WCK45*
FB_WCK
FB_WCK
OUT
OUT
11
11

10 AA1 FBC_DQM1 FBC_WCKB45 H9


10
10
BI
BI
BI
FBC_DBI<2>
FBC_DBI<3>
FBC_DBI<4>
U7
T1
F12
FBC_DQM2
FBC_DQM3
FBC_DQM4
I FBC_WCK67
FBC_WCK67
FBC_WCKB67
G11
F10
H11
FBC_WCK67
FBC_WCK67*
FB_WCK
FB_WCK
OUT
OUT
11
11
11 BI
FBC_DBI<5>
11 A12 FBC_DQM5 FBC_WCKB67 G10

T
BI
FBC_DBI<6> H6
11 BI FBC_DQM6
FBC_DBI<7> A7
11 BI FBC_DQM7

10
10
IN
IN
FBC_EDC<0>
FBC_EDC<1>
FBC_EDC<2>
AB8
AA2
FBC_DQS_WP0
FBC_DQS_WP1
H
10 T5 FBC_DQS_WP2
IN
FBC_EDC<3> T2
10 IN FBC_DQS_WP3
FBC_EDC<4>
11
11
11
IN
IN
IN
FBC_EDC<5>
FBC_EDC<6>
FBC_EDC<7>
H13
B12
G7
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
G FB_PLLVDD
4
11 B7 FBC_DQS_WP7 FBC_PLL_AVDD P8 4,15
4
IN

M IN
1

AA7 C612
FBC_DQS_RN0
AA3
T6
T3
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
2 0.1uF
16V
10%
X7R
2

G12
C12
F7
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
0 0402
COMMON

C7 FBC_DQS_RN7

6 GND FBVDDQ

R546 R573
10k 10k
CKE*
5% 5%
0402 0402
COMMON COMMON
FBC_CMD<30>
FBC_CMD<14>

FBC_CMD<29>
FBC_CMD<13>

R569 R547
10k 10k
RST*
5% 5%
0402 0402
COMMON COMMON

5 5

GND

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 9 of 34
A B C D E F G H
A B C D E F G H

M1C
MEMORY: FBC Partition 31..0 @memory.u_mem_sd_ddr5_x32(sym_6):page10_i572
BGA170
COMMON
M1B
@memory.u_mem_sd_ddr5_x32(sym_5):page10_i568
BGA170
Normal FBVDDQ
COMMON J1 MF_VSS/SOE*
add 1k to VSS
FBC_CMD<3> FBC_CMD<12> G3 B10 C10
Fbc_Cmd<3> 3 RAS VSS VDD
FBC_CMD<0> FBC_CMD<15> L3 B5 C5
Fbc_Cmd<0> 0 CAS VSS VDD
FBC_CMD<10> FBC_CMD<5> L12 D10 D11
Fbc_Cmd<10> 10 WE VSS VDD
FBC_CMD<15> FBC_CMD<0> G12 G10 G1
M1D M1A Fbc_Cmd<15> 15 CS VSS VDD
G5 VSS VDD G11
@memory.u_mem_sd_ddr5_x32(sym_1):page10_i480 @memory.u_mem_sd_ddr5_x32(sym_3):page10_i519 FBC_CMD<8>
BGA170 BGA170 FBC_CMD<7> J4 ABI H1 VSS VDD G14
1 Fbc_Cmd<7> 7
1
COMMON COMMON H14 VSS VDD G4
FBC_CMD<5> FBC_CMD<10> H4 K1 L1
NORMAL NORMAL Fbc_Cmd<5> 5 A0_A10 VSS VDD
FBC_CMD<4> FBC_CMD<11> H5 K14 L11
Fbc_Cmd<4> 4 A1_A9 VSS VDD
FBC_D<0> A4 FBC_D<16> V11 FBC_CMD<13> FBC_CMD<2> H11 L10 L14
9 Fbc_D<0> 0 DQ0 9 Fbc_D<16> 16 DQ16 Fbc_Cmd<13> 13 A2_BA0 VSS VDD
FBC_D<1> A2 FBC_D<17> V13 FBC_CMD<14> FBC_CMD<1> H10 L5 L4
9 Fbc_D<1> 1 DQ1 9 Fbc_D<17> 17 DQ17 Fbc_Cmd<14> 14 A3_BA3 VSS VDD
FBC_D<2> B4 FBC_D<18> T11 FBC_CMD<12> FBC_CMD<3> K11 P10 P11
9 Fbc_D<2> 2 DQ2 9 Fbc_D<18> 18 DQ18 Fbc_Cmd<12> 12 A4_BA2 VSS VDD
FBC_D<3> B2 FBC_D<19> T13 FBC_CMD<11> FBC_CMD<4> K10 T10 R10
9 Fbc_D<3> 3 DQ3 9 Fbc_D<19> 19 DQ19 Fbc_Cmd<11> 11 A5_BA1 VSS VDD
FBC_D<4> E4 FBC_D<20> N11 FBC_CMD<8> FBC_CMD<7> K5 T5 R5
9 Fbc_D<4> 4 DQ4 9 Fbc_D<20> 20 DQ20 Fbc_Cmd<8> 8 A6_A11 VSS VDD
FBC_D<5> E2 FBC_D<21> N13 FBC_CMD<9> FBC_CMD<6> K4
9 Fbc_D<5> 5 DQ5 9 Fbc_D<21> 21 DQ21 Fbc_Cmd<9> 9 A7_A8
FBC_D<6> F4 FBC_D<22> M11 FBC_CMD<6> FBC_CMD<9> J5 A1 B1
9 Fbc_D<6> 6 DQ6 9 Fbc_D<22> 22 DQ22 Fbc_Cmd<6> 6 RFU_A12 VSSQ VDDQ
FBC_D<7> F2 FBC_D<23> M13 FBC_CMD<2> A12 B12
9 Fbc_D<7> 7 DQ7 9 Fbc_D<23> 23 DQ23 Fbc_Cmd<2> 2 VSSQ VDDQ
FBC_CMD<1> A14 VSSQ VDDQ B14
FBC_EDC<0> FBC_EDC<2> Fbc_Cmd<1> 1
9 C2 EDC0 9 R13 EDC2 A3 VSSQ VDDQ B3
OUT OUT
FBC_DBI<0> D2 FBC_DBI<2> P13 C1 D1
9 OUT DBI0 9 OUT DBI2 VSSQ VDDQ
VREFD A10 VREFD V10 C11 VSSQ VDDQ D12
FBC_CMD<13> J2 C12 D14
RESET VSSQ VDDQ
x32 x16 x32 x16 FBC_CMD<14> J3 C14 D3
CKE VSSQ VDDQ
FBC_D<8> A11 FBC_D<24> V4 C3 E10
9 Fbc_D<8> 8 DQ8 NC 9 Fbc_D<24> 24 DQ24 NC VSSQ VDDQ
FBC_D<9> A13 FBC_D<25> V2 FBC_CLK0 J12 C4 E5
9 Fbc_D<9> 9 DQ9 NC 9 Fbc_D<25> 25 DQ25 NC 9 IN CLK VSSQ VDDQ
FBC_D<10> B11 FBC_D<26> T4 FBC_CLK0* J11 E1 F1
9 Fbc_D<10> 10 DQ10 NC 9 Fbc_D<26> 26 DQ26 NC 9 IN CLK VSSQ VDDQ
FBC_D<11> B13 FBC_D<27> T2 E12 F12
9 Fbc_D<11> 11 DQ11 NC 9 Fbc_D<27> 27 DQ27 NC VSSQ VDDQ
FBC_D<12> E11 FBC_D<28> N4 E14 F14
9 Fbc_D<12> 12 DQ12 NC 9 Fbc_D<28> 28 DQ28 NC VSSQ VDDQ
FBC_D<13> E13 FBC_D<29> N2 E3 F3
9 Fbc_D<13> 13 DQ13 NC 9 Fbc_D<29> 29 DQ29 NC VSSQ VDDQ
FBC_D<14> F11 FBC_D<30> M4 F10 G13
9 Fbc_D<14> 14 DQ14 NC 9 Fbc_D<30> 30 DQ30 NC VSSQ VDDQ
FBC_D<15> F13 FBC_D<31> M2 R571 R567 F5 G2
9 Fbc_D<15> 15 DQ15 NC 9 Fbc_D<31> 31 DQ31 NC 40.2ohm 40.2ohm VSSQ VDDQ
H13 VSSQ VDDQ H12
FBC_EDC<1> FBC_EDC<3> 1% 1%
9 C13 EDC1 GND 9 R2 EDC3 NC 0402 0402
H2 VSSQ VDDQ H3
OUT OUT
FBC_DBI<1> D13 FBC_DBI<3> P2 K13 K12
9 OUT DBI1 NC 9 OUT DBI3 NC COMMON COMMON VSSQ VDDQ
FBC_CLK0_CM A5 K2 K3
NC_RFU_A5 VSSQ VDDQ
2 FBC_WCK01 D4 FBC_WCK23 P4 V5 M10 L13 2
WCK01 9 WCK23 NC_RFU_V5 VSSQ VDDQ

1
IN IN C603
FBC_WCK01* D5 FBC_WCK23* P5 M5 L2
IN WCK01 9 IN WCK23 10nF VSSQ VDDQ
N1 VSSQ VDDQ M1
16V
N12 VSSQ VDDQ M12
10%
FBVDDQ X7R N14 VSSQ VDDQ M14

2
0402 N3 VSSQ VDDQ M3
COMMON R1 VSSQ VDDQ N10
R556 R11 N5
549ohm VSSQ VDDQ
GND 11 R12 VSSQ VDDQ P1
1% OUT
0402
R14 VSSQ VDDQ P12
COMMON R3 VSSQ VDDQ P14
Use low VGSth part for Pascal FBC_VREFC J14 R4 P3
VREFC VSSQ VDDQ
0.350 1.05V 0.140A V1 VSSQ VDDQ T1

1
R208 R209 C617 1R206 121ohm
2 FBC_ZQ_1 J13 V12 T12
AO3420 ZQ VSSQ VDDQ
1.33k 931ohm 10nF
0402 1% COMMON V14 VSSQ VDDQ T14
1% 1% 6.3V
1G1D1S 3 0402 0402
J10 SEN V3 VSSQ VDDQ T3
D 10%
Q514 COMMON COMMON X5R

2
@discrete.q_fet_n_enh(sym_2):page10_i518 0402
SOT23_1G1D1S
5,7,21
GPIO10_FBVREF_SEL 1G COMMON
COMMON
IN
S 2
60V GND GND GND
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W GND
20V

FBC_VREF_Q
GND 0.350 1.05V

3 3

4 4

FBVDDQ
1

C580 C622 C576 C153 C634 C152 C636 C583 C575 C149
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
2

0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
1

C183 C558 C553 C156 C555 C157 C611 C532


4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF 47uF 47uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
20% 20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R X5R
2

5 0603 0603 0603 0603 0805 0805 0805 0805 5


COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

MICRO-STAR INT'L CO.,LTD


GND
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 10 of 34
A B C D E F G H
A B C D E F G H

MEMORY: FBC Partition 63..32

1 1

2 2

M501C
M501B @memory.u_mem_sd_ddr5_x32(sym_6):page11_i499
3 BGA170
3
@memory.u_mem_sd_ddr5_x32(sym_5):page11_i445
COMMON
BGA170
COMMON FBVDDQ
Normal
FBC_CMD<19> FBC_CMD<28> G3 J1
Fbc_Cmd<19> 19 RAS MF_VSS/SOE*
FBC_CMD<16> FBC_CMD<31> L3
Fbc_Cmd<16> 16 CAS add 1k to VSS
FBC_CMD<26> FBC_CMD<21> L12 B10 C10
M501D M501A Fbc_Cmd<26> 26 WE VSS VDD
FBC_CMD<31> FBC_CMD<16> G12 B5 C5
@memory.u_mem_sd_ddr5_x32(sym_1):page11_i400 @memory.u_mem_sd_ddr5_x32(sym_3):page11_i442 Fbc_Cmd<31> 31 CS VSS VDD
BGA170 BGA170 D10 VSS VDD D11
COMMON COMMON FBC_CMD<23> FBC_CMD<24> J4 G10 G1
Fbc_Cmd<23> 23 ABI VSS VDD
G5 VSS VDD G11
NORMAL NORMAL FBC_CMD<26> H4 H1 G14
FBC_CMD<21> A0_A10 VSS VDD
FBC_D<32> FBC_D<48> Fbc_Cmd<21> 21
FBC_CMD<27>
9 A4 DQ0 9 V11 DQ16 FBC_CMD<20> H5 A1_A9 H14 VSS VDD G4
Fbc_D<32> 32
FBC_D<33> Fbc_D<48> 48
FBC_D<49> Fbc_Cmd<20> 20
FBC_CMD<18>
9 A2 DQ1 9 V13 DQ17 FBC_CMD<29> H11 A2_BA0 K1 VSS VDD L1
Fbc_D<33> 33
FBC_D<34> Fbc_D<49> 49
FBC_D<50> Fbc_Cmd<29> 29
FBC_CMD<17>
9 B4 DQ2 9 T11 DQ18 FBC_CMD<30> H10 A3_BA3 K14 VSS VDD L11
Fbc_D<34> 34
FBC_D<35> Fbc_D<50> 50
FBC_D<51> Fbc_Cmd<30> 30
FBC_CMD<19>
9 B2 DQ3 9 T13 DQ19 FBC_CMD<28> K11 A4_BA2 L10 VSS VDD L14
Fbc_D<35> 35
FBC_D<36> Fbc_D<51> 51
FBC_D<52> Fbc_Cmd<28> 28
FBC_CMD<20>
9 E4 DQ4 9 N11 DQ20 FBC_CMD<27> K10 A5_BA1 L5 VSS VDD L4
Fbc_D<36> 36
FBC_D<37> Fbc_D<52> 52
FBC_D<53> Fbc_Cmd<27> 27
FBC_CMD<23>
9 E2 DQ5 9 N13 DQ21 FBC_CMD<24> K5 A6_A11 P10 VSS VDD P11
Fbc_D<37> 37
FBC_D<38> Fbc_D<53> 53
FBC_D<54> Fbc_Cmd<24> 24
FBC_CMD<22>
9 F4 DQ6 9 M11 DQ22 FBC_CMD<25> K4 A7_A8 T10 VSS VDD R10
Fbc_D<38> 38
FBC_D<39> Fbc_D<54> 54
FBC_D<55> Fbc_Cmd<25> 25
FBC_CMD<25>
9 F2 DQ7 9 M13 DQ23 FBC_CMD<22> J5 RFU_A12 T5 VSS VDD R5
Fbc_D<39> 39 Fbc_D<55> 55 Fbc_Cmd<22> 22
FBC_CMD<18>
FBC_EDC<4> FBC_EDC<6> Fbc_Cmd<18> 18
9 C2 EDC0 9 R13 EDC2 FBC_CMD<17> A1 VSSQ VDDQ B1
BI
FBC_DBI<4>
BI
FBC_DBI<6> Fbc_Cmd<17> 17
9 D2 DBI0 9 P13 DBI2 A12 VSSQ VDDQ B12
BI BI
VREFD A10 VREFD V10 A14 VSSQ VDDQ B14
A3 VSSQ VDDQ B3
x32 x16 x32 x16 FBC_CMD<29> J2 C1 D1
RESET VSSQ VDDQ
FBC_D<40> A11 FBC_D<56> V4 FBC_CMD<30> J3 C11 D12
9 Fbc_D<40> DQ8 NC 9 Fbc_D<56> 56 DQ24 NC CKE VSSQ VDDQ
FBC_D<41> A13 FBC_D<57> V2 C12 D14
9 Fbc_D<41> DQ9 NC 9 Fbc_D<57> 57 DQ25 NC VSSQ VDDQ
FBC_D<42> B11 FBC_D<58> T4 FBC_CLK1 J12 C14 D3
9 Fbc_D<42> DQ10 NC 9 Fbc_D<58> 58 DQ26 NC 9 IN CLK VSSQ VDDQ
FBC_D<43> B13 FBC_D<59> T2 FBC_CLK1* J11 C3 E10
9 Fbc_D<43> DQ11 NC 9 Fbc_D<59> 59 DQ27 NC 9 IN CLK VSSQ VDDQ
4 FBC_D<44> E11 FBC_D<60> N4 C4 E5 4
9 Fbc_D<44> DQ12 NC 9 Fbc_D<60> 60 DQ28 NC VSSQ VDDQ
FBC_D<45> E13 FBC_D<61> N2 E1 F1
9 Fbc_D<45> DQ13 NC 9 Fbc_D<61> 61 DQ29 NC VSSQ VDDQ
FBC_D<46> F11 FBC_D<62> M4 R529 R530 E12 F12
9 Fbc_D<46> DQ14 NC 9 Fbc_D<62> 62 DQ30 NC 40.2ohm 40.2ohm VSSQ VDDQ
FBC_D<47> F13 FBC_D<63> M2 E14 F14
9 Fbc_D<47> DQ15 NC 9 Fbc_D<63> 63 DQ31 NC 1% 1%
VSSQ VDDQ
0402 0402
E3 VSSQ VDDQ F3
FBC_EDC<5> C13 FBC_EDC<7> R2 F10 G13
9 BI EDC1 GND 9 BI EDC3 NC COMMON COMMON VSSQ VDDQ
FBC_DBI<5> D13 FBC_DBI<7> P2 FBC_CLK1_CM F5 G2
9 BI DBI1 NC 9 BI DBI3 NC VSSQ VDDQ
H13 VSSQ VDDQ H12

1
FBC_WCK45 D4 FBC_WCK67 P4 C508 A5 H2 H3
9 IN WCK01 9 IN WCK23 10nF NC_RFU_A5 VSSQ VDDQ
FBC_WCK45* D5 FBC_WCK67* P5 V5 K13 K12
9 IN WCK01 9 IN WCK23 16V
NC_RFU_V5 VSSQ VDDQ
K2 VSSQ VDDQ K3
10%
X7R M10 VSSQ VDDQ L13

2
0402 M5 VSSQ VDDQ L2
COMMON N1 VSSQ VDDQ M1
N12 VSSQ VDDQ M12
FBVDDQ
GND N14 VSSQ VDDQ M14
N3 VSSQ VDDQ M3
R1 VSSQ VDDQ N10
1

C515 C517 C544 C167 C543 C178 C516 C168 C545 C546 R11 N5
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF VSSQ VDDQ
R12 VSSQ VDDQ P1
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V FBC_VREFC
10 J14 VREFC R14 VSSQ VDDQ P12
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% IN
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R R3 VSSQ VDDQ P14
2

1
C507 1R531 121ohm
2 FBC_ZQ_2_B J13 R4 P3
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 ZQ VSSQ VDDQ
10nF
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON 0402 1% COMMON V1 VSSQ VDDQ T1
6.3V
J10 SEN V12 VSSQ VDDQ T12
10%
X5R V14 VSSQ VDDQ T14

2
1

C163 C161 C549 C551 C560 C557 C629 C582 V3 T3


0402 VSSQ VDDQ
4.7uF 4.7uF 4.7uF 4.7uF 10uF 10uF 47uF 47uF COMMON
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
20% 20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R X5R GND GND
2

5 0603 0603 0603 0603 0805 0805 0805 0805 5


COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

GND

GND
MICRO-STAR INT'L CO.,LTD
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 11 of 34
A B C D E F G H
A B C D E F G H

GPU PWR and GND


U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 G1F U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1E @digital.u_gpu_gb2b_192(sym_15):page12_i77 G1G G1H
FBVDDQ
@digital.u_gpu_gb2b_192(sym_14):page12_i76 BGA1428 @digital.u_gpu_gb2b_192(sym_16):page12_i78 @digital.u_gpu_gb2b_192(sym_17):page12_i79
NVVDD NVVDD NVVDD NVVDD
BGA1428 COMMON BGA1428 BGA1428
FBVDDQ
COMMON COMMON COMMON
15/18 GND
14/18 GND 16/18 VDD 17/18 FBVDDQ
BA1 GND GND M17 A41 GND GND AW24 AA11 VDD VDD AN34
BA11 GND GND M19 AA12 GND GND AW25 AA13 VDD VDD AN35 A2 FBVDDQ FBVDDQ B27
BA14 GND GND M21 AA14 GND GND AW27 AA15 VDD VDD AP31 A27 FBVDDQ FBVDDQ B28
1 BA17 GND GND M23 AA16 GND GND AW28 AA17 VDD VDD AP32 A28 FBVDDQ FBVDDQ C1 1
BA2 GND GND M25 AA18 GND GND AW30 AA19 VDD VDD AP33 A3 FBVDDQ FBVDDQ C27
BA20 GND GND M27 AA20 GND GND AW31 AA21 VDD VDD AP34 AA34 FBVDDQ FBVDDQ C28
BA23 GND GND M35 AA22 GND GND AW33 AA23 VDD VDD AP35 AA35 FBVDDQ FBVDDQ C4
BA26 GND GND N12 AA24 GND GND AW34 AA25 VDD VDD AP36 AA36 FBVDDQ FBVDDQ D23
BA29 GND GND N14 AA26 GND GND AY1 AA27 VDD VDD AR32 AA37 FBVDDQ FBVDDQ D27
BA32 GND GND N16 AA28 GND GND AY20 AB12 VDD VDD AR33 AA38 FBVDDQ FBVDDQ D28
BA35 GND GND N18 AA8 GND GND AY23 AB14 VDD VDD AR34 AA39 FBVDDQ FBVDDQ E27
BA5 GND GND N20 AB11 GND GND AY26 AB16 VDD VDD AR35 AA40 FBVDDQ FBVDDQ E28
BA8 GND GND N22 AB13 GND GND AY29 AB18 VDD VDD AR36 AA41 FBVDDQ FBVDDQ E32
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
BB2 GND GND N24 AB15 GND GND AY32 AB20 VDD VDD AR37 AA42 FBVDDQ FBVDDQ F27 G1I
BB3 GND GND N26 AB17 GND GND AY35 AB22 VDD VDD AT33 AA9 FBVDDQ FBVDDQ F28
@digital.u_gpu_gb2b_192(sym_18):page12_i89
C42 GND GND N28 AB19 GND GND B11 AB24 VDD VDD AT34 AB34 FBVDDQ FBVDDQ G1
BGA1428
D11 GND GND P11 AB21 GND GND B14 AB26 VDD VDD AT35 AB35 FBVDDQ FBVDDQ G27 IOVDD
COMMON
D17 GND GND P13 AB23 GND GND B17 AB28 VDD VDD AT36 AB36 FBVDDQ FBVDDQ G28
D20 GND GND P15 AB25 GND GND B20 AC11 VDD VDD AT37 AB37 FBVDDQ FBVDDQ H2 18/18 NC/3V3
D33 GND GND P17 AB27 GND GND B23 AC13 VDD VDD AT38 AB38 FBVDDQ FBVDDQ H27
D35 P19 AB7 B32 AC15 AT39 AB39 H28 AK34 AH8 SNN_3V3AUX_NC
GND GND GND GND VDD VDD FBVDDQ FBVDDQ NC 3V3AUX_NC
D5 GND GND P2 AC12 GND GND B35 AC17 VDD VDD AU35 AB40 FBVDDQ FBVDDQ H5 AM9 NC
D8 GND GND U26 AC14 GND GND B38 AC19 VDD VDD AU36 AB41 FBVDDQ FBVDDQ J1 AN9 NC
E11 GND GND U28 AC16 GND GND B41 AC21 VDD VDD AU37 AB42 FBVDDQ FBVDDQ J10 AT31 NC
E14 GND GND U38 AC18 GND GND B42 AC23 VDD VDD AU38 AB9 FBVDDQ FBVDDQ J11 AW15 NC VDD33 AD6
E17 GND GND U4 AC2 GND GND B5 AC25 VDD VDD AU39 AC34 FBVDDQ FBVDDQ J12 F5 NC VDD33 AD7
E20 GND GND U41 AC20 GND GND B8 AC27 VDD VDD AU40 AC8 FBVDDQ FBVDDQ J13 AT30 NC VDD33 AD8
E23 GND GND U5 AC22 GND GND A40 AD12 VDD VDD AU41 AC9 FBVDDQ FBVDDQ J14 F8 NC VDD33 AE6
E35 GND GND V11 AC24 GND GND AM41 AD14 VDD VDD AU42 AD34 FBVDDQ FBVDDQ J15 AP14 NC VDD33 AE7
E38 GND GND V13 AC26 GND GND AM5 AD16 VDD VDD AV36 AE39 FBVDDQ FBVDDQ J16 AP15 NC VDD33 AE8
E41 GND GND V15 AC28 GND GND AM7 AD18 VDD VDD AV37 B1 FBVDDQ FBVDDQ J17 AP16 NC VDD33 AF8
E5 GND GND V17 AC4 GND GND AR2 AD20 VDD VDD AV38 B2 FBVDDQ FBVDDQ J18 AT24 NC VDD33 AF9
2 E8 GND GND V19 AC5 GND GND AR39 AD22 VDD VDD AV39 P34 FBVDDQ FBVDDQ J19 AT27 NC VDD33 AG8 2
F36 GND GND V21 AD11 GND GND AR41 AD24 VDD VDD AV40 P4 FBVDDQ FBVDDQ J2 G39 NC VDD33 AG9
F39 GND GND V23 AD13 GND GND AR5 AD26 VDD VDD AV41 P9 FBVDDQ FBVDDQ J20 G40 NC VDD33 AH9
G13 GND GND V25 AD15 GND GND AR7 AD28 VDD VDD AW36 R34 FBVDDQ FBVDDQ J21 H10 NC
G22 GND GND V27 AD17 GND GND AT11 AE11 VDD VDD AW37 R9 FBVDDQ FBVDDQ J22 H14 NC
G33 GND GND V8 AD19 GND GND AT14 AE13 VDD VDD AW38 T34 FBVDDQ FBVDDQ J23
G38 GND GND W12 AD21 GND GND AT17 AE15 VDD VDD AW39 T9 FBVDDQ FBVDDQ J24 IOVDD
G6 GND GND W14 AD23 GND GND AT20 AE17 VDD VDD AW40 U34 FBVDDQ FBVDDQ J25 3V3_AON AJ8
G9 GND GND W16 AD25 GND GND AT23 AE19 VDD VDD AW41 U39 FBVDDQ FBVDDQ J26 3V3_AON AJ9
H12 GND GND W18 AD27 GND GND AT26 AE21 VDD VDD AW42 U9 FBVDDQ FBVDDQ J27
H16 GND GND W20 AE12 GND GND AT29 AE23 VDD VDD AY36 V34 FBVDDQ FBVDDQ J28
H18 GND GND W22 AE14 GND GND AT32 AE25 VDD VDD AY37 V9 FBVDDQ FBVDDQ J29
H21 GND GND W24 AE16 GND GND AV11 AE27 VDD VDD AY38 W34 FBVDDQ FBVDDQ J3
H32 GND GND W26 AE18 GND GND AV14 AF12 VDD VDD AY39 W9 FBVDDQ FBVDDQ J30
H34 GND GND W28 AE20 GND GND AV17 AF14 VDD VDD AY40 Y34 FBVDDQ FBVDDQ J31
H39 GND GND W8 AE22 GND GND AV2 AF16 VDD VDD AY41 Y9 FBVDDQ FBVDDQ J32
H41 GND GND Y11 AE24 GND GND AV35 AF18 VDD VDD AY42 FBVDDQ J33
H7 GND GND Y13 AE26 GND GND AV5 AF20 VDD VDD BA37 FBVDDQ J34
K35 GND GND Y15 AE28 GND GND AV8 AF22 VDD VDD BA38 FBVDDQ J4
K37 GND GND Y17 AF11 GND GND AW19 AF24 VDD VDD BA39 FBVDDQ J5
L12 GND GND Y19 AF13 GND GND AW21 AF26 VDD VDD BA40 FBVDDQ J6
L14 GND GND Y2 AF15 GND GND AW22 AF28 VDD VDD BA41 FBVDDQ J7
L16 GND GND Y21 AF17 GND GND P38 AG11 VDD VDD BA42 FBVDDQ J8
L18 GND GND Y23 AF19 GND GND P39 AG13 VDD VDD BB37 FBVDDQ J9
L20 GND GND Y25 AF2 GND GND P41 AG15 VDD VDD BB39 FBVDDQ K1
L22 GND GND Y27 AF21 GND GND P5 AG17 VDD VDD BB40 FBVDDQ K2
L24 GND GND Y4 AF23 GND GND R12 AG19 VDD VDD BB41 FBVDDQ K3
L26 GND GND Y5 AF25 GND GND R14 AG21 VDD VDD L11 FBVDDQ K34
L28 GND GND P25 AF27 GND GND R16 AG23 VDD VDD L13 AC39 GND_OPT FBVDDQ K4
L38 GND GND P27 AF35 GND GND R18 AG25 VDD VDD L15 AC41 GND_OPT FBVDDQ K5
3 L39 GND GND AL9 AF41 GND GND R20 AG27 VDD VDD L17 AD36 GND_OPT FBVDDQ K6 3
L41 GND GND AK9 AF5 GND GND R22 AG28 VDD VDD L19 B26 GND_OPT FBVDDQ L34
M11 GND AF7 GND GND R24 AH12 VDD VDD L21 B29 GND_OPT FBVDDQ L9
M13 GND AG12 GND GND R26 AH14 VDD VDD L23 C3 GND_OPT FBVDDQ M34
M15 GND AG14 GND GND R28 AH16 VDD VDD L25 D26 GND_OPT FBVDDQ M9
AG16 GND GND R35 AH18 VDD VDD L27 D29 GND_OPT FBVDDQ N34
AG18 GND GND R7 AH20 VDD VDD M12 E2 GND_OPT FBVDDQ N9
AG20 GND GND T11 AH22 VDD VDD R19 G25 GND_OPT
AG22 GND GND T13 AH24 VDD VDD R21 G30 GND_OPT
AG24 GND GND T15 AH26 VDD VDD R23 H3 GND_OPT
AG26 GND GND T17 AH27 VDD VDD R25 L2 GND_OPT
GND GND AG36 GND GND T19 AH28 VDD VDD R27 L4 GND_OPT
AH11 GND GND T21 AM34 VDD VDD T12 M7 GND_OPT
AH13 GND GND T23 M14 VDD VDD T14 W36 GND_OPT
AH15 GND GND T25 M16 VDD VDD T16 Y39 GND_OPT
AH17 GND GND T27 M18 VDD VDD T18 Y41 GND_OPT
AH19 GND GND T36 M20 VDD VDD T20
AH21 GND GND T8 M22 VDD VDD T22
AH23 GND GND U12 M24 VDD VDD T24
AH25 GND GND U14 M26 VDD VDD T26
AH35 GND GND U16 M28 VDD VDD T28 FBVDDQ_SENSE AR31
AJ2 GND GND U18 N11 VDD VDD U11 GND FB_GND_PROBE AR30
AJ38 GND GND U2 N13 VDD VDD U13
AJ39 GND GND U20 N15 VDD VDD U15 FB_CLAMP AJ34
AJ41 GND GND U22 N17 VDD VDD U17
AJ5 GND GND U24 N19 VDD VDD U19 FB_VREF H33
AJ7 GND GND P21 N21 VDD VDD U21 FBVDDQ
AK35 GND GND P23 N23 VDD VDD U23
AL35 GND N25 VDD VDD U25 FB_CAL_PD_VDDQ U35 FB_CAL_PD_VDDQ 1R576 40.2ohm
2
AM2 GND N27 VDD VDD U27 0402 1% COMMON
4 AM38 GND P12 VDD VDD V12 FB_CAL_PU_GND N35 FB_CAL_PU_GND 1R574 40.2ohm
2 GND 4
AM39 GND P14 VDD VDD V14 0402 1% COMMON
P16 VDD VDD V16 FB_CALTERM_GND Y35 FB_CAL_TERM_GND 1R578 60.4ohm
2
P18 VDD VDD V18 0402 1% COMMON
P20 VDD VDD V20
P22 VDD VDD V22
GND GND P24 VDD VDD V24
P26 VDD VDD V26 GND
P28 VDD VDD V28
R11 VDD VDD W11
R13 VDD VDD W13
R15 VDD VDD W15
R17 VDD VDD W17
Y20 VDD VDD W19
Y22 VDD VDD W21
Y24 VDD VDD W23
Y26 VDD VDD W25
Y28 VDD VDD W27
VDD Y12
VDD Y14
VDD Y16
VDD Y18

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 12 of 34
A B C D E F G H
A B C D E F G H

GPU Decoupling

FBVDDQ NVVDD
FBVDDQ

NVVDD

1 1

under GPU under GPU

C654 C655 NVVDD


330uF 330uF near the GPU

1
C635 C627 C596 C597 C594 C180
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF COMMON COMMON
16V 16V 16V 16V 16V 16V 20% 20%
2V 2V
10% 10% 10% 10% 10% 10%
AL-Polymer AL-Polymer
2 X7R X7R X7R X7R X7R X7R under GPU

1
0402 0402 0402 0402 0402 0402
3.5A@105degC,100KHz 3.5A@105degC,100KHz C628 C707
22uF 1uF

1
0.006ohm 0.006ohm C735
COMMON COMMON COMMON COMMON COMMON COMMON
SMD_7343 SMD_7343 22uF
6.3V 6.3V
20% 10% 6.3V
X5R X5R

2
20%
0805 0402 X5R

2
1

1
C591 C592 C598 C610 C656 C647 C138 C588 C618 COMMON COMMON 0805
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF COMMON
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V GND
10% 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R
2

2
0402 0402 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
1

1
C587 C630 C642 C564 C565 C552 C563

1
C615 C614 C692 C626 C644 C604 C608 C700
4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R 10% 10% 10% 10% 10% 10% 10% 10%
2

2
X5R X5R X5R X5R X5R X5R X5R X5R

2
0603 0603 0603 0603 0603 0603 0603
0402 0402 0402 0402 0402 0402 0402 0402
2 COMMON COMMON COMMON COMMON COMMON COMMON COMMON 2
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

Spare

1
C688 C663 C605 C676 C625 C645 C664 C699
1uF 1uF 0.1uF 1uF 1uF 1uF 1uF 1uF

1
C657 C698 C691 C669
1uF 1uF 1uF 1uF
1

1
C590 C577 C662 C589 C643 C651 6.3V 6.3V 16V 6.3V 6.3V 6.3V 6.3V 6.3V
1uF 1uF 1uF 1uF 1uF 1uF 6.3V 6.3V 6.3V 6.3V 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X7R X5R X5R X5R X5R X5R

2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10% 10% 10% 10%
X5R X5R X5R X5R 0402 0402 0402 0402 0402 0402 0402 0402

2
10% 10% 10% 10% 10% 10%
0402 0402 0402 0402 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
X5R X5R X5R X5R X5R X5R
2

2
0402 0402 0402 0402 0402 0402 COMMON COMMON COMMON COMMON
COMMON COMMON COMMON COMMON COMMON COMMON

GND

GND

1
C638 C689 C670 C641 C607 C675 C697 C682

1
C706
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF
16V 16V 16V 16V 16V 16V 16V 16V
16V
10% 10% 10% 10% 10% 10% 10% 10%
10%
X7R X7R X7R X7R X7R X7R X7R X7R

2
X7R

2
0402 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON 0402
COMMON

GND

1
3 C631 C640 C648 C616 3
1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10%
X5R X5R X5R X5R

2
0402 0402 0402 0402
COMMON COMMON COMMON COMMON

Place under/near the GPU

GND
1

C600
1

C695 C585 C562 C586 C579 C561 C559


10uF
10uF 10uF 10uF 22uF 22uF 22uF 22uF
6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20%
20% 20% 20% 20% 20% 20% 20%
X5R
2

X5R X5R X5R X5R X5R X5R X5R


2

0805
0805 0805 0805 0805 0805 0805 0805
COMMON
COMMON COMMON COMMON COMMON COMMON COMMON COMMON

1
C649 C701 C690 C606 C613
1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R

2
GND 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON

GND
4 4

1
C709 C623 C658 C710 C708 C624
1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R

2
0402 0402 0402 0402 0402 0402
IOVDD COMMON COMMON COMMON COMMON COMMON COMMON

GND
1

C666 C668 C673 C667 C87 C687 C123 C671 C733 C681
4.7uF 4.7uF 4.7uF 2.2uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
6.3V 6.3V 6.3V 6.3V 6.3V 16V 16V 16V 16V 16V
20% 20% 20% 20% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X7R X7R X7R X7R X7R
2

0603 0603 0603 0402 0402 0402 0402 0402 0402 0402
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
Under GPU Near GPU

NVVDD 90uF + 1x 330uF 88uF


GND near the GPU
SVVDD 32uF 22uF

Combined (Maxwell) 122uF + 1x 330uF 110uF


1

1
C747 C794 C749 C744
10uF 22uF 47uF 47uF
6.3V 6.3V 6.3V 4V
5 20% 20% 20% 20% 5
X5R X5R X5R X5R
2

2
0805 0805 1206 0805
COMMON COMMON COMMON COMMON

MICRO-STAR INT'L CO.,LTD


GND
MS-V32015ci203
MS-V320
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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 13 of 34
A B C D E F G H
A B C D E F G H

DACA Interface
NV3V3

15 IN
Q11B

5
G
@discrete.q_fet_n_enh(sym_2):page14_i681
SOT363

D
COMMON

nv_res

3
1 GENERIC_SEZ1 GENERIC_SEZ1 1
GENERIC_SEZ1 1R620 56ohm
2 DACA_I2C_SCL_R 1 R57 0ohm
2 DACA_I2C_SCL_R1 LB1 0.068uH DACA_I2C_SCL_DVI
15
BI
0402 5% COMMON 04020.05 ohm COMMON GENERIC_SEZ1 0603 COMMON

1
C50
R777 R52 2.2pF
NV3V3
2.2k 2.2k
50V
5% 5%
0402 0402
5V 0.1pF
C0G

2
COMMON COMMON
Q11A 0402
COMMON

2
G
@discrete.q_fet_n_enh(sym_2):page14_i682
R776 SOT363
R60

D
2.2k COMMON
2.2k GND
5%
5%
0402 nv_res

6
0402
COMMON
COMMON
GENERIC_SEZ1 GENERIC_SEZ1
GENERIC_SEZ1 1R640 56ohm
2 DACA_I2C_SDA_R 1 R65 0ohm
2 DACA_I2C_SDA_R1 LB2 0.068uH DACA_I2C_SDA_DVI
15
BI
0402 5% COMMON 04020.05 ohm COMMON GENERIC_SEZ1 0603 COMMON

1
C59
2.2pF
50V
0.1pF
C0G

2
0402
COMMON
15 IN

GND

2 2

GENERIC_SEZ1
GENERIC_SEZ1 L1 0.027uH DACA_HS_DVI
OUT 15
5V 0603 COMMON

1
C55
2.2pF

5
D503B 50V
@discrete.d_3pin_ac(sym_1):page14_i669 0.1pF
3 C0G

2
0.215A
100V 0402
SC70-6_DUAL COMMON
COMMON

4
GND

GND

GENERIC_SEZ1 L5 0.027uH DACA_VS_DVI


FB_IFP_ABCDEF_PLLVDD
OUT 15
5V 0603 COMMON
15,16,18,19 IN

1
C56
R176 U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 2.2pF

2
0ohm G1J D503A 50V
@digital.u_gpu_gb2b_192(sym_5):page14_i659 0.1pF
@discrete.d_3pin_ac(sym_1):page14_i672
BGA1428
6 C0G

2
0402 0.215A
COMMON
COMMON 100V 0402
5/18 DAC SC70-6_DUAL COMMON
COMMON
DACA_VDD AR18 AU7 DACA_I2C_SCL

1
DACA_VDD I2CA_SCL
3 AY5 DACA_I2C_SDA GND 3
I2CA_SDA
DACA_VREF AT18 DACA_VREF
1

C757 C720 C124 C125 DACA_RSET AT19 AU18 DACA_HSYNC GND


0.1uF 0.1uF 0.1uF 0.1uF DACA_RSET DACA_HSYNC
AV18 DACA_VSYNC
DACA_VSYNC
1

16V 16V 16V 16V C736 R662


10% 10% 10% 10% 0.1uF 124ohm
X7R X7R X7R X7R DAC_RGB
2

16V 1% DACA_RED L2 0.027uH DACA_RED_DVI


0402 0402 0402 0402 0402 DACA_RED BB16 DAC_RGB 15
10% OUT
COMMON COMMON COMMON COMMON 0603 COMMON
X7R COMMON
2

0402 BA16 DACA_GREEN


DACA_GREEN DAC_RGB

1
COMMON R58 C61 C53
DACA_BLUE 75ohm 22pF 2.2pF
DACA_BLUE BB15 DAC_RGB
1% 50V 50V
0402 5% 0.1pF
COMMON C0G C0G

2
GND 0402 0402
GND COMMON COMMON

GND GND GND

DAC_RGB
L3 0.027uH DACA_GREEN_DVI
OUT 15
0603 COMMON

1
R59 C62 C54
75ohm 22pF 2.2pF
1% 50V 50V
0402 5% 0.1pF
COMMON C0G C0G

2
0402 0402
4 COMMON COMMON 4

GND GND GND

DAC_RGB
L4 0.027uH DACA_BLUE_DVI
OUT 15
0603 COMMON

1
R55 C57 C52
75ohm 22pF 2.2pF
1% 50V 50V
0402 5% 0.1pF
COMMON C0G C0G

2
0402 0402
COMMON COMMON

GND GND GND

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 14 of 34
A B C D E F G H
A B C D E F G H

IFPAB DVI-I-DL

14 BI

DACA_I2C_SDA_DVI
14 BI
1 1

U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1K
@digital.u_gpu_gb2b_192(sym_6):page15_i507
BGA1428
COMMON

6/18 IFPAB
nv_res DDC_5V
nv_res
GK106 GM206
AP10 IFPA_AUX_SDA 1R645 0ohm
2 DACA_I2C_SDA_R
NC IFPA_AUX_SDA BI 14
AP11 IFPA_AUX_SCL GENERIC_SEZ1 1R613 0ohm
2 0402 COMMON
0.05 ohm DACA_I2C_SCL_R
NC IFPA_AUX_SCL BI 14
GENERIC_SEZ1 0402 COMMON
0.05 ohm

1
C49
4.7nF
NC IFPB_AUX_SDA AP12
FB_PLLVDD 16V
4,9 NC IFPB_AUX_SCL AP13
IN 10%
X5R

2
0402
DNI SHIELD1
25
SHIELD2
26
IOVDD DP_SIGNALS
SHIELD3
27
DP LVDS/DVI/HDMI DP_SIGNALS GND SHIELD4
28

PEX_VDD BB10 IFPAB_TXC* C962


1 0.1uF
2 IFPAB_TXD0_C* TX0-
17
IFPA_TXC DP_SIGNALS DP_SIGNALS J6
2 R579 LB502 DPA_L3 BB9 IFPAB_TXC COMMON C957
1 0.1uF
2 IFPAB_TXD0_C TX0+
18 2
Kepler IFPA_TXC DP_SIGNALS DP_SIGNALS
0ohm 30ohm TX1- @electro_mechanic.con_dvi_i(sym_8):page15_i508
Maxwell Kepler COMMON
DP_SIGNALS IFPAB_TXD1_C* 9
R173 1R661 1k 2IFPAB_RSET AT16 IFPAB_TXD1_C TX1+
10
17 9 1 DVI_I_(SLIM_)SHLD_B
0603 COMMON
0ohm IFPAB_RSET DP_SIGNALS
0402 1% COMMON BA9 IFPAB_TXD0* C931
1 0.1uF
2 IFPAB_TXD2_C* TX2-
1 DVI_I_TALL_9SHLD
COMMON BEAD_0603 IFPA_TXD0 DP_SIGNALS DP_SIGNALS
DPA_L2 AY9 IFPAB_TXD0 COMMON C933
1 0.1uF
2 IFPAB_TXD2_C TX2+
2 COMMON
Colayout 0603 IFPA_TXD0 DP_SIGNALS DP_SIGNALS
COMMON
COMMON SHLD24
3
GND SHLD13
11
1R174 0ohm
2 IFPAB_PLLVDD AR17 BB13 IFPAB_TXD1* C929
1 0.1uF
2 SHLD05
19
IFPAB_PLLVDD IFPA_TXD1 DP_SIGNALS
0402 COMMON DPA_L1 BB12 IFPAB_TXD1 COMMON C930
1 0.1uF
2 IFPAB_TXD4_C* TX3-
12
IFPA_TXD1 DP_SIGNALS
Unstuff for Kepler COMMON IFPAB_TXD4_C TX3+
13
1

C719 C128 IFPAB_TXD5_C* TX4-


4
1uF 0.1uF IFPAB_TXD2* C927 0.1uF TX4+
IFPA_TXD2 AY10 DP_SIGNALS 1 2 IFPAB_TXD5_C 5
FB_IFP_ABCDEF_PLLVDD 6.3V 16V DPA_L0 IFPAB_TXD2 C928 0.1uF TX5-
14,16,18,19 IFPA_TXD2 BA10 DP_SIGNALS
COMMON 1 2 IFPAB_TXD6_C* 20
OUT 10% 10%
COMMON IFPAB_TXD6_C TX5+
21
X5R X7R
2

0402 0402 DACA_I2C_SCL_DVI DDCC


6
COMMON COMMON BA12 DDCD
7
IFPA_TXD3
IFPA_TXD3 AY12 VDDC
14
PEX_VDD 3V3_BLK GND
15
SHLDC
22
IFPB_TXC AV16 IFPAB_TXC_C* TXC-
24
GND DPB_L3 AU16 IFPAB_TXC_C TXC+
23
R172 R171 IFPB_TXC
DACA_VS_DVI VSYNC
8
0ohm 0ohm 14 IN
DVIA_HPD_C HPD
Kepler AT15 IFPAB_IOVDD 16
24 16 8
AR16 BA13 IFPAB_TXD4* C935
1 0.1uF
2
0402 Maxwell 0402 IFPAB_IOVDD IFPB_TXD4 DP_SIGNALS DP_SIGNALS
DPB_L2 AY13 IFPAB_TXD4 COMMON C944
1 0.1uF
2 DACA_RED_DVI R C1
COMMON COMMON IFPB_TXD4 DP_SIGNALS DP_SIGNALS 14 IN
AR14 COMMON DACA_GREEN_DVI G C2
IFPB_IOVDD 14 IN
IFPAB_IOVDD AR15 IFPB_IOVDD
DACA_BLUE_DVI B C3
IFPAB_TXD5* C926 0.1uF 14 IN
AGND1 C3 C1
IFPB_TXD5 AW13 DP_SIGNALS 1 2 DP_SIGNALS C5
DPB_L1 AY14 IFPAB_TXD5 COMMON C925
1 0.1uF
2
IFPB_TXD5 DP_SIGNALS DP_SIGNALS
1

C121 C718 C717 C127 COMMON AGND2


C5A
C5 C5A

4.7uF 1uF 0.1uF 0.1uF DACA_HS_DVI HSYNC


3
14 C4 3
6.3V 6.3V 16V 16V C948 0.1uF IN C4 C2
AY15 IFPAB_TXD6* 1 2
20% 10% 10% 10% IFPB_TXD6 DP_SIGNALS DP_SIGNALS
DPB_L0 AW14 IFPAB_TXD6 COMMON C952
1 0.1uF
2 SHIELD5
29
X5R X5R X7R X7R IFPB_TXD6 DP_SIGNALS DP_SIGNALS
2

0603 0402 0402 0402 COMMON SHIELD6


30
COMMON COMMON COMMON COMMON SHIELD7
31
AU15 SHIELD8
32
IFPB_TXD7
IFPB_TXD7 AV15 SHIELD9
33

GND

IFPAB GND

499ohm
2 R833
1 IFPAB_TXC_C*
NV3V3 COMMON 1% 0402
499ohm
2 R830
1 IFPAB_TXC_C U100 U101
COMMON 1% 0402 IFPAB_TXD0_C 1 NC 10 IFPAB_TXD0_C IFPAB_TXD4_C* 1 NC 10 IFPAB_TXD4_C*
499ohm
2 R795
1 IFPAB_TXD0_C* IFPAB_TXD0_C* 2
R63 NC 9 IFPAB_TXD0_C* IFPAB_TXD4_C 2 NC 9 IFPAB_TXD4_C
COMMON 1% 0402
10k 499ohm R799 IFPAB_TXD0_C
2 1 IFPAB_TXD1_C 4 7 IFPAB_TXD1_C IFPAB_TXD6_C 4 7 IFPAB_TXD6_C
5% NC NC
0402
COMMON 1% 0402 IFPAB_TXD1_C* 5 NC 6 IFPAB_TXD1_C* IFPAB_TXD6_C* 5 NC 6 IFPAB_TXD6_C*
COMMON
499ohm
2 R786
1 IFPAB_TXD1_C*
PLACE CLOSE COMMON 1% 0402 ESD-ESD3V3U4ULC-RH ESD-ESD3V3U4ULC-RH

8
GPIO14_IFPA_HPD 3 TO CONNECTOR 499ohm
2 R790
1 IFPAB_TXD1_C
21 OUT C VVVV32020 VVVV32020
4 Q520 COMMON 1% 0402 4
1 B DVIA_HPD_R_Q 1
@discrete.q_npn(sym_1):page15_i376 1 R62 100k2 DVIA_HPD_R 1 R51 0ohm
2 499ohm
2 R780
1 IFPAB_TXD2_C* D0G-05A0300-I14 D0G-05A0300-I14
SOT23_1B1C1E
0402 5% COMMON 0603 COMMON COMMON 1% 0402 ESD_2_5X1 ESD_2_5X1
COMMON
2 E 499ohm
2 R783
1 IFPAB_TXD2_C COMMON COMMON
1

R61 C63 C58 COMMON 0402


1%
100k 220pF 220pF 499ohm R804 IFPAB_TXD4_C*
2 1
5% 50V 50V
COMMON 1% 0402
0402 5% 5%
COMMON
499ohm
2 R808
1 IFPAB_TXD4_C U102 U103
C0G C0G
2

0402 0402 COMMON 1% 0402 IFPAB_TXD5_C 1 NC 10 IFPAB_TXD5_C IFPAB_TXC_C* 1 NC 10 IFPAB_TXC_C*


499ohm
2 R779
1 IFPAB_TXD5_C* IFPAB_TXD5_C* 2 NC 9 IFPAB_TXD5_C* IFPAB_TXC_C 2 NC 9 IFPAB_TXC_C
COMMON DNI

GND COMMON 1% 0402


499ohm
2 R778
1 IFPAB_TXD5_C IFPAB_TXD2_C* 4 7 IFPAB_TXD2_C* 4 7
NC NC
GND GND GND COMMON 1
1% 0402 IFPAB_TXD2_C 5 NC 6 IFPAB_TXD2_C 5 NC 6
NV3V3 499ohm
2 R812
1 IFPAB_TXD6_C*
COMMON 1% 0402 ESD-ESD3V3U4ULC-RH ESD-ESD3V3U4ULC-RH

8
IFPAB_TERM_CM 499ohm
2 R824
1 IFPAB_TXD6_C
0.406 COMMON 1% 0402 VVVV32020 VVVV32020
0V
D0G-05A0300-I14 D0G-05A0300-I14
1G1D1S 3 ESD_2_5X1 ESD_2_5X1
D Q522 COMMON COMMON
@discrete.q_fet_n_enh(sym_2):page15_i384
SOT23_1G1D1S
1G COMMON
S 2
60V
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W
20V

GND
5 5

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 15 of 34
A B C D E F G H
A B C D E F G H

Page18: IFPEF with IFPE DP


Two cases to be considered: DP_PWR_EF

1. DP AUX to DP connector: AUX AC coupled


2. DP AUX to DP-DVI dongle: AUX pass through
R836
100k

1
5% C972
0402 0.1uF

2
COMMON D512
16V
@discrete.d_3pin_ac(sym_1):page16_i380
C965 0.1uF 10%
1 1 2 3 0.1A X7R
1

2
0402 16V 100V
0402
SOT23
10% DNI
DNI
X7R

1
COMMON

GND
IFPE_AUX_BYP* GENERIC_DEZ1 NV12V
NV3V3
Q528A Q528B

4
@discrete.q_fet_n_enh(sym_2):page16_i445 @discrete.q_fet_n_enh(sym_2):page16_i444 GND
R849

D
S
SOT363 SOT363
10k

S
COMMON COMMON
5% R858

2 G
0402 4.7k

5G
COMMON
5%
0402
IFPE_MODE 3 1B1C1E COMMON
Q529B C
5B IFPE_MODE*
@discrete.q_npn(sym_1):page16_i448 6 1B1C1E

1
C975 SOT363
Q529A C
10nF COMMON
4 E 2 B IFPE_MODE_R
@discrete.q_npn(sym_1):page16_i449 1R844 4.7k2
16V SOT363
0402 5% COMMON

G
COMMON

5
10%
Q526A Q526B

G
X7R 1 E

2
D
0402

S
@discrete.q_fet_n_enh(sym_2):page16_i447 @discrete.q_fet_n_enh(sym_2):page16_i446

D
COMMON
SOT363 SOT363

2
COMMON COMMON D513
@discrete.d_3pin_ac(sym_1):page16_i373

4
IFPE_AUX_BYP GENERIC_DEZ1 3 0.1A GND GND GND
100V
SOT23
DNI
2 DP_PWR_EF 2

1
R837
100k
C966 0.1uF 5%
1 2 0402
0402 16V COMMON
10%
X7R
J3 DP_PWR_EF
COMMON

R862 R851 IFPE_C_HPD_C 18 Hot_Det 20


DP_PWR
100k 100k

1
C964
GND
5% 5% 0.1uF
0402 0402
17 AUX_CHn
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 AUX_CHp 16V
G1L COMMON COMMON 15
10%
@digital.u_gpu_gb2b_192(sym_9):page16_i431 X7R

2
BGA1428 0402
COMMON ML_Lane_3n
12 COMMON

9/18 IFPEF 10 ML_Lane_3p

GND GND
DVI-DL DVI/HDMI DP 9 ML_Lane_2n
GND
7 ML_Lane_2p

AW4 IFPE_AUX* IFPE_AUX_C*


IFPE_AUX_SDA IFPE_AUX_C GENERIC_DEZ1 GENERIC_DEZ1 IFPE_AUX_C
AY4 IFPE_AUX IFPE_AUX_C 6 ML_Lane_1n
IFPE_AUX_SCL IFPE_AUX_C GENERIC_DEZ1 GENERIC_DEZ1 IFPE_AUX_C
4 ML_Lane_1p

IFPE_MODE_C
IFPE_L3 AU2 IFPE_L3*
DP_SIGNALS 1C12 0.1uF
2 DP_SIGNALS
IFPE_L3_C* 3 ML_Lane_0n
TXC
1R594 1k 2IFPEF_RSET AR8 IFPEF_RSET IFPE_L3 AU3 IFPE_L3 DP_SIGNALS
COMMON 1C16 0.1uF
2 DP_SIGNALS
IFPE_L3_C 1 ML_Lane_0p
TXC R838
0402 1% COMMON MEC1
MEC1 1M
COMMON IFPE_L2 AT1 IFPE_L2*
DP_SIGNALS 1C18 0.1uF
2 DP_SIGNALS
IFPE_L2_C*
TXD0 AU1 IFPE_L2 COMMON 1C27 0.1uF
2 IFPE_L2_C 5%
TXD0 IFPE_L2 DP_SIGNALS DP_SIGNALS 0402
GND COMMON
COMMON

14,15,18,19
FB_IFP_ABCDEF_PLLVDD AT8 IFPEF_PLLVDD IFPE_L1 AW1 IFPE_L1* DP_SIGNALS 1C37 0.1uF
2 DP_SIGNALS
IFPE_L1_C*
IN TXD1
3 IFPE_L1 AY2 IFPE_L1 DP_SIGNALS
COMMON 1C41 0.1uF
2 DP_SIGNALS
IFPE_L1_C PWR_RTN 19 3
TXD1 COMMON
X1 X1
1

C716 AT3 IFPE_L0* 1C44 0.1uF


2 IFPE_L0_C* X2
0.1uF TXD2 IFPE_L0 DP_SIGNALS DP_SIGNALS X2

16V
IFPE TXD2 IFPE_L0 AT2 IFPE_L0
DP_SIGNALS
COMMON 1C46 0.1uF
2 DP_SIGNALS
IFPE_L0_C
X3 X3 GND
COMMON 13 MODE X4
X4
10%
X7R GND_0 2
2

0402 NV3V3 GND_1 5


COMMON
GND_2 8
GND_3 11
R54 14 16
CEC GND_6
10k
PEX_VDD
5%
GND 0402
DP_W/GASKET
COMMON
not found Hotplug Detection PLACE CLOSE VVVV32020
AN7 3 TO CONNECTOR N5W-20M0610-A43
IFPEF_IOVDD 1B1C1E GND
AN8 Q521 C
IFPEF_IOVDD
DVI-DL DVI/HDMI DP 1B
@discrete.q_npn(sym_1):page16_i326 IFPE_C_HPD_R_Q 1 R53 100k2 IFPE_C_HPD_R 1 R50 0ohm
2
1

C752 C714 C763 AP7 SOT23_1B1C1E


0402 COMMON 0603 COMMON
IFPF_IOVDD COMMON 5%
4.7uF 1uF 0.1uF IFPF_AUX*
AP8 IFPF_IOVDD IFPF_AUX_SDA AY3 17 2 E

1
6.3V 6.3V 16V BI R56 C60 C960
BA3 IFPF_AUX
20% 10% 10% IFPF_AUX_SCL BI 17 100k 220pF 220pF
X5R X5R X7R
nv_cap nv_cap nv_cap nv_cap nv_cap
2

DP_PWR_EF
0603 0402 0402
5% 50V 50V Quadro
0402 5% 5%
COMMON COMMON COMMON AU9 IFPF_L3*
TXC IFPF_L3 17 COMMON C0G C0G

2
BI
AU8 IFPF_L3 0402 0402
TXC IFPF_L3 BI 17
GND COMMON DNI
AY8 IFPF_L2*

1
TXD3 TXD0 IFPF_L2 BI 17 C5 C4 C7 C2 C3
GND AW8 IFPF_L2 22uF 22uF 22uF 22uF 22uF
TXD3 TXD0 IFPF_L2 BI 17
GND GND GND 6.3V 6.3V 6.3V 6.3V 6.3V
AW9 IFPF_L1* 20% 20% 20% 20% 20%
TXD4 TXD1 IFPF_L1 BI 17
AV9 IFPF_L1 X5R X5R X5R X5R X5R

2
TXD4 TXD1 IFPF_L1 BI 17 0805 0805 0805 0805 0805
4 4
COMMON COMMON COMMON COMMON COMMON
AV10 IFPF_L0*
TXD5 TXD2 IFPF_L0 BI 17
IFPF TXD5 TXD2 IFPF_L0 AU10 IFPF_L0
BI 17

NV3V3

GND
Fused DP_PWR
DP-SKU
R1654
4.7k
U508 DP_PWR_EF
3V3_F 5%
@analog.u_sw_pwr_tps2031(sym_1):page16_i338
0402
SO8 3.3V
COMMON
COMMON 1.0A
2 IN OUT 8 0.406
3 IN OUT 7

1
6 R825 C949 C958
OUT 4.7k 0.1uF 22uF

1
C934 Desktop
0.1uF 5% 16V 6.3V
1R801 10k 2 3V3_DP_PWR_EF_EN 4 EN 0402
16V 10% 20%
0402 5% COMMON COMMON X7R X5R

2
10%
X7R 5 OC* GND 1 0402 0805

2
0402 COMMON COMMON
COMMON

GND GND GND GND


GPIO18_IFPE_HPD
21 OUT
GND GND

5 5

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 16 of 34
A B C D E F G H
A B C D E F G H

IFPF DP

Two cases to be considered: DP_PWR_EF

1 1. DP AUX to DP connector: AUX AC coupled 1

2. DP AUX to DP-DVI dongle: AUX pass through


R839
100k

1
5% C973
0402 0.1uF

2
COMMON D514
16V
@discrete.d_3pin_ac(sym_1):page17_i45
C967 0.1uF 10%
1 2 3 0.1A X7R

2
0402 16V 100V
0402
SOT23
10% DNI
DNI
X7R

1
COMMON

GND
IFPF_AUX_BYP* NV12V
GENERIC_DEZ1

Q530A Q530B NV3V3

4
@discrete.q_fet_n_enh(sym_2):page17_i98 @discrete.q_fet_n_enh(sym_2):page17_i97 GND
R850

D
S
SOT363 SOT363
10k

S
COMMON COMMON
5% R859

2 G
0402 4.7k

5G
COMMON
5%
0402
IFPF_MODE 6 1B1C1E COMMON
Q531A C
2B IFPF_MODE*
@discrete.q_npn(sym_1):page17_i100 3 1B1C1E

1
C976 SOT363
Q531B C
10nF COMMON
1 E 5 B IFPF_MODE_R
@discrete.q_npn(sym_1):page17_i99 1R845 4.7k2
16V SOT363
2 0402 5% COMMON 2

G
COMMON

5
10%
Q527A Q527B

G
X7R 4 E

2
D
0402

S
@discrete.q_fet_n_enh(sym_2):page17_i96 @discrete.q_fet_n_enh(sym_2):page17_i95

D
COMMON
SOT363 SOT363

2
COMMON COMMON D515
@discrete.d_3pin_ac(sym_1):page17_i38

4
IFPF_AUX_BYP 3 0.1A GND GND GND
GENERIC_DEZ1
100V
SOT23
DNI

1
R840
100k
C968 0.1uF 5%
1 2 0402
0402 16V COMMON
10%
X7R
DP_PWR_EF DP_PWR_EF
COMMON

R863 R852
100k 100k

1
C963
5% 5% 0.1uF
0402 0402 GND
16V
COMMON COMMON
10%
X7R

2
0402
COMMON
J4

GND GND
IFPF_HPD_C 18 Hot_Det 20 GND
DP_PWR

IFPF_AUX* IFPF_AUX_C* 17
16 BI IFPF_AUX_C GENERIC_DEZ1 IFPF_AUX_C GENERIC_DEZ1 AUX_CHn
IFPF_AUX IFPF_AUX_C GENERIC_DEZ1
IFPF_AUX_C IFPF_AUX_C GENERIC_DEZ1 15 AUX_CHp
16 BI
3 3
IFPF_MODE_C
IFPF_L3* C953
1 0.1uF
2 IFPF_L3_C* 12 ML_Lane_3n
16 DP_SIGNALS DP_SIGNALS
BI C954 0.1uF
IFPF_L3 COMMON 1 2 IFPF_L3_C 10 ML_Lane_3p
16 BI DP_SIGNALS DP_SIGNALS
COMMON R841
IFPF_L2* C950 0.1uF IFPF_L2_C* 1M
16 DP_SIGNALS 1 2 DP_SIGNALS 9 ML_Lane_2n
BI C951 0.1uF 5%
IFPF_L2 COMMON 1 2 IFPF_L2_C 7 ML_Lane_2p
16 DP_SIGNALS DP_SIGNALS 0402
BI
COMMON
COMMON
IFPF_L1* C955
1 0.1uF
2 IFPF_L1_C* 6 ML_Lane_1n
16 BI DP_SIGNALS DP_SIGNALS
IFPF_L1 COMMON C956
1 0.1uF
2 IFPF_L1_C 4 ML_Lane_1p
16 DP_SIGNALS DP_SIGNALS
BI
COMMON
IFPF_L0* C945
1 0.1uF
2 IFPF_L0_C* 3 ML_Lane_0n
16 DP_SIGNALS DP_SIGNALS
BI C946 0.1uF
IFPF_L0 DP_SIGNALS
COMMON 1 2 IFPF_L0_C DP_SIGNALS 1 ML_Lane_0p
GND
16 BI
COMMON MEC1
MEC1
NV3V3

R82
10k
PWR_RTN 19
5%
0402
Hotplug Detection X1 X1
COMMON not found X2 X2
GPIO8_IFPF_HPD 3 X3
21 1B1C1E X3
OUT C
Q16 13 MODE
X4 X4
1B
@discrete.q_npn(sym_1):page17_i5 IFPF_HPD_R_Q 1 R64 100k2 IFPF_HPD_R 1 R49 0ohm
2 GND_0 2
SOT23_1B1C1E
COMMON
0402 5% COMMON 0603 COMMON GND_1 5
2 E GND_2 8
1
R69 C64 11
GND_3
100k 220pF

1
C961 14 16
CEC GND_6
5% 50V 220pF
PLACE CLOSE
0402 5% 50V
COMMON C0G
2

5%
4 TO CONNECTOR DP_W/GASKET 4
GND 0402 C0G

2
COMMON 0402
VVVV32020
DNI N5W-20M0610-A43
GND
GND GND
GND

5 5

MICRO-STAR INT'L CO.,LTD


MS-V32015ci203
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 17 of 34
A B C D E F G H
A B C D E F G H

* I2C to DDC level switching

Page20: IFPC HDMI/DP IFPC_MODE_Q*


NV3V3 DP-SKU ONLY

1
C13
10nF
16V
10%
X7R

2
R16
0402
COMMON
0ohm
DDC_5V HDMI
VVVV32020
0402
ALL COMMON

R843 VVVV32020
NV3V3 DP HDMI GND remove DP colay
0ohm

2
Q5A

G
1 @discrete.q_fet_n_enh(sym_2):page18_i205 1
R11 0402

D
SOT363 COMMON
10k
FOR ESD DIODES 5%
HDMI COMMON XXXV32020 DP DP
VVVV32020

6
0402
DVI_HDMI_SIGNALS COMMON
I2CW_SDA_Q
VVVV32020
IFPC_ESD 1

HDMI

1
C947 IFPC_ESD R829
DP
0.1uF 2k
DP HDMI
16V 5%
DDC_5V 0402

2
10%
X7R D508 D511 COMMON

2
0402 @discrete.d_3pin_ac(sym_1):page18_i47 @discrete.d_3pin_ac(sym_1):page18_i58 VVVV32020
DNI 0.1A 3 3 0.1A DDC_5V
XXXV32020 100V 100V
ALL SOT23 SOT23 R809
NV3V3 DNI DNI
2k

5
Q5B

G
DP HDMI

1
5%
GND @discrete.q_fet_n_enh(sym_2):page18_i207 XXXV32020 XXXV32020 0402
R21 C969

D
Place near ESD diodes 10k SOT363 COMMON
100pF
HDMI COMMON VVVV32020
5% 50V
VVVV32020 GND GND

3
0402 5%
DVI_HDMI_SIGNALS COMMON C0G
I2CW_SCL_Q 0402
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 VVVV32020
DNI
G1M XXXV32020
@digital.u_gpu_gb2b_192(sym_7):page18_i192 J5
BGA1428 GND 19
COMMON
18 HP_DET
DP
17 +5V
7/18 IFPC HDMI
2 GND X1 2
DP
2 1k R639
1 IFPC_RSET AT12 I2CW_SDA_C 16 SHELL1
IFPCD_RSET
COMMON 0402 I2CW_SCL_C 15 SDA X2
1% DVI/HDMI DP DP
VVVV32020 SCL SHELL2
nv_res 14 MEC1
AT13 AV3 I2CW_AUX* 13 NC MEC1
GND IFPCD_PLLVDD IFPC_AUX_SDA
AV4 I2CW_AUX CE Remote
IFPC_AUX_SCL nv_res
FB_IFP_ABCDEF_PLLVDD R1663
1 5.1ohm
2 IFPC_TXC_RC1* 12
14,15,16,19 CK-
1

IN C728 0402 % COMMON


nv_res
5 11
0.1uF IFPC_TXC* C936 0.1uF IFPC_TXC_C1* R1666 5.1ohm CK_Shield
TXC IFPC_L3 AW10 DVI_HDMI_SIGNALS 1 2 DVI_HDMI_SIGNALS 1
VVVV32020 2 IFPC_TXC_RC1 10
16V
AY11 IFPC_TXC 0402 COMMON C937
1 0.1uF
2 IFPC_TXC_C1 0402 COMMON
CK+
10% TXC IFPC_L3 DVI_HDMI_SIGNALS DVI_HDMI_SIGNALS nv_res
5%
0402 COMMON R1661
1 5.1ohm
2
VVVV32020 IFPC_TXD0_RC1* 9
X7R
2

AW12 IFPC_TXD0* C938 0.1uF


1 VVVV32020
2 IFPC_TXD0_C1* 0402 COMMON 8 D0-
0402 IFPC_L2 DVI_HDMI_SIGNALS DVI_HDMI_SIGNALS nv_res
5%
TXD0 IFPC_TXD0 C939 0.1uF IFPC_TXD0_C1 R1667 5.1ohm D0_Shield
COMMON
TXD0 IFPC_L2 AW11 DVI_HDMI_SIGNALS 0402 COMMON 1 VVVV32020
2 DVI_HDMI_SIGNALS VVVV320201 2 IFPC_TXD0_RC1 7
VVVV32020 0402 COMMON 0402 % COMMON
D0+ MEC2
nv_res
5
IFPC IFPC_L1 AV12 IFPC_TXD1* DVI_HDMI_SIGNALS
C940 0.1uF
1 VVVV32020
2 IFPC_TXD1_C1* DVI_HDMI_SIGNALS
R1662
1 5.1ohm
2
VVVV32020 IFPC_TXD1_RC1* 6 MEC2
TXD1 D1-
AU12 IFPC_TXD1 0402 COMMON C941 0.1uF
1 VVVV32020
2 IFPC_TXD1_C1 0402 % COMMON 5 X3
GND TXD1 IFPC_L1 DVI_HDMI_SIGNALS DVI_HDMI_SIGNALS nv_res
5
0402 COMMON R1665
1
VVVV32020 5.1ohm
2 IFPC_TXD1_RC1 4 D1_Shield SHELL3
PEX_VDD AV13 IFPC_TXD2* C942 0.1uF
1 VVVV32020
2 IFPC_TXD2_C1* 0402 % COMMON
D1+ X4
IFPC_L0 DVI_HDMI_SIGNALS DVI_HDMI_SIGNALS nv_res
5
TXD2 IFPC_TXD2 C943 0.1uF IFPC_TXD2_C1 R1660 5.1ohm SHELL4
TXD2 IFPC_L0 AU13 DVI_HDMI_SIGNALS 0402 COMMON 1 VVVV32020
2 DVI_HDMI_SIGNALS 1 2
VVVV32020 IFPC_TXD2_RC1* 3
0402 COMMON 0402 5% COMMON 2 D2-
NV3V3 VVVV32020 R1664
1
VVVV32020 5.1ohm
2 IFPC_TXD2_RC1 1 D2_Shield
1
AR10 VVVV32020 0402 5% COMMON
D2+
IFPCD_IOVDD
AR11 IFPCD_IOVDD VVVV32020 HDMI19PSM_BLACK-RH-5
R5 HDMI_S19_16
U105
1

C711 10k
1

C725 C715 HDMI_C_HPD_R_Q HDMI_C_HPD_R HDMI_C_HPD_C IFPC_TXC_RC1* 1 COMMON


4.7uF
0.1uF 0.1uF 5% 1R847 100k2 1R846 0ohm
2 NC 10 IFPC_TXC_RC1*
IFPC_TXC_RC1 2 VVVV32020
6.3V
16V 16V
VVVV32020
0402 0402 5% COMMON 0603 COMMON NC 9 IFPC_TXC_RC1 GND
N5Y-19M0760-W06
GND
20% COMMON not found VVVV32020 VVVV32020

1
10% 10% GPIO15_IFPC_HPD C970 C971
X5R 3 IFPC_TXD0_RC1* 4 7 IFPC_TXD0_RC1*
2

X7R X7R 21 VVVV32020 1B1C1E


2

0603 OUT
Q2 C 220pF 220pF NC
COMMON
0402 0402 IFPC_TXD0_RC1 5 NC 6 IFPC_TXD0_RC1
50V 50V
3 VVVV32020 COMMON COMMON 1B
@discrete.q_npn(sym_1):page18_i88 3
VVVV32020 VVVV32020 SOT23_1B1C1E 5% 5%
COMMON C0G C0G ESD-ESD3V3U4ULC-RH

8
2 E 0402 0402
R848 VVVV32020
COMMON DNI U106
100k VVVV32020 XXXV32020 D0G-05A0300-I14
GND VVVV32020 IFPC_TXD1_RC1* 1 NC 10 IFPC_TXD1_RC1*
5% ESD_2_5X1
0402 GND IFPC_TXD1_RC1 2 NC 9 IFPC_TXD1_RC1
GND COMMON
COMMON
GND VVVV32020 IFPC_TXD2_RC1* 4 7 IFPC_TXD2_RC1*
NC
IFPC_TXD2_RC1 5 NC 6 IFPC_TXD2_RC1

ESD-ESD3V3U4ULC-RH

8
GND
VVVV32020
nv_ind_noxnet D0G-05A0300-I14
ESD_2_5X1
COMMON
R823
nv_ind_noxnet
R822 R821 R820 R819 R818 R817 R816
499ohm
499ohm 499ohm 499ohm 499ohm 499ohm 499ohm 499ohm
1% nv_ind_noxnet
1% 1% 1% 1% 1% 1% 1%
0402
0402 0402 0402 0402 0402 0402 0402
COMMON
COMMON nv_ind_noxnet
COMMON COMMON COMMON COMMON COMMON COMMON
LB40 600ohm VVVV32020
BEAD_0402 COMMON
IFPC_TERM_BEAD_1 VVVV32020 VVVV32020 VVVV32020
nv_ind_noxnet
VVVV32020 VVVV32020 VVVV32020 VVVV32020 DP FOR QUADRO
VVVV32020 LB41 600ohm
IFPC_TERM_BEAD_2

BEAD_0402 COMMON nv_ind_noxnet


VVVV32020 LB42 600ohm
IFPC_TERM_BEAD_3

BEAD_0402 COMMON nv_ind_noxnet


VVVV32020 LB43 600ohm
IFPC_TERM_BEAD_4

BEAD_0402 COMMON nv_ind_noxnet


VVVV32020 LB44 600ohm
IFPC_TERM_BEAD_5

BEAD_0402 COMMON
4 VVVV32020 LB45 600ohm 4
IFPC_TERM_BEAD_6

BEAD_0402 COMMON
VVVV32020 LB46 600ohm
IFPC_TERM_BEAD_7

BEAD_0402 COMMON
NV3V3 IFPC_TERM_EN_D VVVV32020 LB47 600ohm
IFPC_TERM_BEAD_8

0V BEAD_0402COMMON
NV3V3 1G1D1S 3 0.406 VVVV32020
D Q523
Fused DP_PWR @discrete.q_fet_n_enh(sym_2):page18_i104
SOT23_1G1D1S
DP-SKU 1G COMMON
R1655 S 2 remove DP colay
4.7k 60V
U510 DP_PWR
0.26A
3V3_F 5% 3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
@analog.u_sw_pwr_tps2031(sym_1):page18_i164 0.31A
0402
SO8 3.3V 0.3W
COMMON 20V
COMMON 1.0A VVVV32020
XXXV32020 2 8
IN OUT 0.406
3 IN OUT 7
1

6 R7 C6 C8 C1704 C1705 C1706 C1707 C1708


OUT 4.7k 0.1uF 22uF 22uF 22uF 22uF 22uF 22uF
1

C974
GND
0.1uF 5% 16V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1R855 10k 2 3V3_DP_PWR_EN 4 EN 0402
16V 10% 20% 20% 20% 20% 20% 20%
0402 5% COMMON COMMON X7R X5R X5R X5R X5R X5R X5R
2

10%
X7R
VVVV32020 5 OC* GND 1 VVVV32020 0402 0805 0805 0805 0805 0805 0805
2

0402 COMMON COMMON COMMON COMMON COMMON COMMON COMMON


COMMON VVVV32020 VVVV32020 VVVV32020 VVVV32020 VVVV32020 VVVV32020 VVVV32020 VVVV32020
VVVV32020

GND GND GND GND GND GND GND GND

GND GND USE NVPN 080-0424-000

5 5
560uF change to MLCC 22uFx5

MICRO-STAR INT'L CO.,LTD


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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 18 of 34
A B C D E F G H
A B C D E F G H

IFPD DP

Two cases to be considered: DP_PWR

1 1. DP AUX to DP connector: AUX AC coupled 1

2. DP AUX to DP-DVI dongle: AUX pass through


R834
100k

1
5% C43
0402 0.1uF

2
COMMON D509
16V
@discrete.d_3pin_ac(sym_1):page19_i249
10%
1C38 0.1uF
2 3 0.1A X7R

2
0402 16V 100V
0402
SOT23
10% DNI
DNI
X7R

1
COMMON

GND
IFPD_AUX_BYP* NV12V
GENERIC_DEZ1

Q7A Q7B NV3V3

4
@discrete.q_fet_n_enh(sym_2):page19_i343 @discrete.q_fet_n_enh(sym_2):page19_i345 GND 1
R1

D
S
SOT363 SOT363
10k

S
COMMON COMMON
5% R4

2 G
0402 4.7k

5G
COMMON
5%
0402
DP_MODE 6 1B1C1E COMMON
Q1A C
2B DP_MODE*
@discrete.q_npn(sym_1):page19_i346 3 1B1C1E

1
C1 SOT363
Q1B C
10nF COMMON
1 E 5 B DP_MODE_R
@discrete.q_npn(sym_1):page19_i344 1 R3 4.7k2
16V SOT363
2 0402 5% COMMON 2

G
COMMON

5
10%
Q8A Q8B

G
X7R 4 E

2
D
0402

S
@discrete.q_fet_n_enh(sym_2):page19_i348 @discrete.q_fet_n_enh(sym_2):page19_i347

D
COMMON
SOT363 SOT363

2
COMMON COMMON D510
@discrete.d_3pin_ac(sym_1):page19_i244

4
IFPD_AUX_BYP 3 0.1A GND GND GND
GENERIC_DEZ1
100V
SOT23
DNI

1
R835
100k
5%
1C39 0.1uF
2 0402
0402 16V COMMON
10%
X7R
DP_PWR
COMMON

U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 R800 R796 DP_PWR


G1N 100k 100k

1
C11
@digital.u_gpu_gb2b_192(sym_8):page19_i337 0.1uF
5% 5%
BGA1428 GND
0402 0402 16V
COMMON
COMMON COMMON
10%
8/18 IFPD X7R

2
0402
COMMON
GM206 GK106
1R602 1k 2 IFPD_RSET AT10 NC RSET J1
GND
0402 1% COMMON DVI/HDMI DP GND GND
DP_D_HPD_C 18 Hot_Det 20 GND
DP_PWR
FB_IFP_ABCDEF_PLLVDD

6,18 1R175 0ohm


2 AT9 NC PLLVDD IFPD_AUX_SDA AW3 IFPD_AUX*
IFPD_AUX_C GENERIC_DEZ1
IFPD_AUX_C*
GENERIC_DEZ1 17 AUX_CHn
IN
0402 COMMON IFPD_PLLVDD AW2 IFPD_AUX IFPD_AUX_C 15 AUX_CHp
IFPD_AUX_SCL IFPD_AUX_C GENERIC_DEZ1 GENERIC_DEZ1
3 3
1

C758
DP_MODE_C
0.1uF
TXC IFPD_L3 BA4 IFPD_L3* DP_SIGNALS 1C19 0.1uF
2 IFPD_L3_C* DP_SIGNALS 12 ML_Lane_3n
16V
TXC IFPD_L3 BB4 IFPD_L3
DP_SIGNALS
COMMON 1C20 0.1uF
2 IFPD_L3_C
DP_SIGNALS 10 ML_Lane_3p
10% R6
COMMON
X7R
2

1M
0402 IFPD_L2 AY6 IFPD_L2* DP_SIGNALS 1C21 0.1uF
2 IFPD_L2_C* DP_SIGNALS 9 ML_Lane_2n
TXD0 5%
COMMON
TXD0 IFPD_L2 BA6 IFPD_L2
DP_SIGNALS
COMMON 1C22 0.1uF
2 IFPD_L2_C
DP_SIGNALS 7 ML_Lane_2p
0402
COMMON
IFPD IFPD_L1 BB6 IFPD_L1*
DP_SIGNALS 1C23 0.1uF
2 IFPD_L1_C*
DP_SIGNALS 6 ML_Lane_1n
COMMON
TXD1
GND TXD1 IFPD_L1 BB7 IFPD_L1 DP_SIGNALS
COMMON 1C24 0.1uF
2 IFPD_L1_C DP_SIGNALS 4 ML_Lane_1p
COMMON

IFPD_L0 BA7 IFPD_L0*


DP_SIGNALS 1C25 0.1uF
2 IFPD_L0_C*
DP_SIGNALS 3 ML_Lane_0n
TXD2
PEX_VDD
TXD2 IFPD_L0 AY7 IFPD_L0 DP_SIGNALS
COMMON 1C26 0.1uF
2 IFPD_L0_C DP_SIGNALS 1 ML_Lane_0p
GND
COMMON MEC1
MEC1

AP9 IFPD_IOVDD
AR9 IFPD_IOVDD

PWR_RTN 19
X1 X1
X2 X2
X3 X3
13 MODE
X4 X4
GND_0 2
GND_1 5
NV3V3 GND_2 8
GND_3 11
14 CEC GND_6 16
R10
10k
5% DP_W/GASKET
4 4
0402
COMMON
Hotplug Detection VVVV32020
GPIO17_IFPD_HPD 3 N5W-20M0610-A43
21 OUT
1B1C1E GND
Q3 C
1B DP_D_HPD_R_Q
@discrete.q_npn(sym_1):page19_i307 1 R20 100k2 DP_D_HPD_R 1 R24 0ohm
2
SOT23_1B1C1E
0402 5% COMMON 0603 COMMON
COMMON
2 E

1
R14 C17 C15
100k 220pF 220pF
5% 50V 50V
0402 5% 5%
COMMON C0G C0G

2
GND 0402 0402
COMMON COMMON

GND GND GND

5 5

MICRO-STAR INT'L CO.,LTD


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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 19 of 34
A B C D E F G H
A B C D E F G H

MIOA/SLI Interface

stereo header
DDC_5V

1R165 33ohm
2 STEREO_HDR
0402 5% COMMON
1 1
DDC_5V

1
C116
22pF J7 1
@electro_mechanic.hdr_1x4(sym_1):page20_i917
2
50V
MALE
DDC_5V 3

1
5% 2.0MM C114

5
U7 C0G 4

2
90 0.1uF
0402 PEX_RST_BUF*
1 @logic.u_and_2in(sym_1):page20_i870
STEREO_HDR_R COMMON
NORM
16V 3,32 IN
COMMON
4 1R166 33ohm
2 10%

2
2 X7R

2
SC70-5 0402 5% COMMON D4

1
C115 0402
COMMON @discrete.d_3pin_ac(sym_1):page20_i889 COMMON
0.1uF GND
3 0.1A

3
100V 16V GND
SOT23 10%
DNI X7R

2
GND
0402

1
COMMON

GND
MIOD4_STEREO2_R
1R169 0ohm
2
0402 COMMON
GND ADD TI NPR PART

NV3V3 NV3V3

C120 0.1uF 3V3_F


1 2 3V3_F
0402 16V
10%
R168
X7R
4.7k COMMON
5%
0402 GND

5
2 COMMON U9 2
1 @logic.u_and_2in(sym_1):page20_i864
4

1
C45
2 10nF

1
SC70-5 C959 U1
COMMON 10nF 16V
GPIO19_STEREO_OUT @logic.u_buf_3_state(sym_9):page20_i932
16V 10%

3
21 X7R DFN06_OEH

2
IN 10%
1 R38 0ohm
2 X7R 0402 COMMON

6
0402 COMMON 0402 COMMON

1
1R803 0ohm
2 COMMON VCC
MIOD8_REFCLK2 1 R28 0ohm
2 OE
GND 0402 COMMON
GPIO5_FRAME_LOCK_INT 0402 COMMON MIO_FLREFCLK_R GND
21 1 R48 0ohm
2 2 A O 4
BI GND
1R789 0ohm
2 XTALSSIN_GPU_TRISTATE

1
0402 COMMON U509 NC
1R828 0ohm
2 0402 COMMON @analog.u_lvds_rcvr(sym_1):page20_i923
0402 COMMON SOT23_5 GND
GPIO24_SWAPRDY_OUT R26 3

5
1 R42 0ohm
2 100ohm COMMON R40
21 5 XTALSSIN_R

3
IN
RCVR
22ohm
0402 COMMON 5%
4 5%
1R806 0ohm
2 0402
0402
COMMON
0402 COMMON COMMON
GPIO23_RASTER_SYNC1
21 1R811 0ohm
2 MIOD7_REFCLK2* 1 R34 0ohm
2 GND
BI

2
0402 COMMON 0402 COMMON
MIOHSYNC_FLREFCLK_R*
1 R44 0ohm
2 MIOD3_REFCLK1* 1R794 0ohm
2
0402 COMMON
I2CB_SCL_R 0402 COMMON
21 1 R46 0ohm
2 XTALSSIN_GPU
IN GND
0402 COMMON
MIOD11_I2C_SCL1
OUT 22
1R815 0ohm
2
0402 COMMON
I2CB_SDA_R MIOD10_I2C_SDA2
21 1 R23 0ohm
2
BI
0402 COMMON
1R785 0ohm
2
MIO_SIGNALS
MIOA_D[11..0] 0402 COMMON
3 3

4 MIOA_D4
1 R17 0ohm
2 CN1
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1 0402 COMMON
G1O @electro_mechanic.con_mio_26(sym_10):page20_i786
IOVDD @digital.u_gpu_gb2b_192(sym_10):page20_i956
7 MIOA_D7
1R781 0ohm
2
NONPHY_4GND_LED
BGA1428 0402 COMMON
COMMON COMMON

10/18 MIOA SLI-FL_A - EMI SHIELD


0 MIOA_D0
1R784 0ohm
2 MIOD0_I2C_SDA1 A2 DR<0> | SDA GND B3
MIOAD0 AD4 0 MIOA_D0 1 MIOA_D1 0402 COMMON 1 R43 0ohm
2 MIOD1_RASTER_SYNC2 B4 DR<1> | RSTR_SYNC GND B7
MIOAD1 AD2 1 MIOA_D1 2 MIOA_D2
1R788 0ohm
2 0402 COMMON MIOD2_REFCLK1 A4 DR<2> | REFCLK GND B11
MIOAD2 AD1 2 MIOA_D2
NV3V3 3 MIOA_D3
0402 COMMON 1R793 0ohm
2 A5 DR<3> | REFCLK* GND A3
MIOAD3 AD3 3 MIOA_D3 4 MIOA_D4
1 R37 0ohm
2 0402 COMMON MIOD4_STEREO2 B6 DR<4> | STEREO GND A11
MIOAD4 AF3 4 MIOA_D4 5 MIOA_D5 0402 COMMON 1R797 0ohm
2 A6 DR<5> | SWAPRDY_IN
MIOAD5 AG4 5 MIOA_D5 6 MIOA_D6
1R802 0ohm
2 0402 COMMON MIOD6_STEREO1 A8 DR<6> | STEREO GND 1
MIOAD6 AG2 6 MIOA_D6 7 MIOA_D7
0402 COMMON 1 R33 0ohm
2 B9 DR<7> | REFCLK* GND 2
AF4 7 MIOA_D7
R179 8 MIOA_D8
1 R27 0ohm
2 0402 COMMON B10 3
MIOAD7 1k DR<8> | REFCLK GND
MIOAD8 AG5 8 MIOA_D8 9 MIOA_D9
0402 COMMON 1R810 0ohm
2 MIOD9_RASTER_SYNC1 A10 DR<9> | RSTR_SYNC GND 4
5%
MIOAD9 AG3 9 MIOA_D9
0402
10 MIOA_D10
1 R22 0ohm
2 0402 COMMON B12 DR<10>| SDA
MIOAD10 AH4 10 MIOA_D10 COMMON 11MIOA_D11 0402 COMMON 1R814 0ohm
2 A12 DR<11>| SCL
1R582 49.9ohm
2 MIOA_CAL_PD_VDDQ AD5 MIOACAL_PD_VDDQ MIOAD11 AH1 11 MIOA_D11 0402 COMMON A13 DR<12>| FL_INT
0402 1% COMMON MIOD5_SWAPRDY_IN1 1 B5
1R798 0ohm
2 DR<13>| SWAPRDY_OUT*
1R584 49.9ohm
2 MIOA_CAL_PU_GND AE5 MIOACAL_PU_GND A9 DR<14>| SWAPRDY_OUT* GND
0402 COMMON
0402 1% COMMON
1 R36 0ohm
2
1 R19 1 0ohm
2 B13 DR_CMD| FL_SYNC
R592 0402 COMMON
1 R32 0ohm
2 0402 COMMON B8 DR_CLK| SWAPRDY_IN
1k
AH5 MIOA_VREF 0402 COMMON LED | GND A7
1%
GND 0402 21
GPIO21_RASTER_SYNC0 1 R25 33ohm
2 MIOA_RASTER_SYNC0_FL_SYNC_R 1R782 0ohm
2 MIOA_RASTER_SYNC0_FL_SYNC A1 RSTR_SYNC | FL_SYNC
BI
COMMON 21
GPIO22_SWAPRDY_IN 0402 5% COMMON 1 R47 0ohm
2 0402 COMMON MIOA_SWAPRDY_FL_INT2 B1 SWAP_RDY | FL_INT
BI
0402 COMMON
4 B2 EXT_REFCLK | SCL 4
MIOA_VREF
3.3V MIOA_CTL3 AH3 MIOA_CTL3 MIO_SIGNALS 1R827 0ohm
2 MIOA_CTL3_FL_INT1

MIOA_HSYNC AE3 MIOA_HSYNC


MIO_SIGNALS 0402 COMMON 1 R41 0ohm
2 MIOHSYNC_SWAPRDY_OUT2
1

C685 R589 AG1 MIOA_VSYNC 1R805 0ohm


2 0402 COMMON MIOVSYNC_SWAPRDY_OUT1
0.1uF 1k MIOA_VSYNC MIO_SIGNALS
MIOA_DE AH2 MIOA_DE MIO_SIGNALS 0402 COMMON 1 R18 0ohm
2 MIODE_FL_SYNC
16V 1%
0402 COMMON
10% 0402
X7R COMMON 1 R39 0ohm
2
2

0402 MIO_SIGNALS 0402 COMMON


COMMON
MIOA_CLKOUT AE2 MIOA_CLKOUT 1 R35 0ohm
2 MIOA_CLKOUT_SWAPRDY_IN2

MIOA_CLKOUT AE1 0402 COMMON

MIOA_CLKIN AE4 MIOA_CLKIN


MIO_SIGNALS 1 R45 0ohm
2 MIOCLKIN_I2C_SCL2
0402 COMMON

GND

SLI_LED
32 IN 0.381

5 5
NET VOLTAGE MAX_CURRENT MIN_WIDTH

MIOA_VREF 3.3V 0.305


IN

MIOA_CAL_PD_VDDQ 0.305
2.5V
IN
MIOA_CAL_PU_GND
IN
0.0V 0.305
MICRO-STAR INT'L CO.,LTD
MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 20 of 34
A B C D E F G H
A B C D E F G H

IOVDD

MISC1: Fan, Thermal, JTAG, GPIO


R184
10k
5%
0402
COMMON

1 1

NV3V3
NV3V3

R183 Q32A
10k

2
G
@discrete.q_fet_n_enh(sym_2):page21_i507
5%
0402 SOT363

D
COMMON COMMON
THERM_OVERT_GPU* THERM_OVERT*
OUT 31

6
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1P
@digital.u_gpu_gb2b_192(sym_11):page21_i416 1R185 0ohm
2
BGA1428 NV3V3 NV3V3 0402 COMMON
COMMON

11/18 MISC_1
AV6 I2CS_SCL R178 R601
I2CS_SCL IN 3 10k 10k
AN3 AU6 I2CS_SDA
OVERT GPIO8 I2CS_SDA BI 3 5% 5%
0402 0402
GM206 GK106 COMMON COMMON
I2CC_SCL AW7 I2CC_SCL 1R644 33ohm
2 I2CC_SCL_GPU
21
OUT
I2CC_SDA AV7 I2CC_SDA 0402 5% COMMON 1R643 33ohm
2 I2CC_SDA_GPU
21
BI
0402 5% COMMON
1

2 C702 GPU_THERMDN AM8 2


0.2pF THERMDN
I2CB_SCL AW5 I2CB_SCL 1R641 33ohm
2 I2CB_SCL_GPU
21
50V OUT
GPU_THERMDP AL8 AW6 I2CB_SDA 1R642 33ohm
2 0402 5% COMMON I2CB_SDA_GPU
0.1pF THERMDP I2CB_SDA BI 21
0402 5% COMMON
C0G
2

0402 GPIO9_GPU_THERM_ALERT*
COMMON
OUT 21
GK106 GM206 OUT 5,7,10
AT6 GPIO0_NVAPI_1_PWM_VID
GPIO0 OUT 25
GPIO1 AT7 colay 6pin housing
pads for deadbugging GPIO2 AL1
AL2 GPIO3_OC_WARN* R593
GPIO3 FOR GK106 ONLY 30 J201
IN 10k
GPIO4 AP3 GPIO4_GPU_IFPF_HPD_GK106 1R595 0ohm
2 12V_PEX6_F1 6
GPIO5_FRAME_LOCK_INT 5%
GPIO5 AP4 0402 COMMON
20 0402
NV3V3 NV3V3 NV3V3 12V_F 5
OUT
AK1 GPIO6_GPU_PSI* 4
GPIO6 OUT 21 COMMON
AK2 GPIO7_FBVDD_SEL 3
GPIO7 OUT 24 R545 R537 R555 R210
BA18 JTAG_TCK GPIO8_NC GPIO8 AG7 GPIO8_GPU_IFPF_HPD 1R198 0ohm
2 GPIO8_IFPF_HPD
17
D501 2
10k 10k 0ohm 0ohm

3
IN
AW16 JTAG_TMS GPIO9 AR6 0402 COMMON @discrete.d_3pin_cc(sym_2):page21_i301 1
GPIO10_FBVREF_SEL 5% 5% 30V
AW18 JTAG_TDI GPIO10 AM3 0402 0402 0805 0805
GPIO11_LOGO_LED 0.2A
AY18 JTAG_TDO GPIO11 AM4 32 GND COMMON COMMON COMMON COMMON BH1X6H-2PITCH-RH-1
OUT SOT23
AY16 AR3 GPIO12_GPU_LOW_PERF*
JTAG_TRST GPIO12 21

2
IN COMMON
AJ3 TOWS_BHEAD1X6_1
GPIO13
AL3 GPIO14_IFPA_HPD 1 J9
GPIO14 IN 15
AL4 GPIO15_IFPC_HPD GPIO13_FAN_TACH 2 @electro_mechanic.hdr_1x4(sym_1):page21_i307
GPIO15 IN 18 MALE
AR4 GPIO16_FAN_PWM 25MIL 3
GPIO16 2.0MM
AP5 GPIO17_IFPD_HPD FAN_PWR 4 N/A
GPIO17 19 12V

1
IN R541 C536 C542
AN5 GPIO18_IFPE_HPD NORM
GPIO18 IN 16 10k 1nF 1uF COMMON
AK3 GPIO19_STEREO_OUT
GPIO19 OUT 20 5% 16V 16V
AK4 GPIO20_SLI_LED_DIM
GPIO20 IN 32 0402 10% 10%
AL5 GPIO21_RASTER_SYNC0
GPIO21 20 DNI X7R X5R

2
BI
AK5 GPIO22_SWAPRDY_IN 0402 0603
GPIO22 BI 20
AJ4 GPIO23_RASTER_SYNC1 COMMON COMMON NV3V3
GPIO23 BI 20
3 AN4 GPIO24_SWAPRDY_OUT NV3V3 3
GPIO24 OUT 20
GPIO25_NC GPIO25 AK8
GPIO26_NC GPIO26 AH6
AG6 GPIO27 R522 Q504A
GPIO27_NC GPIO27 GND
10k

2
G
@discrete.q_fet_n_enh(sym_2):page21_i509
5%
0402 SOT363
R586

D
COMMON COMMON
10k GPIO6_GPU_PSI* GPIO6_PSI*
5% 21 IN BI 25,3

6
0402
COMMON 1 1
1G1D1S 3
D Q31 1R502 0ohm
2
@discrete.q_fet_n_enh(sym_2):page21_i394 R202 R616 R599 R590 R607 0402 COMMON
SOT23_1G1D1S 10k 10k 10k 10k 10k
IOVDD 1G DNI
* JTAG 5% 5% 5% 5% 5%
S 2 60V NV3V3 NV3V3
R182 0.26A
0402 0402 0402 0402 0402
GND 3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V COMMON DNI DNI DNI COMMON NV3V3
10k 0.31A
0.3W
5% 20V
0402 R501
DNI
Q504B
10k

5
R131 R121 R112 3V3_F

G
@discrete.q_fet_n_enh(sym_2):page21_i508
10k 10k 180ohm 5%
0402 SOT363
5% 5% 5%

D
0402 0402 0402 Use Low Vth device for 16nm NV3V3 1 COMMON COMMON
DNI DNI DNI NV3V3
1 GPIO12_GPU_LOW_PERF* GPIO12_LOW_PERF*
21 OUT IN 30,3
GND

3
JTAG_TCLK R1656
3 OUT
JTAG_TMS R668 Q30B 2.2k
3 2.2k

5
OUT 5%
JTAG_TDI 1R521 0ohm

G
3 @discrete.q_fet_n_enh(sym_2):page21_i502
0402
2
OUT 5%
JTAG_TDO SOT363 COMMON 0402 COMMON
3 IN 0402

D
JTAG_TRST*
3 OUT COMMON COMMON
I2CC_SDA_GPU I2CC_SDA_R NV3V3 NV3V3 3V3_F
21 OUT BI 30
4 4

3
R687 R736
10k 270ohm
5% 5%
1R164 0ohm
2 R188 Q32B R190
0402 0402 10k 10k

5
G
COMMON DNI 0402 COMMON @discrete.q_fet_n_enh(sym_2):page21_i506
3V3_F 5% 5%
0402 SOT363 0402

D
1 COMMON COMMON COMMON
NV3V3 GPIO9_GPU_THERM_ALERT* GPIO9_THERM_ALERT*
21 OUT IN 30
NV3V3

3
R1657
2.2k
R649 Q516B 5%
1R189 0ohm
2
GND 0402
2.2k

5
3V3_F

G
@discrete.q_fet_n_enh(sym_2):page21_i504
COMMON 0402 COMMON
5%
0402 SOT363
1

D
COMMON COMMON NV3V3
I2CB_SCL_GPU I2CB_SCL_R NV3V3
21 OUT OUT 20
R1659

3
2.2k
R671 Q30A 5%
2.2k

2
1R652 0ohm

G
2 @discrete.q_fet_n_enh(sym_2):page21_i503
0402
5% COMMON
0402 COMMON 3V3_F 0402 SOT363

D
1 COMMON COMMON
NV3V3 I2CC_SCL_GPU I2CC_SCL_R
21 OUT OUT 30
NV3V3

6
R1658
2.2k
R650 Q516A 5%
1R161 0ohm
2
2.2k 0402

2
G
COMMON
@discrete.q_fet_n_enh(sym_2):page21_i505 0402 COMMON
5%
0402 SOT363

D
COMMON COMMON
5 I2CB_SDA_GPU I2CB_SDA_R 5
21 OUT BI 20

6
1R651 0ohm
2
0402 COMMON

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CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 21 of 34
A B C D E F G H
A B C D E F G H

MISC2: ROM, XTAL, Straps


KEPLER MAXWELL GND 3V3
STRAP0 USER_BIT [3:0]*
5k 0000 1000

10k 0001 1001


STRAP1 3GIO_PADCFG_LUT_ADR*
15k 0010 1010
1 1
20k 0011 1011
STRAP2 PCI_DEVID [3:0]*
25k 0100 1100

30k 0101 1101


STRAP3 SOR_EXPOSED [3:0]*
35k 0110 1110

45k 0111 1111


STRAP4 DP_PLL_VDD_33V*

PEX_MAX_SPEED*

PEX_SPD_CHANGE_GEN3*

RAMCFG[0]* RAMCFG[0]*

2 2
RAMCFG[1]* RAMCFG[1]*
ROM_SI
IOVDD

RAMCFG[2]* RAMCFG[2]*

U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
RAMCFG[3]* RAMCFG[3]* G1R R191 U501
@digital.u_gpu_gb2b_192(sym_13):page22_i172 10k @memory.u_mem_fl_ser_256kx8(sym_1):page22_i66
SO8 IOVDD
BGA1428 5%
0402 SO8
COMMON
COMMON COMMON
VGA_DEVICE* VGA_DEVICE* 13/18 MISC_2 7 HOLD VCC 8
3 WP

1
AU5 ROM_CS* 1R192 33ohm
2 ROM_CS_R 1 C146
ROM_CS CS 0.1uF
0402 5% COMMON
SMB_ALT_ADDR* SMB_ALT_ADDR* ROM_SI AT5 ROM_SI 1R201 33ohm
2 ROM_SI_R 5 SI
16V

ROM_SO ROM_SO AT4 ROM_SO 0402 5% COMMON 2 SO


10%
X7R

2
STRAP0 AK7 STRAP0 ROM_SCLK AU4 ROM_SCLK 1R196 33ohm
2 ROM_SCLK_R 6 SCK GND 4 0402
STRAP1 AL6 0402 5% COMMON COMMON
STRAP1
FB[0]_APERTURE_SIZE* PCIE_CFG* STRAP2 AK6 STRAP2
STRAP3 AP6 STRAP3
STRAP4 AN6 STRAP4
FB[1]_APERTURE_SIZE* DEVID_SEL* GND

AL7 GPU_BUFRST*
BUFRST 32
PEX_PLL_EN_TERM100* SOR0_EXPOSED* OUT

3 3

1R587 40.2k
2 MULTISTRAP_REF0_GND AH7 MULTISTRAP_REF0_GND
PCI_DEVID_EXT[5]* SOR1_EXPOSED* 0402 1% COMMON
IOVDD C696
1 0.1uF
2
ROM_SCLK GND
0402 16V
10%
SUB_VENDOR* SOR2_EXPOSED* GND
X7R
COMMON U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
Smart Fan
LB503 30ohm C683
1 10uF
2 G1Q
BEAD_0603 COMMON PEX_VDD 0603 6.3V
@digital.u_gpu_gb2b_192(sym_12):page22_i171
1V_PLL 20% BGA1428 KEPLER
PCI_DEVID_EXT[4]* SOR3_EXPOSED* X5R
COMMON
COMMON
LB504 300ohm 12/18 XTAL/PLL
BEAD_0603 COMMON XTALSSIN XTALOUTBUFF Inverted PWM %
VID_PLL
1R588 0ohm
2 SP_PLLVDD AR12 SP_PLLVDD
MAXWELL 0402 COMMON PU PU 66 (33% HIGH)
AR13 VID_PLLVDD
STRAP0 PU PD 50 (50% HIGH)

1
MULTI_STRAP_REF0_GND C730
0.1uF
PD PU 33 (66% HIGH)
16V
BINARY PRODUCTION NC 3.3V 1.65V 0V 1R591 0ohm
2 GPU_PINAL34
GM206 GK106
10%
0402 COMMON PD PD 0 (100% HIGH)
X7R

2
BINARY BRINGUP NC GC6+ ISLAND GC6+ DEBUG GC6+ ISLAND 0402 AL34 NC DLL_AVDD0
ENABLED MODE DISABLED COMMON 1R572 0ohm
2 FB_PLL_DLL_AVDD H19 FB_PLL_DLL_AVDD DLL_AVDD2
MULTI-LEVEL 40.2k 1% TO GND 0402 COMMON MAXWELL
GND
AH34 GPCPLL0_AVDD XTALOUTBUFF

1
C650 C661 C660 C680 PEX_VDD AD9
22uF 0.1uF 0.1uF 0.1uF GPCPLL2_AVDD
LB505 30ohm 3.3V 1.65V 0V
6.3V 16V 16V 16V
4 IOVDD IOVDD BEAD_0603 COMMON AE9 LSX_PLLVDD 4

1
20% 10% 10% 10% C599
X5R X7R X7R X7R 66% 33% DISABLED

2
0.1uF
0805 0402 0402 0402
16V
COMMON COMMON COMMON COMMON
10%
X7R

2
0402
R604 R611 R598 R624 R618 R197 R193 R195 COMMON
4.99k 4.99k 4.99k 45.3k 4.99k 4.99k 10k 4.99k
GND IOVDD IOVDD
1% 1% 1% 1% 1% 1% 5% 1%
0402 0402 0402 0402 0402 0402 0402 0402 GND
DNI DNI DNI COMMON DNI DNI DNI DNI
1R627 100k2 AP2 XTALSSIN XTALOUTBUFF AP1 XTALOUTBUFF 1R615 100k2
STRAP0 ROM_SI 0402 5% COMMON 0402 5% COMMON
AN2 XTALIN XTALOUT AN1
R628
STRAP1 ROM_SO 10k R606
5% 330ohm
0402 Y1 5%
DNI 0402
STRAP2 ROM_SCLK @clocks.xtal_4pin(sym_2):page22_i83
DNI
SMD_32X25
27MHz GENERIC_SEZ1
GENERIC_SEZ1 COMMON
STRAP3 R200 R194 R199
GND
45.3k 30.1k 24.9k XTALSSIN_GPU XTALIN XTALOUT
20 1 3
1% 1% 1% IN
0402 0402 0402
4 2 GND
STRAP4 R1641
COMMON COMMON COMMON
10k

1
R638 C143 C144
5% 10k 18pF 18pF
R603 R610 R597 R623 R617 0402 5% 50V 50V
DNI 0402
4.99k 4.99k 24.9k 34.8k 45.3k FL_REFCLK_T
5% 5%
DNI C0G C0G

2
1
1% 1% 1% 1% 1% C740
0402 0402 0402 0402 0402
0402 GND GND 0402
18pF COMMON COMMON
COMMON COMMON COMMON DNI COMMON
5 ROM_SI GND
50V
5
5%
C0G 2
SAMSUNG HYNIX ELPIDA 0402 GND GND
DNI
45.3k PD 34.8k PD 30.1k PD

GND
GND
MICRO-STAR INT'L CO.,LTD
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CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents15ci203 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 22 of 34
A B C D E F G H
A B C D E F G H

PS: 5V, PEX_VDD


5V / DDC SUPPLY
12V_F

5V
R91
PLACE 0603 10UF FOOTPRINT @power_supply.u_vreg_3pin(sym_2):page23_i27
0ohm
ON TOP OF 0805 FOOTPRINT SOT223_GOI F501
U505 GOI,IGOI,TO263 0.75A DDC_5V
0603
COMMON 1.25V 5V 1206 5V
COMMON
COMMON
0.400 0.2A 0.2A
1R102 0ohm
2 5V_VIN_D 3 2 20MIL 1 2 0.400
IN OUT
1 0603 COMMON 12V 4 1

1
C88 C89 TAB

GND/ADJ
POLYSWITCH
10uF 10uF

1
C91 R110 C923 C924 C898 C897 C94
16V 16V 0.1uF 124ohm 10uF 10uF 4.7uF 0.1uF 470pF
20% 10% 16V 1% 16V 6.3V 6.3V 16V 50V
X5R X5R

1
10% 0402 20% 20% 20% 10% 5%
* DDC backdrive 0603 0805 X7R COMMON X5R X5R X5R X7R C0G

2
12V COMMON COMMON 0402 0603 0805 0603 0402 0603
0.400 @discrete.d_schottky(sym_3):page23_i8 COMMON 5V_ADJ COMMON COMMON COMMON COMMON COMMON
2D1 1
R114
PLACE 0603 10UF FOOTPRINT
SOD323 383ohm
20V ON TOP OF 0805 FOOTPRINT
1%
1A
COMMON 0402
COMMON GND GND
GND

Vref=1.256V
Vo_Typ=1.256*(1+383/124)+60uA*383=5.16V

GND

2 2

1V PLL SUPPLY

PEX_VDD 1V_PLL

1.05V
LB506 30ohm
BEAD_0603 COMMON 0.400

3 3

FBVDDQ

PEXVDD - PEXVDD - LINEAR OPTION

1
C755 C760
EM5103GE: 315-0612-000
10uF 4.7uF
GS7103NVSO-R: 315-0614-000
6.3V 6.3V
20% 20%

VID PLL SUPPLY X5R X5R

2
0805 0603
U10 PEX_VDD
COMMON COMMON
@power_supply.u_vreg_apl5910(sym_1):page23_i168
SOP8 1.0V
5V COMMON 2.7A
GND GND 3 VIN VOUT 6 0.400
PEX_VDD BYPASS VID_PLL
4 4 VCNTL 4

1
C753 R648 C134 C135 C745 C131
PS_PEXVDD_EN 1nF 0ohm 0.1uF 10uF 22uF 4.7uF
31 2 EN

1
C756 IN 16V 16V 6.3V 6.3V 6.3V
LB3 30ohm PS1_1V_FB
1uF FB 7 10% 0402 10% 20% 20% 20%
BEAD_0603 COMMON PS_PEXVDD_PGOOD 1
31 POK X7R COMMON X7R X5R X5R X5R

2
16V OUT
3V3_F
U8 GND 9 0402 local sense 0402 0805 0805 0603
10%
1.05V X5R 5 NC GND 8 COMMON COMMON COMMON COMMON COMMON

2
@power_supply.u_vreg_5pin(sym_15):page23_i132 0603
COMMON
SC705
COMMON ADD TESTPOINT VIA TO PEXVDD_PGOOD
315-0217-000 PEX_VDD
1 IN OUT 5 1.0V GND Vref=0.8V GND remote sense
GND

0.406
PS_VIDPLL_EN 3 EN GND/NC 4 Vout = Vref * (1+Rtop/Rbot) PS1_1V_RS 1R605 0ohm
2
31 IN
0402 COMMON
GND1 1.047V = 0.8 * (1+3.09K/10.0K)
1

C119 C126 C122


2

1uF 1uF 10uF R653


6.3V 6.3V 6.3V 3.09k
10% 10% 20% 1%
X5R X5R X5R
2

0402
0402 0402 0603 COMMON
COMMON COMMON COMMON

GND GND GND GND GND


R656
10k
1%
0402
COMMON

5 GND 5

MICRO-STAR INT'L CO.,LTD


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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 23 of 34
A B C D E F G H
A B C D E F G H

PS: FBVDDQ

1 1

12V_F
12V_F PLACE CLOSE TO TOP FET

12V_F

1
C75
0.47uF
D507

2
16V
@discrete.d(sym_1):page24_i27
10%
SOD323
X7R

2
75V
R723 0603
0.3A
2.2ohm COMMON

1
COMMON
5%
0603 PS_FB_HDRV PS_FB_HDRV_R GND
COMMON U506 1R745 0ohm
2
0.300 0.300
@power_supply.u_swreg_up6101(sym_1):page24_i166 0603 COMMON
0.5V
PSOP8
COMMON LFPAK D 5
PS_FB_VCC5 5 VCC BOOT
1 PS_FB_BST 1R722 0ohm
2 PS_FB_BST_R Q17
0.300 0.300 0603 COMMON 0.300 @discrete.q_fet_n_enh(sym_5):page24_i39
1

1
C831 C844 4G LFPAK
12V
1uF 0.1uF COMMON
S 1 30V
16V 16V 13.2A

10% HDRV 2 10%


R746 2 7.3mohm@10V / 10.8mohm@4.5V / -1000mohm@2.5V
81A
X5R X7R 10k 3 2.49W
2

2
20V
2 0402 PHASE 8 0603 5% FBVDDQ 2
COMMON COMMON 0402
PS_FB_SW COMMON output ripple: 4.55A p-p, 1uH, 300kHz
L10 1uH 1.5V 16A 0.500
7 COMP/EN
SMD_420X400 COMMON
0.500 22A

1
3 GND PS_FB_LDRV C845 0.00307ohm C796 C797
LDRV/OCS 4 2.2nF 10uF 10uF
C103 C104
9 GND FB 6 0.300 24A 820uF 820uF
GND 50V 6.3V 6.3V
23.5A
R1709 10% 20% 20% COMMON COMMON
X7R X5R X5R 20% 20%

2
13K
OCP:13K(60A) 0603 0805 0805 2.5V 2.5V
5%
0402 LFPAK D 5 LFPAK D 5 COMMON COMMON COMMON AL-Polymer AL-Polymer

COMMON Q24 Q23


GND 0.007ohm 0.007ohm
@discrete.q_fet_n_enh(sym_5):page24_i40 @discrete.q_fet_n_enh(sym_5):page24_i100 PS_FB_SW_RC
TH_D63P25 TH_D63P25
4G LFPAK 4G LFPAK
0.300
COMMON COMMON
S 1 30V S 1 30V

2 19.7A
2 19.7A R739
GND 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V
140A 140A 2.2ohm
3 2.57W 3 2.57W
20V 20V 5%
FBVDDQ GND
1R105 30k 2 1206
0402 COMMON COMMON
5% APW8720KE R577 R1651
Rocp2 0ohm 0ohm
Remote Remote

0402 0402 R1652


GND GND GND COMMON COMMON
0ohm
Local

0402
COMMON
for voltage-mode error amp
C85
1 220pF
2
0402 50V
5%
PS_FB_R
3 C0G RT8101 0.300 3
COMMON R712
150ohm
1%
0402
COMMON

PS_FB_COMP 1C86 47nF


2 PS_FB_RC_CP 1R108 3.92k
2 PS_FB_C
0402 6.3V 0402 1% COMMON
0.100 0.100 0.300
10%

1
X5R R728 C836
COMMON 1.78k 10nF
1% 16V
0402 10%
COMMON X7R

2
1

C80 R98 PS_FB_FB


Rtop 0402
100pF 10k
COMMON
0.300
50V 1%
5% 0402
C0G COMMON
2

0402 GPIO7 FBVDDQ R729 R730


COMMON 5.62k 1k
1% 1%
NV3V3 0402 0402
0 1.38V COMMON COMMON
APW8720KE Rbot1 Rbot

1 1.55V <= DEFAULT R703 PS_FB_RBOT


GND GND
10k
for transconductance error amp GND
3 5%
D Q519B 0402 1G1D1S 6
D Q519A
@discrete.q_fet_n_enh(sym_2):page24_i92 COMMON
PS_FBVDDQ_EN* SOT363 @discrete.q_fet_n_enh(sym_2):page24_i93
5G SOT363
31 IN
S
COMMON
21
GPIO7_FBVDD_SEL 1R708 10k 2 PS_FB_VSEL 2G COMMON
4 IN
S
0402 5% COMMON 1

1
4 60V C816 4
0.115A 60V
5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V 1nF 0.115A
0.8A 5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V
0.2W 16V 0.8A
20V
Vout = Vref * (1 + Rtop / Rbot) 10%
0.2W
20V
X7R

2
Vout = Vref * (1 + Rtop / (Rbot ll Rbot1)) 0402
COMMON

GND
GND

FBVDDQ
GND
can be colayouted with output bulks

Vref
Vref accuracy Fosc GPIO7

APW8720KE 0.5V 1% 300kHz 0 Vout = .5*(1+1.78k/1k) = 1.39V

1 Vout = .5*(1+1.78k/(1k||5.62k)) = 1.548V

RT8101GSP 0.8V 1% 300kHz 0 Vout = .8*(1+1k/1.37k) = 1.384V

1 Vout = .8*(1+1k/(1.37k||4.87k)) = 1.549V

5 5
GND

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 24 of 34
A B C D E F G H
A B C D E F G H

PS: NVVDD Controller


Overshoot Recovery Enhancement

PS_VFB_OSE 1 R80 49.9k


2 PS_VFB
25
BI
0402 1% COMMON
R70
9.09k
1%
0402
1C73 150pF
2 GND
COMMON 1B1C1E 3 0402 50V
C Q18 5%
B1 C0G
1 PS_BASE_OSE @discrete.q_npn(sym_1):page25_i325 1
SOT23_1B1C1E COMMON
COMMON
12V_F OUT 25 E 2

1
R75 C71 PS_COMP_OSE 1C77 10nF
2 PS_COMP
1k 0.1uF BI 25
1 R67 620ohm
2 PS_VCC5V 0402 16V
1% 16V 10%
0603 5% COMMON 0.381 0402 10% X7R
COMMON X7R

2
COMMON
1 R66 620ohm
2 0402
0603 COMMON 12V_F COMMON R78
5%
33.2k
1%
0402
1 R68 620ohm
2 GND GND COMMON
0603 COMMON
R719
5%
10k
5%
0402
1R774 620ohm
2 COMMON
0603 5% COMMON
U507 GND
1R773 620ohm
2 @power_supply.u_openvreg_type4(sym_1):page25_i317
0603 5% COMMON 2V

1
C65 R755 C830 QFN32
1uF 1k 10nF COMMON
16V 1% 10V
0402 OPEN VREG
3V3_F 10% 10%
NVVDD_GATE1
X7R COMMON X5R 30 VCC PWM1 25 26

2
OUT
0603 0402 0.300
1R761 10k 2 COMMON COMMON PS_12VMON 6 12VMON PWM2 26 NVVDD_GATE2
26
OUT
0402 5% COMMON 0.300
GND GND GND 27 NVVDD_GATE3
PWM3 OUT 27
21,31
GPIO6_PSI* 1R760 0ohm
2 NVVDD_GPIO6_PSI* 5 PSI* 0.300
IN
2 0402 COMMON 28 NVVDD_GATE4 2
PWM4 OUT 27
NVVDD_EN 4 EN 0.300
30,31 IN
1R762 10k 2
GND GPIO0_NVAPI_1_PWM_VID
0402 5% COMMON
21 2 VID
IN
25 OUT
1R768 4.75k
2 PS_VREF 31 VREF
0402 1% COMMON 18 NVVDD_CS1
CS1P IN 26
R_VREF1 R_VREF2 R_REFADJ Vboot Vmax Vmin R_VREF1 PS_REFIN 32 REFIN

1
C72 1R767 6.04k
2 PS_VIDBUF 1
1uF REFADJ
6.98k 6.04k 6.04k 0.95V 1.302V 0.604V C_VREF 0402 1% COMMON CS1N 17 NVVDD_CS1N
6.3V IN 26

1
10% R76
X5R
R_REFADJ

2
4.22k R_VREF2
0402
COMMON
1% C74 20 NVVDD_CS2
0402 10nF CS2P IN 26
COMMON
C_REFIN

2
PS_GND 6.3V
10%
X7R
0402 19 NVVDD_CS2N
R83 CS2N IN 26
COMMON
0ohm

0402 R86 22 NVVDD_CS3


COMMON
10k CS3P IN 27
1%
0402
GND DNI
NVVDD_VS* 10 VSN/FBRTN 21 NVVDD_CS3N
25 IN CS3N IN 27
0.300
IN 27
NVVDD

3
25
NVVDD_VS 9 VSP/NC CS4P 24 NVVDD_CS4 1R701 0ohm
2 3
IN
0.300 0402 COMMON
1R107 1k 2 1C81 47pF
2 PS_COMP 12 COMP/VDROOP 1R770 0ohm
2 stuff both these as 0ohm for 3phase NVVDD
0402 DNI 0402 50V 5% 0402 COMMON
1%
C0G COMMON
CS4N 23
1 R94 3.3k2 PS_COMP_RC 1C78 2.2nF
2 25
NVVDD_CS4N
27
BI IN
0402 1% COMMON 0402 16V
X7R 10% 3V3_F
COMMON BI 25
1C90 2.2nF
2 PS_TYPE2_B 1R106 0ohm
2
0402 16V 0402 DNI PS_VFB 13
X7R VFB R72
10%
DNI 10k
C828
1 470pF
2 PS_TYPE2_A 1R718 75ohm
2 PS_DIFFOUT 11 VSDIFF/STRAP1 5%
0402 16V 0402 COMMON
COMMON 0402
RDRP1 RDRP2 CDRP X7R 10%
DNI
DRV_EN 29 NVVDD_DRVON
0 ohm DC Loadline OUT 26,27
open circuit dont care dont care 1R732 1k 2
0402 1% COMMON R73
dont care
1.91k 4.7nF 1.3mOhm AC Loadline, 9us recovery 10k
1R731 5.49k
2 VR_RDY 3 PS_NVVDD_PGOOD
31 5%
OUT
0402 1% COMMON 1R117 4.99k
2 0402
RDRP1 0402 1% COMMON
DNI
PS_VREF
RDRP2 CDRP 0.300 IN 25
1R115 4.99k
2 PS_DRP_RC 1C92 2.2nF
2
0402 1% COMMON 0402 16V
COMMON R81
PS_NTC_P 1R714 13k 2 X7R 10% PS_DRP_TCOMP 14 CS_TCOMP1
RLIM1 GND
OUT 25 12.1k RLIM1 RLIM2 OCP
0402 1% COMMON
PS_VDFB_TCOMP 1%
R100 15 CS_TCOMP2 0402
1

R735 C837 C829


10k COMMON
10k 100pF 15pF PS_ILIM
1% ILIM 8
4 1% 50V 50V 0402 12.1k 8.06k 240A 4
0402 5% 5% COMMON 12V_F
COMMON C0G C0G
2

1
0402 0402 C79
PS_NTC_N
25
COMMON COMMON 1R111 4.02k
2 1R104 12.7k
2 PS_CSSUM_SS 16 CSSUM/STRAP2 FS 7 PS_ROSC 1R720 34k 2 100pF
OUT R87
0402 1% COMMON 0402 1% COMMON 0402 1% DNI 50V
4.99k
NVVDD 1C82 15pF
2 GND 33 GND 5%
1% C0G

2
0402 50V
R101 R743 0402
5% RLIM2 COMMON
0402
RESERVE FOR NTC C0G 34k 34k R721 COMMON

R125 COMMON 28k


1% 1% ROSC
100ohm 0402 0402 1%
DNI COMMON 0402
1% R163 100k,B25/85@[ ]
0402
PS_NTC_P
25 1R716 13k 2 PS_NTC_N
25 COMMON
IN IN
COMMON 0603 5% DNI PS_NTC_MID 0402 1% COMMON
GND

3
NVVDD_SENSE 1R124 0ohm
2 NVVDD_VS
25 GND GND GND GND
IN OUT
0.300 0402 COMMON PLACE NTC_N RESISTOR CLOSE TO PHASE 1 INDUCTOR AND
PS_VCC5V
1

C84 IN 25
ON THE SAME OF THE BOARD AS THE INDUCTOR
220pF ROSC Fsw
50V
5%
C0G
34k 300kHz
2

0402

3
GND_SENSE 1R123 0ohm
2 DNI NVVDD_VS*
25
IN OUT
0.300 0402 COMMON 28k 350kHz

R122
100ohm
1%
0402
5 COMMON 5

GND

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 25 of 34
A B C D E F G H
A B C D E F G H

PS: NVVDD Phase 1,2


12V_F

1
C70
1 0.1uF 1
16V
10%
X7R near NVVDD control side

2
0402
COMMON NVVDD_CS1 25
OUT
12V_F

GND
NVVDD_GATE1 1R748 10k 2 NVVDD_CS1N
25
IN OUT
0402 5% DNI

R71 R694
2.2ohm U2 * place close to drain of Top FET C847 0.22uF
1 2
5% @power_supply.u_swreg_adp3110(sym_1):page26_i315
0603 NCP81062MNTWG LFPAK D 5 0402 16V COMMON

COMMON DFN8
Q15
2k
COMMON 0.381 0.381 @discrete.q_fet_n_enh(sym_5):page26_i130
COMMON
2 IN DRVH 8 PS_NVVDD_UG1 1R747 0ohm
2 PS_NVVDD_UG1_R 4G LFPAK
0402
COMMON
0.500 0603 COMMON S 1 30V
13.2A
SWN 7 2 7.3mohm@10V / 10.8mohm@4.5V / -1000mohm@2.5V
R741 3 81A
NVVDD_DRVON 0.381 2.49W
C865 0.1uF 10k
25,26,27 1R1710 49.9R
2 3 OD*/NC BST 1 PS_NVVDD_BOOT1 1 R79 1ohm
2 1 2 20V
300-0788-000
IN 5%
0402 1% COMMON 0603 0603 16V SP25 SP26
0402
COMMON 10%
COMMON
XXXV32020 XXXV32020 NVVDD
X7R
PLACE 0603 1UF FOOTPRINT COMMON
ON TOP OF 0805 FOOTPRINT 0.305
PS_NVVDD_VCC1 4 VCC colayout 0.22uH 1.05V
PS_NVVDD_PHASE1 L9 20MIL 125A
1

C872 TH COMMON
1uF
2 2

1
16V
5 5 C834
LFPAK D LFPAK D 1nF

1
10% C775 C784 C785 C774
X5R
Q28 Q22
2

16V 22uF 22uF 22uF 22uF


0603 6 PGND 0.381 @discrete.q_fet_n_enh(sym_5):page26_i58 @discrete.q_fet_n_enh(sym_5):page26_i306
10% 6.3V 6.3V 6.3V 6.3V
COMMON 9 TP DRVL 5 PS_NVVDD_LG1 4G LFPAK 4G LFPAK
X7R

2
COMMON COMMON 20% 20% 20% 20%
S 1 30V S 1 30V 0402 X5R X5R X5R X5R

2
19.7A 19.7A
2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V
COMMON 0805 0805 0805 0805
140A 140A
3 2.57W 3 2.57W
PS_NVVDD_NVVDD_RC1 COMMON COMMON COMMON COMMON
20V 20V
GND 300-0787-000 300-0787-000 0.406
R715
1ohm
NVVDD
5%
GND 1206
NVVDD
GND COMMON
GND

C1703 C111 C110 C113 C112


820uF 820uF 820uF 820uF 820uF
COMMON COMMON COMMON COMMON COMMON
add 820uF X1 20% 20% 20% 20% 20%
GND 2.5V 2.5V 2.5V 2.5V 2.5V
AL-Polymer AL-Polymer AL-Polymer AL-Polymer AL-Polymer

0.007ohm 0.007ohm 0.007ohm 0.007ohm 0.007ohm


TH_D63P25 TH_D63P25 TH_D63P25 TH_D63P25 TH_D63P25

NVVDD
12V_PEX6_F1 GND
NVVDD
3 3

C734

1
C68
0.1uF 330uF
16V COMMON
10% 20%
X7R 2V

2
0402 AL-Polymer
COMMON
0.006ohm
12V_F SMD_7343

GND

NVVDD_GATE2 GND
IN
* place close to drain of Top FET
near NVVDD control side
R95 NVVDD_CS2
2.2ohm colayout OUT 25
5% U3
0603
@power_supply.u_swreg_adp3110(sym_1):page26_i316
resistors
COMMON NCP81062MNTWG LFPAK D 5 1R750 10k 2 NVVDD_CS2N
25
OUT
DFN8
Q13 0402 5% DNI
COMMON
R697
0.381 0.381 @discrete.q_fet_n_enh(sym_5):page26_i204
2 1R763 0ohm 4G LFPAK C853 0.22uF
IN DRVH 8 PS_NVVDD_UG2 2 PS_NVVDD_UG2_R
COMMON
1 2
0603 S 1 30V 0402 16V COMMON
13.2A
SWN 7 0.500 COMMON 2 7.3mohm@10V / 10.8mohm@4.5V / -1000mohm@2.5V
81A 2k
0.381 3 2.49W
C857 0.1uF R757 COMMON
25,26,27
NVVDD_DRVON 1R1711 49.9R
2 3 OD*/NC BST 1 PS_NVVDD_BOOT2 1 R84 1ohm
2 1 2 20V
300-0788-000 0402
IN 10k
0402 1% COMMON 0603 0603 16V
10% 5%
4 COMMON 4
0402
PLACE 0603 1UF FOOTPRINT colayout X7R
COMMON SP27 SP28
COMMON
XXXV32020 XXXV32020 NVVDD
ON TOP OF 0805 FOOTPRINT resistors
0.305 PS_NVVDD_VCC2 4 VCC
0.22uH
1

C854 PS_NVVDD_PHASE2 L7
1uF
TH COMMON
16V
LFPAK D 5 LFPAK D 5

1
10% C850
X5R
Q20 Q26
2

1nF

1
6 C772 C746 C793
0603 PGND 0.381 @discrete.q_fet_n_enh(sym_5):page26_i201 @discrete.q_fet_n_enh(sym_5):page26_i308
16V 22uF 22uF 22uF
COMMON 9 TP DRVL 5 PS_NVVDD_LG2 4G LFPAK 4G LFPAK
COMMON COMMON 10% 6.3V 6.3V 6.3V
S 1 30V S 1 30V
X7R

2
19.7A 19.7A 20% 20% 20%
2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 0402 X5R X5R X5R

2
140A 140A
3 2.57W 3 2.57W
COMMON 0805 0805 0805
20V 20V
300-0787-000 300-0787-000 PS_NVVDD_NVVDD_RC2 COMMON COMMON COMMON

GND 0.406
R738
1ohm
5%
GND GND 1206
COMMON

GND

GND

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 26 of 34
A B C D E F G H
A B C D E F G H

PS: NVVDD Phase 3,4


12V_PEX6_F1

1
C66 C67
near NVVDD control side
0.1uF 0.1uF
16V 16V
10% 10%
1 X7R X7R
1

2
12V_F 0402 0402 NVVDD_CS3 25
OUT
COMMON COMMON

1R740 10k 2 NVVDD_CS3N


25
OUT
0402 5% COMMON

25 NVVDD_GATE3 GND
IN GND R710
C849
1 0.22uF
2
R126 0402 16V COMMON
2.2ohm * place close to drain of Top FET
5% U5 2k
0603 COMMON
@power_supply.u_swreg_adp3110(sym_1):page27_i332
COMMON NCP81062MNTWG LFPAK D 5 0402
DFN8
Q12
COMMON 0.381 0.381 @discrete.q_fet_n_enh(sym_5):page27_i336
2 IN DRVH 8 PS_NVVDD_UG3 1R764 0ohm
2 PS_NVVDD_UG3_R 4G LFPAK
COMMON
0.500 0603 COMMON S 1 30V
13.2A
SWN 7 2 7.3mohm@10V / 10.8mohm@4.5V / -1000mohm@2.5V

0.381
R113 3 81A
2.49W
NVVDD_DRVON 1R1712 49.9R
2 3 1ohm C827 0.1uF R765 20V

25,26,27 IN
OD*/NC BST 1 PS_NVVDD_BOOT3 1 2 1 2
10k
300-0788-000
0402 1% COMMON 0603 0603 16V
10% 5%
COMMON SP29 SP30
X7R 0402
PLACE 0603 1UF FOOTPRINT COMMON
XXXV32020 XXXV32020 NVVDD
COMMON
ON TOP OF 0805 FOOTPRINT
PS_NVVDD_VCC3 0.305 4 VCC 0.22uH
PS_NVVDD_PHASE3 L6
1

C823 TH COMMON
1uF

1
16V
5 5 C848 C786 C792 C791
10%
LFPAK D LFPAK D 1nF 22uF 22uF 22uF
2 X5R
Q25 Q19 2
2

16V 6.3V 6.3V 6.3V


0603 6 PGND 0.381 @discrete.q_fet_n_enh(sym_5):page27_i337 @discrete.q_fet_n_enh(sym_5):page27_i338
10% 20% 20% 20%
COMMON 9 TP DRVL 5 PS_NVVDD_LG3 4G LFPAK 4G LFPAK
X7R X5R X5R X5R

2
COMMON COMMON
S 1 30V S 1 30V 0402 0805 0805 0805
19.7A 19.7A
2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V
COMMON COMMON COMMON COMMON
140A 140A
3 2.57W 3 2.57W
PS_NVVDD_NVVDD_RC3
20V 20V
300-0787-000 300-0787-000 0.406
R737
GND
1ohm
5%
GND GND 1206
COMMON
GND

GND

12V_PEX6_F1

near NVVDD control side


3 3

NVVDD_CS4 25
OUT

1
C69
0.1uF
16V
10%
12V_F X7R

2
0402 1R754 10k 2 NVVDD_CS4N
25
OUT
COMMON 0402 5% COMMON

NVVDD_GATE4 R702
25 IN C852 0.22uF
1 2
GND 0402 16V COMMON
R103 R97
0ohm 2.2ohm 2k
5% 5% U4 COMMON
stuff 0ohm for 3phase * place close to drain of Top FET 0402
0402 0603
@power_supply.u_swreg_adp3110(sym_1):page27_i334
COMMON COMMON NCP81062MNTWG LFPAK D 5
DFN8
Q14
COMMON 0.381 0.381 @discrete.q_fet_n_enh(sym_5):page27_i335
2 IN DRVH 8 PS_NVVDD_UG4 1R734 0ohm
2 PS_NVVDD_UG4_R 4G LFPAK
COMMON
GND 0.500 0603 COMMON S 1 30V
13.2A
SWN 7 2 7.3mohm@10V / 10.8mohm@4.5V / -1000mohm@2.5V

0.381
R109 3 81A
2.49W
NVVDD_DRVON 1R1713 49.9R
2 3 1ohm C832 0.1uF R753 20V

25,26,27 IN
OD*/NC BST 1 PS_NVVDD_BOOT4 1 2 1 2
10k
300-0788-000
0402 1% COMMON 0603 0603 16V
10% 5%
COMMON
X7R 0402
PLACE 0603 1UF FOOTPRINT 0.305 COMMON SP32
COMMON
ON TOP OF 0805 FOOTPRINT SP31 XXXV32020
XXXV32020 NVVDD
4 PS_NVVDD_VCC4 4 VCC 4
0.22uH
1

C843 PS_NVVDD_PHASE4 L8
1uF
TH COMMON
16V
LFPAK D 5 LFPAK D 5

1
10% C851 C789 C788 C773
X5R
Q27 Q21
2

1nF 22uF 22uF 22uF


0603 6 PGND @discrete.q_fet_n_enh(sym_5):page27_i339 @discrete.q_fet_n_enh(sym_5):page27_i340
16V 6.3V 6.3V 6.3V
COMMON 9 TP DRVL 5
PS_NVVDD_LG4 PS_NV_SV_LG4 4G LFPAK 4G LFPAK
COMMON COMMON 10% 20% 20% 20%
0.381 0.381 S 1 30V S 1 30V
X7R X5R X5R X5R

2
19.7A 19.7A
2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 2 3.4mohm@10V / 5mohm@4.5V / -1000mohm@2.5V 0402 0805 0805 0805
140A 140A
GND 3 2.57W 3 2.57W
COMMON COMMON COMMON COMMON
20V 20V
300-0787-000 300-0787-000
PS_NVVDD_NVVDD_RC4
0.406
R759
1ohm
5%
GND GND 1206
COMMON

GND

GND

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 27 of 34
A B C D E F G H
A B C D E F G H

1 1

2 2

[RESERVED]

3 3

4 4

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
Custom 01_Table of Contents 2.0
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. Date: Monday, November 17, 2014 Sheet 28 of 34

A B C D E F G H
A B C D E F G H

PS: NVVDD OVR2+1 POWER

1 1

2 2

3 3

4 4

5 5

MICRO-STAR INT'L CO.,LTD


MS-V320
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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 29 of 34
A B C D E F G H
A B C D E F G H

PS: Inputs, Filtering, and Monitoring


PEX 3V3 INPUT - 10W
PLACE 0603 10UF FOOTPRINT
ON TOP OF 0805 FOOTPRINT
3V3_F 3V3 3V3_F
3.3V
3A
place caps close to INA3221 0.400

1
C799
0.1uF U6 INA3221_VIN1P 1R134 20ohm
2 12V_INP
30

1
16V @digital.u_pwrmtr_ina3221(sym_1):page30_i159 IN C821 C810 C811 C118 C814
1 0402 1% COMMON 1
0.1uF 10uF 10uF 1uF 0.1uF

1
10% QFN16 C812 LB507 220ohm
X7R

2
COMMON 10uF 16V 16V 6.3V 16V 16V

12
0402 BEAD_0805 COMMON
16V 10% 20% 20% 10% 10%
COMMON
VIN1P LB508 220ohm
X7R X5R X5R X5R X7R

2
10%
4 VS X5R 0402 BEAD_0805 COMMON 0603 0805 0402 0402

2
GND 0805 COMMON COMMON COMMON COMMON COMMON

21
I2CC_SCL_R 6 SCL COMMON INA3221_VIN1N 1R133 20ohm
2 12V_INN
30
IN IN
I2CC_SDA_R 7 11 0402 1% COMMON
21 BI SDA VIN1N

5 A0
INA3221_VIN2P 1R154 20ohm
2 12V_PEX6_1_INP
30
IN
0402 1% COMMON GND GND

1
C805
10uF
VIN2P 15
16V
GND 10%
X5R

2
0805
VIN2N 14 COMMON INA3221_VIN2N 1R149 20ohm
2 12V_PEX6_1_INN
30
IN
0402 1% COMMON

PEX_12V INPUT - 66W 12V_F

31
PS_PCIE_PGOOD 10 PV VIN3P 2 INA3221_VIN3 1R670 100ohm
2 12V
OUT
13 TC 0402 5% COMMON bead change to choke 5.5A
GPIO12_LOW_PERF* 1 0ohm
2 INA3221_VPU 16 VPU 12V 0.400
21,31 IN C102 1uF2
0402 COMMON 1 12V
R158 GND 2512_2PIN_KELVIN
VIN3N 1 0402 16V 5.5A
10% 1 4 0.400 L20 0.47uH
X5R RS501
2 0.005ohm
3 SMD_420X400 COMMON
COMMON
0.00307ohm

1
2 8 INA3221_WARN* 1R692 0ohm
2 NVVDD_EN C840 C839 C838 COMMON
2
WARN OUT 25,31 0.1uF 1uF 10uF 24A
3 GND 0402 DNI
GPIO9_THERM_ALERT_R* 16V 16V 16V 23.5A
TP PAD CRIT 1R139 0ohm
2
10% 10% 10%
0402 DNI
X7R X5R X5R

2
GPIO9_THERM_ALERT*
1R693 0ohm
2 21 0402 0603 0805
OUT
I2C Address:(1000 000b) 0402 COMMON COMMON COMMON COMMON

GND

1R138 0ohm
2 GPIO3_OC_WARN*
21
OUT
0402 COMMON GND

12V_F
C893,C895 must be low profile component if stuffed with FET heatsink 12V_INP
30 OUT

C48
12V_INN
1

C858 C860 C892 C893 C895 220uF 30 OUT


10uF 10uF 10uF 10uF 10uF
COMMON
16V 16V 16V 16V 16V 20%
10% 10% 10% 10% 10% 16V
X5R X5R X5R X5R X5R
2

AL-Polymer
0805 0805 0805 0805 0805 4.3A@105degC,100KHz
COMMON COMMON COMMON COMMON COMMON 0.013ohm
COMBI_TH_D80_D50
3 3

12V_PEX6_F1
colayout 603 on 805s
GND
PEX6 INPUT - 2x3 PCIE CON 75W
C160
1

C880 C875 C877 C883 C890 12V_PEX6_1_INN


10uF 10uF 10uF 10uF 10uF 220uF 30 OUT
16V 16V 16V 16V 16V COMMON
10% 10% 10% 10% 10% 20% PLACE ON NORTH SIDE
16V 12V_PEX6_1_INP 12V_PEX6_F1
X5R X5R X5R X5R X5R 30
2

OUT
0805 0805 0805 0805 0805 AL-Polymer
COMMON COMMON COMMON COMMON COMMON 4.3A@105degC,100KHz
0.013ohm
COMBI_TH_D80_D50 colay 8pin power header
TRUE COMMON
bead change to choke 12V
12V_PEX6_F1 J10 2 3 6.25A
colayout 603 on 805s +12V 6 PEX6_12V 6.25A 1
RS2 4
0.005ohm 0.400
GND +12V 7 0.400 L21 0.33uH
+12V 8 2512_2PIN_KELVIN
SMD_420X400 COMMON

1
C164 C165
0.00307ohm
0.1uF 10uF
VVVV32020
16V 16V 24A
C47
1

C887 C885 10% 10% 23.5A


N93-08M0361-W06
220uF X7R X5R

2
10uF 10uF
GND 1 0402 0805
16V 16V COMMON
20% GND 2 GND COMMON COMMON
10% 10%
X5R X5R 16V GND 4
2

0805 0805 AL-Polymer


4.3A@105degC,100KHz R1708 0
4 COMMON COMMON
SENSE_1 3 6P_SENSE_A 4
0.013ohm
5 0402 +0.05R COMMON
COMBI_TH_D80_D50 SENSE_2 GND
VVVV32020
C1702 R11-0000012-W08
POWER_HEADER
POWCONN_D8_10 47PF
COMMON 50V
GND 5%
colayout 603 on 805s C0G
12V_PEX6_F1 0402 INPUT_PEX6_DT1* 31
OUT
COMMON
VVVV32020
GND
C11-4701012-W08
J1003
+12V 4
1

C873 5
1

C882 +12V
10uF
10uF +12V 6 PEX6_12V
16V
16V
10%
10%
X5R
2

X5R
2

0805 XXXV32020
0805
COMMON
COMMON
N93-06M0431-W06 GND 1
GND 3
GND

12V_F colayout 603 on 805s Sense 2 6P_SENSE_A


GND
POWER_HEADER
POWCONN_D6_15
COMMON
1

C867 C868 C871 C862 C904 C903 C902 C76 C864


10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
5 16V 16V 16V 16V 16V 16V 16V 16V 16V 5
10% 10% 10% 10% 10% 10% 10% 10% 20%
X5R X5R X5R X5R X5R X5R X5R X5R X5R
2

0805 0805 0805 0805 0805 0805 0805 0805 0603


COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

C76 must be low profile component if stuffed with FET heatsink GND MICRO-STAR INT'L CO.,LTD
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CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 30 of 34
A B C D E F G H
A B C D E F G H

PS: Sequence and Shutdown


3V3_F 3V3_F 3V3_F
3V3_F

R147 R144 12V_F


10k 10k R89 12V_F 1G1D1S 3
5% 5% 10k D Q29B
0402 0402 5%
@discrete.q_fet_n_enh(sym_2):page31_i375
COMMON COMMON 0402 SOT363
COMMON 5G COMMON
PS_PCIE_PGOOD 1R156 0ohm
2 NVVDD_EN
25 25,30 PS_NVVDD_PGOOD S 4
IN OUT IN R127
0402 COMMON 60V
0.115A 10k
5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V
0.8A 5%
1 0.2W 1
0402
PS_IOVDD_PGOOD 1R151 0ohm
2 20V
COMMON
IN
0402 COMMON 3V3_FET

1
C101
10nF R1650 PS_FBVDDQ_EN*
16V 10k OUT 24
10% 5%
X5R

2
0402

1
6 C95
0402 COMMON 1G1D1S
COMMON D Q29A 10nF
@discrete.q_fet_n_enh(sym_2):page31_i376 16V
SOT363 10%
PS_CORE_PGOOD 1R137 1k 2 PS_FBVDDQ_EN 2G COMMON X5R

2
GND 1 R96 0ohm
2 0402 5% COMMON S 1 0402
0402 COMMON 60V
COMMON
0.115A
5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V
0.8A
0.2W GND
20V

1R143 0ohm
2 PS_IOVDD_EN R128
OUT 33 10k
0402 COMMON

1
C93 5%
10nF 0402
DNI
16V
10%
1R142 0ohm
2 X5R

2
0402 DNI 0402 GND
COMMON

GND
GND
1R140 1k 2 PS_PEXVDD_EN
23
OUT
2 0402 5% COMMON 2

1R145 1k 2
0402 5% DNI

3V3_F

VID PLL
R527
10k
1R136 1k 2 PS_VIDPLL_EN
23
5% OUT
12V_F 3V3_F 0402 5% COMMON
0402
COMMON

1
C97

R517 R518
POWER CONNECTOR HOT-UNPLUG DETECT 10nF
16V
10k 1k PEX Input Present 10%
X5R

2
5% 1%
0402 0402 not found 0402
COMMON DNI 1B1C1E 3 INPUT_HOTUNPLUG* 1R528 0ohm
2 COMMON
R525 C Q512 0402 COMMON 3V3_F
INPUT_PEX6_DT1* 1R512 1k 2 1 10k 2 INPUT_HOT_UNPLUG_DT_R B1 @discrete.q_npn(sym_1):page31_i240
IN SOT23_1B1C1E
0402 1% COMMON 0402 5% COMMON POWER OFF GND
COMMON
R511 E 2 ON HOTPLUG EVENT PEX VDD
3.24k
1

C503
STUFF TO LATCH
1% 0.1uF
0402
3V3_F
23
PS_PEXVDD_PGOOD 1R655 10k 2
25V IN
COMMON 0402 5% COMMON
10%
X7R
2

0603 INPUT_EN_HPD
COMMON R507
10k
5%
3 GND not found 3
0402
GND COMMON 1B1C1E 3
C Q508
INPUT_HOT_UNPLUG_R INPUT_HOT_UNPLUG_Q
3not found B1 @discrete.q_npn(sym_1):page31_i239
R523 C Q507 SOT23_1B1C1E
1B1C1E COMMON
1 10k 2 B1 @discrete.q_npn(sym_1):page31_i236 E 2
SOT23_1B1C1E
0402 5% COMMON
COMMON
1

C501 E 2
0.1uF
16V
10%
INPUT_EN_HPD_Q
X7R
2

0402
COMMON GND 1G1D1S 3
D Q510
R524 GND @discrete.q_fet_n_enh(sym_2):page31_i235
PEX Input - Power Level/PSI* Control GPIO12_LOW_PERF* GPU SPEED
10k 2 SOT23_1G1D1S
1 INPUT_NVVDD_EN_HPD 1G COMMON
0402 5% COMMON S 2 60V
1

C504 0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V 0 Slow
0.1uF 0.31A
0.3W
16V 20V

10%
1 Normal
X7R
2

0402 3V3_F
COMMON GND

R516
GND
10k
5%
0402
COMMON

GPIO12_LOW_PERF*
OUT 21,30
4
THERM OVERT SHUTDOWN LATCH 4

21
THERM_OVERT* 1R157 0ohm
2 3V3_F
IN
0402 COMMON
3V3_F

R510
10k
R515 5%
10k 0402
DNI
5%
0402
COMMON not found GPIO6_PSI_R* 1R520 0ohm
2 GPIO6_PSI*
21,25
OUT
1B1C1E 3 0402 COMMON
3 C Q506
1G1D1S
D Q505B 6 LOWPWR_MODE 1R519 100ohm
2 LOWPWR_MODE_R B1 @discrete.q_npn(sym_1):page31_i271
1G1D1S
@discrete.q_fet_n_enh(sym_2):page31_i373 D Q505A 0402 COMMON
SOT23_1B1C1E
1% COMMON
SOT363
INPUT_PEX6_DT1_R* 5G COMMON
@discrete.q_fet_n_enh(sym_2):page31_i374 E 2
S 4 2G SOT363 R509
COMMON 100k
60V S 1
0.115A 5%
5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V 60V
0.8A 0.115A
0402
0.2W 5000mohm@10V / 7500mohm@4.5V / -1000mohm@2.5V COMMON
20V 0.8A
0.2W
20V

GND GND
GND GND

5 5

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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 31 of 34
A B C D E F G H
A B C D E F G H

LEDs

1 1

2 2

IFP_IOVDD (backdrive prevention)

Kepler Only 3V3_F


3V3_BLK

1G1D1S 3
R503 D Q503
GPU_BUFRST* 1 1k 2 @discrete.q_fet_p_enh(sym_2):page32_i750
22 IN
3 0402 1% DNI 1G1D1S 3 IFP_IOVDD_EN 1G SOT23_1G1D1S
3.3V 3
D COMMON
Q502 S 2 16MIL
@discrete.q_fet_n_enh(sym_2):page32_i752 -20V
SOT23_1G1D1S
3,20
PEX_RST_BUF* 1R504 1k 2 GPU_RST_R* 1G COMMON
-3A
-1000mohm@10V / 70mohm@4.5V / 115mohm@2.5V
IN
0402 1% COMMON S 2 60V 1R506 10k 2 -9A
[]

1
C502 R505 0.26A
0402 COMMON
12V
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V 5%
100pF 10k 0.31A
0.3W
50V 5% 20V

5% 0402
C0G DNI

2
0402
DNI

GND GND GND

SLI LED and Quadro LED 3V3_F


LED HEADER
NV3V3
GeForce Logo LED (C0MM0N) 12V_F
Quadro LED
R2
470ohm
R853 12V_F
5%
3.3k 0402
5% COMMON
R177 R180 R660 R657 0402
QUADRO_LED

-1000mohm@10V / 60mohm@4.5V / 96mohm@2.5V


COMMON
604ohm 680ohm 1k 1k
4 4
DS1

2
1% 5% 5% 5%
603 603 603 603 21
GPIO20_SLI_LED_DIM 1R860 10k 2
IN @discrete.led(sym_1):page32_i792 R864 R857
DNI COMMON COMMON COMMON 0402 5% COMMON
20mA 44.2ohm 44.2ohm
12V_F 2.5V 1% 1%
12V_F
0603 0603
Default
NV3V3 J8

INS10914818
COMMON COMMON

SOT23_1G1D1S
1
LED 0805
1 R854
LED_Q* 2 27k COMMON R861

COMMON
-3.5A
1.5W
-14A

-20V
27k

12V

D Q534
5% SLI_LED_R SLI_LED
20

3
R666 5% OUT
HEADER_1X2_SHROUDED not found 0402
10k 0402
COMMON
3 3

S
1G1D1S 1B1C1E COMMON
5% D Q517 N32-1020511-J11 C Q525 GPIO5_LED_Q SLI_LED_Q
402 R856
R665 1k INS9694989 VVVV32020 B1 @discrete.q_npn(sym_1):page32_i248 3 6

1 G
COMMON 1G1D1S
R667 0ohm SOT23_1G1D1S SOT23_1B1C1E D D 0ohm
21
GPIO11_LOGO_LED GPIO11_LOGO_LED_R LED_ON 1G COMMON COMMON
Q532B Q532A
IN
402 0.05 ohmCOMMON 402 COMMON S 2 E 2 NV3V3 @discrete.q_fet_n_enh(sym_2):page32_i780 @discrete.q_fet_n_enh(sym_2):page32_i781
C764 SOT363 SOT363 0402
1% 60V 5G COMMON 2G COMMON DNI
0.26A
0.1uF 3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V S 4 S 1 GPIO5_LED_Q_N
0.31A
16V 0.3W 3
10%
20V
Q533 D
X7R @discrete.q_fet_n_enh(sym_2):page32_i256
402 SOT23_1G1D1S G1
GND COMMON
COMMON
2 S GND
GND GND

GND

5 5

MICRO-STAR INT'L CO.,LTD


MS-V320
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ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 32 of 34
A B C D E F G H
A B C D E F G H

PS: IOVDD, NV3V3, NV12V

1 1

OVR0 1.8V REGULATOR. STUFF FOR 16nm


3V3_F 5V 12V_F 3V3_F 5V

R1646 R1647
0ohm 0ohm 0ohm 0ohm 0ohm
0.05 ohm 0.05 ohm
0402 0402 0402 0603 0603
COMMON COMMON COMMON COMMON COMMON

PS_VIN_IOVDD

3V3_F nv_res
5V

1
1uF

1
R1649
16V 22uF 0ohm 10k
10% 25V 5%
X5R

2
10% 0402 0402
0603 X5R COMMON COMMON

2
COMMON 1206 PS_BOOT_IOVDD
@power_supply.u_openvreg_type0(sym_1):page33_i17
0.6V COMMON

GND DFN10 GND .4


COMMON
3A 0.065ohm IOVDD
PS_IOVDD_PGOOD 9 3
OUT PGOOD VIN 1.3A
OpenVReg 1.9A
PS_IOVDD_EN 10
IN EN/FS
8 1 0.1uF
2 L19 1uH
BOOT/NC
0.381 0402 16V SMD_3X3 COMMON
2 PS_IOVDD_VCC 2 10% 2
VCC X7R
0.381 SW 6 COMMON

1
7 PS_SW_IOVDD C705
SW 22uF 22uF
GND 4 0.381 Special Note:
PS_FB_IOVDD 6.3V 6.3V
1 FB GND 5 1. Place [C_OUT] close to [L_OUT]
20% 20%
THERM 11 X5R X5R
2. Use local FB sense (refer to design guide for detals)

2
PS_FF_FB_OVR0 0805 0805 3. Place PLL/IO filter ferrite bead to the same position as FB local sense point
COMMON COMMON
15nF
2 1 1nv_res 0ohm
2
16V 0402 0402 COMMON
10%
GND 0.508
X7R R1648 2k 2
COMMON
1 GND
0402 1% COMMON GND

1k BYPASS. STUFF FOR 28nm


1%
0402
COMMON

3V3_F IOVDD

1 0ohm
2
GND 0805 COMMON

1 0ohm
2 3.3V
0805 COMMON

NV3V3
3 3

Gated rails required for 16nm 1 0ohm


2 3.3V
0805 COMMON

12V_F NV12V
12V_F

R514 1 0ohm
2 12V
10k
0402 COMMON
5%
0402 10k
COMMON
5%
0402 1G1D1S
PS_PG_IOVDD_R2 COMMON 8V
0.34W
S -5A
[ ]@10V / 150mohm@4.5V / 190mohm@2.5V
G 2 -1.3A NV12V 3V3_F
-20V
3 PS_PG_IOVDD* 1 NV3V3
1G1D1S COMMON
D Q509 D SOT323_1G1D1S NV3V3
@discrete.q_fet_n_enh(sym_2):page33_i73 @discrete.q_fet_p_enh(sym_2):page33_i29
SOT23_1G1D1S
1G COMMON 3
S 2 1G1D1S 3

1
D
60V @discrete.d_zener(sym_2):page33_i58
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
@discrete.q_fet_n_enh(sym_2):page33_i32 SOD123
SOT23_1G1D1S
0.31A
0.3W 1G COMMON IOVDD 1.89V
20V 0.5W
S 2

2
DNI
GND 20V
1A
-1000mohm@10V / 213mohm@4.5V / -1000mohm@2.5V
100k
1

5A
0.6W
5% 0.1uF 16V
4 4
0402

1
16V
COMMON
10% 100k 0.1uF
X7R
2

5% 16V
0402
0402 10%
COMMON
COMMON X7R

2
0402
GND GND COMMON

GND GND

5 5

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 33 of 34
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A B C D E F G H

Mechanical: Bracket/Thermal Solution

1 1

2 2

Brackets:

BKT1
@mechanic.bracket(sym_4):page34_i31
ATX_2X_2P
COMMON

1 MEC17 MEC21 MEC10


H_R220D125 H_R220D125 H_R220D125
HDMISCREW1
1 1 1 HDMI_FEE1
DNI DNI DNI MEC_SCREW_PH1

MEC22 MEC11
COMMON

HDMI
MEC18 H_R220D125 H_R220D125
$$$$$$
MECH. MOUNTING ALL

H_R220D125 1 1
1 DNI DNI M3_SCREW HDMI_FEE
DNI E43-1303012-H75 COMMON
MEC7 MEC12 VVVV32020
H_R220D125 H_R220D125 VVVV32020 Y01-RHDMI03-000
MEC19 1 1
H_R220D125 DNI DNI

2 1
3 DNI MEC8 MEC13 3
MECS1
H_R220D125 H_R220D125
1 1 MEC_SCREW_HEX_JACK
MEC20 DNI DNI COMMON

H_R220D125 MEC23
GND 1 MEC9 H_R220D125
DNI H_R220D125 1 E42-5047001-H75
1 DNI
DNI MEC24 VVVV32020
H_R220D125
MECS2
1
DNI MEC_SCREW_HEX_JACK
COMMON

GND

E42-5047001-H75

VVVV32020

GND

J11 J12
3 1 3 1
4 4 2 4 2 4
impedence impedence

FM1 FM2 FM3 FM4


TOP:PEX_RX6 BOT:IFPC_TXC

0.101 / 0.123mm 90ohm +/-10% 0.102 / 0.178mm 95ohm +/-10%


OPT OPT OPT OPT
F_PAD_X F_PAD_X F_PAD_X F_PAD_X

FM5 FM6 FM7 FM8

J16 J17

OPT OPT OPT OPT


F_PAD_X F_PAD_X F_PAD_X F_PAD_X

X_PIN1*2 X_PIN1*2

5
TOP:FBC_D<56> L3:FBC_DBI<6> 5

47ohm / 0.126mm 47ohm / 0.127mm

MICRO-STAR INT'L CO.,LTD


MS-V320
MSI
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY Size Document Description Rev
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL Custom 01_Table of Contents 2.0
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Date: Monday, November 17, 2014 Sheet 34 of 34
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