A B C D E

1 1

Compal Confidential
KALG1- M/B Schematics Document
2 2

Intel Penryn Processor with Cantiga + DDRII + ICH9M

2009-04-17
REV 01
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 1 of 45
A B C D E
 A B C D E

Compal Confidential
Model Name : KALG1-
Intel Penryn Processor Thermal Sensor Clock Generator
File Name : LA-XXXXP Fan Control
page 4
EMC 1402 ICS9LPRS387
1
uPGA-478 Package page 4 page 16 1

(Socket P) page 4,5,6

FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.

page 24 page 17 page 18
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
TMDS LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

LVDS uFCBGA-1329 1.8V DDRII 667/800

HDMI PCI-Express
page 7,8,9,10,11,12,13
ASM1442T
page 24
LS-4494P
DMI C-Link USB conn x3 Bluetooth CMOS Finger Print
USB port 0, 1, 6 Conn Camera AES1610
2 2
page 29 page 29 page 17 page 29

PCI-Express
Intel ICH9-M 3.3V 48MHz USB
3.3V 24.576MHz/48Mhz HD Audio
S-ATA
BGA-676 Card Reader
LAN(GbE) MINI Card x1 NEW Card page 20,21,22,23 RTS5159-GR
ATHEROS AR8131 WLAN page 25
page 26 page 28 page 28 GMCH HDA MDC 1.5 HDA Codec
port 2

port 1

port 0
Conn ALC888S-VC
page 08 page 32 page 33

RJ45 ESATA CDROM SATA HDD

page 27
Conn. Conn. Conn. Audio AMP
3
page 29 page 23 page 23 APA2051 3

page 34
LPC BUS

ENE KB926 Phone Jack x3

page 30 page 34

RTC CKT.
page 20
Int.KBD
Touch Pad page 31
page 31
Power On/Off CKT.
page 32

DC/DC Interface CKT. BIOS CIR

page 31 page 30
page 37
4 4

Power Circuit DC/DC

page 38,39,40,41,42,43
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

POWER SW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev

WWW.AliSaler.Com Page 36 B 0.1

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 2 of 45
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.75VS 0.75VS power rail for DDR3 terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for NB(LVDS) ON ON OFF Vcc 3.3V +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Ra/Rc/Re 100K +/- 5%
+3V_LAN 3.3V power rail for LAN ON ON ON Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3V 3.3V power rail for SB ON ON OFF 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1
+5VALW 5V always on power rail ON ON ON* 2
+5V 5V power rail for SB ON ON OFF 3
+5VS 5V switched power rail ON OFF OFF 4
+VSB VSB always on power rail ON ON ON* 5
+RTCVCC RTC power ON ON ON 6
7
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table
Board ID PCB Revision
External PCI Devices 0 PCB 08Y LA-5271P REV1 M/B
1
Device IDSEL# REQ#/GNT# Interrupts
2
3
4
5
6
7

EC SM Bus1 address EC SM Bus2 address BTO Option Table

3 3
Device Address Device Address BTO Item BOM Structure
Smart Battery 0001 011X b EMC1402 1001 100X b GL40 GL40@
GM45 GM45@

BOM Configuration Table

Project BOM Configuration
ICH9M SM Bus address KALG1_GM45 GM45@/KALG1@/KAL90_G0_90+@
Device Address
KALG1_GL40 GL40@/KALG1@/KAL90_G0_90+@
KAL90+_GL40 GL40@/KAL90_H0_90+@/KAL90_90+@/KAL90_G0_90+@
Clock Generator 1101 001Xb KAL90+_GM45 GM45@/KAL90_H0_90+@/KAL90_90+@/KAL90_G0_90+@
(ICS9LPRS387, SLG8SP556V)
DDR2 DIMMA 1001 000Xb
KALH0+_GL40 GL40@/KAL90_H0_90+@/KALH0@
DDR2 DIMMB 1001 010Xb
KALH0+_GM45 GM45@/KAL90_H0_90+@/KALH0@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 3 of 45
A B C D E
 5 4 3 2 1

H_A#[3..35]
[7] H_A#[3..35]
H_REQ#[0..4]
[7] H_REQ#[0..4]
H_RS#[0..2]
[7] H_RS#[0..2]

FAN1 Conn
JCPU1A +5VS
D H_A#3 J4 H1 C81 10U_0805_10V4Z +5VS D
A[3]# ADS# H_ADS# [7]

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# [7] 1 2
H_A#5 A[4]# BNR#
L4 A[5]# BPRI# G5 H_BPRI# [7]

1
H_A#6 K5
H_A#7 A[6]# U4 D16
M3 A[7]# DEFER# H5 H_DEFER# [7]
H_A#8 N2 F21 1 8 1SS355_SOD323-2
A[8]# DRDY# H_DRDY# [7] VEN GND
H_A#9 J1 E1 2 7
A[9]# DBSY# H_DBSY# [7] VIN GND
H_A#10 N3 +VCC_FAN1 3 6

2
H_A#11 A[10]# VO GND
P5 A[11]# BR0# F1 H_BR0# [7] [30] EN_DFAN1 2 R43 1 4 VSET GND 5 D15
H_A#12 P2 300_0402_5% 1 2
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# 1 APL5605KI-TRL SOP 8P
H_A#14 A[13]# IERR# C73 BAS16_SOT23-3
P4 A[14]# INIT# B3 H_INIT# [20]
H_A#15 P1 C88
H_A#16 A[15]# 0.1U_0402_16V4Z 10U_0805_10V4Z
R1 A[16]# LOCK# H4 H_LOCK# [7] 2
[7] H_ADSTB#0 M1 ADSTB[0]# 1 2
C1 H_RESET# H_RESET# [7]
H_REQ#0 RESET# H_RS#0 +3VS C82
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1 1000P_0402_50V7K
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3 1 2

1
H_REQ#3 J3 G2 H_TRDY# [7]
H_REQ#4 REQ[3]# TRDY# R46
L1 REQ[4]#
G6 10K_0402_5%
HIT# H_HIT# [7]
H_A#17 Y2 E4 40mil
A[17]# HITM# H_HITM# [7]
H_A#18 U5 JP27

2
H_A#19 A[18]# +VCC_FAN1
R3 A[19]# BPM[0]# AD4 1
ADDR GROUP_1
H_A#20 W6 AD3
A[20]# BPM[1]# [30] FAN_SPEED1 2
H_A#21 U4 AD1
H_A#22 A[21]# BPM[2]# +1.05VS 3
Y5 A[22]# BPM[3]# AC4 1
XDP/ITP SIGNALS
H_A#23 U1 AC2 C83 ACES_85205-03001
C H_A#24 A[23]# PRDY# XDP_BPM#5 1000P_0402_50V7K CONN@ C
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
A[25]# TCK

1
H_A#26 XDP_TDI 2
T3 A[26]# TDI AA6
H_A#27 W2 AB3 R48 @
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5 56_0402_5%
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# [21]

2
H_A#31 A[30]# DBR#
V4 A[31]#
H_A#32 W3 A[32]#

2
B
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#

E
H_A#35 AA3 D21 H_PROCHOT# 3 1 OCP# [21]
A[35]# PROCHOT#

C
V1 A24 H_THERMDA
[7] H_ADSTB#1 ADSTB[1]# THERMDA Q5 +1.05VS
B25 H_THERMDC
THERMDC MMBT3904_SOT23-3
[20] H_A20M# A6 A20M#
ICH

A5 C7 H_THERMTRIP# [8,20] @
[20] H_FERR# FERR# THERMTRIP#
[20] H_IGNNE# C4 IGNNE#
D5 XDP_TDI R108 1 2 54.9_0402_1%
[20] H_STPCLK# STPCLK#
[20] H_INTR C6 LINT0 H CLK
[20] H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK [16] left NC if no ITP
[20] H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# [16]
XDP_TMS R109 1 2 54.9_0402_1% 39Ohm
M4 RSVD[01]
N5 XDP_BPM#5 R117 1 @ 2 54.9_0402_1%
RSVD[02]
T2 RSVD[03] Layout Note:
V3 RSVD[04] H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RESERVED

B2 RSVD[05]
D2 H_PROCHOT# R53 2 1 56_0402_5%
B RSVD[06] B
D22 RSVD[07]
D3 H_IERR# R52 2 1 56_0402_5%
RSVD[08]
F6 RSVD[09]

Penryn XDP_TRST# R107 2 1 54.9_0402_1%

CONN@
XDP_TCK R116 1 2 54.9_0402_1%

+3VS
C90
0.1U_0402_16V4Z
1 2

U5
H_THERMDA

1 VDD SMCLK 8 EC_SMB_CK2 [30,31]

1
C92 2 7
DP SMDATA EC_SMB_DA2 [30,31]
2200P_0402_50V7K 3 6 1 2 +3VS
2 DN ALERT# R49
10K_0402_5%
BSEL2 BSEL1 BSEL0 BCLK H_THERMDC
4 THERM# GND 5
A A

0 0 0 266 EMC1402-1-ACZL-TR_MSOP8

0 1 0 200
Security Classification Compal Secret Data Compal Electronics, Inc.
0 1 1 166 Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3) & FAN Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63] [7]
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13

DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
[7] H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 [7] C9 VCC[019] VCC[086] AE10
[7] H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 [7] C10 VCC[020] VCC[087] AE12
[7] H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 [7] C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 C
+1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 D[26]# D[58]# AE21 E9 VCC[034]
H_D#27 T24 AD21 H_D#59 E10 G21 +1.05VS
H_D#28 D[27]# D[59]# H_D#60 VCC[035] VCCP[01]
R24 D[28]# D[60]# AC22 E12 VCC[036] VCCP[02] V6
H_D#29 L25 AD23 H_D#61 E13 J6
D[29]# D[61]# VCC[037] VCCP[03]
2

H_D#30 T25 AF22 H_D#62 E15 K6

R385 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% [7] H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 [7] E18 VCC[040] VCCP[06] J21
[7] H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 [7] E20 VCC[041] VCCP[07] K21
[7] H_DINV#1 N24 AC20 H_DINV#3 [7] F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R51 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
Width=4 mil , R54 2 @ 1 1K_0402_5% TEST1 C23 MISC U26 COMP1 R50 1 2 54.9_0402_1% F12 R21
R55 @ 1K_0402_5% TEST2 TEST1 COMP[1] COMP2 R105 27.4_0402_1% VCC[045] VCCP[11]
2 1 D25 AA1 1 2 F14 R6
Spacing: 15mil TEST2 COMP[2] VCC[046] VCCP[12]
2

@ PAD @ TEST3 C24 Y1 COMP3 R106 1 2 54.9_0402_1% F15 T21

T28 TEST3 COMP[3] VCC[047] VCCP[13]
(55Ohm) R386 C457 1 2 0.1U_0402_16V4Z TEST4 AF26 F17 T6
@ TEST5 TEST4 VCC[048] VCCP[14]
2K_0402_1% T31 PAD AF1 TEST5 DPRSTP# E5 H_DPRSTP# [8,20,43] F18 VCC[049] VCCP[15] V21
A26 TEST6 DPSLP# B5 H_DPSLP# [20] F20 VCC[050] VCCP[16] W21
C3 D24 H_DPW R# [7] AA7 20mils
1

TEST7 DPWR# H_PW RGOOD VCC[051]

[16] CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PW RGOOD [20] AA9 VCC[052] VCCA[01] B26 +1.5VS
[16] CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
BSEL[1] SLP# H_CPUSLP# [7] VCC[053] VCCA[02]
[16] CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# [43] AA12 VCC[054] 1 1
AA13 AD6 CPU_VID0 [43] C425 C426
Penryn CONN@ VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1 [43]
AA17 VCC[057] VID[2] AE5 CPU_VID2 [43]0.01U_0402_16V7K
2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3 [43]
AA20 VCC[059] VID[4] AE3 CPU_VID4 [43]
COMP0, COMP2 layout : Width 16mils and Space 25mils (27.4Ohms) AB9 AF3 CPU_VID5 [43] 10U_0805_10V4Z
VCC[060] VID[5]
AC10 AE2 CPU_VID6 [43]
B COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AB10
VCC[061] VID[6]
1 2
B
VCC[062] +CPU_CORE
AB12 R88 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE [43]
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE [43]
VCC[067] VSSSENSE
Penryn CONN@ 1 2
. R89 100_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 R5 +CPU_CORE
VSS[005] VSS[086]
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26 1 2
B13 VSS[012] VSS[093] U3
B16 U6 + C145
VSS[013] VSS[094] 900P_PFAF250E128MNTTE_2.5VM
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
3 4
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
D23 AA16 +CPU_CORE
VSS[033] VSS[114]
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
C E6 AA25 C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 AB4

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
VSS[038] VSS[119]
E14 VSS[039] VSS[120] AB8 1 1 1 1 1 1 1 1
E16 AB11 C445 C446 C447 C448 C428 C429 C430 C431
VSS[040] VSS[121]
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
2 2 2 2 2 2 2 2
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
B B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 +1.05VS
VSS[081] VSS[162]
VSS[163] AF25

Penryn CONN@ 1
. 1 1 1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
330U_D2_2.5VY_R9M

+ C182 C444 C440 C427 C449 C441 C432

2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] [4]
[5] H_D#[0..63] U21A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
D H_D#5 H6 J13 H_A#9 D
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS#
H_D#_33 H_ADS# H_ADS# [4]
C H_D#34 Y6 B16 H_ADSTB#0 C
H_D#_34 H_ADSTB#_0 H_ADSTB#0 [4]
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 [4]
H_D#36 Y12 A9 H_BNR#
H_D#_36 H_BNR# H_BNR# [4]

HOST
H_D#37 Y14 F11 H_BPRI#
H_D#_37 H_BPRI# H_BPRI# [4]
H_D#38 Y7 G12 H_BR0#
H_D#_38 H_BREQ# H_BR0# [4]
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# [4]
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# [4]
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK [16]
H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# [16]
H_D#43 AA9 J11 H_DPW R#
H_D#_43 H_DPWR# H_DPW R# [5]
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# [4]
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# [4]
H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# [4]
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# [4]
H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# [4]
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 [5]
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1 [5]
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 H_DINV#2 [5]
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 [5]
H_D#57 AC1
+1.05VS H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 [5]
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 H_DSTBN#1 [5]
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2 [5]
1

H_D#61 AE8 AE6 H_DSTBN#3

R349 H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3 [5]
AG2 H_D#_62
B 221_0402_1% H_D#63 H_DSTBP#0 B
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 [5]
M8 H_DSTBP#1
+1.05VS H_DSTBP#_1 H_DSTBP#2 H_DSTBP#1 [5]
width=10mil AA6
2

H_SW ING H_DSTBP#_2 H_DSTBP#3 H_DSTBP#2 [5]

C5 H_SWING H_DSTBP#_3 AE5 H_DSTBP#3 [5]
H_RCOMP E3 H_RCOMP H_REQ#[0..4] [4]
C409 width=10mil B15 H_REQ#0
0.1U_0402_16V4Z

H_REQ#_0
2

R350 1 K13 H_REQ#1

H_REQ#_1
1

H_REQ#2
100_0402_1%

H_REQ#_2 F13
R351 B13 H_REQ#3
H_REQ#_3
2

24.9_0402_1% H_RESET# C12 B14 H_REQ#4

2 [4] H_RESET# H_CPURST# H_REQ#_4
R353 H_CPUSLP# E11
[5] H_CPUSLP# H_RS#[0..2] [4]
1

1K_0402_1% H_CPUSLP# H_RS#0

B6
2

H_RS#_0 H_RS#1
H_RS#_1 F12
H_AVREF A11 C8 H_RS#2
1

H_AVREF H_RS#_2
width:spacing=10mil:20mil (<0.5") B11 H_DVREF
1

1 CANTIGA B3_FCBGA1329 GM45@

C413@
R352 0.1U_0402_16V4Z within 100mil to Ball A11,B11
2K_0402_1%
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

U21B R01 +1.8V DDR2

DDR2
M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 [14]

1
N36 AT21 DDRA_CLK1 [14]
RSVD2 SA_CK_1
R33 RSVD3 SB_CK_0 AV24 DDRB_CLK0 [15]
T33 AU20 R343
RSVD4 SB_CK_1 DDRB_CLK1 [15]

COMPENSATION
AH9 1K_0402_1%
RSVD5
AH10 AR24 DDRA_CLK0# [14]

2
RSVD6 SA_CK#_0 SM_RCOMP_VOH
AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# [14]

0.01U_0402_16V7K
AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# [15]

3.01K_0402_1%

2.2U_0603_6.3V6K
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# [15] 1 1

1
AL34 RSVD10
AK34 BC28 R342 C387 C386
RSVD11 SA_CKE_0 DDRA_CKE0 [14]
AN35 AY28 DDRA_CKE1 [14]
D RSVD12 SA_CKE_1 R01 2 2 D
AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 [15]
T24 BB36 DDRB_CKE1 [15]

2
RSVD14 SB_CKE_1
All RSVD balls on GMCH should be left No
Connect. SA_CS#_0 BA17 DDRA_SCS0# [14]
AY16 SM_RCOMP_VOL
SA_CS#_1 DDRA_SCS1# [14]
B31 AV16 DDRB_SCS0# [15]
RSVD15 SB_CS#_0

1
1K_0402_1%

0.01U_0402_16V7K
2.2U_0603_6.3V6K
B2 AR13 DDRB_SCS1# [15] 1 1
RSVD16 SB_CS#_1

DDR CLK/ CONTROL/

M1 R341 C384 C385
RSVD17

RSVD
BD17 DDRA_ODT0 [14]
SA_ODT_0
AY17 DDRA_ODT1 [14]
SA_ODT_1 2 2
AY21 BF15 DDRB_ODT0 [15]

2
RSVD20 SB_ODT_O +1.8V R01 +1.8V
SB_ODT_1 AY13 DDRB_ODT1 [15]
SMRCOMP R340 1 2 80.6_0402_1% R01
SM_RCOMP BG22
DDR2

2
BG23 BH21 SMRCOMP# R339 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# For Cantiga 80 Ohm R103
BF23 RSVD23
BH18 BF28 SM_RCOMP_VOH @ 1K_0402_1% +DIMM_VREF
RSVD24 SM_RCOMP_VOH SM_RCOMP_VOL
BF18 RSVD25 SM_RCOMP_VOL BH28
20mil

1
AV42 SM_VREF 1 2
SM_VREF SM_PWROK R01
SM_PWROK AR36 1 R215 2 0_0402_5% R104 0_0402_5%

2
BF17 SM_REXT 1 R338 2 499_0402_1% 1
SM_REXT R102
SM_DRAMRST# BC36
R01 C171 @ 1K_0402_1%
0.1U_0402_16V4Z
B38 CLK_DREF_96M 2
CLK_DREF_96M [16]

1
DPLL_REF_CLK CLK_DREF_96M#
DPLL_REF_CLK# A38 CLK_DREF_96M# [16]
E41 CLK_DREF_SSC
DPLL_REF_SSCLK CLK_DREF_SSC# CLK_DREF_SSC [16]
DPLL_REF_SSCLK# F41 CLK_DREF_SSC# [16]

CLK
F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL [16]
E43
C PEG_CLK# CLK_MCH_3GPLL# [16]
Strap Pin Table C

011 = FSB667
AE41 DMI_ITX_MRX_N0 CFG[2:0] 010 = FSB800
DMI_RXN_0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N0 [21]
DMI_RXN_1 AE37 DMI_ITX_MRX_N1 [21] 000 = FSB1067
AE47 DMI_ITX_MRX_N2
DMI_RXN_2 DMI_ITX_MRX_N2 [21]
AH39 DMI_ITX_MRX_N3 0 = DMI x 2
DMI_RXN_3 DMI_ITX_MRX_N3 [21]
AE40 DMI_ITX_MRX_P0
CFG5 1 = DMI x 4 * (Default)
MCH_CLKSEL0 DMI_RXP_0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P0 [21]
[16] MCH_CLKSEL0 T25
CFG_0 DMI_RXP_1
AE38 DMI_ITX_MRX_P1 [21] 0 = iTPM Host Interface is enabled
MCH_CLKSEL1 DMI_ITX_MRX_P2
[16] MCH_CLKSEL1
MCH_CLKSEL2
R25
P25
CFG_1 DMI_RXP_2
AE48
AH40 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 [21] CFG6 1 = iTPM Host Interface is Disabled *(Default)
[16] MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 [21]
P20
CFG_3 DMI_MTX_IRX_N0
0 = Lane Reversal Enable
2 PM_EXTTS#0 MCH_CFG_5
P24
CFG_4 DMI_TXN_0
AE35
DMI_MTX_IRX_N1 DMI_MTX_IRX_N0 [21] CFG9 1 = Normal Operation * (Default)

DMI
+3VS 1 C25
CFG_5 DMI_TXN_1
AE43 DMI_MTX_IRX_N1 [21]
R94 10K_0402_5% MCH_CFG_6 N24 AE46 DMI_MTX_IRX_N2 0 = PCIe Loopback Enable
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 [21]
1 2 PM_EXTTS#1 MCH_CFG_7 M24 AH42 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 [21] CFG10 1 = Disable * (Default)
R84 10K_0402_5% CFG_7 CFG DMI_TXN_3
E21
CFG_8
1 2 MCH_CLKREQ# MCH_CFG_9 C23 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 [21] 00 = Reserved
R93 10K_0402_5% MCH_CFG_10 CFG_9 DMI_TXP_0 DMI_MTX_IRX_P1
C24
CFG_10 DMI_TXP_1
AE44
DMI_MTX_IRX_P2 DMI_MTX_IRX_P1 [21] CFG[13:12] 01 = XOR Mode Enabled
N21
CFG_11 DMI_TXP_2
AF46 DMI_MTX_IRX_P2 [21] 10 = All Z Mode Enabled
Use VGATE for GMCH_PWROK MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3 11 = Normal Operation * (Default)
MCH_CFG_13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 [21]
T21
VGATE @ GMCH_PWROK CFG_13
[16,21,43] VGATE 1 2 R20
CFG_14 0 = Dynamic ODT Disabled
R101 0_0402_5%
ICH_PWROK 1 2 MCH_CFG_16
M20
L21
CFG_15 CFG16 1 = Dynamic ODT Enabled * (Default)
[21] ICH_PWROK CFG_16
R100 0_0402_5% H21 0 = Normal Operation *(Default)
CFG_17
P29 CFG19 1 = DMI Lane Reversal Enable
GRAPHICS VID

MCH_CFG_19 CFG_18
R28
MCH_CFG_20 CFG_19
T28
CFG_20 GFX_VID_0
B33 0 = Only PCIE or SDVO is operational.
GFX_VID_1
B32
G33
CFG20 * (Default)
B GFX_VID_2
F33 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu. B
R110 1 PM_SYNC#_R GFX_VID_3
[21] PM_SYNC# 2 0_0402_5% R29
PM_SYNC# GFX_VID_4
E33
R64 1 2 0_0402_5% PM_DPRSTP#_R
[5,20,43] H_DPRSTP#
PM_EXTTS#0
B7
PM_DPRSTP# 0 = No SDVO Card Present * (Default)
[14] PM_EXTTS#0 N33
PM_EXT_TS#_0 SDVO_CTRLDATA 1 = SDVO Card Present
PM

[15] PM_EXTTS#1 PM_EXTTS#1 P32

GMCH_PWROK PM_EXT_TS#_1
R62 1 2 100_0402_5% MCH_RSTIN#
AT40
PWROK GFX_VR_EN
C34 0 = LFP Disable * (Default)
[19,26,30] PLT_RST#
THERMTRIP#_R
AT11
RSTIN# +1.05VS
L_DDC_DATA 1 = LFP Card Present; PCIE disable
[4,20] H_THERMTRIP# R70 1 2 0_0402_5% T20
R111 1 0_0402_5% DPRSLPVR_R THERMTRIP#
[21,43] PM_DPRSLPVR 2 R32
DPRSLPVR R97
0 = Digital DisplayPort Disable * (Default)
DDPC_CTRLDATA 1 = Digital DisplayPort Device Present

1K_0402_1%
BG48 AH37 CL_CLK0 [21]
NC_1 CL_CLK
BF48 AH36 CL_DATA0 [21]
NC_2 CL_DATA
ME

BD48 AN36 ICH_PWROK

NC_3 CL_PWROK MCH_CFG_5 @
BC48 AJ35 CL_RST#0 [21] 2 1

1
NC_4 CL_RST# CL_VREF R355 2.21K_0402_1%
BH47 AH34
NC_5 CL_VREF MCH_CFG_6 @
BG47 2 1
NC_6

2
BE47 R77 4.02K_0402_1%
NC_7 R98 MCH_CFG_7 @
BH46 N28 1 2 1
NC_8 DDPC_CTRLCLK
NC

BF46 M28 C164 R78 2.21K_0402_1%

NC_9 DDPC_CTRLDATA

511_0402_1%
BG45 G36 SDVO_SCLK MCH_CFG_9 2 @ 1
+3VS NC_10 SDVO_CTRLCLK SDVO_SCLK [24]

0.1U_0402_16V4Z
BH44 E36 SDVO_SDATA R66 2.21K_0402_1%
SDVO_SDATA [24]

1
NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 MCH_CFG_10 @
BH43 K36 MCH_CLKREQ# [16] 2 1
NC_12 CLKREQ#
MISC

BH6 H36 MCH_ICH_SYNC# [21] R67 2.21K_0402_1%

NC_13 ICH_SYNC#
1

+3VS BH5 MCH_CFG_12 2 @ 1

R56 NC_14 R69 2.21K_0402_1%
BG4
1K_0402_5% NC_15 MCH_TSATN# MCH_CFG_13 @
BH3 B12 2 1
NC_16 TSATN#
1

+1.05VS BF3 R71 2.21K_0402_1%

R57 NC_17 MCH_CFG_16 @
BH2 2 1
2

1K_0402_5% NC_18 R68 2.21K_0402_1%

MCH_TSATN_EC# [30] BG2
NC_19
1

BE2 B28 HDA_BITCLK_MCH

NC_20 HDA_BCLK HDA_BITCLK_MCH [20]
1

R61 C BG1 B30 HDA_RST_MCH#

HDA_RST_MCH# [20]
2

A 54.9_0402_1% Q6 NC_21 HDA_RST# HDA_SDIN2_MCH A

2 BF1 B29 1 2 HDA_SDIN2 [20]
B NC_22 HDA_SDI HDA_SDOUT_MCH MCH_CFG_19
R58 MMBT3904_SOT23-3 BD1 NC_23 HDA_SDO C29 HDA_SDOUT_MCH [20]R356 33_0402_5% 2 @ 1 +3VS
1

C E BC1 A28 HDA_SYNC_MCH R86 4.02K_0402_1%

HDA

HDA_SYNC_MCH [20]
2

MCH_TSATN# Q7 NC_24 HDA_SYNC MCH_CFG_20

1 2 2 F1 2 @ 1
B NC_25 R87 4.02K_0402_1%
MMBT3904_SOT23-3 A47 NC_26 Notice: Please check HDA power rail to select HDA controller.
330_0402_5% E
3

CANTIGA B3_FCBGA1329 GM45@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(2/7)-DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

R01

D D

[15] DDRB_SDQ[0..63]
U21E
[14] DDRA_SDQ[0..63]
U21D DDRB_SDQ0 AK47 BC16
SB_DQ_0 SB_BS_0 DDRB_SBS0# [15]
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ1 AH46 BB17
SA_DQ_0 SA_BS_0 DDRA_SBS0# [14] SB_DQ_1 SB_BS_1 DDRB_SBS1# [15]
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ2 AP47 BB33
SA_DQ_1 SA_BS_1 DDRA_SBS1# [14] SB_DQ_2 SB_BS_2 DDRB_SBS2# [15]
DDRA_SDQ2 AN38 AT25 DDRB_SDQ3 AP46
SA_DQ_2 SA_BS_2 DDRA_SBS2# [14] SB_DQ_3
DDRA_SDQ3 AM38 DDRB_SDQ4 AJ46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ5 SB_DQ_4
AJ36 BB20 DDRA_SRAS# [14] AJ48 AU17 DDRB_SRAS# [15]
DDRA_SDQ5 SA_DQ_4 SA_RAS# DDRB_SDQ6 SB_DQ_5 SB_RAS#
AJ40 BD20 DDRA_SCAS# [14] AM48 BG16 DDRB_SCAS# [15]
DDRA_SDQ6 SA_DQ_5 SA_CAS# DDRB_SDQ7 SB_DQ_6 SB_CAS#
AM44 AY20 DDRA_SWE# [14] AP48 BF14 DDRB_SWE# [15]
DDRA_SDQ7 SA_DQ_6 SA_WE# DDRB_SDQ8 SB_DQ_7 SB_WE#
AM42 AU47
DDRA_SDQ8 SA_DQ_7 DDRB_SDQ9 SB_DQ_8
AN43 AU46
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ10 SB_DQ_9
AN44 BA48
DDRA_SDQ10 SA_DQ_9 DDRB_SDQ11 SB_DQ_10
AU40 AY48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ12 SB_DQ_11
AT38 DDRA_SDM[0..7] [14] AT47
DDRA_SDQ12 SA_DQ_11 DDRB_SDQ13 SB_DQ_12
AN41 AR47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ14 SB_DQ_13
AN39 AM37 BA47 DDRB_SDM[0..7] [15]
DDRA_SDQ14 SA_DQ_13 SA_DM_0 DDRA_SDM1 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU44 AT41 BC47 AM47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ16 SB_DQ_15 SB_DM_0 DDRB_SDM1
AU42 AY41 BC46 AY47
DDRA_SDQ16 SA_DQ_15 SA_DM_2 DDRA_SDM3 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AV39 AU39 BC44 BD40
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ18 SB_DQ_17 SB_DM_2 DDRB_SDM3
AY44 BB12 BG43 BF35
DDRA_SDQ18 SA_DQ_17 SA_DM_4 DDRA_SDM5 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4
BA40 AY6 BF43 BG11
DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ20 SB_DQ_19 SB_DM_4 DDRB_SDM5
BD43 AT7 BE45 BA3
DDRA_SDQ20 SA_DQ_19 SA_DM_6 DDRA_SDM7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AV41 AJ5 BC41 AP1
SA_DQ_20 SA_DM_7 SB_DQ_21 SB_DM_6

B
DDRA_SDQ21 AY43 DDRB_SDQ22 BF40 AK2 DDRB_SDM7
DDRA_SDQ22 SA_DQ_21 A DDRB_SDQ23 SB_DQ_22 SB_DM_7
BB41 BF41
DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ24 SB_DQ_23
BC40 AJ44 DDRA_SDQS0 [14] BG38
DDRA_SDQ24 SA_DQ_23 SA_DQS_0 DDRA_SDQS1 DDRB_SDQ25 SB_DQ_24 DDRB_SDQS0
AY37 AT44 DDRA_SDQS1 [14] BF38 AL47 DDRB_SDQS0 [15]
DDRA_SDQ25 SA_DQ_24 SA_DQS_1 DDRA_SDQS2 DDRB_SDQ26 SB_DQ_25 SB_DQS_0 DDRB_SDQS1

MEMORY
BD38 BA43 DDRA_SDQS2 [14] BH35 AV48 DDRB_SDQS1 [15]
DDRA_SDQ26 SA_DQ_25 SA_DQS_2 DDRA_SDQS3 DDRB_SDQ27 SB_DQ_26 SB_DQS_1 DDRB_SDQS2
AV37 BC37 BG35 BG41
MEMORY

SA_DQ_26 SA_DQS_3 DDRA_SDQS3 [14] SB_DQ_27 SB_DQS_2 DDRB_SDQS2 [15]

DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 [14] SB_DQ_28 SB_DQS_3 DDRB_SDQS3 [15]
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 [14] SB_DQ_29 SB_DQS_4 DDRB_SDQS4 [15]
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 [14] SB_DQ_30 SB_DQS_5 DDRB_SDQS5 [15]
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 [14] SB_DQ_31 SB_DQS_6 DDRB_SDQS6 [15]
DDRA_SDQ31 AW36 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_31 SB_DQ_32 SB_DQS_7 DDRB_SDQS7 [15]
C DDRA_SDQ32 BD13 DDRB_SDQ33 BG12 C
DDRA_SDQ33 SA_DQ_32 DDRA_SDQS0# DDRB_SDQ34 SB_DQ_33
AU11 AJ43 DDRA_SDQS0# [14] BH11
DDRA_SDQ34 SA_DQ_33 SA_DQS#_0 DDRA_SDQS1# DDRB_SDQ35 SB_DQ_34 DDRB_SDQS0#
BC11 AT43 DDRA_SDQS1# [14] BG8 AL46 DDRB_SDQS0# [15]
SA_DQ_34 SA_DQS#_1 SB_DQ_35 SB_DQS#_0

SYSTEM
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# [14] SB_DQ_36 SB_DQS#_1 DDRB_SDQS1# [15]
DDRA_SDQ36 AU13 BD37 DDRA_SDQS3# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SYSTEM

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# [14] SB_DQ_37 SB_DQS#_2 DDRB_SDQS2# [15]

DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# [14] SB_DQ_38 SB_DQS#_3 DDRB_SDQS3# [15]
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# [14] SB_DQ_39 SB_DQS#_4 DDRB_SDQS4# [15]
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# [14] SB_DQ_40 SB_DQS#_5 DDRB_SDQS5# [15]
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# [14] SB_DQ_41 SB_DQS#_6 DDRB_SDQS6# [15]
DDRA_SDQ41 BA9 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_41 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7# [15]
DDRA_SDQ42 AU10 DDRB_SDQ43 AY1
SA_DQ_42 DDRA_SMA[0..14] [14] SB_DQ_43
DDRA_SDQ43 AV9 DDRB_SDQ44 BF6 DDRB_SMA[0..14] [15]
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ45 SB_DQ_44 DDRB_SMA0
BA11 BA21 BF5 AV17

DDR
DDRA_SDQ45 SA_DQ_44 SA_MA_0 DDRA_SMA1 DDRB_SDQ46 SB_DQ_45 SB_MA_0 DDRB_SMA1
BD9 BC24 BA1 BA25
SA_DQ_45 SA_MA_1 SB_DQ_46 SB_MA_1
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ47 BD3 BC25 DDRB_SMA2

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ48 SB_DQ_47 SB_MA_2 DDRB_SMA3
BA6 BH24 AV2 AU25
DDRA_SDQ48 SA_DQ_47 SA_MA_3 DDRA_SMA4 DDRB_SDQ49 SB_DQ_48 SB_MA_3 DDRB_SMA4
AV5 BG25 AU3 AW25
DDRA_SDQ49 SA_DQ_48 SA_MA_4 DDRA_SMA5 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AV7 BA24 AR3 BB28
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ51 SB_DQ_50 SB_MA_5 DDRB_SMA6
AT9 BD24 AN2 AU28
DDRA_SDQ51 SA_DQ_50 SA_MA_6 DDRA_SMA7 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AN8 BG27 AY2 AW28
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ53 SB_DQ_52 SB_MA_7 DDRB_SMA8
AU5 BF25 AV1 AT33
DDRA_SDQ53 SA_DQ_52 SA_MA_8 DDRA_SMA9 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AU6 AW24 AP3 BD33
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ55 SB_DQ_54 SB_MA_9 DDRB_SMA10
AT5 BC21 AR1 BB16
DDRA_SDQ55 SA_DQ_54 SA_MA_10 DDRA_SMA11 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AN10 BG26 AL1 AW33
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ57 SB_DQ_56 SB_MA_11 DDRB_SMA12
AM11 BH26 AL2 AY33
DDRA_SDQ57 SA_DQ_56 SA_MA_12 DDRA_SMA13 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AM5 BH17 AJ1 BH15
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ59 SB_DQ_58 SB_MA_13 DDRB_SMA14
AJ9 AY25 AH1 AU33
DDRA_SDQ59 SA_DQ_58 SA_MA_14 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AJ8 AM2
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ61 SB_DQ_60
AN12 AM3
DDRA_SDQ61 SA_DQ_60 DDRB_SDQ62 SB_DQ_61
AM13 AH3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ63 SB_DQ_62
AJ11 AJ3
DDRA_SDQ63 SA_DQ_62 SB_DQ_63
AJ12
SA_DQ_63 CANTIGA B3_FCBGA1329 GM45@
CANTIGA B3_FCBGA1329 GM45@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(3/7)-DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

U21C

[17] DPST_PW M L32 L_BKLT_CTRL

[30] ENBKL ENBKL G32 T37 PEG_COMP 1 2 +1.05VS
LCTLA_CLK L_BKLT_EN PEG_COMPI R96 49.9_0402_1%
LCTLB_DATA
M32 L_CTRL_CLK PEG_COMPO T36 10mils
M33 L_CTRL_DATA
[17] GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK
D [17] GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44 D
[17] GMCH_ENVDD M29 L_VDD_EN PEG_RX#_1 J46

2
PEG_RX#_2 L44
R92 1 2 LVDS_IBG C44 L40
R357 2.37K_0402_1% LVDS_IBG PEG_RX#_3
100K_0402_5% B43 LVDS_VBG PEG_RX#_4 N41
2 1 E37 LVDS_VREFH PEG_RX#_5 P48
R91 0_0402_5% E38 N44

1
LVDS_VREFL PEG_RX#_6
PEG_RX#_7 T43
GMCH_TXCLK- C41 U43
[17] GMCH_TXCLK- LVDSA_CLK# PEG_RX#_8
GMCH_TXCLK+ C40 Y43
[17] GMCH_TXCLK+ LVDSA_CLK PEG_RX#_9
B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 LVDSB_CLK PEG_RX#_11 Y36

LVDS
PEG_RX#_12 AA43
GMCH_TXOUT0- H47 AD37
[17] GMCH_TXOUT0- LVDSA_DATA#_0 PEG_RX#_13
GMCH_TXOUT1- E46 AC47
[17] GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- G40 AD39
[17] GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
A40 LVDSA_DATA#_3
PEG_RX_0 H43
GMCH_TXOUT0+ H48 J44
[17] GMCH_TXOUT0+ LVDSA_DATA_0 PEG_RX_1
GMCH_TXOUT1+ D45 L43
[17] GMCH_TXOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TXOUT2+ F40 L41 TMDS_B_HPD#
[17] GMCH_TXOUT2+ LVDSA_DATA_2 PEG_RX_3 TMDS_B_HPD# [24]
B40 LVDSA_DATA_3 PEG_RX_4 N40
PEG_RX_5 P47
A41 LVDSB_DATA#_0 PEG_RX_6 N43
H38 LVDSB_DATA#_1 PEG_RX_7 T42
G37 LVDSB_DATA#_2 PEG_RX_8 U42
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
B42 LVDSB_DATA_0 PEG_RX_11 Y37
C G38 AA42 C
LVDSB_DATA_1 PEG_RX_12
F37 LVDSB_DATA_2 PEG_RX_13 AD36
K37 LVDSB_DATA_3 PEG_RX_14 AC48

PCI-EXPRESS
PEG_RX_15 AD40

Change to 0Ohm when use PM chip J41 PCIE_MTX_GRX_N0 1 2 HDMI_PCIE_MTX_C_GRX_N0

PEG_TX#_0 PCIE_MTX_GRX_N1 C176 0.1U_0402_16V7K HDMI_PCIE_MTX_C_GRX_N1
PEG_TX#_1 M46 1 2
GMCH_TV_COMPS F25 M47 PCIE_MTX_GRX_N2 1 2 C403 0.1U_0402_16V7K HDMI_PCIE_MTX_C_GRX_N2
GMCH_TV_LUMA TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C401 0.1U_0402_16V7K HDMI_PCIE_MTX_C_GRX_N3
H25 TVB_DAC PEG_TX#_3 M40 1 2
GMCH_TV_CRMA K25 M42 C177 0.1U_0402_16V7K
TVC_DAC PEG_TX#_4
PEG_TX#_5 R48
2

TV
H24 TV_RTN PEG_TX#_6 N38
R74 R75 R76 T40
75_0402_1% 75_0402_1% 75_0402_1% PEG_TX#_7
PEG_TX#_8 U37
U40 HDMI_PCIE_MTX_C_GRX_N[0..3]
PEG_TX#_9 HDMI_PCIE_MTX_C_GRX_N[0..3] [24]
C31 Y40 CLOSE SPLIT POINT
1

TV_DCONSEL_0 PEG_TX#_10 HDMI_PCIE_MTX_C_GRX_P[0..3]

E32 TV_DCONSEL_1 PEG_TX#_11 AA46 HDMI_PCIE_MTX_C_GRX_P[0..3] [24]
PEG_TX#_12 AA37
PEG_TX#_13 AA40
PEG_TX#_14 AD43
PEG_TX#_15 AC46
Change to 0Ohm when use PM chip PCIE_MTX_GRX_P0 HDMI_PCIE_MTX_C_GRX_P0
[18] GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42 1 2
2 1 L46 PCIE_MTX_GRX_P1 C175 0.1U_0402_16V7K 1 2 HDMI_PCIE_MTX_C_GRX_P1
R80 150_0402_1% PEG_TX_1 PCIE_MTX_GRX_P2 C406 0.1U_0402_16V7K HDMI_PCIE_MTX_C_GRX_P2
[18] GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2
2 1 M39 PCIE_MTX_GRX_P3 C402 0.1U_0402_16V7K 1 2 HDMI_PCIE_MTX_C_GRX_P3
PEG_TX_3

VGA
R73 150_0402_1% J28 M43 C178 0.1U_0402_16V7K
[18] GMCH_CRT_R CRT_RED PEG_TX_4
2 1 PEG_TX_5 R47
R82 150_0402_1% G29 N37
B CRT_IRTN PEG_TX_6 B
PEG_TX_7 T39
GMCH_CRT_CLK H32 U36
[18] GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA J32 U39
[18] GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
[18] GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39
CRT_IREF E29 Y46
CRT_TVO_IREF PEG_TX_11
PEG_TX_12 AA36
PEG_TX_13 AA39
[18] GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42
PEG_TX_15 AD46
+3VS
2

R79 CANTIGA B3_FCBGA1329 GM45@

R83 1 2 2.2K_0402_5% GMCH_LCD_CLK 1K_0402_1%

R81 1 2 2.2K_0402_5% GMCH_LCD_DATA

1

R95 1 2 10K_0402_5% LCTLB_DATA

R85 1 2 10K_0402_5% LCTLA_CLK

R440 1 2 2.2K_0402_5% GMCH_CRT_CLK

R447 1 2 2.2K_0402_5% GMCH_CRT_DATA

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(4/7)-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

U21F
+1.05VS
R01 +1.8V

2600mA VCC_AXG_NTCF_1 W28

AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26 Place close to the GMCH
BH32 V26
VCC_SM_3 VCC_AXG_NCTF_4
D
BG32
VCC_SM_4 VCC_AXG_NCTF_5
W25
+1.05VS VCC: 1930.4mA (GMCH), 1210.34mA (MCH) D
BF32 V25
BD32
VCC_SM_5 VCC_AXG_NCTF_6
W24 (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM_6 VCC_AXG_NCTF_7
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 W23 +1.05VS
VCC_SM_8 VCC_AXG_NCTF_9 1

VCC

10U_0805_10V4Z

0.1U_0402_16V4Z
0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
220U_D2_4VY_R15M
BA32 V23 1 1 U21G
VCC_SM_9 VCC_AXG_NCTF_10 + C93 C162 C152 C163 C151
AY32 AM21
VCC_SM_10 VCC_AXG_NCTF_11 @
AW32 AL21 AG34
VCC_SM_11 VCC_AXG_NCTF_12 VC VCC_1
AV32 AK21 AC34
VCC_SM_12 VCC_AXG_NCTF_13 2 2 2 VCC_2
AU32 W21 AB34
VCC_SM_13 VCC_AXG_NCTF_14 VCC_3
AT32 V21 AA34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_4
AR32 U21 Y34
VCC_SM_15 VCC_AXG_NCTF_16 VCC_5
AP32 AM20 V34

VCC CORE
VCC_SM_16 VCC_AXG_NCTF_17 VCC_6
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 U34 VCC_7
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 AM33 VCC_8
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 Cavity Capacitors AK33 VCC_9
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AJ33 VCC_10
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AG33 VCC_11
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19 AF33 VCC_12
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
+1.05VS VCC_AXG: 6326.84mA
BD29 AG19
BC29
VCC_SM_25 VCC_AXG_NCTF_26
AF19 (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) AE33
VCC_SM_26 VCC_AXG_NCTF_27 VCC_13
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 AC33 VCC_14

10U_0805_10V4Z

10U_0805_10V4Z
1U_0402_6.3V6K
0.47U_0603_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
Reference PILLAR_ROCK CRB Rev1.0 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 AA33 VCC_15
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 1 1 1 1 1 Y33 VCC_16
GFX NCTF
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 W33 VCC_17
Pins BA36, BB24, BD16, AV29 W19 V33

POWER
VCC_SM_31 VCC_AXG_NCTF_32 C123 C133 C106 C132 C135 C134 VCC_18
BB21, AW16, AW13, AT13 AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 U33 VCC_19
AT29 U19 2 2 2 2 2 AH28
could be left NC for DDR2 AR29
VCC_SM_33 VCC_AXG_NCTF_34
AM17 AF28
VCC_20
board. VCC_SM_34 VCC_AXG_NCTF_35 VCC_21
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AC28 VCC_22
VCC_AXG_NCTF_37 AH17 Cavity Capacitors AA28 VCC_23
C C
VCC_AXG_NCTF_38 AG17 AJ26 VCC_24
VCC_AXG_NCTF_39 AF17 AG26 VCC_25
VCC_SM_BA36 BA36 AE17 AE26
VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_26
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AC26 VCC_27
VCC_SM_BD16 +1.05VS
VCC

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AH25 VCC_28
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AG25 VCC_29
VCC_SM_AW16 AW16 W17 1 1 @ AF25
VCC_SM_40/NC VCC_AXG_NCTF_44 VCC_30
AW13 V17 AG24 AM32
VCC_SM_41/NC VCC_AXG_NCTF_45 VCC_31 VCC_NCTF_1

C147

C521
VCC_SM_AT13 AT13 AM16 + + AJ23 AL32
VCC_SM_42/NC VCC_AXG_NCTF_46 VC VCC_32 VCC_NCTF_2
AL16 AH23 AK32
VCC_AXG_NCTF_47 VCC_33 VCC_NCTF_3
AK16 AF23 AJ32
VCC_AXG_NCTF_48 VCC_34 VCC_NCTF_4
POWER

2 2
AJ16 T32 AH32
+1.05VS VCC_AXG_NCTF_49 VCC_35 VCC_NCTF_5
AH16 AG32
VCC_AXG_NCTF_50 VCC_NCTF_6
AG16 AE32
VCC_AXG_NCTF_51 VCC_NCTF_7
VCC_AXG_NCTF_52
AF16 Place close to the GMCH VCC_NCTF_8
AC32
Y26 AE16 AA32
VCC_AXG_1 VCC_AXG_NCTF_53 VCC_NCTF_9
AE25 AC16 Y32
VCC_AXG_2 VCC_AXG_NCTF_54 VCC_NCTF_10
AB25 AB16 W32
VCC_AXG_3 VCC_AXG_NCTF_55 VCC_NCTF_11
AA25 AA16 U32
VCC_AXG_4 VCC_AXG_NCTF_56 VCC_NCTF_12
AE24 Y16 AM30
VCC_AXG_5 VCC_AXG_NCTF_57 VCC_NCTF_13
AC24
VCC_AXG_6 VCC_AXG_NCTF_58
W16 VCC_SM: 2600mA VCC_NCTF_14
AL30
AA24 V16 AK30
Y24
VCC_AXG_7 VCC_AXG_NCTF_59
U16 +1.8V (330UF*1, 22UF*2, 0.1UF*1) DDR2 VCC_NCTF_15
AH30

R01
VCC_AXG_8 VCC_AXG_NCTF_60 VCC_NCTF_16
AE23 AG30
VCC_AXG_9 VCC_NCTF_17

330U_D2_2.5VY_R9M
AC23 AF30
VCC_AXG_10 VCC_NCTF_18
AB23 1 AE30
VCC_AXG_11 VCC_NCTF_19

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
AA23 1 1 1 AC30

NCTF
VCC_AXG_12 VCC_NCTF_20

C168
AJ21 + AB30
VCC_AXG_13 VCC_NCTF_21
AG21 AA30
VCC_AXG_14 C157 C156 C155 VCC_NCTF_22
AE21 Y30
VCC_AXG_15 2 2 2 2 VCC_NCTF_23
AC21 W30
VCC_AXG_16 VCC_NCTF_24
AA21 V30
B VCC_AXG_17 VCC_NCTF_25 B
Y21 U30
VCC_AXG_18 VCC_NCTF_26
VCC

VCC
AH20 AL29
VCC_AXG_19 VCC_NCTF_27
AF20
VCC_AXG_20 Place on the edge VCC_NCTF_28
AK29
AE20 AJ29
VCC_AXG_21 VCC_NCTF_29
AC20
VCC_AXG_22 Reference PILLAR_ROCK CRB Rev1.0 VCC_NCTF_30
AH29
AB20 AG29
VCC_AXG_23 VCC_NCTF_31
AA20 AE29
GFX

VCC_AXG_24 VCC_SM_BA36 VCC_NCTF_32

T17 AC29
VCC_AXG_25 VCC_SM_BB24 VCC_NCTF_33
T16 AA29
VCC_AXG_26 VCC_SM_BD16 VCC_NCTF_34
AM15 Y29
VCC_AXG_27 VCC_SM_AW16 VCC_NCTF_35
AL15 W29
VCC_AXG_28 VCC_SM_AT13 VCC_NCTF_36
AE15 V29
VCC_AXG_29 VCC_NCTF_37
AJ15 AL28
VCC_AXG_30 VCC_NCTF_38
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
AH15 1 1 1 1 1 AK28
VCC_AXG_31 VCC_NCTF_39
0.1U_0402_16V7K

AG15 AL26
VCC_AXG_32 VCC_NCTF_40
AF15 AK26
VCC_AXG_33 C114 C104 C125 C137 C165 VCC_NCTF_41
AB15 AK25
VCC_AXG_34 @ 2 @ 2 @ 2 @ 2 @ 2 VCC_NCTF_42
AA15 AK24
VCC_AXG_35 VCC_NCTF_43
Y15 AK23
VCC_AXG_36 VCC_NCTF_44
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40 VCCSM_LF1
U14 AV44
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 BA37
VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
AM40
VCC_SM_LF3 VCCSM_LF4
AV21
VCC_SM_LF4 VCCSM_LF5
AY5
@ VCC_AXG_SENSE VCC_SM_LF5 VCCSM_LF6 CANTIGA B3_FCBGA1329 GM45@
T4 PAD AJ14 AM10
VSS_AXG_SENSE VCC_AXG_SENSE VCC_SM_LF6 VCCSM_LF7
0.22U_0402_6.3V6K

@ PAD AH14 BB13

T3 VSS_AXG_SENSE VCC_SM_LF7
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.47U_0603_16V4Z
0.22U_0402_6.3V6K

1 1 1 1 1 1 1
C115 C113 C105 C136 C166 C167 C170
A A

2 2 2 2 2 2 2

CANTIGA B3_FCBGA1329 GM45@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(5/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

+1.05VS_HPLL
+1.05VS_DPLLA
+1.05VS L29 1 2
MBK1608121YZF_0603 1 1 +1.05VS 1 2
VCCA_HPLL: 24mA C391 C393 L14 1 1 U21H
+1.05VS
VTT: 852mA
0_1210_5% VC 1
(4.7UF*1, 0.1UF*1) + + C183 (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
4.7U_0805_10V4Z
2 2
C174 852mA
C523 @ 0.1U_0402_16V4Z 73mA VTT_1 U13
0.1U_0402_16V4Z 150U_B2_6.3VM_R45M 220U_D2_4VY_R15M +3VS_CRTDAC B27 T13 1
2 2 2 VCCA_CRT_DAC_1 VTT_2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.47U_0603_16V4Z
2.2U_0603_6.3V6K
220U_D2_4VY_R15M
A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1 1
VCCA_DPLLA T12 C396 + C400 C397 C122 C101
+1.05VS_MPLL VTT_4
VCCA_DPLLB: 64.8mA U11
VTT_5
120Ohm@100MHz 2.69mA VTT_6
T11
(220UF*1, 0.1UF*1) +1.05VS_DPLLB 2 2 2 2 2

CRT
D L28 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 T10
VTT_8

1
VCCA_MPLL: 139.2mA C103 1 2 B25 VSSA_DAC_BG VTT_9 U9
R344 L31 1 1 T9
(22UF*1, 0.1UF*1) 0.5_0603_1% 0_1210_5% C405 VTT_10
U8
2 VTT_11
64.8mA VTT_12
T8

VTT
0.1U_0402_16V4Z C408 +1.05VS_DPLLA F47 U7

2
2
10U_0805_10V4Z 2 VCCA_DPLLA VTT_13
1 T7
0.1U_0402_16V4Z VTT_14
+1.05VS_DPLLB L48 U6
C389 VCCA_DPLLB VTT_15
T6
24mA VTT_16

PLL
22U_0805_6.3V6M +1.05VS_HPLL AD1 U5
2 VCCA_HPLL VTT_17
+1.8V_TX_LVDS VTT_18 T5
1 AE1 139.2mA V3
+1.05VS_MPLL VCCA_MPLL VTT_19
C410 U3
VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21 V2

A PEG A LVDS
R346 1000P_0402_50V7K J48 U2
0_0402_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23
+1.5VS 1 2 J47 V1
+3VS_CRTDAC VSSA_LVDS VTT_24
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) 1 VTT_25 U1
C395 VCCA_PEG_BG: 0.414mA 0.414mA
L32 1 2 AD48
+3VS (0.1UF*1) VCCA_PEG_BG
MBK1608301YZF_0603 0.1U_0402_16V4Z
2 +1.05VS_AXF
VCC_AXF: 321.35mA
1 1 (10UF*1, 1UF*1)
1 C418 C417 50mA
AA48 VCCA_PEG_PLL
1 2 +1.05VS
C424 + 0.1U_0402_16V4Z 0.01U_0402_16V7K L30 1 2 +1.05VS_PEGPLL R354
2 2 +1.05VS 1 1
MBK1608121YZF_0603 1 VCCA_PEG_PLL: 50mA C422 C414 0_0603_5%
220U_D2_4VY_R15M 2 1 1 2 C394 @
2 C399 R347 (0.1UF*1) 10U_0805_6.3V6M 1U_0402_6.3V6K
2 2
Close to Ball A26, B27 10U_0805_6.3V6M 1_0402_1%
2
0.1U_0402_16V4Z 480mA POWER
AR20 VCCA_SM_1
+1.05VS_A_SM VCCA_SM: AP20
C VCCA_SM_2 C
(22UF*2, 4.7UF*1, 1UF*1) AN20 VCCA_SM_3 VCC_SM_CK: 119.85mA
+1.05VS 1 2 AR17 (10UF*1, 0.1UF*1)
VCCA_SM_4 +1.8V_SM_CK +1.8V

A SM
1 R63 1 1 1 AP17
0_0805_5% C124 C116 VCCA_SM_5
AN17 VCCA_SM_6 VCC_AXF_1 B22 1uH 30%
+

AXF
C94 C138 AT16 B21 R01 1 2 R01
VC 4.7U_0805_10V4Z VCCA_SM_7 VCC_AXF_2 L12
AR16 VCCA_SM_8 VCC_AXF_3 A21
220U_D2_4VY_R15M 2 2 2 AP16 MBK1608121YZF_0603
2 VCCA_SM_9 1
22U_0805_6.3V6M 1U_0402_6.3V6K C139
1 R72 2 1 2
0.1U_0402_16V4Z 1_0402_1% C140 10U_0805_6.3V6M
BF21 2
VCC_SM_CK_1

SM CK
VCCA_DAC_BG: 2.6833333mA +1.05VS_A_SM_CK VCC_SM_CK_2
BH20
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3
BG20
(22UF*1, 2.2UF*1, 0.1UF*1) 24mA VCC_SM_CK_4
BF20
+1.8V_TX_LVDS
+1.05VS 1 2 AP28
VCCA_SM_CK_1 +1.8V_TX_LVDS: 118.8mA
1 2 R99 1 1 1 AN28 0.1uH 20%
+3VS
L10 0_0603_5% C148 C153 C154 AP25
VCCA_SM_CK_2 (22UF*1, 1000PF*1) 1 2
VCCA_SM_CK_3 +1.8V
MBK1608221YZF_0603 1 1 1 @ AN25
VCCA_SM_CK_4 118.8mA 1 1 R358
C415 C416 C423 2.2U_0603_6.3V6K 0.1U_0402_16V4Z AN24 K47 C407 C411 0_0603_5%
2 2 2 VCCA_SM_CK_5 VCC_TX_LVDS

A CK
AM28
0.1U_0402_16V4Z 10U_0805_6.3V6M 22U_0805_6.3V6M VCCA_SM_CK_NCTF_1 1000P_0402_50V7K
AM26
2 2 2 VCCA_SM_CK_NCTF_2 2 2 10U_0805_10V4Z
AM25
VCCA_SM_CK_NCTF_3 105.3mA VCC_HV: 105.3mA
0.01U_0402_16V7K NO_STUFF AL25 C35 +3VS
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 B35 1
VCCA_SM_CK_NCTF_5 VCC_HV_2

HV
Close to Ball A25 AL24 A35 C419
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23
VCCA_SM_CK_NCTF_7 0.1U_0402_16V4Z
AL23
VCCA_SM_CK_NCTF_8 2
1782mA +1.05VS_PEG
VCC_PEG_1
V48 +1.05VS_PEG: 1782mA
U48
VCC_PEG_2 (220UF*1, 22UF*1, 4.7UF*1)

PEG
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_3
V47 1 2 +1.05VS

220U_D2_4VY_R15M
B 0.01UF*1 for each DAC) 87.79mA VCC_PEG_4
U47 1 1 R112
B
+3VS_TVDAC B24 U46 C169 1 0_0805_5%
+3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5 10U_0805_10V4Z + C184 + C522
A24
VCCA_TV_DAC_2

TV
@ 150U_B2_6.3VM_R45M
+3VS L11 1 2 VCCD_HDA: 50mA 2 2 2
MBK1608221YZF_0603 50mA 456mA VC
(0.1UF*1) +1.5VS_HDA
180Ohm@100MHz 1 1 +1.5VS 1 2 A32
VCC_HDA VCC_DMI_1
AH48
+1.05VS

HDA
C130 C131 R359 1 AF48
VCC_DMI_2

DMI
0_0402_5% C420 Close to A32 AH47
0.1U_0402_16V4Z VCC_DMI_3 +1.05VS_DMI
AG47 1 2
2 2 VCC_DMI_4
0.1U_0402_16V4Z
2
58.696mA R345
0.01U_0402_16V7K +1.5VS_TVDAC M25
VCCD_TVDAC VCC_DMI: 456mA 1 0_0805_5%

D TV/CRT
C392
L28 48.363mA (0.1UF*1)
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
+1.05VS_HPLL AF1
VCCD_HPLL VTTLF_CAP1
A8
+1.05VS_PEGPLL 50mA VTTLF1 VTTLF_CAP2
AA47 L1
VCCD_PEG_PLL VTTLF2

VTTLF
VCCD_TVDAC: 58.696mA AB2 VTTLF_CAP3
+1.5VS_TVDAC VTTLF3
(0.1UF*1, 0.01UF*1) 60.31mA
M38 1 1 1
VCCD_LVDS_1
LVDS

+1.5VS 1 2 L37 C102 C404 C412

L13 VCCD_LVDS_2
1 1
MBK1608221YZF_0603 C146 C149 Also power for internal VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z
2 2
0.47U_0603_16V4Z
2
Thermal Sensor (0.1UF*1) CANTIGA B3_FCBGA1329
0.1U_0402_16V4Z GM45@ 0.47U_0603_16V4Z
2 2 +1.8V_LVDS
+1.8V 1 2
0.022U_0402_16V7K R348
0_0603_5% 1 1
C398 C161

10U_0805_6.3V6M 1U_0402_6.3V6K
A 2 2 A
VCCD_QDAC: 48.363mA +1.5VS_QDAC R65
D17
(0.1UF*1, 0.01UF*1) 2 1 1 2
+1.05VS +3VS
+1.5VS 1 2 VCCD_LVDS: 60.311111mA
R90 1 1 10_0603_5%
100_0603_1% C150 C160 (1UF*1) CH751H-40PT_SOD323-2
180Ohm@100MHz
0.1U_0402_16V4Z
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K Issued Date 2008/11/10 2008/11/24 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (6/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

U21I U21J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 L36 AU21 E8
VSS_4 VSS_103 VSS_202 VSS_300
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 U35 M21 AA7
VSS_11 VSS_110 VSS_209 VSS_307
T47 T35 J21 N7
D VSS_12 VSS_111 VSS_210 VSS_308 D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 AM34 BC20 BG6
VSS_14 VSS_113 VSS_212 VSS_310
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 AE34 AT20 AT6
VSS_17 VSS_116 VSS_215 VSS_313
AY46 W34 AJ20 AM6
VSS_18 VSS_117 VSS_216 VSS_314
AV46 B34 AG20 M6
VSS_19 VSS_118 VSS_217 VSS_315
AR46 A34 Y20 C6
VSS_20 VSS_119 VSS_218 VSS_316
AM46 BG33 N20 BA5
VSS_21 VSS_120 VSS_219 VSS_317
V46 BC33 K20 AH5
VSS_22 VSS_121 VSS_220 VSS_318
R46 BA33 F20 AD5
VSS_23 VSS_122 VSS_221 VSS_319
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
VSS_52 VSS_151 VSS_250 VSS_348
AH41 AB28 BC13 P1
VSS_53 VSS_152 VSS_251 VSS_349
AD41 Y28 BA13 H1
VSS_54 VSS_153 VSS_252 VSS_350
AA41 P28
VSS_55 VSS_154
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 H28 AN13 U28
VSS_57 VSS_156 VSS_255 VSS_352
T41 F28 AJ13 U25
VSS_58 VSS_157 VSS_256 VSS_353
M41 C28 AE13 U29
VSS_59 VSS_158 VSS_257 VSS_354
G41 BF26 N13
VSS_60 VSS_159 VSS_258
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
VSS_62 VSS_161 VSS_260 VSS_NCTF_2
BB40 AB26 E13 V32
VSS_63 VSS_162 VSS_261 VSS_NCTF_3
AV40 AA26 BF12 AJ30
VSS_64 VSS_163 VSS_262 VSS_NCTF_4
AN40 C26 AV12 AM29
VSS_65 VSS_164 VSS_263 VSS_NCTF_5
H40 B26 AT12 AF29
VSS_66 VSS_165 VSS_264 VSS_NCTF_6
E40 BH25 AM12 AB29
VSS_67 VSS_166 VSS_265 VSS_NCTF_7
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 BB25 J12 U23
VSS_69 VSS_168 VSS_267 VSS_NCTF_9
AJ39 AV25 A12 AL20
VSS_70 VSS_169 VSS_268 VSS_NCTF_10
AE39 AR25 BD11 V20
VSS_71 VSS_170 VSS_269 VSS_NCTF_11
N39 AJ25 BB11 AC19
VSS_72 VSS_171 VSS_270 VSS_NCTF_12
L39 AC25 AY11 AL17
VSS_73 VSS_172 VSS_271 VSS_NCTF_13
B39 Y25 AN11 AJ17
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 N25 AH11 AA17
VSS_75 VSS_174 VSS_273 VSS_NCTF_15
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 J25 Y11
VSS_77 VSS_176 VSS_275
AU38 G25 N11
VSS_78 VSS_177 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 BF24 C11 BH1
VSS_80 VSS_179 VSS_278 VSS_SCB_2
AA38 AD12 BG10 A48
VSS_81 VSS_180 VSS_279 VSS_SCB_3
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 AT24 AT10 A3
VSS_83 VSS_182 VSS_281 VSS_SCB_5
T38 AJ24 AJ10
VSS_84 VSS_183 VSS_282
J38 AH24 AE10
VSS_85 VSS_184 VSS_283
F38 AF24 AA10
VSS_86 VSS_185 VSS_284
C38 AB24 M10
VSS_87 VSS_186 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 L24 BC9 D2
VSS_89 VSS_188 VSS_287 NC_27
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 J24 AM9 B4
VSS_91 VSS_190 VSS_289 NC_29
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 B23 AT8 D47
VSS_98 VSS_197 VSS_296 NC_36
AU36 A23 B47
VSS_99 VSS_198 NC_37
AJ6 A46
VSS_199 NC_38
F48
CANTIGA B3_FCBGA1329 GM45@ NC_39
E48
NC_40
C48
NC_41
B48
NC_42

CANTIGA B3_FCBGA1329 GM45@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JDIMM1 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4 +DIMM_VREF
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5 20mils
DDRA_SDQ1 DQ0 DQ5 R1196
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
[9] DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS
12
DDRA_SDQ6
1 20mils
13 14 C534 To SODIMM and GMCH

2
[9] DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 16 +DIMM_VREF
D DDRA_SDQ2 VSS DQ7 0.1U_0402_16V4Z D
17 18
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ12 2
DQ3 DQ12 DDRA_SDQ13 R1197
21 22
DDRA_SDQ8 VSS DQ13
23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 1K_0402_1%
25 26
DQ9 DM1
27 28

2
DDRA_SDQS1# VSS VSS
29 30 DDRA_CLK0 [8]
[9] DDRA_SDQS1# DDRA_SDQS1 DQS1# CK0
31 32 DDRA_CLK0# [8]
[9] DDRA_SDQS1 DQS1 CK0#
33 34
DDRA_SDQ10 VSS VSS DDRA_SDQ14
35 36
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 38
DQ11 DQ15 DDRA_SMA[0..14]
39 VSS VSS 40 [9] DDRA_SMA[0..14]
DDRA_SDQ[0..63]
[9] DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 [9] DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 VSS VSS 48
DDRA_SDQS2# 49 50
[9] DDRA_SDQS2# DDRA_SDQS2 DQS2# NC DDRA_SDM2 PM_EXTTS#0 [8]
51 DQS2 DM2 52
[9] DDRA_SDQS2
53 VSS VSS 54 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ22 C539 C540 C536 C533 C541
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ24 VSS VSS DDRA_SDQ28 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# [9]
69 NC DQS3 70
DDRA_SDQS3 [9]
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 +1.8V
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 +0.9VS
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 DDRA_SBS2# 1 4
[8] DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 [8] DDRA_CKE0
81 VDD VDD 82 2 3 1 1 1 1
83 84 RP18 56_0404_4P2R_5% C537 C181 C528 C531
DDRA_SBS2# NC NC/A15 DDRA_SMA14
[9] DDRA_SBS2# 85 BA2 NC/A14 86
87 88 DDRA_SMA9 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA12 2 2 2 2
89 A12 A11 90 2 3
DDRA_SMA9 91 92 DDRA_SMA7 RP8 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6
93 94
A8 A6 DDRA_SMA5
95 96 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA8
97 98 2 3
DDRA_SMA3 A5 A4 DDRA_SMA2 RP10 56_0404_4P2R_5%
99 100
DDRA_SMA1 A3 A2 DDRA_SMA0
101 102
A1 A0 DDRA_SMA1
103 104 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA3 +0.9VS
105 106 DDRA_SBS1# [9] 2 3
DDRA_SBS0# A10/AP BA1 DDRA_SRAS# RP9 56_0404_4P2R_5%
[9] DDRA_SBS0# 107 108 DDRA_SRAS# [9]
DDRA_SWE# BA0 RAS# DDRA_SCS0#
[9] DDRA_SWE# 109 110 DDRA_SCS0# [8]
WE# S0# DDRA_SBS0#
111 112 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SMA10
[9] DDRA_SCAS# 113 114 DDRA_ODT0 [8] 2 3 1 1 1 1 1
DDRA_SCS1# CAS# ODT0 DDRA_SMA13 RP19 56_0404_4P2R_5% C538 C542 C529 C527 C543
[8] DDRA_SCS1# 115 116
NC/S1# NC/A13
117 118
DDRA_ODT1 VDD VDD DDRA_SCAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
[8] DDRA_ODT1 119 120 1 4
NC/ODT1 NC DDRA_SWE# 2 2 2 2 2
121 122 2 3
DDRA_SDQ32 VSS VSS DDRA_SDQ36 RP20 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 124
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 126
DQ33 DQ37 DDRA_SCS1#
127 128 1 4
DDRA_SDQS4# VSS VSS DDRA_SDM4 DDRA_ODT1
129 130 2 3
[9] DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP15 56_0404_4P2R_5% +0.9VS
131 132
[9] DDRA_SDQS4 DQS4 VSS DDRA_SDQ38
133 134
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 136
DDRA_SDQ35 DQ34 DQ39
137 138
DQ35 VSS DDRA_SDQ44 DDRA_SMA14
139 140 1 4 1 1 1 1 1
B DDRA_SDQ40 VSS DQ44 DDRA_SDQ45 DDRA_SMA11 C526 C530 C525 C546 C545 B
141 142 2 3
DDRA_SDQ41 DQ40 DQ45 RP11 56_0404_4P2R_5%
143 144
DQ41 VSS DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
145 146
DDRA_SDM5 VSS DQS5# DDRA_SDQS5 DDRA_SDQS5# [9] DDRA_SMA7 2 2 2 2 2
147 148 1 4
DM5 DQS5 DDRA_SDQS5 [9] DDRA_SMA6 0.1U_0402_16V4Z 0.1U_0402_16V4Z
149 150 2 3
DDRA_SDQ42 VSS VSS DDRA_SDQ46 RP13 56_0404_4P2R_5%
151 152
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 154
DQ43 DQ47 DDRA_SMA4
155 156 1 4
DDRA_SDQ48 VSS VSS DDRA_SDQ52 DDRA_SMA2 +0.9VS
157 158 2 3
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 RP17 56_0404_4P2R_5%
159 160
DQ49 DQ53
161 162
VSS VSS DDRA_SBS1#
163 164 DDRA_CLK1 [8] 1 4
NC,TEST CK1 DDRA_SMA0
165 166 DDRA_CLK1# [8] 2 3 1 1 1
DDRA_SDQS6# VSS CK1# RP14 56_0404_4P2R_5% C188 C544 C535
167 168
[9] DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
169 170
[9] DDRA_SDQS6 DQS6 DM6 DDRA_SCS0# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
171 172 1 4
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SRAS# 2 2 2
173 174 2 3
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55 RP12 56_0404_4P2R_5% 0.1U_0402_16V4Z
175 176
DQ51 DQ55
177 178
DDRA_SDQ56 VSS VSS DDRA_SDQ60 DDRA_SMA13
179 180 1 4
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_ODT0
181 182 2 3
DQ57 DQ61 RP16 56_0404_4P2R_5%
183 184
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 186
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# [9] DDRA_CKE1
187 188 1 2
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 [9] R1198 56_0402_5%
189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 192
DQ59 DQ62 DDRA_SDQ63
193 194
D_CK_SDATA VSS DQ63
[15,16] D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R123 1
[15,16] D_CK_SCLK 197
SCL SAO
198 2 10K_0402_5%
+3VS 199 200 R122 1 2 10K_0402_5%
VDDSPD SA1

A FOX_ASOA426-M4R-TR A

+3VS
CONN@

1 1
C532 C547

0.1U_0402_16V4Z
DIMM1 REV H:5.6mm (BOT) Security Classification
2007/09/29
Compal Secret Data
2008/11/24 Title
Compal Electronics, Inc.
2 2 Issued Date Deciphered Date
2.2U_0603_6.3V6K JDIMM1 --- Change to low size
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KALG1- 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 24, 2009 Sheet 14 of 45
5 4 3 2 1
 5 4 3 2 1

+DIMM_VREF +1.8V
R01

+1.8V +1.8V

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
1 1
1 1

C91

C95
JDIMM2 C566 C558 + +
+DIMM_VREF 1 2 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
VREF VSS DDRB_SDQ4
3 VSS DQ4 4
DDRB_SDQ0 5 6 DDRB_SDQ1 2 2 2 2
DDRB_SDQ5 DQ0 DQ5
7 8
DQ1 VSS DDRB_SDM0
9 10
D DDRB_SDQS0# VSS DM0 D
11 12
[9] DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
13 14
[9] DDRB_SDQS0 DQS0 DQ6 DDRB_SDQ7
15 VSS DQ7 16
DDRB_SDQ2 17 18
DDRB_SDQ3 DQ2 VSS DDRB_SDQ12
19 20
DQ3 DQ12 DDRB_SDQ13
21 22
DDRB_SDQ8 VSS DQ13
23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 26
DQ9 DM1
27 28
DDRB_SDQS1# VSS VSS
29 30 DDRB_CLK0 [8]
[9] DDRB_SDQS1# DDRB_SDQS1 DQS1# CK0
31 32 DDRB_CLK0# [8]
[9] DDRB_SDQS1 DQS1 CK0#
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..14]
DQ10 DQ14 [9] DDRB_SMA[0..14]
DDRB_SDQ11 37 38 DDRB_SDQ15
DQ11 DQ15 DDRB_SDQ[0..63]
39 VSS VSS 40
[9] DDRB_SDQ[0..63]
DDRB_SDM[0..7]
[9] DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
DDRB_SDQS2# 49 50
[9] DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2 PM_EXTTS#1 [8]
51 DQS2 DM2 52
[9] DDRB_SDQS2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# +1.8V
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# [9] +0.9VS
69 NC DQS3 70
C DDRB_SDQS3 [9] C
71 VSS VSS 72
DDRB_SDQ26 73 74 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31 DDRB_SBS2#
75 DQ27 DQ31 76 1 4 1 1 1 1 1
77 78 DDRB_CKE0 2 3 C550 C548 C554 C559 C564
DDRB_CKE0 VSS VSS DDRB_CKE1 RP21 56_0404_4P2R_5%
[8] DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 [8]
81 82 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
VDD VDD DDRB_SMA12 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
83 NC NC/A15 84 1 4
DDRB_SBS2# 85 86 DDRB_SMA14 DDRB_SMA9 2 3
[9] DDRB_SBS2# BA2 NC/A14
87 88 RP24 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 90
DDRB_SMA9 A12 A11 DDRB_SMA7 DDRB_SMA8
91 92 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 94 2 3
A8 A6 RP30 56_0404_4P2R_5%
95 96
DDRB_SMA5 VDD VDD DDRB_SMA4
97 98
DDRB_SMA3 A5 A4 DDRB_SMA2 DDRB_SMA3
99 100 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 102 2 3 1 1 1 1
A1 A0 RP26 56_0404_4P2R_5% C549 C565 C191 C555
103 104
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# [9]
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# DDRB_SMA10 0.1U_0402_16V4Z 0.1U_0402_16V4Z
[9] DDRB_SBS0# 107 108 DDRB_SRAS# [9] 1 4
DDRB_SWE# BA0 RAS# DDRB_SCS0# DDRB_SBS0# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
[9] DDRB_SWE# 109 110 DDRB_SCS0# [8] 2 3
WE# S0# RP27 56_0404_4P2R_5%
111 112
DDRB_SCAS# VDD VDD DDRB_ODT0
[9] DDRB_SCAS# 113 114 DDRB_ODT0 [8]
DDRB_SCS1# CAS# ODT0 DDRB_SMA13 DDRB_SWE#
[8] DDRB_SCS1# 115 116 1 4
NC/S1# NC/A13 DDRB_SCAS#
117 118 2 3
DDRB_ODT1 VDD VDD RP31 56_0404_4P2R_5%
[8] DDRB_ODT1 119 120
NC/ODT1 NC
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 DDRB_SCS1#
123 124 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 126 2 3
DQ33 DQ37 RP25 56_0404_4P2R_5%
127 128
DDRB_SDQS4# VSS VSS DDRB_SDM4
129 130
[9] DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4
131 132
[9] DDRB_SDQS4 DQS4 VSS DDRB_SDQ38
133 134 1 1 1 1 1
B DDRB_SDQ34 VSS DQ38 DDRB_SDQ39 DDRB_SMA14 C568 C556 C190 C524 C567 B
135 136 1 4
DDRB_SDQ35 DQ34 DQ39 DDRB_SMA11
137 138 2 3
DQ35 VSS DDRB_SDQ44 RP33 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
139 140
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 142
DDRB_SDQ41 DQ40 DQ45 DDRB_SMA6
143 144 1 4
DQ41 VSS DDRB_SDQS5# DDRB_SMA7
145 146 2 3
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# [9] RP22 56_0404_4P2R_5%
147 148
DM5 DQS5 DDRB_SDQS5 [9]
149 150
DDRB_SDQ42 VSS VSS DDRB_SDQ46 DDRB_SMA4 +0.9VS
151 152 1 4
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA2
153 154 2 3
DQ43 DQ47 RP23 56_0404_4P2R_5%
155 156
DDRB_SDQ48 VSS VSS DDRB_SDQ52
157 158
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53 DDRB_SMA0
159 160 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SBS1# C551 C562 C560 C553 C557
161 162 2 3
VSS VSS RP28 56_0404_4P2R_5%
163 164 DDRB_CLK1 [8]
NC,TEST CK1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
165 166 DDRB_CLK1# [8]
DDRB_SDQS6# VSS CK1# DDRB_SRAS# 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
167 168 1 4
[9] DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SCS0#
169 170 2 3
[9] DDRB_SDQS6 DQS6 DM6 RP29 56_0404_4P2R_5%
171 172
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55 DDRB_ODT0 +0.9VS
175 176 1 4
DQ51 DQ55 DDRB_SMA13
177 178 2 3
DDRB_SDQ56 VSS VSS DDRB_SDQ60 RP32 56_0404_4P2R_5%
179 180
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 182
DQ57 DQ61 DDRB_CKE1
183 184 1 2 1 1 1
DDRB_SDM7 VSS VSS DDRB_SDQS7# R1199 56_0402_5% C561 C563 C552
185 186
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# [9]
187 188
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 [9] 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 190
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
191 192
DQ59 DQ62 DDRB_SDQ63
193 194
D_CK_SDATA VSS DQ63
[14,16] D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R216 1
[14,16] D_CK_SCLK 197 SCL SA0 198 2 10K_0402_5%
A R217 1 A
+3VS 199 200 2 10K_0402_5% +3VS
VDDSPD SA1

FOX_AS0A426-N8RN-7F

CONN@

DIMM2 REV H:9.2mm (BOT) Security Classification

2007/09/29
Compal Secret Data
2008/11/24 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
JDIMM2 --- Change to high size
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KALG1- 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 24, 2009 Sheet 15 of 45
5 4 3 2 1
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI

+CLK_VDDSRC +CLK_VDD
Clock Generator
L22 L21
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +1.05VS 2 1
KC FBM-L11-201209-221LMAT_0805
+3VS 2 1
KC FBM-L11-201209-221LMAT_0805

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0805_10V4Z

0.1U_0402_16V4Z
0 0 0 266 100 33.3 C274 C285 C272 C273 C288 C282 C286 C271 C300 C281 C312 C313 C301 C287
C267 C266
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 1 0 200 100 33.3 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

0 1 1 166 100 33.3 U12

1 1
+CLK_VDD ICS9LPRS387, PN:SA000020H10
Table : ICS9LPRS387 D_CK_SDATA
9
SLG8SP556V, PN:SA000020K00 SDATA D_CK_SDATA [14,15]
CLK_REQ# Control Free-Run 6 VDDREF D_CK_SCLK
SCLK 10 D_CK_SCLK [14,15]
CR#_10(WLAN) PCIEX10 PCIEX0 19 VDD48
CR#_6(MCH) PCIEX6 PCIEX1 72 71 CLK_CPU_BCLK
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK [4]

CR#_4(NEW CARD) PCIEX4 12 70 CLK_CPU_BCLK#

VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# [4]

CR#_9(MINI CARDII) PCIEX9 27 VDDPLL3

68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK [7]
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] 55 VDDSRC CLK_MCH_BCLK#
CPUC1_LPR_F 67 CLK_MCH_BCLK# [7]
+3VS
+CLK_VDDSRC 52 VDDSRC_IO
24 CLK_DREF_96M
SRCT0_LPR/DOTT_96_LPR CLK_DREF_96M [8]
38 VDDSRC_IO
1 2 CLK_PCI2 25 CLK_DREF_96M#
SRCC0_LPR/DOTC_96_LPR CLK_DREF_96M# [8]
R275 10K_0402_5% 62 VDDSRC_IO
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)
31 28 CLK_DREF_SSC
VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 CLK_DREF_SSC [8]
@
mount to Enable ITP_CLK CLK_DREF_SSC#
1 2 66 VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 29 CLK_DREF_SSC# [8]
R281 10K_0402_5% +3VS
23 VDD96_IO
1 2 CLK_PCI5 32 CLK_PCIE_SATA
SRCT2_LPR/SATAT_LPR CLK_PCIE_SATA [20]
2

R280 10K_0402_5%
2 R268 @ 33 CLK_PCIE_SATA# 2
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# [20]
CLK_PCI5=0, Pin63,64 is SRC_CLK 10K_0402_5% H_STP_CPU# 53
[21] H_STP_CPU# CPU_STOP#
CLK_PCI5=1, Pin63,64 is ITP_CLK H_STP_PCI# CLK_PCIE_ICH
[21] H_STP_PCI# 54 35 CLK_PCIE_ICH [21]
1

CK505_PW RGD PCI_STOP# SRCT3_LPR

1 2 CLK_PCI4 36 CLK_PCIE_ICH#
D SRCC3_LPR CLK_PCIE_ICH# [21]
1

R277 10K_0402_5%
CLK_PCI4=0, Pin28, 29 is SRC_CLK 2 @ T26
CLK_ENABLE# [43]
G PAD 13 39 CLK_PCIE_CARD
Pin24, 25 is DOT96_CLK Q28 @ PCI1 SRCT4_LPR CLK_PCIE_CARD [28]
S
3

1 @ 2 CK_PW RGD 2N7002_SOT23 CLK_PCI2 14 40 CLK_PCIE_CARD#

PCI2/TME SRCC4_LPR CLK_PCIE_CARD# [28]
R238 10K_0402_5%
CLK_PCI_LPC R276 2 1 33_0402_5% CLK_PCI3 15
[30] CLK_PCI_LPC PCI3
57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL [8]
@ CLK_PCI4 16
C314 1 10P_0402_50V8J CLK_PCI_LPC PCI4/27_SELECT CLK_MCH_3GPLL#
2 SRCC6_LPR 56 CLK_MCH_3GPLL# [8]
@ CLK_PCI_ICH R279 2 1 33_0402_5% CLK_PCI5 17
[19] CLK_PCI_ICH PCI_F5/ITP_EN
C315 1 2 10P_0402_50V8J CLK_PCI_ICH
SRCT7_LPR 61
For EMI 0_0402_5% 2 1 R239 CK505_PW RGD1
[21] CK_PW RGD CK_PWRGD/PD#
0_0402_5% 2 @ 1 R240 60
[8,21,43] VGATE SRCC7_LPR
+1.05VS C311 27P_0402_50V8J
1 2 CLK_XTALIN 5 64
X1 CPUT2_ITP_LPR/SRCT8_LPR
2

R245 @ CLK_XTALOUT 4 63
56_0402_5% Y2 X2 CPUC2_ITP_LPR/SRCC8_LPR
C310 14.31818MHz_20P_FSX8L14.318181M20FDB
R243 R246 27P_0402_50V8J 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2 [28]
2

3 2.2K_0402_5% 1K_0402_5% NC SRCT9_LPR 3

1 2
1

CLKSEL0 1 2 1 2 45 CLK_PCIE_MINI2#
MCH_CLKSEL0 [8] SRCC9_LPR CLK_PCIE_MINI2# [28]
CLK_ICH_48M 1 2 CLKSEL0 20
[21] CLK_ICH_48M USB_48MHz/FSLA
1 2 1 2 CPU_BSEL0 [5] R241 22_0402_5% 50
R244 @ R247 CLK_SD_48M CLKSEL1 SRCT10_LPR
[25] CLK_SD_48M 1 2 2 FSLB/TEST_MODE
1K_0402_5% 0_0402_5% R242 22_0402_5% 51
CLK_ICH_14M R273 2 SRCC10_LPR
[21] CLK_ICH_14M 1 33_0402_5% CLKSEL2 7 FSLC/TEST_SEL/REF0
+1.05VS PAD 8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN [26]
T27 @
47 CLK_PCIE_LAN#
SRCC11_LPR CLK_PCIE_LAN# [26]
2

R271 @
1K_0402_5% +3VS 69
R294 GNDCPU PRE-MP
R269 4.7K_0402_5% 3 37 KAL90_H0_90+@
GNDREF CR#3
2

1K_0402_5%
G

1 2 +3VS 1 2 +3VS
1

CLKSEL1 1 2 18 41 R482 10K_0402_5%

MCH_CLKSEL1 [8] GNDPCI CR#4 EXP_CLKREQ# [28]
[21,28] ICH_SMBDATA 1 3 D_CK_SDATA
22 58
D

GND48 CR#6 MCH_CLKREQ# [8]

1 2 1 2 CPU_BSEL1 [5] Q29 (Pull High to +3VS at GMCH side)
R272 @ R270 2N7002_SOT23 30 65
0_0402_5% 0_0402_5% GND CR7#
1 2 +3VS
+3VS 26 43 R195 10K_0402_5%
GND CR#9 MINI2_CLKREQ# [28]
R282
4.7K_0402_5% 34 49
GNDSRC CR10#
2

+1.05VS
G

1 2 +3VS 1 2 +3VS
59 46 R32 10K_0402_5%
GNDSRC CR#11 LAN_CLKREQ# [26]
4 [21,28] ICH_SMBCLK 1 3 D_CK_SCLK 4
2

R293 @ 42 21
D

GNDSRC CR#A SATA_CLKREQ# [21]

1K_0402_5% Q23 73 (Pull High to +3VS at ICH side)
2N7002_SOT23 GND_THERMAL_PAD
R274 R278 ICS9LPRS387BKLFT_MLF72_10x10
10K_0402_5% 1K_0402_5%
1

CLKSEL2 1 2 1 2 MCH_CLKSEL2 [8] Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title
1
R291 @
2 1
R292
2 CPU_BSEL2 [5]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
0_0402_5% 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 16 of 45
A B C D E F G H
 5 4 3 2 1

+LCDVDD
LCD POWER CIRCUIT
+3V +3VS
W=60mils

1
D D
R11

1
300_0603_5% 1
R22 C18
100K_0402_5%

3 2
4.7U_0805_10V4Z
2

2
Q1B

3
S
G
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q2
R21 1K_0402_5% AO3413_SOT23-3
D
1

1
6

C12

0.047U_0402_16V7K
+LCDVDD
W=60mils
Q1A
2 2
[10] GMCH_ENVDD
2N7002DW-T/R7_SOT363-6 1 1
C14 C13

1
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
R12 2 2
100K_0402_5%

2
C C
+3VS

1
DAC_BRIG 1 2
+INVPWR_B+ B+ R10 C7 220P_0402_50V7K
INVTPWM 1 2
4.7K_0402_5% C8 220P_0402_50V7K
D6 DISPOFF#
L2 2 1 1 2

2
W=40mils KC FBM-L11-201209-221LMAT_0805 BKOFF# 1 2 DISPOFF# C9 220P_0402_50V7K
[30] BKOFF#
L1 2 1
KC FBM-L11-201209-221LMAT_0805 CH751H-40PT_SOD323-2
1 1
C5 C6

680P_0402_50V7K 68P_0402_50V8J
2 2

+3VS

5
U1

P
NC
INVTPWM DPST_PWM [10]
4 2
Y A

G
B NC7SZ14P5X_NL_SC70-5 B

LCD/PANEL BD. Conn.

2
+INVPWR_B+

G
JLVDS1 @
+3VS 42 GND GND 41 1 @ 2 INVTPWM 1 3
+3VS
40 40 DAC_BRIG
39 39

S
DAC_BRIG [30]
38 38 INVTPWM R20 10K_0402_5%
37 37 DISPOFF#
36 36
GMCH_LCD_CLK 35 35 Q3
[10] GMCH_LCD_CLK
[10] GMCH_LCD_DATA
34 34
GMCH_LCD_DATA
32 32
33 33
31 31
+LCDVDD 2N7002_SOT23 For GMCH DPST
30 30
29 29 W=60mils
28 28
27 27 GMCH_TXOUT0-
26 26
25 25 GMCH_TXOUT0+
GMCH_TXOUT0- [10] +3VS +LCDVDD
24 24
23 23 GMCH_TXOUT0+ [10]
22 22
21 21 GMCH_TXOUT1-
20 20
19 19 GMCH_TXOUT1+ GMCH_TXOUT1- [10]
18 18
17 17 GMCH_TXOUT1+ [10]
16 16
15 15 GMCH_TXOUT2+
1
C15
1
C11
1
C10
14 14
13 13 GMCH_TXOUT2- GMCH_TXOUT2+ [10]
12 12
11 11 GMCH_TXOUT2- [10]
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
10 10
9 9 GMCH_TXCLK- 2 2 2
8 8
R13 0_0402_5% 7 7 GMCH_TXCLK+
GMCH_TXCLK- [10]
6 6
5 5 GMCH_TXCLK+ [10]
[21] USB20_N3 1 2 USB20_CMOS_N3 4 4
3 3
1 2 USB20_CMOS_P3 2 2
[21] USB20_P3
R14 0_0402_5% 1 1 +3VS
ACES_88242-4001

A CONN@ A
CMOS Camera

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/24 Deciphered Date 2008/11/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & Camera Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 17 of 45
5 4 3 2 1
 A B C D E

CRT Connector

1 1

D14 D13 D11

W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D10 F1 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
C56

3
0.1U_0402_16V4Z
2
+3VS

JCRT1
6 RGND
R472 0_0805_5% L8 FCM2012C-800_0805 11
GMCH_CRT_R CRT_R_1 CRT_R_2 ID0
[10] GMCH_CRT_R 1 2 1 2 1 Red
7 GGND
R473 0_0805_5% L6 FCM2012C-800_0805 12
GMCH_CRT_G CRT_G_1 CRT_G_2 SDA
[10] GMCH_CRT_G 1 2 1 2 2 Green
8 BGND
R474 0_0805_5% L3 FCM2012C-800_0805 13
GMCH_CRT_B CRT_B_1 CRT_B_2 Hsync
[10] GMCH_CRT_B 1 2 1 2 3 Blue
9 +5V
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
2

C85

C78
2
1 1 1 1 1 1 1 1 1 14 Vsync
1

1
150_0402_1%

150_0402_1%

150_0402_1%

C87

C80

C72

C86

C79

C71
4 res
R47

R45

R42

C77 10
10P_0402_50V8J SGND
15 SCL
2 2 2 2 2 2 2 2 2 5 GND
2

+CRT_VCC 16 GND
17
GND
2 1
L42 1 2 CRT_HSYNC_2 R41 100K_0402_5%
MBK1608301YZF_0603 SUYIN_070546FR015S263ZR
CRT_DET# [21]
CONN@
L41 1 2 CRT_VSYNC_2
MBK1608301YZF_0603 1 1 DSUB_12
+CRT_VCC C518
C519

100P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J
1 2 2 1 10P_0402_50V8J 10P_0402_50V8J
C493 0.1U_0402_16V4Z R446 10K_0402_5% 2 2
DSUB_15
5

U26
OE#
P

GMCH_CRT_HSYNC 2 4 CRT_HSYNC_1
[10] GMCH_CRT_HSYNC A Y
1 1 1
G

74AHCT1G125GW_SOT353-5
3

+CRT_VCC 2 2 2

C517

C520

C516
+CRT_VCC
1 2 Place closed to chipset
C494 0.1U_0402_16V4Z
5

U25
OE#
P

3 GMCH_CRT_VSYNC 2 4 CRT_VSYNC_1 +3VS 3

[10] GMCH_CRT_VSYNC A Y

1
G

74AHCT1G125GW_SOT353-5 R465 R464

3

4.7K_0402_5% 4.7K_0402_5%

2
G
DSUB_12 1 3
GMCH_CRT_DATA [10]

S
Q39

2
2N7002_SOT23

G
DSUB_15 1 3
GMCH_CRT_CLK [10]

S
Q38
2N7002_SOT23

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 18 of 45
A B C D E
 5 4 3 2 1

DMI for ESI-compatible operation

+3VS
Low= DMI for ESI-compatible operation
PCI_GNT#1 High= Default* (Internal pull-up)
RP3
1 8 PCI_TRDY#
2 7 PCI_FRAME#
D 3 6 PCI_REQ#1 D
4 5 PCI_REQ#2
U22B
8.2K_1206_8P4R_5% D11 F1 PCI_REQ#0
AD0 REQ0# PCI_GNT#0
C8 AD1 GNT0# G4
RP7 PCI_REQ#1
1 8 PCI_PLOCK#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1
AD3 GNT1#/GPIO51 PAD T32
2 7 PCI_IRDY# E9 F13 PCI_REQ#2 @
PCI_PERR# AD4 REQ2#/GPIO52 PCI_GNT#2
3 6 C9 AD5 GNT2#/GPIO53 F12 PAD T13
4 5 PCI_PIRQB# E10 E6 PCI_REQ#3 @
AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6
8.2K_1206_8P4R_5% C7 AD8 PCI_CBE#0
C5 AD9 C/BE0# D8 PAD T12
G11 B4 PCI_CBE#1 PAD @
AD10 C/BE1# T35
F8 D6 PCI_CBE#2 PAD @
AD11 C/BE2# T19
F11 A5 PCI_CBE#3 PAD @
+3VS AD12 C/BE3# T18
E7 @
AD13 PCI_IRDY#
A3 AD14 IRDY# D3
RP6 D2 E3 PCI_PAR PAD @
AD15 PAR T17
1 8 PCI_PIRQG# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# [28]
2 7 PCI_REQ#0 D5 C6 PCI_DEVSEL#
PCI_PIRQH# AD17 DEVSEL# PCI_PERR#
3 6 D10 AD18 PERR# E4
4 5 PCI_PIRQE# B3 C2 PCI_PLOCK#
AD19 PLOCK# PCI_SERR#
F7 AD20 SERR# J4
8.2K_1206_8P4R_5% C3 A4 PCI_STOP#
AD21 STOP# PCI_TRDY#
F3 AD22 TRDY# F5
RP2 F4 D7 PCI_FRAME#
PCI_PIRQF# AD23 FRAME#
1 8 C1 AD24
2 7 PCI_SERR# G7 C14 PLT_RST#
AD25 PLTRST# PLT_RST# [8,26,30]
C 3 6 PCI_PIRQA# H7 D4 CLK_PCI_ICH C
AD26 PCICLK CLK_PCI_ICH [16]
4 5 PCI_PIRQC# D1 R2
AD27 PME#
8.2K_1206_8P4R_5%
G5 AD28 Place closely pin B10
H6 AD29
G1 AD30
RP4 H3 CLK_PCI_ICH
PCI_DEVSEL# AD31
1 8

2
2 7 PCI_REQ#3
PCI_STOP#
3
4
6
5 PCI_PIRQD# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# R421
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# 10_0402_5%
E1 PIRQB# PIRQF#/GPIO3 K6
8.2K_1206_8P4R_5% PCI_PIRQC# J6 F2 PCI_PIRQG# @

1
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
1
ICH9-M ES_FCBGA676 C476
10P_0402_50V8J
@
2

A16 Swap Override Strap

Low= A16 swap override Enable
PCI_GNT#3 High= Default*

R422 1 2 1K_0402_5% PCI_GNT#3

@
B B

+3VS

5
U23
Boot BIOS Strap PLT_RST# 2 B

P
Y 4 PLT_RST_BUF# [28]
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 1 A

G
1

1
NC7SZ08P5X_NL_SC70-5

3
R228 R394
0 1 SPI 100K_0402_5% 100K_0402_5%
@
1 0 PCI
2

2
1 1 LPC*

R175 1 @ 2 1K_0402_5% PCI_GNT#0

R382 1 @ 2 1K_0402_5% SPI_CS#1 [21]

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 19 of 45
5 4 3 2 1
 5 4 3 2 1

+RTCVCC CMOS Settings R337 TPM Settings R336

C438
12P_0402_50V8J Clear CMOS SHORT Clear ME RTC Registers SHORT
2 1 ICH_RTCX1 +1.05VS

1
Keep CMOS OPEN Keep ME RTC Registers OPEN
R391 X2 H_DPRSTP#

10M_0402_5%
2 1

1
3 4 R371 @ 56_0402_5%
NC OUT

R363
1M_0402_5% Reset r1290 for power on then shut down issue H_DPSLP# 2 1
32.768KHZ_12.5P_MC-306 2 1 R160 @ 56_0402_5%
2

SM_INTRUDER# NC IN
C437 U22A

2
D 12P_0402_50V8J C23 K5 LPC_AD0 D
RTCX1 FWH0/LAD0 LPC_AD0 [30]
2 1 ICH_RTCX2 C24 K4 LPC_AD1
+RTCVCC RTCX2 FWH1/LAD1 LPC_AD1 [30]
L6 LPC_AD2
FWH2/LAD2 LPC_AD2 [30]
+RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3 [30]
R376 +RTCVCC 1 2 ICH_SRTCRST# F20
20K_0402_5% R180 SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# [30]
1

20K_0402_5%

RTC

LPC
R383 close to RAM door close to RAM door ICH_INTVRMEN B22 INTVRMEN LDRQ0# J3
332K_0402_1% A22 J1
LAN100_SLP LDRQ1#/GPIO23 R166 2
1 2 1 2 1 10K_0402_5% +3VS
R337 @ R336 @ E25 N7 EC_GA20
EC_GA20 [30]
2

10K_0603_5% 10K_0603_5% GLAN_CLK A20GATE H_A20M#

A20M# AJ27 H_A20M# [4]
ICH_INTVRMEN C13 LAN_RSTSYNC DPRSTP# R375 1 0_0402_5% H_DPRSTP#
High = Internal VR Enable DPRSTP# AJ25
DPSLP# R158 1
2
0_0402_5% H_DPSLP#
H_DPRSTP# [5,8,43]
1 2 1 2 F14 LAN_RXD0 DPSLP# AE23 2 H_DPSLP# [5]
1U_0603_10V6K 1U_0603_10V6K G13
+3V C450 C248 LAN_RXD1 FERR# H_FERR#
D14 LAN_RXD2 FERR# AJ26 1 2 H_FERR# [4]

LAN / GLAN
R374 56_0402_5%
D13 AD22 H_PW RGOOD 2 1 +1.05VS
LAN_TXD_0 CPUPWRGD H_PW RGOOD [5]
D12 R370 56_0402_5%
LAN_TXD_1
1

E13 AF25 H_IGNNE#

LAN_TXD_2 IGNNE# H_IGNNE# [4]
R399
10K_0402_5% PROJECT_ID2 B10 AE22 H_INIT# 2 1
GPIO56 INIT# H_INIT# [4] +3VS
@ AG25 H_INTR R168 10K_0402_5%

CPU
INTR H_INTR [4]
+1.5VS_PCIE_ICH 1 2 GLAN_COMP B28 L3 EC_KBRST#
EC_KBRST# [30]
2

R365 24.9_0402_1% GLAN_COMPI RCIN#

B27 GLAN_COMPO
PROJECT_ID2 1 2 HDA_BITCLK_ICH AF23 H_NMI
[32] HDA_BITCLK_MDC NMI H_NMI [4]
R151 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# [4]
[32] HDA_SYNC_MDC 1 2 HDA_SYNC_ICH AH4 HDA_SYNC
1

C R149 33_0402_5% AH27 H_STPCLK# C

STPCLK# H_STPCLK# [4]
R397 1 2 HDA_RST_ICH# AE7
PRE-MP [32] HDA_RST_MDC# HDA_RST#
10K_0402_5% R152 33_0402_5% AG26 THRMTRIP_ICH# R373 1 2 54.9_0402_1% H_THERMTRIP#
THRMTRIP# H_THERMTRIP# [4,8]
KALG1@ [33] HDA_SDIN0 AF4 HDA_SDIN0
[32] HDA_SDIN1 AG4 AG27 2 1 +1.05VS
2

HDA_SDIN1 TP12 R372 56_0402_5%

[8] HDA_SDIN2 AH3 HDA_SDIN2
AE5

IHDA
HDA_SDIN3
SATA4RXN AH11 R372 need to place within 2" of ICH9M
[32] HDA_SDOUT_MDC 1 2 HDA_SDOUT_ICH AG5 HDA_SDOUT SATA4RXP AJ11 R373 must be place within 2" of R372 w/o stub.
+3VS R150 33_0402_5% AG12
SATA4TXN
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
AE8 HDA_DOCK_RST#/GPIO34
1

MAINPW ON [38,39]
R144 [36] SATA_LED# SATA_LED# AG8 SATALED# SATA_DTX_C_IRX_N5
SATA5RXN AH9 SATA_DTX_C_IRX_N5 [29]
10K_0402_5% [23] SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AJ16 AJ9 SATA_DTX_C_IRX_P5 SATA_DTX_C_IRX_P5 [29] R369 @
SATA0RXN SATA5RXP

1
SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N5 330_0402_5% C
SATA for HDD [23] SATA_DTX_C_IRX_P0 AH16 AE10
2

SATA_ITX_DRX_N0 SATA0RXP SATA5TXN SATA_ITX_DRX_P5 Q34

AF17 SATA0TXN SATA5TXP AF10 +1.05VS 1 2 2
SATA_LED# SATA_ITX_DRX_P0 AG17 B 2SC2411K_SOT23
SATA0TXP CLK_PCIE_SATA# E @
AH18 CLK_PCIE_SATA# [16]

3
SATA_CLKN

SATA
[23] SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
PROJECT_ID SATA1RXN SATA_CLKP CLK_PCIE_SATA [16]
SATA for ODD [23] SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 AJ13 AJ7 SATARBIAS
SATA_ITX_DRX_N1 SATA1RXP SATARBIAS# R401 1
AG14 SATA1TXN SATARBIAS AH7 2 24.9_0402_1% H_THERMTRIP#
ID0 ID1 ID2 SATA_ITX_DRX_P1 AF14 SATA1TXP 10mils width less than 500mils
KAL90 0 0 0
ICH9-M ES_FCBGA676
KAL90+ 1 0 0

B KALG1 0 1 0 HDA_BITCLK_ICH
close ICH9 B
[33] HDA_BITCLK_AUDIO 1 2
R423 33_0402_5% SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
KALG0 1 1 0 HDA_SYNC_ICH C202 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 [23]
[33] HDA_SYNC_AUDIO 1 2
HDA for AUDIO R424 33_0402_5% SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0 +RTCBATT
KALG1_H0+ 0 0 1 HDA_RST_ICH# C203 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 [23]
[33] HDA_RST_AUDIO# 1 2
R425 33_0402_5%
KALG1_90+ 1 0 1 1 2 HDA_SDOUT_ICH
[33] HDA_SDOUT_AUDIO
R409 33_0402_5% SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1
C201 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 [23]
1 2 HDA_BITCLK_ICH SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
[8] HDA_BITCLK_MCH SATA_ITX_C_DRX_P1 [23]

2
R142 33_0402_5% C200 0.01U_0402_16V7K
[8] HDA_SYNC_MCH 1 2 HDA_SYNC_ICH R304
R140 33_0402_5% C199 KAL90_90+@ 1K_0402_5%
HDA for GMCH 1 2 HDA_RST_ICH# SATA_ITX_DRX_N5 1 2 SATA_ITX_C_DRX_N5
[8] HDA_RST_MCH# SATA_ITX_C_DRX_N5 [29]
R143 33_0402_5% 0.01U_0402_16V7K

1 1
[8] HDA_SDOUT_MCH 1 2 HDA_SDOUT_ICH SATA_ITX_DRX_P5 1 2 SATA_ITX_C_DRX_P5
R141 33_0402_5% C198 0.01U_0402_16V7K SATA_ITX_C_DRX_P5 [29]
D30 BAS40-04_SOT23-3
KAL90_90+@
+VCC_HDA_ICH

+RTCVCC +CHGRTC

2
R404
1K_0402_5%
@
1
HDA_SDOUT_ICH C331
Flash Descriptor Security Override Strap 0.1U_0402_16V4Z
A ICH_TP3 [21]
Low= Descriptor Security override
2 RTC Conn A

XOR Chain Entrance Strap GPIO33

R388
1K_0402_5%
High= Default* (Internal pull-up)
@
ICH_TP3 HDA_SDOUT Description
0 0 RSVD Security Classification Compal Secret Data Compal Electronics, Inc.
0 1 Enter XOR Chain Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

1 0 Normal Operation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
1 1 Set PCIE port config bit 1 Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS
Place closely pin B2 Place closely pin AC1
1 2 SERIRQ U22C
R167 10K_0402_5% ICH_SMBCLK G16 AH23 PROJECT_ID1 CLK_ICH_48M CLK_ICH_14M
[16,28] ICH_SMBCLK SMBCLK SATA0GP/GPIO21
PM_CLKRUN# ICH_SMBDATA PROJECT_ID0
1
R169
2
8.2K_0402_5%
[16,28] ICH_SMBDATA
LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19 AF19
AE21 R159 1 2 10K_0402_5%

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

1
1 2 EC_THERM# ICH_SMLINK0 C17 AD20
R379 8.2K_0402_5% ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R148 R420
B18 SMLINK1
1 2 H_STP_PCI# H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
EC_SWI# CLK14 CLK_ICH_48M CLK_ICH_14M [16]
R395 @ 10K_0402_5% F19 clocks AF3 @ @
H_STP_CPU# [30] EC_SWI# RI# CLK48 CLK_ICH_48M [16]
1 2

2
R229 @ 10K_0402_5% @ SUS_STAT# R4 P1 SUS_CLK @ 1 1
T10 PAD SUS_STAT#/LPCPD# SUSCLK PAD T34
1 2 SB_SPKR XDP_DBRESET# G19 C197 C472
[4] XDP_DBRESET# SYS_RESET#
R170 @ 1K_0402_5% C16 PM_SLP_S3# 10P_0402_50V8J 10P_0402_50V8J
D PM_SYNC# SLP_S3# PM_SLP_S4# PM_SLP_S3# [30] D
M6 E16 @ @
R01 [8] PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S5# PM_SLP_S4# [30] 2 2
G17 PM_SLP_S5# [30]

SYS / GPIO
OCP# EC_LID_OUT# SLP_S5#
1 2 [30] EC_LID_OUT# A17 SMBALERT#/GPIO11
R145 10K_0402_5% C10 S4_STATE#
ICH_GPIO17 H_STP_PCI# S4_STATE#/GPIO26
1 2 [16] H_STP_PCI# A14
R154 @ 10K_0402_5% H_STP_CPU# STP_PCI# ICH_PWROK
[16] H_STP_CPU# E19 G20 ICH_PWROK [8]
ICH_GPIO18 STP_CPU# PWROK
1 2
R419 @ 10K_0402_5% PM_CLKRUN# L4 M2 DPRSLPVR 1 2 PM_DPRSLPVR [8,43]

Power MGT
ICH_GPIO20 [30] PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 R417 100_0402_5%
1 2
R153 @ 10K_0402_5% ICH_PCIE_WAKE# E20 B13 PM_BATLOW#
SATA_CLKREQ# [28] ICH_PCIE_WAKE# SERIRQ WAKE# BATLOW#
1 2 [30] SERIRQ M5
SERIRQ
R418 10K_0402_5% EC_THERM# AJ23 R3 PBTN_OUT# ICH_PWROK 1 2
ICH_GPIO38 [30] EC_THERM# THRM# PWRBTN# PBTN_OUT# [30]
1 2 R179 10K_0402_5%
R155 @ 10K_0402_5% VGATE 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
ICH_GPIO39 [8,16,43] VGATE VRMPWRGD LAN_RST#
1 2 R231 0_0402_5% R213 10K_0402_5% No used Integrated LAN,
R147 @ 10K_0402_5% @ ICH_TP11 A20 D22 SB_RSMRST# EC_PWROK 1 2
ICH_GPIO48 T23 PAD TP11 RSMRST# connecting LAN_RST# to GND
1 2 R384 10K_0402_5%
R157 10K_0402_5% OCP# AG19 R5 CK_PWRGD
[4] OCP# CRT_DET GPIO1 CK_PWRGD CK_PWRGD [16]
AH21 GPIO6
AG21 R6 ICH_PWROK R232 2 @ 1 0_0402_5%
EC_SMI# GPIO7 CLPWROK
[30] EC_SMI# A21 GPIO8
C12 B16 PM_SLP_M# @ +3VS
[30] EC_SCI# GPIO12 SLP_M# PAD T30
CP_PE# C21
+3V [28] CP_PE# ICH_GPIO17 GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 [8]

5
ICH_GPIO18 K1 B19 U10

GPIO
GPIO18 CL_CLK1

Controller Link
1 2 ICH_SMBCLK ICH_GPIO20 AF8 2 EC_PWROK

P
GPIO20 ICH_PWROK B EC_PWROK [30,32]
R176 2.2K_0402_5% AJ22 F22 4
ICH_SMBDATA +3V ICH_GPIO27 SCLOCK/GPIO22 CL_DATA0 CL_DATA0 [8] Y VGATE
1 2 @ A9 C19 1
T20 PAD GPIO27 CL_DATA1 A

G
R396 2.2K_0402_5% @ ICH_GPIO28 D19
T14 PAD GPIO28
1 2 EC_SWI# SATA_CLKREQ# L1 C25 CL_VREF0_ICH NC7SZ08P5X_NL_SC70-5
[16] SATA_CLKREQ#

3
SATACLKREQ#/GPIO35 CL_VREF0
1

R230 10K_0402_5% ICH_GPIO38 AE19 A19 CL_VREF1_ICH

ICH_SMLINK0 R403 ICH_GPIO39 SLOAD/GPIO38 CL_VREF1
1 2 AG22 SDATAOUT0/GPIO39
C R211 10K_0402_5% 10K_0402_5% ICH_GPIO48 C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 [8]
1 2 ICH_SMLINK1 @ ICH_GPIO49 AH24 D18
R392 10K_0402_5% ICH_GPIO57 GPIO49 CL_RST1# R367 2 @
A8 1 0_0402_5%
2

LINKALERT# ICH_GPIO57 GPIO57/CLGPIO5 ICH_GPIO24

1 2 MEM_LED/GPIO24 A16 PAD T29 @ 2 1 +3V
R210 10K_0402_5% SB_SPKR M7 C18 ICH_GPIO10 R209 100K_0402_5%
[33] SB_SPKR SPKR GPIO10/SUS_PWR_ACK
1

1 2 XDP_DBRESET# AJ24 C11 ICH_ACIN 2 1 SB_RSMRST# 1 Q33 3

MMBT3906_SOT23-3 C
MISC
[8] MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN [30,35,36,37,40] EC_RSMRST# [30]
R177 10K_0402_5% R402 ICH_GPIO9
B21 C20 PAD T21 D26

E
[20] ICH_TP3 TP3 WOL_EN/GPIO9
1 2 ICH_PCIE_WAKE# 100K_0402_5% @
T7 PAD ICH_TP8 AH20 @ CH751H-40PT_SOD323-2
TP8

1
R178 1K_0402_5% @ ICH_TP9 AJ20

B
T5 PAD

2
PM_BATLOW# @ ICH_TP10 TP9 R366
1 2 T6 PAD AJ21 1 2 +3V
2

R398 8.2K_0402_5% TP10 R361 4.7K_0402_5%

10K_0402_5%
1 2 EC_LID_OUT# ICH9-M ES_FCBGA676
R393 10K_0402_5% D31A

2
1 2 ICH_GPIO10 U22D 1
R212 10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_MTX_IRX_N0 6
CP_PE# [28] PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PERN1 DMI0RXN DMI_MTX_IRX_P0 DMI_MTX_IRX_N0 [8]
1 2 [28] PCIE_PTX_C_IRX_P1 N28 V26 DMI_MTX_IRX_P0 [8] 2
R214 10K_0402_5% C1586 0.1U_0402_16V7K PCIE_ITX_PRX_N1 PERP1 DMI0RXP DMI_ITX_MRX_N0
For Express Card [28] PCIE_ITX_C_PRX_N1 2KAL90_H0_90+@
1 P27 U29 DMI_ITX_MRX_N0 [8]
S4_STATE# C1587 0.1U_0402_16V7K PCIE_ITX_PRX_P1 PETN1 DMI0TXN DMI_ITX_MRX_P0
1 2 2KAL90_H0_90+@
1 P26 U28 BAV99DW-7_SOT363

Direct Media Interface

[28] PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P0 [8]
R208 @ 10K_0402_5%
PCIE_PTX_C_IRX_N2 L29 Y27 DMI_MTX_IRX_N1 D31B
PROJECT_ID0 [28] PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PERN2 DMI1RXN DMI_MTX_IRX_P1 DMI_MTX_IRX_N1 [8]
1 2 [28] PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 [8] 4
R156 10K_0402_5% @ C251 2 0.1U_0402_16V7K PCIE_ITX_PRX_N2 PERP2 DMI1RXP DMI_ITX_MRX_N1
For Wireless LAN [28] PCIE_ITX_C_PRX_N2 1
PCIE_ITX_PRX_P2
M27
PETN2 DMI1TXN
W29
DMI_ITX_MRX_P1 DMI_ITX_MRX_N1 [8] 3
1 2 [28] PCIE_ITX_C_PRX_P2 C252 2 1 0.1U_0402_16V7K M26 W28 5
PETP2 DMI1TXP DMI_ITX_MRX_P1 [8]

1
R146 10K_0402_5% KALG1@

PCI - Express
1 2 PRE-MP PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 BAV99DW-7_SOT363 R360
[26] PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PERN3 DMI2RXN DMI_MTX_IRX_P2 DMI_MTX_IRX_N2 [8]
R381 10K_0402_5% KALG1@ J28 AB26 2.2K_0402_5%
[26] PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 [8]
1 2 PROJECT_ID1 For PCIE LAN C258 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
[26] PCIE_ITX_C_PRX_N3 PETN3 DMI2TXN DMI_ITX_MRX_N2 [8]
R380 @ 10K_0402_5% [26] PCIE_ITX_C_PRX_P3 C259 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
DMI_ITX_MRX_P2 [8]

2
PM_DPRSLPVR PETP3 DMI2TXP
1 2
R436 @ 100K_0402_5% G29 AD27 DMI_MTX_IRX_N3
ICH_GPIO49 PERN4 DMI3RXN DMI_MTX_IRX_P3 DMI_MTX_IRX_N3 [8]
1 2 G28 AD26 DMI_MTX_IRX_P3 [8]
R378 @ 1K_0402_5% +3VS PERP4 DMI3RXP DMI_ITX_MRX_N3
H27 AC29 DMI_ITX_MRX_N3 [8]
B PETN4 DMI3TXN DMI_ITX_MRX_P3 B
H26 AC28 DMI_ITX_MRX_P3 [8]
PETP4 DMI3TXP +3VS
2

E29 T26 CLK_PCIE_ICH#

+3V PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# [16]
R387 E28 T25
PERP5 DMI_CLKP CLK_PCIE_ICH [16]
10K_0402_5% F27
PETN5 R362 24.9_0402_1% R219
High: CRT Plugged F26
PETP5 DMI_ZCOMP
AF29
DMI_IRCOMP
Within 500 mils
AF28 1 2 +1.5VS_PCIE_ICH 3.24K_0402_1%
1

CRT_DET DMI_IRCOMP
C29
PERN6/GLAN_RXN
1 2 USB_OC#11 C28 AC5 USB20_N0
USB20_N0 [29]
PERP6/GLAN_RXP USBP0N
1

R207 10K_0402_5% D USB20_P0 CL_VREF0_ICH

D27
PETN6/GLAN_TXN USBP0P
AC4 USB20_P0 [29] USB/B
1 2 USB_OC#7 [18] CRT_DET# 2 D26
PETP6/GLAN_TXP USBP1N
AD3 USB20_N1
USB20_N1 [29]
USB20_P1
[29] USB\ESATA
R206 10K_0402_5% Q13G AD2 1
USBP1P USB20_P1
2N7002_SOT23 S D23 AC1 C280 R220
3

SPI_CLK USBP2N 453_0402_1%

D24 AC2
USB_OC#3 SPI_CS0# USBP2P USB20_N3 0.1U_0402_16V4Z
1 8 [19] SPI_CS#1 F23
SPI_CS1#GPIO58/CLGPIO6 USBP3N
AA5 USB20_N3 [17]
USB_OC#2 USB20_P3 2
2 7
USBP3P
AA4 USB20_P3 [17] CMOS Camera
USB_OC#0 USB20_N4
3 6
USB_OC#5
D25
SPI_MOSI SPI USBP4N
AB2
USB20_P4 USB20_N4 [25]
4 5 E23
SPI_MISO USBP4P
AB3
USB20_N5 USB20_P4 [25] Cardreader
AA1 USB20_N5 [28]
RP1 10K_1206_8P4R_5% USBP5N USB20_P5
[29] USB_OC#0 N4
OC0#/GPIO59 USBP5P
AA2 USB20_P5 [28] New Card
USB_OC#1 N5 W5 USB20_N6 +3V
[29] USB_OC#1 OC1#/GPIO40 USBP6N USB20_N6 [29]
USB_OC#4 USB_OC#2 USB20_P6
1 8
USB_OC#8 USB_OC#3
N6
OC2#/GPIO41 USB USBP6P
W4 USB20_P6 [29] USB CONN
2 7 P6 Y3
USB_OC#9 USB_OC#4 OC3#/GPIO42 USBP7N
3 6 M1
OC4#/GPIO43 USBP7P
Y2
4 5 USB_OC#10 USB_OC#5 N2 W1 USB20_N8 R390
OC5#/GPIO29 USBP8N USB20_N8 [29]
M4 W2 USB20_P8 Bluetooth 3.24K_0402_1%
[29] USB_OC#6 OC6#/GPIO30 USBP8P USB20_P8 [29]
RP5 10K_1206_8P4R_5% USB_OC#7 M3 V2 USB20_N9
USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 USB20_N9 [29]
USB_OC#9
N3
OC8#/GPIO44 USBP9P
V3
USB20_N10 USB20_P9 [29] Finger Print CL_VREF1_ICH
N1 U5 USB20_N10 [28]
USB_OC#10 OC9#/GPIO45 USBP10N USB20_P10
USB_OC#11
P5
OC10#/GPIO46 USBP10P
U4 USB20_P10 [28] Mini Card(WLAN)
P3 U1 1
OC11#/GPIO47 USBP11N C456 R389
USBP11P U2
A USBRBIAS 453_0402_1% A
AG2
2 1 AG1
USBRBIAS
USBRBIAS#
No Reboot Strap 0.1U_0402_16V4Z
R413 2
Within 500 mils
22.6_0402_1% ICH9-M ES_FCBGA676
SB_SPKR Low= Default*
High= "No Reboot"
Internal TPM Strap DMI Termination Voltage
Low= Disable* Low= Desktop used
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/11/10 2008/11/24 Title
SPI_MOSI High= iTPM enable by MCH strap GPIO49 High= Mobile* (Internal pull-up)
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS U22F

+RTCVCC A23 A15 +1.05VS U22E
VCCRTC VCC1_05[01]
1 1 B15 AA26 H5
VCC1_05[02] VSS[001] VSS[107]

2
C452 C451 +ICH_V5REF A6 C15 1 1 AA27 J23
R405 D32 V5REF VCC1_05[03] C247 C235 VSS[002] VSS[108]
D15 AA3 J26
100_0402_1% 0.1U_0402_16V4Z VCC1_05[04] VSS[003] VSS[109]
CH751H-40PT_SOD323-2 E15 AA6 J27
2
1U_0402_6.3V6K 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[004] VSS[110]
AE1 F15 AB1 AC22
V5REF_SUS VCC1_05[06] 2 2 VSS[005] VSS[111]
L11 AA23 K28
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[006] VSS[112]
AA24 L12 AB28 K29
VCC1_5_B[01] VCC1_05[08] VSS[007] VSS[113]
1 AA25 L14 AB29 L13
VCC1_5_B[02] VCC1_05[09] VSS[008] VSS[114]
AB24 L16 AB4 L15
C464 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 L17 AB5 L2
1U_0402_6.3V6K VCC1_5_B[04] VCC1_05[11] VSS[010] VSS[116]
AC24 L18 AC17 L26
2 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH VSS[011] VSS[117]
AC25 M11 AC26 L27
VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
AD24 M18 AC27 L5
VCC1_5_B[07] VCC1_05[14] L34 1 VSS[013] VSS[119]

CORE
D AD25 P11 2 +1.5VS AC3 L7 D
+5VALW +5V +3V VCC1_5_B[08] VCC1_05[15] MBK1608301YZF_0603 VSS[014] VSS[120]
AE25 P18 AD1 M12
VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26
VCC1_5_B[10] VCC1_05[17]
T11
C435
1 (10UF*1, 0.01UF*1) AD10
VSS[016] VSS[122]
M13
AE27 T18 AD12 M14
VCC1_5_B[11] VCC1_05[18] VSS[017] VSS[123]
2

AE28 U11 C436 AD13 M15

R416 R415 D33 VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]
AE29 U18 10U_0805_10V4Z AD14 M16
@ 100_0402_1% VCC1_5_B[13] VCC1_05[20] 2 VSS[019] VSS[125]
F25 V11 AD17 M17
10_0402_5% CH751H-40PT_SOD323-2 VCC1_5_B[14] VCC1_05[21] 0.01U_0402_16V7K VSS[020] VSS[126]
G25 V12 AD18 M23
VCC1_5_B[15] VCC1_05[22] VSS[021] VSS[127]
H24 V14 AD21 M28
1

+ICH_V5REF_SUS VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]

H25 V16 AD28 M29
VCC1_5_B[17] VCC1_05[24] VSS[023] VSS[129]
1 J24 V17 +1.05VS AD29 N11
VCC1_5_B[18] VCC1_05[25] VSS[024] VSS[130]

VCCA3GP
J25 V18 AD4 N12
C470 VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
1U_0402_6.3V6K
K24
VCC1_5_B[20] C246
1 (4.7UF*1) AD5
VSS[026] VSS[132]
N13
K25 AD6 N14
2 VCC1_5_B[21] VSS[027] VSS[133]
L23 AD7 N15
+1.5VS_PCIE_ICH VCC1_5_B[22] 4.7U_0805_10V4Z VSS[028] VSS[134]
L24 R29 AD9 N16
VCC1_5_B[23] VCCDMIPLL 2 VSS[029] VSS[135]
(220UF*1, 22UF*2, 2.2UF*1) L25
VCC1_5_B[24]
AE12
VSS[030] VSS[136]
N17
+1.5VS L33 2 1 M24 W23 AE13 N18
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[25] VCC_DMI[1] VSS[031] VSS[137]
1 M25 Y23 AE14 N26
VCC1_5_B[26] VCC_DMI[2] VSS[032] VSS[138]
1 1 N23 AE16 N27
C434 + C250 C249 C243 VCC1_5_B[27] VSS[033] VSS[139]
N24 AB23 +1.05VS AE17 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25 AC23 1 1 AE2 P13
220U_D2_4VY_R15M 10U_0805_10V4Z VCC1_5_B[29] V_CPU_IO[2] C242 C206 C236 VSS[035] VSS[141]
2 2 2
P24
VCC1_5_B[30] (4.7UF*1, 0.1UF*2) AE20
VSS[036] VSS[142]
P14
P25 AG29 AE24 P15
10U_0805_10V4Z 2.2U_0603_6.3V6K VCC1_5_B[31] VCC3_3[01] 4.7U_0805_10V4Z 0.1U_0402_16V4Z VSS[037] VSS[143]
R24 AJ6 AE3 P16
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[038] VSS[144]
R25 AC10 AE4 P17
VCC1_5_B[33] VCC3_3[07] 0.1U_0402_16V4Z VSS[039] VSS[145]
R26 AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
R27 AD19 AE9 P23
VCC1_5_B[35] VCC3_3[03] VSS[041] VSS[147]

VCCP_CORE
T24 AF20 AF13 P28
VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27
VCC1_5_B[37] VCC3_3[05]
AG24 close to AG29 close to AD19 close to G6 AF16
VSS[043] VSS[149]
P29
T28 AC20 AF18 P4
VCC1_5_B[38] VCC3_3[06] VSS[044] VSS[150]
T29 +3VS AF22 P7
+1.5VS_SATAPLL_ICH VCC1_5_B[39] VSS[045] VSS[151]
U24 AH26 R11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C VCC1_5_B[40] VSS[046] VSS[152] C
U25 B9 AF26 R12

0.1U_0402_16V4Z
VCC1_5_B[41] VCC3_3[08] 1 1 1 1 1 1 VSS[047] VSS[153]
+1.5VS L35 1 2 V24 F9 C433 C462 C205 C279 C253 C245 AF27 R13
MBK1608301YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[048] VSS[154]
V25 G3 AF5 R14
VCC1_5_B[43] VCC3_3[10] VSS[049] VSS[155]
1 1 U23 G6 AF7 R15
VCC1_5_B[44] VCC3_3[11] VSS[050] VSS[156]

PCI
2 2 2 2 2 2
W24 J2 AF9 R16
C453 C454 VCC1_5_B[45] VCC3_3[12] VSS[051] VSS[157]
W25 J7 AG13 R17
VCC1_5_B[46] VCC3_3[13] VSS[052] VSS[158]
10U_0805_10V4Z K23 K7 AG16 R18
2 2 VCC1_5_B[47] VCC3_3[14] VSS[053] VSS[159]
(10UF*1, 1UF*1) 1U_0402_6.3V6K
Y24
VCC1_5_B[48] close to AJ6 close to B9 close to K7 AG18
VSS[054] VSS[160]
R28
Y25 AG20 T12
VCC1_5_B[49] +VCC_HDA_ICH VSS[055] VSS[161]
AJ4 +3VS AG23 T13
VCCHDA R408 @ 0_0603_5% VSS[056] VSS[162]
AG3 T14
VSS[057] VSS[163]
AJ3 +1.5VS AG6 T15
+5VALW VCCSUSHDA R407 0_0603_5% VSS[058] VSS[164]
AJ19 1 AG9 T16
VCCSATAPLL C466 VSS[059] VSS[165]
AH12 T17
VSS[060] VSS[166]
AC8 TP_VCCSUS1_05_ICH_1 PAD T8
@ AH14 T23
VCCSUS1_05[1] VSS[061] VSS[167]
+1.5VS AC16 F17 TP_VCCSUS1_05_ICH_2 PAD T15
@ 0.1U_0402_16V4Z AH17 B26
VCC1_5_A[01] VCCSUS1_05[2] VSS[062] VSS[168]
3

2
S
AD15 AH19 U12
G VCC1_5_A[02] VSS[063] VSS[169]
[35] SBPWR_EN# 2 1 1 AD16 AH2 U13
C458 C460 VCC1_5_A[03] +VCCSUS_HDA_ICH VSS[064] VSS[170]
AE15 AD8 TP_VCCSUS1_5_ICH_1 PAD T9
@ +3V AH22 U14
VCC1_5_A[04] VCCSUS1_5[1] VSS[065] VSS[171]
ARX

1 Q36 D AF15 R411 @ 0_0603_5% AH25 U15

1

C471 AO3413_SOT23-3 VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 VSS[066] VSS[172]

AG15 F18 +1.5V AH28 U16
2
1U_0402_6.3V6K 2 VCC1_5_A[06] VCCSUS1_5[2] R410 0_0603_5% VSS[067] VSS[173]
AH15 1 1 AH5 U17
0.1U_0402_16V4Z 1U_0402_6.3V6K VCC1_5_A[07] C254 C468 VSS[068] VSS[174]
AJ15 AH8 AD23
2 +5V VCC1_5_A[08] VSS[069] VSS[175]
A18 AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[070] VSS[176]
AC11 D16 AJ14 U27
VCC1_5_A[09] VCCSUS3_3[02] VSS[071] VSS[177]
VCCPSUS

AD11 D17 2 2 AJ17 U3

VCC1_5_A[10] VCCSUS3_3[03] VSS[072] VSS[178]
AE11 E22 AJ8 V1
VCC1_5_A[11] VCCSUS3_3[04] VSS[073] VSS[179]
AF11 B11 V13
VCC1_5_A[12] VSS[074] VSS[180]
ATX

AG10 B14 V15

VCC1_5_A[13] VSS[075] VSS[181]
AG11 B17 V23
VCC1_5_A[14] VSS[076] VSS[182]
AH10 B2 V28
VCC1_5_A[15] VSS[077] VSS[183]
AJ10 AF1 +3V B20 V29
VCC1_5_A[16] VCCSUS3_3[05] VSS[078] VSS[184]
B B23 V4 B
VSS[079] VSS[185]
AC9 1 1 B5 V5
VCC1_5_A[17] C455 C234 C233 VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC18 C26 W27
VCC1_5_A[18] 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19
VCC1_5_A[19] 2 2 (0.1UF*1, 0.022UF*2) C27
VSS[083] VSS[189]
W3
T1 E11 Y1
VCCSUS3_3[06] 0.022U_0402_16V7K VSS[084] VSS[190]
AC21 T2 E14 Y28
VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
T3 E18 Y29
VCCSUS3_3[08] VSS[086] VSS[192]
G10 T4 E2 Y4
VCC1_5_A[21] VCCSUS3_3[09] VSS[087] VSS[193]
G9
VCC1_5_A[22] VCCSUS3_3[10]
T5 close to A18 close to T1 E21
VSS[088] VSS[194]
Y5
T6 E24 AG28
VCCSUS3_3[11] VSS[089] VSS[195]
AC12 U6 E5 AH6
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]

AC13 U7 E8 AF2
VCC1_5_A[24] VCCSUS3_3[13] VSS[091] VSS[197]
close to AC7 AC14
VCC1_5_A[25] VCCSUS3_3[14]
V6 F16
VSS[092] VSS[198]
B25
V7 F28
VCCSUS3_3[15] VSS[093]
+1.5VS AJ5 W6 F29
VCCUSBPLL VCCSUS3_3[16] VSS[094]
1 1 W7 G12
VCCSUS3_3[17] VSS[095]
USB CORE

C204 C465 AA7 Y6 G14 A1

VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
0.1U_0402_16V4Z
close to AJ5 AB6
VCC1_5_A[27] VCCSUS3_3[19]
Y7 G18
VSS[097] VSS_NCTF[02]
A2
AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 G24 A29
0.1U_0402_16V4Z VCC1_5_A[29] VSS[099] VSS_NCTF[04]
AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 AH29
VSS[101] VSS_NCTF[06]
2 1 +VCCLAN1_05_INT_ICH A10 G8 AJ1
C463 VCCLAN1_05[1] +VCCCL1_05_INT_ICH VSS[102] VSS_NCTF[07]
A11 G22 H2 AJ2
0.1U_0402_16V4Z VCCLAN1_05[2] VCCCL1_05 +VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
G23 H23 AJ28
+VCCLAN_ICH VCCCL1_5 VSS[104] VSS_NCTF[09]
+3VS A12 H28 AJ29
R400 0_0603_5% VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
1 B12 1 1 1 H29 B1
C461 VCCLAN3_3[2] C256 C257 C255 VSS[106] VSS_NCTF[11]
A24 +3VS B29
VCCCL3_3[1] @ @ VSS_NCTF[12]
VCCCL3_3[2]
B24 (0.1UF*1)
GLAN POWER

+1.5VS +VCC_GLANPLL_ICH A27 1U_0402_6.3V6K

2 R368 0_0603_5% VCCGLANPLL 2 2 2 ICH9-M ES_FCBGA676
1
0.1U_0402_16V4Z C442 D28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A
C443 VCCGLAN1_5[1] A
D29
VCCGLAN1_5[2]
(10UF*1, 2.2UF*1)10U_0805_10V4Z
2
E26
VCCGLAN1_5[3]
2.2U_0603_6.3V6K
E27
VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
A26
+VCCGLAN_ICH VCCGLAN3_3
+1.5VS
R364 0_0603_5% ICH9-M ES_FCBGA676
C439
(4.7UF*1)
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn.

JSATA1

1 GND
SATA_ITX_C_DRX_P0 2
[20] SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 HTX+
[20] SATA_ITX_C_DRX_N0 3 HTX-
4 GND
D [20] SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 C376 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5 D
SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 HRX-
[20] SATA_DTX_C_IRX_P0 1 2 6 HRX+
C377 0.01U_0402_16V7K 7 GND

+3VS 8 VCC3.3
9 VCC3.3
10 VCC3.3
11 GND
12 GND
13 GND
+5VS +3VS 14
+5VS VCC5
15 VCC5
16

1000P_0402_50V7K

0.1U_0402_16V4Z
VCC5

C381

C380
17

1000P_0402_50V7K
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
GND

C382
18 RESERVED

C379

C378

C374
1 1 1 1 1 1 19 GND
20 VCC12
21 VCC12 GND 24
22 VCC12 GND 23
2 2 2 2 2 2

OCTEK_SAT-22SU1G_NR
CONN@

C C

SATA ODD Conn.

JSATA2

1 1
SATA_ITX_C_DRX_P1 2
B [20] SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 2 B
[20] SATA_ITX_C_DRX_N1 3 3
4 4
[20] SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 C265 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5
SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1 5
[20] SATA_DTX_C_IRX_P1 1 2 6 6
C264 0.01U_0402_16V7K 7
R174 1 @ 7
2 1K_0402_1% 8 8
+5VS 9 9
10 10
11 11
12 12
13 13
+5VS 14 16
14 GND
15 15 GND 17
10U_0805_10V4Z
1000P_0402_50V7K

1 1 1
0.1U_0402_16V4Z

C241 C240 C239 OCTEK_SLS-13DB1G_NR

2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

+HDMI_5V_OUT
close to U1 VCC (+3VS) pins (one Pin one Capacitor)
+3VS +3VS D20 F2
+HDMI_5V
W=40mils
+5VS 2 1 1 2
1
RB491D_SC59-3 1.1A_6VDC_FUSE

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 C172
C469 C484 C485 C473 C486 C487 C474 C467 PSOT24C-LF-T7_SOT23-3 0.1U_0402_16V4Z
2
@ @ @ @
2 2 2 2 2 2 2 2
D +HDMI_5V_OUT D

R449 R448

2
1
2.2K_0402_5%

2.2K_0402_5%
U7

+3VS 25 HDMI_DET#

1
2
OE*
2 +3VS
VCC3V HDMI_SCLK
11 28
VCC3V SCL_SINK
15
VCC3V

2
21 29 HDMI_SDATA
VCC3V SDA_SINK R115
26
VCC3V
33 2.2K_0402_5%
R128 1 VCC3V HDMI_DET
+3VS 2 4.7K_0402_5% 40 30
VCC3V HPD_SINK
46

1
R431 1 @ VCC3V
2 4.7K_0402_5% 32 R435 1 2 4.7K_0402_5% +3VS
+3VS DDC_EN HDMI_DET#
+3VS R127 1 @ 2 4.7K_0402_5%
3 34 R434 1 @ 2 4.7K_0402_5% +3VS
FUNCTION1 FUNCTION3

1
R432 1 @ D
2 4.7K_0402_5% 4 35
FUCNTION2 FUNCTION4
1

1
R433 1 @ 2 4.7K_0402_5% HDMI_DET 2 Q12
R124 R125 PRE-MP G 2N7002_SOT23
47K_0402_5% 47K_0402_5% 1 2 6 R414 1 @ 2 4.7K_0402_5% +3VS S

3
R126 3.6K_0402_5% ANALOG1(REXT)

2
7 R412 1 @ 2 4.7K_0402_5% 1

100K_0402_5%

0.1U_0402_16V4Z
[10] TMDS_B_HPD#
2

HPD_SOURCE
To GMCH

R441

C475
SDVO_SDATA 8 @
[8] SDVO_SDATA SDA_SOURCE
SDVO_SCLK 9 2
[8] SDVO_SCLK

1
SCL_SOURCE
For Power Saving Application
+3VS R511 1 2 4.7K_0402_5% 10
ANALOG2 When Plug-in HDMI
@
HDMI_HPD=High OE#=Low Enable Level Shift
C UMA_DVI_TXC- 13 48 HDMI_PCIE_MTX_C_GRX_N3 C
UMA_DVI_TXC+ 14
OUT_D4+ IN_D4+
47 HDMI_PCIE_MTX_C_GRX_P3 When Plug-out HDMI
OUT_D4- IN_D4-
UMA_DVI_TXD1- 16 45 HDMI_PCIE_MTX_C_GRX_N1
HDMI_HPD=Low OE#=High Disable Level Shift
UMA_DVI_TXD1+ OUT_D3+ IN_D3+ HDMI_PCIE_MTX_C_GRX_P1
17 44
OUT_D3- IN_D3-
UMA_DVI_TXD2+ 19 42 HDMI_PCIE_MTX_C_GRX_P0
UMA_DVI_TXD2- OUT_D2+ IN_D2+ HDMI_PCIE_MTX_C_GRX_N0
20 41
OUT_D2- IN_D2-
UMA_DVI_TXD0+ 22 39 HDMI_PCIE_MTX_C_GRX_P2
UMA_DVI_TXD0- OUT_D1+ IN_D1+ HDMI_PCIE_MTX_C_GRX_N2 HDMI_PCIE_MTX_C_GRX_N[0..3]
23 38 HDMI_PCIE_MTX_C_GRX_N[0..3] [10]
OUT_D1- IN_D1-
Trace AS Short PASS 49 HDMI_PCIE_MTX_C_GRX_P[0..3]
THERMAL_GND HDMI_PCIE_MTX_C_GRX_P[0..3] [10]
1
GND
5
GND
12
GND 20071031:
18
24
GND Add U1. 49 (THERMAL_GND) to GND Plane
GND
27
GND
31
GND
36
GND
37
GND
43
GND

ASM1442T QFN 48P

UMA_DVI_TXC- 1 2 HDMI_R_CK-
R130 0_0402_5%

4 3
4 3

1 2
1 2
B B
L15 @ WCM-2012-900T_0805

UMA_DVI_TXC+ 1 2 HDMI_R_CK+
R131 0_0402_5% +HDMI_5V_OUT

(pin 19) plug in 5V

UMA_DVI_TXD0- 1 2 HDMI_R_D0-
R139 0_0402_5% JHDMI1
HDMI_DET 19
L18 @ WCM-2012-900T_0805 HP_DET
18
1
1 2
2
HDMI_SDATA
17
16
+5V
DDC/CEC_GND
Intel Cantiga TMDS Pin Definition
HDMI_SCLK SDA
4 3
15
14
SCL TMDS_B_CLK PEG_TXP_3
4 3 Reserved
HDMI_R_CK-
13
12
CEC
20
TMDS_B_CLK# PEG_TXN_3
CK- GND
11 21
UMA_DVI_TXD0+ HDMI_R_CK+ CK_shield GND
R138
1 2
0_0402_5% HDMI_R_D0-
10
9
CK+ GND
22
23
TMDS_B_DATA0 PEG_TXP_2
D0- GND
HDMI_R_D0+
8
7
D0_shield TMDS_B_DATA0# PEG_TXN_2
UMA_DVI_TXD1- HDMI_R_D1- D0+
1 2 6
R132 0_0402_5% D1-
HDMI_R_D1+
5
4
D1_shield TMDS_B_DATA1 PEG_TXP_1
HDMI_R_D2- D1+
4 3
3
2
D2- TMDS_B_DATA1# PEG_TXN_1
4 3 HDMI_R_D2+ D2_shield
1
D2+
1 2 TYCO_1939864-1 TMDS_B_DATA2 PEG_TXP_0
1 2 CONN@
L16 @ WCM-2012-900T_0805
TMDS_B_DATA2# PEG_TXN_0
DIP
UMA_DVI_TXD1+
R133
1 2
0_0402_5% TMDS_B_HPD# PEG_RXP_3

UMA_DVI_TXD2- 1 2
A R137 0_0402_5% A

L17 @ WCM-2012-900T_0805
1 2
1 2

4 3
4 3

UMA_DVI_TXD2+
R136
1 2
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/16 Deciphered Date 2008/10/16 Title
HDMI ASM1442T

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 24 of 45
5 4 3 2 1
 5 4 3 2 1

2 1
R303 0_0402_5%

U14

2 1 1 AV_PLL
+3VS 2 1 C328 0.1U_0402_16V4Z 3
R265 0_0603_5% NC
7 NC
+3VALW 2 1 +XDPWR_SDPWR_MSPWR 9
R290 @ 0_0603_5% CARD_3V3
D 11 D3V3
D
33 D3V3 VREG 10 1 2
22 C325 1U_0402_6.3V4Z
MS_D4
1 NC 30
8 3V3_IN
C309 @ RST# 44
4.7U_0603_6.3V6K MODE_SEL RST#
45 MODE_SEL

2
2 XTLO XDCLE
47 XTLO XD_CLE_SP19 43
1 XTLI 48 42 XDCE#
R306 XTLI XD_CE#_SP18 XDALE
XD_ALE_SP17 41
@ 100K_0402_5% C326 USB20_N4 4 40 SDDAT2_XDRE#
[21] USB20_N4 DM SD_DAT2/XD_RE#_SP16
0.1U_0402_16V4Z USB20_P4 5 39 SDDAT3_XDWE#
[21] USB20_P4

1
2 DP SD_DAT3/XD_WE#_SP15 XD_RDY
[36] 5IN1_LED# 14 GPIO0 XD_RDY_SP14 38
RST#_L 2 1 RST# 37 SDDAT4_XDWP#_MSD7
R307 0_0402_5% SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5_XDD0_MSD6
SD_DAT5/XD_D0/MS_D6_SP12 35
SDCLK_XDD1_MSCLK_L SDCLK_XDD1_MSCLK
Vender suggesttion SD_CLK/XD_D1/MS_CLK_SP11 34
31 SDDAT6_XDD7_MSD3
2
R301
1
0_0402_5%
1 SD_DAT6/XD_D7/MS_D3_SP10
29 MS_INS#
C335 MS_INS#_SP9 SDDAT7_XDD2_MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
1U_0402_6.3V4Z 27 SDDAT0_XDD6_MSD0
2 SD_DAT0/XD_D6/MS_D0_SP7 SDDAT1_XDD3_MSD1
SD_DAT1/XD_D3/MS_D1_SP6 26
25 XDD5_MSBS
XD_D5_SP5 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 23
21 SDCD
MODE_SEL SD_CD#_SP3 SDWP
SD_WP_SP2 20
19 XDCD
XD_CD#_SP1
EEDI 18
1 1
R308 2 13 XTAL_CTR 2 1 +3VS
@ C336 0_0402_5% RREF XTAL_CTR R236 0_0603_5%
MS_D5 24
47P_0402_50V8J 12 XTAL_CTR
2 DGND
32 15 If Open , use 12MHz. crystal
2

DGND EEDO
EECS 16 If Pull high , use CLKGEN 48MHz.
6 AGND EESK 17
46 36 SD_CMD
C
XTLI AGND SD_CMD C
[16] CLK_SD_48M 1 2

2
R311 0_0402_5%
1/9 R302
@ 6.19K_0402_1% RTS5159-GR LQFP 48P

2
R309
R310 0_0402_5% Change to RT5159-GR <SA00002YP00>

1
0_0402_5% 20081104
1

1
R312 @
@ 33_0402_5% 1 2
C338 6P_0402_50V8D
2

1
1
@ C339
22P_0402_50V8J @ Y3
2 12MHZ_16PF_6X12000012
2

EMI @
1 2 XTLO
C337 6P_0402_50V8D

+XDPWR_SDPWR_MSPWR

JREAD1 +XDPWR_SDPWR_MSPWR
3 XD-VCC SD-VCC 21
B
MS-VCC 28 B
SDDAT5_XDD0_MSD6 32

10U_0805_10V4Z
SDCLK_XDD1_MSCLK XD-D0 SDCLK_XDD1_MSCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
2 1 SDDAT7_XDD2_MSD2 9 XD-D2 SD-DAT0 14 SDDAT0_XDD6_MSD0 1
SDDAT1_XDD3_MSD1 8 12 XDD4_SDDAT1
R235 C299 XDD4_SDDAT1 XD-D3 SD-DAT1 SDDAT2_XDRE# @

C297
7 XD-D4 SD-DAT2 30
100K_0402_5% 0.1U_0402_16V4Z XDD5_MSBS 6 29 SDDAT3_XDWE#
2 SDDAT0_XDD6_MSD0 XD-D5 SD-DAT3 SDDAT4_XDWP#_MSD7 2
5 27
1

SDDAT6_XDD7_MSD3 XD-D6 SD-DAT4 SDDAT5_XDD0_MSD6

4 XD-D7 SD-DAT5 23
18 SDDAT6_XDD7_MSD3
SDDAT3_XDWE# SD-DAT6 SDDAT7_XDD2_MSD2
34 XD-WE SD-DAT7 16
SDDAT4_XDWP#_MSD7 33 25 SD_CMD
XDALE XD-WP SD-CMD SDCD
35 XD-ALE SD-CD-SW 1
XDCD 40
XD_RDY XD-CD SDWP
39 XD-R/B SD-WP-SW 2
SDDAT2_XDRE# 38
XDCE# XD-RE
37 XD-CE
XDCLE 36 26 SDCLK_XDD1_MSCLK
XD-CLE MS-SCLK SDDAT0_XDD6_MSD0
MS-DATA0 17
11 15 SDDAT1_XDD3_MSD1
7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2 SDCLK_XDD1_MSCLK
31 7IN1 GND MS-DATA2 19
24 SDDAT6_XDD7_MSD3
MS-DATA3 MS_INS#
MS-INS 22
13 XDD5_MSBS
MS-BS

1
41 7IN1 GND
42 R237
7IN1 GND @ 33_0402_5%
TAITW_R015-B10-LM CONN@

2
1
C298 1/5
@ 22P_0402_50V8J
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader Realtek5159
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 25 of 45
5 4 3 2 1
 A B C D

1 1

+3VALW
+3V_LAN

60mil
1 2
R44 0_1206_5% R471 0_0402_5%

10U_0805_10V4Z

10U_0805_10V4Z
1 2

1U_0402_6.3V4Z

0.1U_0402_16V4Z
1 1 1 1

C75

C74

C68

C67
2 2 2 2 D12
10/100_LINK_LED 2
1 LAN_LINK# [27]
1000_LINK_LED 3
@
Place Close to Pin 2 CHP202UPT_SOT323-3

+1.8_VDD/LX
+AVDD_CEN

L5
1 2 +1.8_VDD/LX
S INDUC_ 4.7UH +-20% SIA4012-4R7M
1 1 pin 1 = 1A
C84

C76

U3
Place Close to LAN chip
pin 1,2 60mil LAN_MIDI0+ 1 2
2 2 +3V_LAN R30 49.9_0402_1%
2
2 C25 0.1U_0402_16V4Z
10U_0805_10V4Z

2
1 30 1
0.1U_0402_16V4Z

+AVDD_CEN VDDHO/VDD18O/VDD18O TWSI_DATA LAN_MIDI0-

TWSI_CLK 29 1 2
48 10/100_LINK_LED R29 49.9_0402_1%
LED_LINK10_100n LAN_MIDI1+
2 VDD3V LED_ACTn 47 LAN_ACTIVITY# [27] 1 2
C37 R28 49.9_0402_1% 1 2 C24 0.1U_0402_16V4Z
0.1U_0402_16V7K 27 1 2 LAN_CLKREQ# [16] LAN_MIDI1- 1 2
SPI_CS/LED_DUPLEXn/LED_DUPLEXn R35 0_0402_5% R27 49.9_0402_1%
2 1 6 VDD3V/VDDHO/VDDHO
C1977 close to Pin6 LAN_MIDI2+ 1 2
26 1000_LINK_LED R26 49.9_0402_1% 1 2 C23 0.1U_0402_16V4Z
CTR12 SPI_DI/NC/LED_Link1000n LAN_MIDI2-
1 2 5 VDDLO/CTR12/CTR12 1 2
C38 0.1U_0402_16V4Z 40 R25 49.9_0402_1%
REFCLKN CLK_PCIE_LAN# [16] LAN_MIDI3+
REFCLKP 41 1 2
3 CLK_PCIE_LAN [16] R24 49.9_0402_1% 1 2 C22 0.1U_0402_16V4Z
[8,19,30] PLT_RST# PERSTn
14 LAN_MIDI0- LAN_MIDI3- 1 2
TXN0/TXN0/TRXN0 LAN_MIDI0- [27]
13 LAN_MIDI0+ R23 49.9_0402_1%
TXP0/TXP0/TRXP0 LAN_MIDI0+ [27]
7 18 LAN_MIDI1-
VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 LAN_MIDI1- [27]
17 LAN_MIDI1+
RXP1/RXP1/TRXP1 LAN_MIDI1+ [27]
4 21 LAN_MIDI2-
[30] EC_PME# WAKEn NC/NC/TRXN2 LAN_MIDI2- [27]
C60 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 LAN_MIDI2+

Atheros
[21] PCIE_PTX_C_IRX_N3 1 37 TX_N NC/NC/TRXP2 20 LAN_MIDI2+ [27]
[21] PCIE_PTX_C_IRX_P3 C61 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 38 24 LAN_MIDI3-
TX_P NC/NC/TRXN3 LAN_MIDI3- [27]
PCIE_ITX_C_PRX_N3 44 23 LAN_MIDI3+
[21] PCIE_ITX_C_PRX_N3 RX_N NC/NC/TRXP3 LAN_MIDI3+ [27]
PCIE_ITX_C_PRX_P3 43
[21] PCIE_ITX_C_PRX_P3 RX_P
XTALO
AR8121/8131 +1.2_AVDDL
9 XTLO AVDDL0 42

C58

C36

C62

C63

C59
LAN_XTALI 10 XTLI AVDDL1 39
2

R36 AVDDL2 36 C64

DVDDL/AVDDL/AVDDL 22 0.1U_0402_16V4Z
34 AVDDL3 16

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0_0402_5% TESTMODE 1 1 1 1 1
35 +AVDDVCO1
NC AVDDL4 11 1 2
+1.2_AVDDL
8
1

Y1 AVDDL5 1.1V regulator output

2 2 2 2 2

C31

C57
3
LAN_XTALO 2 1 3

31 46 +1.2_DVDDL
25MHZ_20P SMCLK DVDDL0
1 1 33 SMDATA AVDDL/DVDDL/DVDDL 45

C35

C66
32

1U_0402_6.3V4Z

0.1U_0402_16V4Z
DVDDL1 1 1
C39 C33 28 +1.2_DVDDL
33P_0402_50V8J 33P_0402_50V8J SPI_CLK/DVDDL/DVDDL
2 2
49

1U_0402_6.3V4Z

0.1U_0402_16V4Z
GND 1 1 2 2

C34

C65
25 CTR12
SPI_DO/AVDDH/AVDDH
AVDDH0 19
12 15 CTR12
RBIAS AVDDH1 2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1
2

C32

C29

C30
1 1 1
AR8131L-AL1E_QFN48_6X6
R33 2 2
SA000031Z00 S IC AR8131-AL1E QFN 48P E-LAN CTRL 1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2.37K_0402_1%
2 2 2
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2008/11/24 Title
Atheros AR8131

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 26 of 45
A B C D
 5 4 3 2 1

D D

+AVDD_CEN pull down circuit :

more power saving in
no-overclocking mode JLAN
T2 12 Yellow LED-

[26] LAN_MIDI0+ LAN_MIDI0+ 1 16 RJ45_MIDI0+ 2 1 L_LAN_ACTIVITY# 11

LAN_MIDI0- TD+ TX+ RJ45_MIDI0- [26] LAN_ACTIVITY# R438 Yellow LED+
[26] LAN_MIDI0- 2 TD- TX- 15
3 14 510_0402_5% RJ45_MIDI3- 8
CT CT PR4-
4 NC NC 13
5 12 RJ45_MIDI3+ 7
NC NC PR4+
6 CT CT 11
[26] LAN_MIDI1+ LAN_MIDI1+ 7 10 RJ45_MIDI1+ RJ45_MIDI1- 6
LAN_MIDI1- RD+ RX+ RJ45_MIDI1- PR2-
[26] LAN_MIDI1- 8 RD- RX- 9
C RJ45_MIDI2- 5 C
PR3-

1
C481 2
BOTHHAND_NS0013LF 220P_0402_50V7K RJ45_MIDI2+ 4
R437 PR3+
5.1K_0402_5% RJ45_MIDI1+ 3
1 PR2+

2
RJ45_MIDI0- 2 PR1-
SHLD2 14
T1 RJ45_MIDI0+ 1 PR1+
SHLD1 13
[26] LAN_MIDI2+ LAN_MIDI2+ 1 16 RJ45_MIDI2+ LAN_LINK# 10
LAN_MIDI2- TD+ TX+ RJ45_MIDI2- [26] LAN_LINK# Green LED-
[26] LAN_MIDI2- 2 TD- TX- 15
3 CT CT 14 +3V_LAN 2 1 9 Green LED+
4 13 R439 510_0402_5%
NC NC SUYIN_100073FR012G101ZL
5 NC NC 12
6 CT CT 11
[26] LAN_MIDI3+ LAN_MIDI3+ 7 10 RJ45_MIDI3+ 1 2
LAN_MIDI3- RD+ RX+ RJ45_MIDI3-
[26] LAN_MIDI3- 8 RD- RX- 9
C483
220P_0402_50V7K
BOTHHAND_NS0013LF

RJ45_GND 1 2 LANGND 40mil

C507 1 1
1000P_1206_2KV7K

C479
2 2 C515
B B
R427

R428

R429

R430

+AVDD_CEN 4.7U_0805_10V4Z
C20

C26

C21

C19

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1
75_0402_1%

75_0402_1%

75_0402_1%

75_0402_1%

2 2 2 2 L_LAN_ACTIVITY# 1 2
2

C480 @
68P_0402_50V8J

LAN_LINK# 1 2
2

Place close to TCT pin C482 @

RJ45_GND 68P_0402_50V8J

40mil
For EMI

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 27 of 45
5 4 3 2 1
 A B C D E

For Wireless LAN

+3VS_WLAN 1A +1.5VS

Mini Card Power Rating

+3VS_WLAN 1 2 +3VS 1 1 1 1 1 1
R329 0_1206_5% C358 C359 C357 C362 C361 C360 Power Primary Power (mA) Auxiliary Power (mA)
1 R328 1 @ 1
2 0_1206_5% +3V
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Peak Normal Normal
2 2 2 2 2 2
+3VS 1000 750
@ JMINI2 +3V 330 250 250 (wake enable)
ICH_PCIE_WAKE#1 R326 2 0_0402_5% 1 (WAKE#) 2
[21] ICH_PCIE_WAKE# 1 2 +3VS_WLAN
WLAN_BT_DATA 3 4 +1.5VS 500 375 5 (Not wake enable)
[29] WLAN_BT_DATA WLAN_BT_CLK 3 4
[29] WLAN_BT_CLK 5 6 +1.5VS
5 6
[16] MINI2_CLKREQ# 7 8
7 8
9 10
9 10
[16] CLK_PCIE_MINI2# 11 11 12 12
[16] CLK_PCIE_MINI2 13 13 14 14
15 15 16 16

17 17 18 18
19 20 WL_OFF#
19 20 PLT_RST_BUF# WL_OFF# [30]
21 21 22 22 PLT_RST_BUF# [19]
23 24 +3V_WLAN R323 1 2 0_0603_5% +3VS
[21] PCIE_PTX_C_IRX_N2 23 24
25 26 R322 1 @ 2 0_0603_5% +3V
[21] PCIE_PTX_C_IRX_P2 25 26
27 27 28 28
29 30 MINI2_SMBCLK R283 1 @ 2 0_0402_5% ICH_SMBCLK
29 30 ICH_SMBCLK [16,21]
31 32 MINI2_SMBDATA R295 1 @ 2 0_0402_5% ICH_SMBDATA
[21] PCIE_ITX_C_PRX_N2 31 32 ICH_SMBDATA [16,21]
[21] PCIE_ITX_C_PRX_P2 33 33 34 34
35 35 36 36 USB20_N10 [21]
37 37 38 38 USB20_P10 [21]
+3VS_WLAN 39 39 40 40
41 42 (LED_WWAN#)
41 42 MINI1_LED#
43 44 (LED_WLAN#) MINI1_LED# [31]
43 44
For MINICARD Port80 Debug 45 45 46 46
2 E51TXD_P80DATA 1 R321 2 0_0402_5% CL_RST#2_R
47
49
47 48 48
50
(9~16mA) 2
[30] E51TXD_P80DATA E51RXD_P80CLK 49 50
[30] E51RXD_P80CLK 51 51 52 52

G1
G2
G3
G3
FOX_AS0B226-S99N-7F

53
54
55
56
CONN@

New Card Power Switch

New Card Socket (Left/TOP)
U28 +3VALW_CARD +3VS_CARD +1.5VS_CARD
40mil
+1.5VS 12 11 +1.5VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A JEXP1
3 1.5Vin 1.5Vout 3
14 13
1.5Vin 1.5Vout

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
GND
10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
60mils C1588
1
C1589
1
C1590
1
C1591
1
C1592
1
C1593
1 [21] USB20_N5 2
USB_D-
+3VS 2 3 +3VS_CARD [21] USB20_P5 3
3.3Vin 3.3Vout USB_D+

KAL90_H0_90+@

KAL90_H0_90+@
4 5 CP_USB# 4
3.3Vin 3.3Vout CPUSB#
KAL90_H0_90+@

KAL90_H0_90+@

KAL90_H0_90+@

KAL90_H0_90+@
40mil 2 2 2 2 2 2
5
RSV
+3V 17 15 +3VALW_CARD 6
AUX_IN AUX_OUT ICH_SMBCLK RSV
7
PCI_RST# ICH_SMBDATA SMB_CLK
[19] PCI_RST# 6 19 8
SYSRST# OC# SMB_DATA
+1.5VS_CARD 9
SYSON PERST1# +1.5V
[30,35,41,42] SYSON 20 8 10
SHDN# PERST# ICH_PCIE_WAKE# +1.5V
11
SUSP# +3VS WAKE#
[30,32,35,41,42] SUSP# 1 16 +3VALW_CARD 12
STBY# NC PERST1# +3.3VAUX
13
CP_PE# PERST#
10 7 +3VS_CARD 14
(Internal Pull High to AUXIN) CPPE# GND +3VS +3.3V
1 15
CP_USB# C1594 CLKREQ1# +3.3V
9 21 16
(Internal Pull High to AUXIN) CPUSB# Thermal_Pad KAL90_H0_90+@ CP_PE# CLKREQ#
[21] CP_PE# 17
CPPE#
1

RCLKEN1 18 0.1U_0402_16V4Z 18
RCLKEN 2 [16] CLK_PCIE_CARD# REFCLK-
R484 19
[16] CLK_PCIE_CARD REFCLK+
5

G577NSR91U_TQFN20_4x4 10K_0402_5% 20
KAL90_H0_90+@ CLKREQ1# GND
2 21
G Vcc

B [21] PCIE_PTX_C_IRX_N1 PERn0

KAL90_H0_90+@ 4 22
EXP_CLKREQ# [16] [21] PCIE_PTX_C_IRX_P1
2

Y PERp0
1 23
A U29 GND
[21] PCIE_ITX_C_PRX_N1 24
PETn0
1

D KAL90_H0_90+@ [21] PCIE_ITX_C_PRX_P1 25

3

RCLKEN1 2 Q42 NC7SZ32P5X_NL_SC70-5 PETp0

26
G 2N7002_SOT23 GND
+3VS +3V +1.5VS S KAL90_H0_90+@ 27 29
3

GND GND
28 30
GND GND
1 1 1 SANTA_131851-A_LT
4 C1595 C1596 C1597 CONN@ 4
KAL90_H0_90+@ KAL90_H0_90+@ KAL90_H0_90+@
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & MINI CARD-WLAN
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 28 of 45
A B C D E
 A B C D E

+3V +3VS
JUSB2
+USB_VCCA 1
USB20_N1 VCC
2 D-

1
USB20_P1 3
R134 R135 D+
4 GND
0_0603_5% 0_0603_5%
@ KAL90_G0_90+@ 5
C196 JP16 GND1
6

2
KAL90_G0_90+@ GND2
6 G2 7 GND3
0.1U_0402_16V4Z 5 8
G1 GND4
2 1 4
1 [21] USB20_N9
USB20_N9
USB20_P9
3
2
4
3 Finger Print Conn. SUYIN_020173MR004G565ZR
CONN@ 1
[21] USB20_P9 2
1
1

2
D23 ACES_85201-04051 PCB FootPrint :
SM05T1G_SOT23-3
"SUYIN_020173MR004G565ZR_4P-S"
CONN@ only for CO- LAY JP17 USE
@

1
ESATA CONN

+3VALW +3VS

+USB_VCCA
W=60mils
1 1
C367 C364 D18 KAL90_G0_90+@ +USB_VCCA 1000P_0402_50V7K
USB20_P1 6
0.1U_0402_16V4Z 1U_0603_10V4Z CH3 CH2 3 1
1 1
3
2 2
S
C495 +
G
1 2 2 C508 C509
[30] BT_ON#
R330 10K_0402_5% Q31 +USB_VCCA 5 2 220U_6.3Φ*5.9_6.3VM
D AO3413_SOT23-3 Vp Vn 2 2 2
1

1 0.1U_0402_16V4Z
C368 W=40mils
4 1 USB20_N1 JESATA
+BT_VCC CH4 CH1
0.1U_0402_16V4Z 1 USB
2 2 CM1293-04SO_SOT23-6 USB20_N1 VBUS 2
1 1 [21] USB20_N1 2 D-

1
C365 C366 USB20_P1 3
[21] USB20_P1 D+
R327 4
4.7U_0805_10V4Z 300_0603_5% GND
2 2 5
0.1U_0402_16V4Z SATA_ITX_C_DRX_P5 GND
[20] SATA_ITX_C_DRX_P5 6
2

SATA_ITX_C_DRX_N5 A+ ESATA
[20] SATA_ITX_C_DRX_N5 7 A-
8 12
GND SHIELD
1

D
[20] SATA_DTX_C_IRX_N5
C158 2 1 KAL90_90+@ 0.01U_0402_16V7K SATA_IRX_DTX_N5 9
B- SHIELD
13
2 Q32 2 1 SATA_IRX_DTX_P5 10 14
[20] SATA_DTX_C_IRX_P5 B+ SHIELD
G 2N7002_SOT23 C159 KAL90_90+@ 0.01U_0402_16V7K 11 15
GND SHIELD
S
3

D19 KAL90_90+@ TYCO_1909574-1

SATA_IRX_DTX_P5 6 SATA_ITX_C_DRX_P5
CH3 CH2 3
CONN@

+BT_VCC 5 2
TYCO_1759594-1_11P
CONN@ +USB_VCCA Vp Vn
ACES_87213-0800G
8 8 GND 10
7 7 SATA_ITX_C_DRX_N5 4 1 SATA_IRX_DTX_N5
CH4 CH1
[21] USB20_P8 6 6
5 5 CM1293-04SO_SOT23-6
[21] USB20_N8
4 4
R325 10_0402_5%2 @ 3 3
[28] WLAN_BT_DATA
[28] WLAN_BT_CLK 1 2 2 2
R324 0_0402_5% @ 1 1 GND 9 +3V

JP18
+5VALW 80mil

1
+USB_VCCA R452
U27 0_0402_5%
3 R450 3
1 8 1 2
:Conn. reverse Bluetooth Conn. 2
3
GND
IN
OUT
OUT
7
6
100K_0402_5%
USB_OC#1 [21]

2
SYSON# IN OUT
1 4 5 1 2 USB_OC#6 [21]
C510 EN# FLG R451
TPS2061DRG4_SO8 10K_0402_5% 1
4.7U_0805_10V4Z C496
2
0.1U_0402_16V4Z
+USB_VCCA 2

W=80mils
+USB_VCCA
1 To USB/B Connector
470P_0402_50V7K

1
C511

C497 +

220U_6.3Φ*5.9_6.3VM
2 2
80mil
JP15
1 +5VALW
D21 KAL90_G0_90+@ JUSB1 1 +5VALW
2
USB20_P6 2 SYSON#
6
CH2 3
1 3 SYSON# [35]
CH3 USB20_N6 VCC 3
[21] USB20_N6 2 4
USB20_P6 D- 4 USB20_N0
[21] USB20_P6 3 5 USB20_N0 [21] 1
D+ 5 USB20_P0 C363
4 6 USB20_P0 [21]
GND 6
+USB_VCCA 5 2 7
Vp Vn 7 4.7U_0805_10V4Z
5 8 USB_OC#0 [21]
GND1 8 2
6 9
GND2 GND
7 GND3 GND 10
4 USB20_N6 4
4 CH4 CH1 1 8 GND4 ACES_85201-08051
CM1293-04SO_SOT23-6 SUYIN_020173MR004G565ZR
CONN@

USB CONN.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BT & & Finger Print & eSATA & USB Conn
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 29 of 45
A B C D E
 5 4 3 2 1

+3VALW

L20
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 +EC_VCCA
1 C278 2 FBM-L11-160808-800LMT_0603
1
C293
1 1 2
1
For EC Tools
+3VALW C306 C290 C305 C261
1000P_0402_50V7K C260 +3VALW
1 2 EC_PME# 2 2 2 2 1 1
1000P_0402_50V7K
KSI[0..7] JP19 Place on RAM door
2 KSI[0..7] [31]
R257 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1

ECAGND
KSO[0..17] 1 E51RXD_P80CLK
KSO[0..17] [31] 2 2 E51RXD_P80CLK [28]
3 E51TXD_P80DATA
3 E51TXD_P80DATA [28]
D
4 4 D

111
125
ACES_85205-0400

22
33
96

67
9
U9 @

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
@ C304
10P_0402_50V8J 1 21 INVT_PW M PAD T25 @
LPC_FRAME# [20] EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
2 1 [20] EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# [33]
3 26 PAD T24 @
[21] SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12
[20] LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF [40]
C316 @ LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
[20] LPC_AD3 LAD3
22P_0402_50V8J @ LPC_AD2 7 PWM Output C262 0.01U_0402_16V7K R184 4.7K_0402_5%
[20] LPC_AD2 LAD2
2 1 2 R253 1 [20] LPC_AD1
LPC_AD1 8 LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP
BATT_TEMP [38]
33_0402_5% LPC_AD0 BATT_OVP
[20] LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP [40]
ADP_I/AD2/GPIO3A 65 ADP_I [40]
12 AD Input 66 AD_BID0
[16] CLK_PCI_LPC PCICLK AD3/GPIO3B
[8,19,26] PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75
2 1 37 76 PAD T11 @ +3VALW
+3VALW ECRST# SELIO2#/AD5/GPIO43
R225 47K_0402_5% EC_SCI# 20 PAD T16 @
[21] EC_SCI# SCI#/GPIO0E
1 [21] PM_CLKRUN# 38 CLKRUN#/GPIO1D
68 DAC_BRIG ID_JAL90_JAW 50# 2 1
DAC_BRIG/DA0/GPIO3C DAC_BRIG [17]
C291 70 EN_DFAN1 R204 @ 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 [4]
0.1U_0402_16V4Z DA Output 71 IREF 2 1
2 IREF/DA2/GPIO3E IREF [40]
KSI0 55 72 R203 @
+3VALW +3VALW KSI0/GPIO30 DA3/GPIO3F CALIBRATE# [40]
KSI1 56 100K_0402_5%
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE [34]
2

C KSI4 59 84 EC_I2C_INT2 C
KSI4/GPIO34 PSDAT1/GPIO4B EC_I2C_INT2 [32] +3VALW
R223 R224 KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C PGD_IN [43]
+5VS 47K_0402_5% 47K_0402_5% KSI6 61 PS2 Interface 86 BT_LED#
KSI6/GPIO36 PSDAT2/GPIO4D BT_LED# [31]
KSI7 62 87 TP_CLK 65W /90W # 2 1
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK [31]
KSO0 39 88 TP_DATA R193 100K_0402_5%
TP_DATA [31]
1

KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F
1 2 TP_CLK KSO1 40 KSO1/GPIO21
R186 4.7K_0402_5% KSO2 41 KSO2/GPIO22
1 2 TP_DATA KSO3 42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S#
3S/4S# [40]
R185 4.7K_0402_5% KSO4 43 98 65W /90W #
+3VALW KSO4/GPIO24 SDICLK/GPXOA01 65W /90W # [40]
KSO5 SBPW R_EN
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
ID_JAL90_JAW 50#
SBPW R_EN [35,41] Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
1 2 EC_SMB_CK1 KSO7 46 SPI Device Interface Please see page 3.
R173 4.7K_0402_5% KSO8 KSO7/GPIO27
47 KSO8/GPIO28
1 2 EC_SMB_DA1 KSO9 48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO
EC_SI_SPI_SO [31]
R172 4.7K_0402_5% KSO10 49 120 EC_SO_SPI_SI +3VALW
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI [31]
2 @ 1 EC_I2C_INT2 KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK [31]
R171 10K_0402_5% KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# [31]

2
KSO13 52
KSO14 KSO13/GPIO2D R191 @
53 KSO14/GPIO2E
1 2 LID_SW # KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX Ra 100K_0402_5%
R254 100K_0402_5% KSO16 81 74 ON_0FF_TP SW #
+3VS KSO16/GPIO48 CIR_RLC_TX/GPIO41 ON_0FF_TP SW # [31]
KSO17 82 89 FSTCHG
FSTCHG [40]

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_RED_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_RED_LED# [36]
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# [36]

1
1 2 EC_SMB_CK2 [31,38] EC_SMB_CK1
EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_Yellow Green_LED#
BATT_Yellow Green_LED# [36]
R190 1
R188 2.2K_0402_5% EC_SMB_DA1 78 93 PW R_LED C263
[31,38] EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_LED [36]
1 2 EC_SMB_DA2 [4,31] EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON [28,35,41,42] Rb 8.2K_0402_5% 0.1U_0402_16V4Z
R187 2.2K_0402_5% EC_SMB_DA2 80 121 VR_ON
+3VS [4,31] EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON [32,43] 2
127 ACIN
ACIN [21,35,36,37,40]

2
B AC_IN/GPIO59 B

@ 1 2 EC_GPIOB PM_SLP_S3# 6 100

[21] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# [21]
R255 4.7K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
[21] PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# [21]
@ 1 2 EC_GPIOC EC_SMI# 15 102 EC_ON
[21] EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON [32]
R256 4.7K_0402_5% LID_SW # 16 103
[31] LID_SW # LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# [21]
EC_GPIOB 17 104 EC_PW ROK EC_CRY1 EC_CRY2
SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK [21,32]
EC_GPIOC 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# [17]
EC_PME# 19 GPIO 106 WL_OFF# 1 1
[26] EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# [28]
25 107 ON_0FF_TP LED# C283 C284
[8] MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10 ON_0FF_TP LED# [31]

4
FAN_SPEED1 28 108 BATTERY_LED#L 1 2
[4] FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 BATTERY_LED# [31]
BT_ON# 29 R205 27P_0402_50V8J 27P_0402_50V8J

IN

OUT
[29] BT_ON# FANFB2/GPIO15 2 2
E51TXD_P80DATA 30 0_0402_5%
E51RXD_P80CLK EC_TX/GPIO16
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# [21]
ON/OFF 32 112 ENBKL
[32] ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL [10]
PW R_SUSP_LED EAPD

NC

NC
[36] PW R_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD [33]
NUM_LED# 36 GPI 115
[31,36] NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# [21]
116 SUSP#
SUSP# [28,32,35,41,42]

3
GPXID5 PBTN_OUT#
GPXID6 117 PBTN_OUT# [21]
118 MC_RST#
GPXID7 MC_RST# [31]
EC_CRY1 122 X1
EC_CRY2 XCLK1 32.768KHZ_12.5P_MC-306
123 XCLK0 V18R 124
+3VALW +3VALW
1
AGND

C289
GND
GND
GND
GND
GND
1

4.7U_0805_10V4Z C270 100P_0402_50V8J

R485 R189 KB926QFD3_LQFP128_14X14 2 BATT_TEMP
1/6 Change version to D3 2 1
CIR
11
24
35
94
113

69

100_0805_5% 10K_0402_5% 20mil C269 100P_0402_50V8J

KAL90_90+@ L19 BATT_OVP
A @ SA00001J580 ECAGND 2 C303
2 1
100P_0402_50V8J
A
1 For KB926 D3 reversion
2

FBM-L11-160808-800LMT_0603 ACIN 2 1
3 4 RCIRRX 1 2 EC_RCIRRX
Vs OUT
1 GND GND 2
1 D45 KAL90_90+@
IR1 KAL90_90+@ CH751H-40PT_SOD323-2
C1599 TSOP36236TR_4P
1 Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z C1598 2008/11/10 2008/11/24 Title
2 KAL90_90+@ 1000P_0402_50V7K
Issued Date Deciphered Date
2 KAL90_90+@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926/CIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 30 of 45
5 4 3 2 1
 +3VALW 1 2 C302 1 2 0.1U_0402_16V4Z
R250 0_0603_5%
U13 & U15 CO-LAY
+SPI_VCC Reserved for BIOS simulator.Footprint SO8
U13 U15
To TP/B Conn.
JP21
EC_SPICS#/FSEL# 1 8 EC_SPICS#/FSEL# 1 8 +SPI_VCC
[30] EC_SPICS#/FSEL# CE# VDD CS# VCC
R284 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R285 1 2 0_0402_5% EC_SPICLK [30]
SPI_WP# 3 6 EC_SPICLK_R +5VS 6 8
R249 1 WP# SCK WP# SCLK 6 8
+3VALW 2 4.7K_0402_5% SPI_HOLD# 7 5 R286 1 2 0_0402_5% EC_SO_SPI_SI [30]
SPI_HOLD# 7 5 EC_SO_SPI_SI
[30] TP_CLK
TP_CLK 5 7
HOLD# SI R248 1 HOLD# SI EC_SI_SPI_SO TP_DATA 5 7
4 2 2 0_0402_5% EC_SI_SPI_SO [30] 4 2 [30] TP_DATA 4
VSS SO GND SO LEFT_BTN# 4
3
MX25L8005M2C-15G_SOP8 @ MX25L512AMC-12G_SO8 RIGHT_BTN# 3
2
2
ENE suggestion SPI Frequency over 66MHz 1
1
1 1
SST: 50MHz C244
C237 ACES_85201-0605
MXIC: 70MHz
100P_0402_50V8J 100P_0402_50V8J
ST: 40MHz 2 2
CONN@

TP_CLK
+3VS +5VS
KSI[0..7] +5VS TP_DATA
KSI[0..7] [30]

3
KSO[0..17]
KSO[0..17] [30]
R227 R226 C192
47K_0402_5% SW2 1.5K_0402_5% D22
KALG1@ KALG1@ KALG1@ 0.1U_0402_16V4Z @
INT_KBD KALH0 SMT1-05-A_4P LED9 PSOT24C_SOT23

1
JP30 INT_KBD JP23
[30] ON_0FF_TP SW#
ON_0FF_TP SW# 3 1 KALG1@

1
2 1 ON_0FF_TP LED#
ON_0FF_TP LED# [30]
(Left) KSO0 1 (Left) KSO0 1 4 2
KSO1 1 KSO1 1
2 2
KSO2 2 KSO2 2 HT-121UD_AMBER
3 3

5
6
KSO3 3 KSO3 3
4 4
KSO4 4 KSO4 4
5 5
KSO5 5 KSO5 5
6 6
KSO6 6 KSO6 6
7 7
KSO7 7 KSO7 7
8 8
KSO8 8 KSO8 8
9 9
KSO9 9 KSO9 9
10 10
KSO10 10 KSO10 10
11 11
KSO11 11 KSO11 11
12 12
KSO12 12 KSO12 12
KSO13
13
14
13 KSO13
13
14
13 M/B TP SW
KSO14 14 KSO14 14 KAL90_G0_90+@ KAL90_G0_90+@
KSO15
15
16
15 KSO15
15
16
15
Lid Switch SW3 SW4
KALH0 TP SW
KSO16 16 KSO16 16 SMT1-05-A_4P SMT1-05-A_4P SW5 KALH0@ SW6 KALH0@
17 17
KSO17 17 KSO17 17 LEFT_BTN# 3 RIGHT_BTN# 3 SMT1-05-A_4P SMT1-05-A_4P
18 18 1 1
KSI0 19
18
19
KSI0 19
18
19
(Hall Effect Switch) LEFT_BTN# 3 1 RIGHT_BTN# 3 1
KSI1 20 KSI1 20 4 2 4 2
KSI2 20 KSI2 20 +3VALW
21 21 4 2 4 2
KSI3 21 KSI3 21
22 22

5
6

5
6
KSI4 22 KSI4 22
23 23

5
6

5
6
KSI5 23 KSI5 23
24 24
KSI6 24 KSI6 24
25 27 25 27
KSI7 25 G1 KSI7 25 G1
26 28 26 28
26 G2 26 G2

1
2

2
(Right) C27 R31
ACES_85201-26051 ACES_85201-26051 47K_0402_5%

VDD
CONN@ CONN@ 0.1U_0402_16V4Z
1 FN/B

2
3 1 2 LID_SW# LID_SW# [30]
OUTPUT D9 RB751V_SOD323

GND
JP26
1
C28 1
KAL90
U2 1
2
+5VS
+3VS e-key/B
1 10P_0402_50V8J 2 MINI1_LED#
A3212ELHLT-T_SOT23W-3 3
2 3 KSI1 JP25 CONN@
4
4 FB_KSI4 KSO0
5 1
5 KSO0 KSI5 1
6 2
6 KSI2 2
7 3
7 BT_LED# 3
8 4
8 FB_KSI3 4
9
9
10
To BTN/B Conn. 10
GND
11
12
E&T_6905-E04N-00R

GND
KSO16 C223 1 100P_0402_50V8J
KSO4 KSO2 KSO3 ACES_85201-1005N KAL90_90+@
KSO15 C222 1 100P_0402_50V8J
2 KSO0 CONN@ R475 0_0402_5%
2
KSO17 C224 1 2 100P_0402_50V8J KSI1 WL_BTN# KSI5 WL_BTN# Volume Down Back Up 1 2 KSI4
KSO14 C221 1 100P_0402_50V8J JP28
2 KALH0 FB_KSI4 KALH0@
KSO13 C220 1 100P_0402_50V8J KSO7 C214 1 100P_0402_50V8J
KSI2 BT_BTN# 1
1 +5VS
R476 0_0402_5%
2 2 Program (KBLG0) 2
2

KSO12 C219 1 100P_0402_50V8J KSO6 C213 1 100P_0402_50V8J

KSI3 EMAIL_BTN# KSI6 BT_BTN# Volume Up 3
3
MINI1_LED#
+3VS 1 2 NUM_LED# [30,36]
2 2 Battery (KALG0) 4
4
FB_KSI4 KAL90_90+@
KSO5 C212 1 100P_0402_50V8J
KSI4 IE_BTN# 5
5
BT_LED# R477 0_0402_5%
2 6
KSI0 C225 1 100P_0402_50V8J 6 FB_KSI3
2 KSI5 E-KEY_BTN# 7 1 2 KSI3
KSO4 C211 1 100P_0402_50V8J 7
2 8
KSO11 C218 1 100P_0402_50V8J 8 FB_KSI3 KALH0@
2 9
GND R478 0_0402_5%
10
KSO10 C217 1 100P_0402_50V8J KSO3 C210 1 100P_0402_50V8J GND
2 2 1 2 MEDIA_LED# [36]
CONN@
KSI1 C226 1 2 100P_0402_50V8J KSI4 C229 1 2 100P_0402_50V8J ACES_85201-08051

KSO2 C209 1 2 100P_0402_50V8J +5VS+3VSMCVCC

KSI2 C227 1 2 100P_0402_50V8J
KSO1 C208 1 100P_0402_50V8J PRE-MP

0_0603_5% R481

R479

R480
2

1
KSO9 C216 1 2 100P_0402_50V8J

1
KAL90_H0_90+@
KSI3 C228 1 2 100P_0402_50V8J KSO0 C207 1 2 100P_0402_50V8J

KALH0@ 0_0603_5%

KAL90_90+@ 0_0603_5%
KSO8 C215 1 2 100P_0402_50V8J KSI5 C230 1 2 100P_0402_50V8J

2
2
KSI6 C231 1 100P_0402_50V8J JP29
2
To Media/B Conn. 1
KALG1
1 +5VS
KSI7 C232 1 2 100P_0402_50V8J 2 KSO4
2 KSO2
3
3 KSO3
4
FOR EMI @ R486 KALH0@ 0_0402_5%
4
5
5
6
KSI5
KSI6
KSI5 C193 1 100P_0402_50V8J JP22 6 BATTERY_LED#
2 [4,30] EC_SMB_CK2 1 2 7 BATTERY_LED# [30]
+3VS R488 KALH0@ 0_0402_5% 7 BT_LED#
1 8 BT_LED# [30]
R129 R489 KAL90_90+@ 0_0402_5% 1 8 MINI1_LED#
[4,30] EC_SMB_DA2 1 2 2 9 MINI1_LED# [28]
10K_0402_5% @ MEDIA_CK 2 9
[30,38] EC_SMB_CK1 1 2 3 10
MINI1_LED# C195 1 100P_0402_50V8J R491 KAL90_90+@ 0_0402_5% 3 10
1 2 2 [32] EC_I2C_INT1 4 11
@ @ MEDIA_DA 4 GND
[30,38] EC_SMB_DA1 1 2 5 12
BT_LED# C194 1 100P_0402_50V8J MC_RST# MC_RST+# 5 GND
2 [30] MC_RST# 1 2 6
@ R492 6 ACES_85201-1005N
7
0_0402_5% 7 CONN@
+3VALW 8
8
2

9
C1600 @ R493 @ GND
10
0.1U_0402_16V4Z 10K_0402_5% GND
ACES_85201-08051
CONN@
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 31 of 45
 A B C D E

TOP Side Power Button D58 USE

R114
1
@
2
10K_0603_5% ON/OFFBTN# PJSOT24C 3P C/A SOT-23
1 2
SCA00000E00
R335 @ 10K_0603_5% 24V

2
+3VALW D1
Bottom Side
1
@
C1

2
100P_0402_50V8J 51ON#
1 R258 EMI Reserve 2 1

1
PJSOT24C_3P_C/A_SOT-23
100K_0402_5%
SW1 MCVCC

1
SMT1-05-A_4P D27

1
3 1 2 ON/OFF [30]
ON/OFFBTN# 1 R506
4 2 3 51ON# KAL90_90+@
51ON# [37]
510K_0402_5%

1
DAN202UT106_SC70-3 MCVCC +3VS D
5
6

2
2 Q43

2
G KAL90_90+@

1000P_0402_50V7K
C317
R507 R508 S 2N7002_SOT23

3
1

1
D KAL90_90+@ KALH0@
2
EC_ON 2 D29 10K_0402_5% 10K_0402_5%
[30] EC_ON
G

1
2

1
Q25 RLZ20A_LL34 D
S

3
R194 1 2 Q44
[31] EC_I2C_INT1

2
2N7002_SOT23 G KAL90_90+@
10K_0402_5% S 2N7002_SOT23

3
1

+3VALW

2
R509 10K_0402_5%
@
D46 @
1SS355_SOD323-2

1
2 2
1 2 EC_I2C_INT2 [30]

1 2

Power ON Circuit PRE-MP

R510
0_0402_5%
KAL90_H0_90+@
RESERVE R01

+3VS +3VALW
+3VALW
1

R201
180K_0402_5% U8B
@ SN74LVC14APWLE_TSSOP14
14

14

@
D25 @ 0_0402_5%
P

P
2

1 2 1 2 3 SYS_PWROK
O 4
[30,43] VR_ON 1 2 EC_PWROK [21,30]
I O I R202 @
G

CH751H-40PT_SOD323-2 2
U8A
For South Bridge
7

C277 SN74LVC14APWLE_TSSOP14
1U_0603_10V6K @
@ 1
HDA MDC Conn.
3 3
+3V
1 2 +3V
15mil R333 0_0402_5% @ 1
JMDC1 C369
+3VS 1 2 +MDC_VCC 1 2
1 2 +1.5V
3 4 R331 0_0402_5% 1U_0603_10V4Z
+3VALW +3VALW [20] HDA_SDOUT_MDC 3 4 2
5 6 +3V
5 6
[20] HDA_SYNC_MDC 7 8
7 8
1

@ [20] HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10

R192 @ @ R332 33_0402_5% 9 10
[20] HDA_RST_MDC# 11 12 HDA_BITCLK_MDC [20]
@ 10K_0402_1% U8C U8D 11 12
14

14

1
R222 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 ACES_88018-124N
10K_0402_1% CONN@ R334
P

P
2

[28,30,35,41,42] SUSP# 1 2 5
I O
6 9
I O
8 VS_ON [41] 0_0402_5%
2
G

G
1

D @

2
SUSP C268
[35,42] SUSP 2 For +VCCP/+1.05VS 1
7

G 0.1U_0402_16V7K C370
Q19 S 1
3

2N7002_SOT23 22P_0402_50V8J
@ 2

For EMI

4 +3VALW +3VALW 4
0.1U_0402_16V4Z
C275 U8E @ U8F @
@ 2 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14
P

1 11 I O 10 13 I O 12 Security Classification Compal Secret Data Compal Electronics, Inc.

G

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

Power OK, Reset, MDC
7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev

WWW.AliSaler.Com
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 32 of 45
A B C D E
 A B C D E F G H

+VDDA J8 @
2 2 1 1

1
+5VAMP JUMP_43X39
R264 60mil (output = 300 mA)
10K_0402_5% L26 1 2 1
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT
5 40mil +VDDA
1 1 2

2
GND
L27 1 2 C352 C355 1 4.75V
1 2 KC FBM-L11-201209-221LMAT_0805 3 4 C350
10U_0805_10V4Z SHDN BYP

1
C296 1U_0402_6.3V6K 2 2
0.1U_0402_16V4Z U19 @ G9191-475T1U_SOT23-5 1 4.7U_0805_10V4Z
R263 C351 2
10K_0402_5%
1
HD Audio Codec 2 1

2
C318
1 2 MONO_IN 0.01U_0402_16V7K

1U_0402_6.3V6K

1
C295 C 1 2 L24
R261 Q26 R287 1.3K_0402_1% MBK1608121YZF_0603
[30] BEEP# 1 2 1 2 2
B 0.1U_0402_16V4Z +3VS_DVDD 20mil 1 2 +3VS
1U_0402_6.3V6K 560_0402_5% E 2SC2411K_SOT23

3
1 1 1
C322 C323 C324
C294
R260 10U_0805_10V4Z
1 2 1 2
[21] SB_SPKR 2 2 2

1
1U_0402_6.3V6K 560_0402_5%
D28 0.1U_0402_16V4Z
R262
10K_0402_5%
CH751H-40PT_SOD323-2 L23
MBK1608121YZF_0603
ANALOG MIC
0.1U_0402_16V4Z +1.5VS_DVDD 1 2 +1.5VS
2

2 +AVDD_HDA
1 1 1 UMA HDMI JP24
C319 C320 C308 DMIC_DATA_R
L25 1 2 0.1U_0402_16V4Z 40mil DMIC_CLK_R
1
2
1
+VDDA 2
FBM-11-160808-700T_0603 1 1 1 10U_0805_10V4Z
C343 C334 2 2 2
C345 3
10U_0805_10V4Z 0.1U_0402_16V4Z G1
4

25

38
G2

9
2 2 2 U17
0.1U_0402_16V4Z ACES_88266-02001

DVDD_IO
AVDD1

AVDD2

DVDD
CONN@

2 AMP_LEFT 2
14 LINE2-L FRONT_L 35 AMP_LEFT [34]
15 36 AMP_RIGHT
LINE2-R FRONT_R AMP_RIGHT [34]
R494 1K_0402_5% 1 2 MIC2_C_L 16 39 HP_LEFT MIC2_VREFO
DMIC_CLK_R 2 MIC2_L SURR_L HP_LEFT [34]
1 INT_MIC_R C1601 KALH0@ 4.7U_0603_6.3V6M
KALH0@ 1 2 MIC2_C_R 17 41 HP_RIGHT
MIC2_R SURR_R HP_RIGHT [34]
C1602 KALH0@ 4.7U_0603_6.3V6M

1
LINE_L 1 2 LINE_C_L 23 45
[34] LINE_L LINE1_L SIDE_L
KAL90_G0_90+@ C333 4.7U_0603_6.3V6M R495
LINE_R 1 2 LINE_C_R 24 46 DMIC_CLK_268 1 2 DMIC_CLK 2.2K_0402_5%
[34] LINE_R LINE1_R SIDE_R
KAL90_G0_90+@ C342 4.7U_0603_6.3V6M R483 @ 0_0402_5% 15mil KALH0@
18 43

2
CD_L CENTER DMIC_CLK
20
CD_R LFE
44 1 2 1 2 C321
R289 22_0402_5% 22P_0402_50V8J For EMI DMIC_DATA
19 R496 @ 0_0603_5%
CD_GND
6 HDA_BITCLK_AUDIO [20]
MIC1_L MIC1_C_L BITCLK
[34] MIC1_L 1 2 21
C327 4.7U_0603_6.3V6M MIC1_L
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
[34] MIC1_R MIC1_R SDATA_IN HDA_SDIN0 [20]
C332 4.7U_0603_6.3V6M R288 33_0402_5%
MONO_IN 12 37
PCBEEP PIN37_VREFO
29
LINE1_VREFO
[20] HDA_RST_AUDIO# 11
R313 39.2K_0402_1% RESET#
31
LINE2_VREFO
[34] HP_PLUG# 2 1 [20] HDA_SYNC_AUDIO 10
SYNC 10mil
28
R299
1
10K_0402_1%
2
[20] HDA_SDOUT_AUDIO 5
SDATA_OUT
MIC1_VREFO_L
32
MIC1_VREFO_L
Digital MIC
[34] LINEIN_PLUG# DMIC_DATA HDA_GPIO0 MIC1_VREFO_R MIC1_VREFO_R +3VS
R504 1 @ 2 0_0402_5% 2
3 R298 20K_0402_1% DMIC_CLK HDA_GPIO3 SPDIFO2 PRE-MP 3
1 2 3
GPIO0/DMIC_CLK MIC2_VREFO
30 MIC2_VREFO
2 1 R499 KAL90_G0_90+@ 0_0402_5% SENSE_A 13 10mil JP13
[34] MIC_PLUG# SENSE A CODEC_VREF
34 27 L44 1
SENSE B VREF DMIC_CLK DMIC_CLK_R 1
1 2 2
2
47 40 1 1 DMIC_DATA DMIC_DATA_R 3 5
[30] EAPD SPDIFI/EAPD JDREF 3 G1

10U_0805_10V4Z

0.1U_0402_16V4Z
4 6
4 G2

C346

C344
12 SPDIF_R 48 33 R19 0_0603_5% 2
[34] SPDIF SPDIFO SENSE C
1

20K_0402_1%

R300 0_0402_5% ACES_88266-04001

2
DMIC_DATA 1 2 4 26 2 2 C16 CONN@
GPIO1/DMIC_DATA AVSS1
R305

R497 KAL90_G0_90+@ 0_0402_5% 7 42 D2 220P_0402_50V8J

DVSS AVSS2 1
1 2 1
R498 KALH0@ 0_0402_5% ALC888S-VC_LQFP48_7x7 SM05T1G_SOT23-3
@
2

C17
DGND AGND 220P_0402_50V8J

1
2 KAL90_G0_90+@

Sense Pin Impedance Codec Signals 1 2 1 2

R314 0_0805_5% R315 0_0805_5%
39.2K PORT-A (PIN 39, 41)
1 2 1 2
20K PORT-B (PIN 21, 22) R406 0_0805_5% R444 0_0805_5%
SENSE A
10K PORT-C (PIN 23, 24) 1 2 1 2
R443 0_0805_5% R426 0_0805_5%
4 4
BOM Option
5.1K PORT-D (PIN 35, 36)
ALC268 268@
39.2K PORT-E (PIN 14, 15) ALC888S-VC 888@ GND GNDA GND GNDA

20K PORT-F (PIN 16, 17) SVID=1025 Security Classification Compal Secret Data Compal Electronics, Inc.
SENSE B
SSID=0260 Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title
10K PORT-G (PIN 43, 44) HD Audio Codec ALC888S-VC
FOR KALG1 and KALG0. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5.1K PORT-H (PIN 45, 46) B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 33 of 45
A B C D E F G H
 A B C D E

+5VAMP
W=40mil
+3VS
1 1
1
C492 C490
C491 0.1U_0402_16V4Z
C514 0.1U_0402_16V4Z 2 2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C
[33] AMP_RIGHT C505 1U_0402_6.3V4Z

15

17

25
8

7
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U24
[33] AMP_LEFT C503 C504 1U_0402_6.3V4Z

CVDD

HVDD

PVDD
PVDD

VDD
1

1
1 0.47U_0603_16V4Z 1
R458 R470

2.2K_0402_5% 2.2K_0402_5% 27 19 SPKR+

INR_A ROUT+ SPKR-
1 18

2
INL_A ROUT-
HPF Fc = 154Hz SPKL+
R460 1 2 100K_0402_5% 24 5
/AMP EN LOUT+ SPKL-
6
+5VAMP R463 1 2 100K_0402_5% 21 HP_EN
LOUT- S/PDIF Out JACK
13 HPOUT_R
+5VAMP HP_RIGHT HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L
1 2 2 28 16
[33] HP_RIGHT
HP_LEFT
C513 4.7U_0805_6.3V6K R459
HP_LEFT_C
39K_0402_5% HP_LEFT_R 2
INR_H
INL_H
HP_L LINE Out/Headphone Out
1 2 1 2 NC 3
[33] HP_LEFT
1

C489 4.7U_0805_6.3V6K R445 39K_0402_5% VOL_AMP 23 14

R461 SET NC

1
43K_0402_1%
VSS 12
1 9 1
2

C477 CP+ C478 D34

11 CP- GND 26 2 2
VOL_AMP 4 C498 C488 PJDLC05_SOT23-3
1U_0402_6.3V4Z PGND 1U_0402_6.3V4Z @
22 BIAS PGND 20
1

D 2 2 1/9 330P_0402_50V7K 330P_0402_50V7K

CGND 10
1

2 EC_MUTE 29 R453 1 1 JHP1

1 EC_MUTE [30] 1 GND
R462 G 56.2_0603_1% 1

3
100K_0402_1% C506 S Q37 C354 APA2051QBI-TRG_TQFN28_4X4 HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
3

2N7002_SOT23 2.2U_0805_10V6K L37 FBM-11-160808-700T_0603 6

2
0.01U_0402_16V7K 2 HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
2

L36 FBM-11-160808-700T_0603
R442 SPDIF_PLUG# 5
56.2_0603_1%
4
SPDIF 7
2 Gain= 10dB [33] SPDIF
+5VSPDIF 8 2

1 10
C499
100P_0402_50V8J 9
2 SINGA_2SJ-E373-T01
+5VAMP CONN@
+5VAMP
HP_PLUG#
HP_PLUG# [33]
2

R466
100K_0402_5%
2

Q40B MIC1_VREFO_L MIC1_VREFO_R

R467 5 2N7002DW-T/R7_SOT363-6 JMIC1
6 1

Q41 100K_0402_5% 8
AO3413_SOT23-3 7
4

2.2K_0402_5%
1
3

1
S
G Q40A

R468
2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6 R454 5
[33] MIC_PLUG#
2.2K_0402_5%
D R456 L39 4
1

1
3

75_0603_1% FBM-11-160808-700T_0603

2
+5VSPDIF D37
[33] MIC1_R 1 2 MIC1_R_1 1 2 MIC1_R_R 3
PJDLC05_SOT23-3 6
20mil 1 2 MIC1_L_1 1 2 MIC1_L_R 2
[33] MIC1_L
@ L38 1

2
R455 FBM-11-160808-700T_0603
75_0603_1% SINGA_2SJ-E351-S01
For ESD Protect 1 1 CONN@
1

C500 C512
3 (HDA Jack) 3

Int. Speaker Conn. 220P_0402_50V7K 2 2 220P_0402_50V7K

MIC JACK

1
D35 @
20mil PJDLC05_SOT23-3
JP14
SPKL+ 1
SPKL- 1
2
SPKR+ 2
3 5
SPKR- 3 G1
4
4 G2
6 kAL90_G0_90+@ JLINE1
ACES_88266-04001 8
3

D8 @ D7 @ CONN@ 7
C43 C42 C40 C41
SM05T1G_SOT23-3

SM05T1G_SOT23-3

1 1 1 1
220P_0402_50V8K

220P_0402_50V8K

220P_0402_50V8K

220P_0402_50V8K

LINEIN_PLUG# 5
[33] LINEIN_PLUG#
KAL90_G0_90+@
R469 L43 KAL90_G0_90+@ 4
1

@ 2 @2 @2 @ 2 75_0603_1% FBM-11-160808-700T_0603
1 2 LINE_R_1 1 2 LINE_R_R 3
[33] LINE_R
6
For ESD 1 2 LINE_L_1 1 2 LINE_L_R 2
[33] LINE_L
L40 1
R457 FBM-11-160808-700T_0603

2
75_0603_1% KAL90_G0_90+@ 1 1 SINGA_2SJ-E351-S03

220P_0402_50V7K
KAL90_G0_90+@ C501

KAL90_G0_90+@ C502
KAL90_G0_90+@ CONN@

220P_0402_50V7K
(HDA Jack)
2 2
LINE-IN JACK
4 4

1
D36 @
PJDLC05_SOT23-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KALG1-
A B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C D
Date: Friday, April 24, 2009

E
Sheet 34 of 45
 A B C D E

+5VALW

+5VALW TO +5VS +3VALW TO +3V_SB(ICH8M AUX Power)

2
Colay @
+3V R297
+5VALW +5VS +3VALW Q30 100K_0402_5%
AO3413_SOT23-3

4
U20

1
S

D
5 3 1
6 3 SYSON#
[29] SYSON#

2
10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
7 2 1 1

6
470_0603_5%
8 1 C373 C375 R162

G
1 1

2
10U_0805_10V4Z
SBPWR_EN#2 1
R316 1 Q24A
C371 C372 SI4800BDY-T1-E3_SO8 2 2 200K_0402_5% C356 SYSON 2
[28,30,41,42] SYSON

1
1 2 2 2N7002DW-T/R7_SOT363-6 1
@

1
0.1U_0603_25V7K

1
3
2 R252
100K_0402_5%
Q15B +3VALW +3V
+VSB 2 1 5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP

2
R161
200K_0402_5% 1

4
6

C238

4
U18
Q15A 0.1U_0603_25V7K 5
SUSP 2 2
2N7002DW-T/R7_SOT363-6 6 3 RTCVREF +5VALW

2
7 2 1 1
1 8 1 C347 C353 R163
1

2
C348 470_0603_5%
10U_0805_10V4Z R266 R251
SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z 100K_0402_5% 100K_0402_5%

3 1
2
10U_0805_10V4Z @

1
SUSP
+3VALW TO +3VS Q14B
SBPWR_EN#
[32,42] SUSP
2N7002DW-T/R7_SOT363-6 5

3
+3VALW +3VS
2 1 3V_GATE
+VSB

4
4

U16 R164 Q24B

6
5 200K_0402_5% 1 5
[28,30,32,41,42] SUSP#
6 3 C349 2N7002DW-T/R7_SOT363-6

2
7 2 1 1 Q14A

4
1
470_0603_5%
10U_0805_10V4Z

1 1 8 1 C330 C329 1U_0603_10V4Z R267 SBPWR_EN# 2 0.1U_0603_25V7K

2
10U_0805_10V4Z

10U_0805_10V4Z

C340 C341 R296

2N7002DW-T/R7_SOT363-6 10K_0402_5%

1
SI4800BDY-T1-E3_SO8 2 2
2 2 2 1 1 2

2
D
2 SUSP
G
S Q27
3

5VS_GATE 2N7002_SOT23

+1.5V to +1.5VS +5VALW

+1.5V +1.5VS

2
+3VS +3VALW U6
40mil width 40mil width 5 R182
6 3 1 1 100K_0402_5%

2
1 2 1 2 7 2 C185 C186
C89 0.1U_0603_25V7K C189 0.1U_0603_25V7K 1 1 8 1 R119

1
@ @ C180 C179 10U_0805_10V4Z 470_0603_5%
2 2
1U_0603_10V4Z
1 2 1 2
C459 0.1U_0603_25V7K C383 0.1U_0603_25V7K 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 SBPWR_EN#
[22] SBPWR_EN#

1
@ @ 2 2
10U_0805_10V4Z
+1.05VS

3
40mil width +1.5VS 40mil width

1
D
1 2 1 2 Q8B [30,41] SBPWR_EN 2
C173 0.1U_0603_25V7K C388 0.1U_0603_25V7K 2 1 1.5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP G
+VSB
@ @ R121 Q17 S

3
1
1 2 1 2 510K_0402_5% 1 2N7002_SOT23

4
C421 0.1U_0603_25V7K C390 0.1U_0603_25V7K C187 R183

6
@ @ 100K_0402_5%
0.1U_0603_25V7K
Q8A 2
FOR EMI

2
SUSP 2 2N7002DW-T/R7_SOT363-6
3 3

2
1
R120
H3 H2 H1 H12 H10 H5 H4 H7 2.2M_0402_1%
H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_4P2 @

1
@ @ @ @ @ @ @ @
1

1
D
2N7002_SOT23
[21,30,36,37,40] ACIN 2
G Q11
S @
3

H13 H14 H8 H6
H_4P2 H_4P2 H_4P2 H_3P7N
@
@ @ @
1

R01
+1.5VS +1.05VS +0.9VS +1.8V +1.5V

H20 H18 H25 H23 H_7P1 H16 H15 H21 H22

2

2
H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H19
@ @ @ @ @ @ @ @ @ H_3P2 R118 @ R233 @ R34 @ R165 @ R113 @
@ 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
1

1
1

1
D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
H11 H24 H9 H17 G G G G G
4 H_4P7X3P7N H_5P1X4P1N H_10P0X6P0N H_5P5X4P3N Q10 @ Q22 @ Q4 @ Q16 @ Q9 @ 4
S S S S S
3

3
@ @ @ @ 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
1

FD2 FD3 FD4 FD1

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title
@ @ @ @
DC Interface & Screw Hole
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 35 of 45
A B C D E
 5 4 3 2 1

Enlightener LED
+5VALW +5VALW KAL90_G0_90+@ KALG1@
LED10 LED11 Blue
(BLUE) (BLUE) R318 330_0402_5% R320 330_0402_5%
2

2
+5VALW 1 2 2 B 1 PW R_LED# +5VALW 1 2 2 B 1 BATT_RED_LED# BATT_RED_LED# [30]
R1 R15
499_0402_1% 1.5K_0402_5% R317 866_0402_1% R319 866_0402_1%
D +5VALW 1 2 4 A 3 PW R_SUSP_LED# +5VALW 1 2 4 A 3 BATT_Yellow Green_LED# BATT_Yellow Green_LED# [30] D
KALG1@ KALG1@
1

1
AMB
HT-297UD/CB _BLUE/AMB_0603 HT-297UD/CB _BLUE/AMB_0603
Change footprint:LED_HT-297DQ-GQ_4P
2

2
LED2 KAL90_G0_90+@ LED3 KAL90_G0_90+@
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 Compal Footprint
4 1
1

1
ACIN# ACIN# (AMB) 3 2
LED15 KALH0@ R500 KALH0@ LED16 KALH0@ R501 KALH0@
453_0402_1% 453_0402_1%
2 PW R_SUSP_LED# PW R_SUSP_LED#
UD
3 1 UD
3 1 2
ON/OFF LED DOWN
+5VALW 1 R502 KALH0@ +5VALW 1 R503 KALH0@ (BLUE)
220_0402_5% 220_0402_5%
NB
2 1 2 PW R_LED# NB
2 1 2 PW R_LED# LED8 KALG1@
HT-191NBQA_BLUE_0603

HT-210UD/NB_AMB/BLUE
(BLUE) HT-210UD/NB_AMB/BLUE PW R_LED#
+5VALW 1 2 2 1

R16 KALG1@
392_0402_1%

2 B 1
C PW R_LED#
(AMB) C
MEDIA_LED NUM_LED CAPS_LED +5VALW 1 2 4 A 3 PW R_SUSP_LED#

6
+5VS +5VS +5VS Q20A R5 KAL90_90+@
(BLUE) (BLUE) (BLUE) 2N7002DW -T/R7_SOT363-6 453_0402_1% LED12
[30] PW R_LED 2 KAL90_90+@
HT-297UD/CB _BLUE/AMB_0603

1
2

2
R259
R17 R7 KALG1@ R9 KALG1@
10K_0402_5% R6 KALG1@ 866_0402_1% 866_0402_1% 10K_0402_5%
@ 866_0402_1%

2
ON/OFF LED RIGHT
1

1
PW R_SUSP_LED#
2

3
LED5 KAL90_G0_90+@ LED6 KAL90_G0_90+@ LED7 KAL90_G0_90+@ Q20B (BLUE) LED4 KALG1@
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 2N7002DW -T/R7_SOT363-6 HT-191NBQA_BLUE_0603
[30] PW R_SUSP_LED 5
+5VALW 1 2 2 1 PW R_LED#

1
1

4
MEDIA_LED# NUM_LED# NUM_LED# [30,31] CAPS_LED# CAPS_LED# [30] R234 R4 KALG1@
604_0402_1%
10K_0402_5%
(AMB) 2 1

2
B

+5VALW 1 2 4 A 3 PW R_SUSP_LED#
B R8 KAL90_90+@ B
PW R_LED# MEDIA_LED# CAPS_LED# 453_0402_1% LED13
KAL90_90+@
PW R_SUSP_LED# NUM_LED# ACIN# HT-297UD/CB _BLUE/AMB_0603
3

D4 D5 D3
FOR EMI
ON/OFF LED LEFT
@
1

PJMBZ6V8_3P_C/A_SOT-23 PJMBZ6V8_3P_C/A_SOT-23 PJMBZ6V8_3P_C/A_SOT-23 PW R_SUSP_LED# C307 1 2 100P_0402_50V8J

KAL90_G0_90+@ KAL90_G0_90+@ @ (BLUE) LED1 KALG1@
PW R_LED# C292 1 2 100P_0402_50V8J HT-191NBQA_BLUE_0603

+5VALW 1 2 2 1 PW R_LED#

R3 KALG1@
392_0402_1%

@ (AMB) 2 B 1
NUM_LED# C3 1 2 100P_0402_50V8J
@
CAPS_LED# C4 1 2 100P_0402_50V8J +5VALW 1 2 4 A 3 PW R_SUSP_LED#
+3VS @
MEDIA_LED# C2 1 2 100P_0402_50V8J R2 KAL90_90+@
Q35A ACIN# 453_0402_1% LED14
2

2N7002DW -T/R7_SOT363-6 KAL90_90+@

A
HT-297UD/CB _BLUE/AMB_0603 A
D
1

[25] 5IN1_LED# 1 6
Q21 2 ACIN [21,30,35,37,40]
SATA_LED# 4 3 MEDIA_LED# KAL90_G0_90+@ G
[20] SATA_LED# MEDIA_LED# [31]
2N7002_SOT23 S
3

Q35B
Security Classification Compal Secret Data Compal Electronics, Inc.
5

+3VS 2N7002DW -T/R7_SOT363-6

Issued Date 2008/11/10 Deciphered Date 2008/11/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 36 of 45
5 4 3 2 1
 A B C D

DC231000500
@
SINGA_2DC-G756I200 PL1
SMB3025500YA_2P
VIN PR1
DC_IN_S1 1 2DC_IN_S2 1M_0402_1%
1
1 2
VIN VIN
G 2 VS
G

1
3 PC2
PC3 PC4 100P_0402_50V8J PC1 @ PR2 PR3
PJP3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 10K_0402_5% 84.5K_0402_1%

2
1 1

PR209 PR5

8
PR4 10K_0402_1% 22K_0402_5%

2
0_0402_5% 3 1 2

P
+
1 2 1 2 1 0
[21,30,35,36,40] ACIN

20K_0402_1%
- 2

1
PR6
PU1A

1
PC6
LM358DT_SO8 PC5

0.1U_0603_25V7K
4
PR7 PD3 1000P_0402_50V7K

2
10K_0402_1% GLZ4.3B_LL34-2

2
2

2
PR123
1 2 PR8
10K_0402_1%
1 2
0_0603_5% RTCVREF
@
PQ25 MCVCC PQ28
@ SI2301BDS-T1-E3_SOT23-3 @ SI2301BDS-T1-E3_SOT23-3
+3VALWP

S
1
S

3 3

D
1 RTCVREF
D

Vin Dectector

G
G
2

2
1

1
PR102 PR122
Min. Typ Max.
@ 200K_0402_1% @ 200K_0402_1% H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V
2

2
2 2

1
D
2
G PQ46
PQ45 S @ 2N7002W -T/R7_SOT323-3 RTC Conn

3
1

D @ 2N7002W -T/R7_SOT323-3
2
G SPOK [38,39]
S
+ -
3

+RTCBATT @
PBJ1

+RTCBATT 1 2

ML1220T13RE

VIN
OTIS
2

PJ2 PJ3
PD4 2 1 2 1
LL4148_LL34-2 +3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V
3
@ JUMP_43X118 @ JUMP_43X79 3

PD5
1

LL4148_LL34-2
BATT+ 2 1
1

PR9 PR10 PJ4 PJ5

PQ1 68_1206_5% 68_1206_5% 2 1 2 1
TP0610K-T1-E3_SOT23-3 +5VALWP 2 1 +5VALW +0.9VSP 2 1 +0.9VS
PR11 @ JUMP_43X118 @ JUMP_43X79
2

200_0603_5%
CHGRTCP 1 2 N1 3 1
VS
PJ6
1

PJ7
1

PR12 PC8 2 1 +1.8VP 2 1 +1.8V

100K_0402_1% PC7 0.1U_0603_25V7K +VSBP 2 1 +VSB 2 1
0.22U_0603_25V7K @ JUMP_43X39 @ JUMP_43X118
2

PR13
2

22K_0402_1%
1 2
[32] 51ON#
PJ8 PJ17
+1.05VSP 2 2 1 1 +1.05VS +1.8VP 2 2 1 1 +1.8V
@ JUMP_43X118 @ JUMP_43X118
RTCVREF
1

PR14
PU2 200_0603_5% PJ16
PR15 PR16 G920AT24U_SOT89-3 2 1
560_0603_5% 560_0603_5% 3.3V +1.05VSP 2 1 +1.05VS
2

1 2 1 2 3 2 N2 @ JUMP_43X118
OUT IN
4
+CHGRTC 4
1

GND PC10
PC9 1U_0805_25V4Z
10U_0805_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR & RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 37 of 45
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
VMB

2
PL2 PR17

1
1 1

PJP2 SMB3025500YA_2P 47K_0402_1%

1 1 BATT_S1 1 2 BATT+ PH1 PC11
MAINPW ON [20,39]
2 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
2 47K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR19 PQ2
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 13.7K_0402_1% DTC115EUA_SC70-3

2
6 PD6
7 1 2 3

P
7 +
O 1 2 1 2
SUYIN_250133MR007G115ZL TM_REF1 2 -

G
PU3A LL4148_LL34-2
@ LM393DG_SO8

3
2

0.22U_0603_16V7K
PR20 PR21
100_0402_1% 100_0402_1%

15.4K_0402_1%
1

1
PC14
PR23

PR22
100K_0402_1%

1000P_0402_50V7K
1

2 1 VL

1
PR24

PC15
6.49K_0402_1%

2
2 1 +3VALW P

1
1

PR25
PR26 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP [30]

EC_SMB_CK1 [30,31] PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
EC_SMB_DA1 [30,31]
Recovery at 47 degree C
VL

2
@ PR27
VL 47K_0402_1%
@ PR28
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0603_1%_TH11-4H104FT VL

B+ 3 1 +VSBP

2
0.22U_1206_25V7K

@ PR30
0.1U_0603_25V7K
1

8
13.7K_0402_1% @ PD7
1

1
PC16

PC17

PR29 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
1
3 3

PR31 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18 @ PR32
0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR33
100K_0402_1%

PR34
1

0_0402_5% PQ4 D
1 2 2
[37,39] SPOK G 2N7002W -T/R7_SOT323-3
0.1U_0402_16V7K

S <BOM Structure>
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
BATTERY CONN / OTP

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 38 of 45
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
@
PR35
PJ10 0_0805_5%
2 1 1 2
D
B+ 2 1
D
JUMP_43X118

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

1
2200P_0402_50V7K

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22
1

8
7
6
5

1
PC25
VL

2
@ PC92

PC41

PC23

PC24
1U_0603_10V6K
2

2
PQ6
2

2
2
@ PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K 4

4.7U_0603_6.3V6M
1
PC27
4

PC28
1
+5VALWP

3
2
1
PL4

1
2
3
PL3 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5
DH3 DH5

PR39
26 UGATE2 UGATE1 15
PR36 PR37 PR40 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
1

AO4712_SO8 2.2_0603_5%

63.4K_0402_1%
1

2
2

2
PR38 PC32 4

2
PC30 + PC31 0.1U_0603_25V7K

PR41
0_0402_5% 4

2
0.1U_0603_25V7K

680P_0402_50V7K
1

1
1
330U_6.3V_M LX3 25 16 LX5 1 PRE-MP
2

2 PC33 PHASE2 PHASE1

PC34
3
2
1

2
C 680P_0402_50V7K + C

1
2
3
DL3 23 18 DL5 PC35

1
LGATE2 LGATE1 150U_D2E_6.3VM_R18
2
2

10K_0402_1%
PGND 22

2
FB3 30
@ PR42 OUT2

PR43
10K_0402_1% 10
OUT1
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN
+3.3VALWP Ipeak=8.444A ; Imax=5.91A @ PR44 0_0402_5%
29 2 1 VL
Choke DCRmax=60m ohm, DCRtyp=54m ohm SKIP
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR45 0_0402_5%
Vlimit=(5E-06 * 330K)/10=165mV 1 2
20 NC POK2 28
Ilimit=165mV/18m ~ 165mV/15m PD8 PR46
=9.167A ~ 11A GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK [37,38]
Iocp=Ilimit+Delta I/2 VS EN_LDO POK1 PR48
2

=10.134A ~ 11.967A 330K_0402_1%

200K_0402_5%

B ILM1 B
PR47

14 12 2 1
Delta I=1.934A (Freq=300KHz) PC37 EN1 ILIM1
0.22U_0603_25V7K
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2
1

NC
2

PD12 PR49
0_0402_5%

1SS355_SOD323-2 VL @ PR50
2
PU4 330K_0402_1%

21
0_0402_5% ISL6237IRZ-T_QFN32_5X5
PR51
2
2

PR52
1

1
806K_0603_1%
1U_0603_10V6K
1

PR54 @ PR55 PR53

+5VALWP Ipeak=8.444A ; Imax=5.91A
2VREF_ISL6237
1

2
0_0402_5% 47K_0402_5% 0_0402_5%
PC143

2 1 1 2 Choke DCRmax=60m ohm, DCRtyp=54m ohm

2
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0402_16V7-K

2VREF_ISL6237

[20,38] MAINPWON
Vlimit=(5E-06 * 330K)/10=165mV
1

PC38

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
1

@ PC39 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)
A 2 PQ35 A
TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 39 of 45
5 4 3 2 1
 A B C D

PQ9 PQ10 B+
AO4407A_SO8 AO4407A_SO8
VIN 8 1 1 8
7 2 2 7 PJ11 @
6 3 3 6 2 PR56
1 2 1 CHG_B+
2 1

1
5 5 0.015_1206_1%

2
JUMP_43X118 PR57

2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
PR58 CHGEN# PC40 100K_0402_1%

2
3.3_1210_5% 0.01U_0402_25V7K

0.01U_0402_25V7K

1
PC42

PC43

PC44
100K_0402_1%

2
1
PC46 PC48

1
2

5
6
7
8

3
2
1
1 1

PC45

PR59
0.1U_0402_16V7K PU5 0.1U_0603_25V7K
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC

1
AO4407A_SO8

1
PR174 PR61 /BATDRV 4

2
3.3_1210_5% PC47 @PC49
@PC49 0_0603_5% PQ11
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR60
340K_0402_1% PD13 ACN 2 26 DH_CHG
ACN HIDRV
1

RLZ24B_LL34 PR912 ACP 3

3
2
1

5
6
7
8
PC50 @ 0_0805_5% ACP

1
2.2U_0805_25V6K 2 1 1 2 ACDRV 4 25 LX_CHG PL5
2

ACDET ACDRV PH PD10 10UH_PCMB104T-100MS_6A_20% PR62 0.02_1206_1%

PRE-MP
5 ACDET
2 1 1 2 1 2 1 4
BATT+
Place close to back to back MOS

10U_1206_25V6M
1
LL4148_LL34-2 PC51

10U_1206_25V6M
REGN
2 3

2
0.1U_0603_25V7K @ PR64 <BOM Structure>

5
6
7
8

PC53
24751_VREF PR63 4.7_1206_5%

PC52
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6
ACDRV ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ13
@ PR65 1U_0603_10V6K 4 AO4466_SO8

@
47K_0402_1% PR66 PC56 PC55
P C55

2
2

0_0402_5% 0.47U_0603_16V7K 680P_0402_50V7K

1 2 1 2 7
1

2
PR67 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
@ PQ14 OVPSET 8 PC57
OVPSET
1

2 D 2N7002W -T/R7_SOT323-3 0.1U_0402_16V7K 2

2 3S/4S# [30] 1 2
G 9 21 ACOFF [30]
AGND LEARN
2

S
3

1
PR68
54.9K_0402_1% PC58 @PC59
@PC59
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
CELLS
1

24751_VREF 10
PQ15 VREF
3

1
SI2301BDS-T1-E3_SOT23-3
PC60
PR69 1U_0603_10V6K 19 SE_CHG+

2
SRP
100K_0402_1% RTCVREF
CP Point Setting 1 2PQ15_GATE
2 11 VDAC SRN 18 SE_CHG-
1

CP point=Iadapter*85% BAT 17
1

PR70

1
65W adapter PC62 100K_0402_1% VADJ 12
0.1U_0603_25V7K VADJ PC61
2

Vacset=3.3*(49.9K/(49.9K+64.9K))=1.434V ACSET 0.1U_0603_25V7K

2

2
TP 29 Icharge Setting
CP POINT=(1.434V/3.3V)*(0.1/0.015)=2.896A ACGOOD# 13 ACGOOD ICHG setting PR71 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
17.4K_0402_1% For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
VMB 16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
/BATDRV 14
SRSET IREF [30] IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
BATDRV

1
PR72
IREF=0.7748*Icharge

1
10_0603_5% PR73
1

15 1 2 100K_0402_1% @PC63
@PC63
IADAPT 0.01U_0402_25V7K

2
VS PR74 BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V

2
3 3

LI-4S :18.0V----BATT-OVP=2.001V 340K_0402_1%

1
Input UVP : 17.26V
2

2
BATT-OVP=0.1112*VMB PC64
0.01U_0402_25V7K

Fsw : 300KHz 100P_0402_50V8J @ PR75

2
LI-3S :13.5V----BATT-OVP=1.5012V 100K_0402_1%
1

PC65

24751_VREF 24751_VREF ADP_I [30] @ PR176

1

BATT-OVP=0.1112*VMB 0_0402_5% 24751_VREF

1
PR76
200K_0402_1%
1 2
2

1
Per cell=4.5V 499K_0402_1%
100K_0402_1%

ACIN [21,30,35,36,37]
1

1
PR180

PQ15_GATE

1
D
PR179

PR78
2
8

PR77 PU1B 887K_0402_1% ACGOOD# 2 @ PQ16

1
10K_0402_1% LM358DT_SO8 PQ36 D PQ17 G 2N7002W -T/R7_SOT323-3
5
P

+ SI2301BDS-T1-E3_SOT23-3 PR80
1 2 7 0 2 S
2

3
[30] BATT_OVP 6 PC163 G 2N7002W -T/R7_SOT323-3 0_0402_5%
-
G

S
0.1U_0402_16V7K PQ37 REGN 3 VADJ

D
S 1 1 2
3
1

ACOFF 1 24751_VREF
2 2
0.01U_0402_25V7K
4

PR79 G 2N7002W -T/R7_SOT323-3

1
PC66

105K_0402_1%

G
S
3

2
1

2
PR82
340K_0402_1%

221K_0402_1%
2

1
PR181

100K_0402_1% PC144 PR81

2

PR84
@ PR177 1000P_0402_50V7K 100K_0402_1%

2
PR83 4.3K_0402_5%

2
64.9K_0402_1%
2

1
24751_VREF 1 2 ACSET CHGEN#

2
1
PQ19 D
1

1
PQ18 D
2
[30] CALIBRATE# G 2N7002W -T/R7_SOT323-3 [30] FSTCHG 2
@ PR85 S <BOM Structure> G 2N7002W -T/R7_SOT323-3

3
100K_0402_1% S <BOM Structure>

3
1

4 4
2

PR86
49.9K_0402_1%
1

PQ20 D

[30] 65W /90W # 2 Charger ADJ Calibrate# PR78 PR84

2

G 2N7002W -T/R7_SOT323-3
S @
3

4.0V L @ @ Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
4.1V L 887K 221K CHARGER

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 40 of 45
A B C D
 A B C D

Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A

PJ9
1.05V_IN 2 1 B+
2 1
@ JUMP_43X118

5
6
7
8

10U_1206_25V6M
1
PC534
PR525

2
1 1
OTIS 300K_0402_5% 4
1.05V_TON 1 2 PQ507
PR526 PR527 AO4466_SO8
PC535
0_0402_5% 0_0603_5%
1 2 1.05V_EN BST_1.05V 1 2BST_1.05V-1
1 2
[28,30,32,35,42] SUSP#

3
2
1
1
0.1U_0603_25V7K

1
PR910 PL502

15

14
1
30K_0402_5% PC536 1UH_PCMC063T-1R0MN_11A_20%
0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.05VSP

2
@

1
UG_1.05V

4.7_1206_5%
2 TON DRVH 13

PR528
PR529 3 12 SW _1.05V
VOUT LL

5
6
7
8
422_0603_1% PQ508

10U_0805_6.3V6M
330U_D2E_2.5VM
1
+5VS 1 2 1.05V_V5FILT 4 11 1.05V_TRIP
1 2 +5VS

1.05V_SNB2
V5FILT TRIP

1
+

PC537

PC538
PR530
1.05V_FB 5 10 5.9K_0402_1%
VFB V5DRV

2
1
@ PR178 LG_1.05V 2
6 PGOOD DRVL 9 4

PGND
0_0402_5% PC539

GND

1
1 2 1.05V_EN 1U_0603_10V6K PC540

2
[30,35] SBPWR_EN

1
@ 47P_0402_50V8J PC541

680P_0603_50V7K
4.7U_0805_10V6K

PC542
1 2

3
2
1
PU503

2
TPS51117RGYR_QFN14_3.5x3.5
AO4456_SO8
PR531
13.7K_0402_1%
@ PR112 1 2
0_0402_5%

1
2 2
1 2
[32] VS_ON OTIS
VFB=0.75V
PR532
33.2K_0402_1%

2
PJ12
1.8V_IN 2 1 B+
2 1
@ JUMP_43X118

5
6
7
8

10U_1206_25V6M
1
PC501
PR501

2
300K_0402_5% 4
1.8V_TON 1 2 PQ501
PR518 PR519 AO4466_SO8
PC525
0_0402_5% 0_0603_5%
1 2 1.8V_EN BST_1.8V 1 2BST_1.8V-1
1 2
[28,30,35,42] SYSON

3
2
1
1

0.1U_0603_25V7K
1

PR911 PL501

15

14
1
30K_0402_5% PC526 1UH_PCMC063T-1R0MN_11A_20%
@0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.8VP
2
2

1
UG_1.8V

4.7_1206_5%
2 TON DRVH 13

PR520
PR521 SW _1.8V

330U_D2E_2.5VM
3 VOUT LL 12

5
6
7
8
422_0603_1%

10U_0805_6.3V6M
1
+5VALW 1 2 1.8V_V5FILT 4 11 1.8V_TRIP
1 2 +5VALW

1.8V_SNB 2
V5FILT TRIP

1
+

PC527

PC528
3
PR522 3
1.8V_FB 5 10 5.9K_0402_1%
VFB V5DRV

2
1

LG_1.8V 2
6 PGOOD DRVL 9 4

PGND
PC529
GND

1U_0603_10V6K PC530
2

1
@ 47P_0402_50V8J

680P_0603_50V7K
PC532
1 2 PC531
7

3
2
1
PU501 4.7U_0805_10V6K

2
TPS51117RGYR_QFN14_3.5x3.5 PQ506

PR523 AO4456_SO8
10K_0402_1%
1 2
1

PR524
7.15K_0402_1% VFB=0.75V
2

Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP / 1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 41 of 45
A B C D
 5 4 3 2 1

PJ13
1.5V_IN 2 1 B+
2 1
@ JUMP_43X118

5
6
7
8

10U_1206_25V6M
D D

1
PR540
0_0402_5%

PC502
1 2 PR502
[28,30,35,41] SYSON

2
300K_0402_5% 4
1.5V_TON 1 2 PQ502
OTIS PR534 AO4466_SO8
PC533
@ PR533 0_0603_5%
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2
[28,30,32,35,41] SUSP#

3
2
1
1
0_0402_5% 0.1U_0603_25V7K

1
PR913 PL503

15

14
1
30K_0402_5% PC548 1UH_PCMC063T-1R0MN_11A_20%
@0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.5VP

2
2

1
UG_1.5V OTIS

4.7_1206_5%
2 TON DRVH 13

PR537
PR536 SW _1.5V

330U_D2E_2.5VM
3 VOUT LL 12

5
6
7
8
422_0603_1%

10U_0805_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW

1.5V_SNB 2
V5FILT TRIP

1
+

PC547

PC546
PR539
1.5V_FB 5 10 5.9K_0402_1%
VFB V5DRV

2
1

LG_1.5V 2
6 PGOOD DRVL 9 4

PGND
PC544

GND
1U_0603_10V6K PC549
2

1
@ 47P_0402_50V8J

680P_0603_50V7K
PC543
1 2 PC545

3
2
1
PU502 4.7U_0805_10V6K

2
TPS51117RGYR_QFN14_3.5x3.5 PQ509

PR535 AO4456_SO8
C 22.1K_0402_1% C

1 2
1

PR538
22.1K_0402_1% VFB=0.75V
2

Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A

B
+1.8V B
1

@ PJ14
1

JUMP_43X79
2

PU8
2

1 VIN VCNTL 6 +3VALW

2 GND NC 5
2

1
1

PC99 3 7 PC100
4.7U_0603_6.3V6M PR118 REFEN NC 1U_0402_6.3V6K
1

1K_0402_1% 4 8
VOUT NC
9
2

GND
RT9173DPSP_SO8
PR119
0.1U_0402_16V7K

+0.9VSP
1

0_0402_5% PQ27 D

[32,35] SUSP
PC101

1 2 2 PR120
1

G 2N7002W -T/R7_SOT323-3
2
1

S <BOM Structure> PC104

3

PC103 1K_0402_1% 10U_0805_6.3V6M

2

0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VP/+0.75VSP

WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 42 of 45
5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_VID6 [5] CPU_B+

2
CPU_VID5 [5] PR125 PL9
1_0603_5% FBMA-L18-453215-900LMA90T_1812
CPU_VID4 [5] 2 1
[30,32] VR_ON

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
CPU_VID3 [5]
PR126

1000P_0603_50V7K
1

1
PC112

PC113
D
499_0402_1% CPU_VID2 [5] D

1
+

PC114
[8,21] PM_DPRSLPVR 1 2 PC110 PC115
220U_25V_M

PC116
CPU_VID1 [5] PC109 2.2U_0603_6.3V6K

2
5
PR127 0_0402_5% 0.022U_0402_16V7K

2
2
[5,8,20] H_DPRSTP# 1 2 CPU_VID0 [5]
PR128 0_0402_5% PR107
1 2 0_0603_5% PQ29

1
[16] CLK_ENABLE#

PR130 0_0402_5%

PR131 0_0402_5%

PR132 0_0402_5%

PR133 0_0402_5%
PR129 0_0402_5%

PR135 0_0402_5%

PR136 0_0402_5%

PR137 0_0402_5%
UGATE_CPU1 2 1 U_CPU1 4 SI7686DP-T1-E3_SO8
PR134 0_0402_5%
+3VS 1 2
+3VS

3
2
1
1
PR138 PC119 PL10

1U_0402_6.3V6K
PC118
2.2_0603_5% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%

1.91K_0402_1%
+CPU_CORE
1
BOOT_CPU1 1 2 1 2 PHASE_CPU1 1 4

2
2

PR140

5
6
7
8

5
6
7
8

1
PR139

6.8_1206_5%
2 3

1
PR142

10K_0402_1%
499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37

1
PR144
3.65K_0805_1%
2

PR143
PQ30 PR145

GND

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1

AO4456_SO8 @ PR146 1_0402_5%

1 2
PQ31 0_0603_5%

680P_0402_50V7K
1 36 4 4

2
[8,16,21] VGATE PGOOD BOOT1 AO4456_SO8 1 2

2
PC120
[5] PSI# PR147
1 20_0402_5% 2 35 UGATE_CPU1
PSI# UGATE1 VSUM 1 2

2
[30] PGD_IN 1@ PR148 2 3 34 PHASE_CPU1

3
2
1

3
2
1
PMON PHASE1

LGATE_CPU1

LGATE_CPU1
PC121
0_0402_5% 1 PR149
2 147K_0402_1% 4 33 0.22U_0603_10V7K VCC_PRM
RBIAS PGND1 ISEN1
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
5
C C

1000P_0603_50V7K
6 NTC PVCC 31

1
PC122

PC123
7 PU10 30 LGATE_CPU2
SOFT LGATE2

PC124

PC117
ISL6266AHRZ-T_QFN48_7X7 PR121
PC125 8 29 0_0603_5%

2
OCSET PGND2
0.022U_0603_25V7K 2 1 U_CPU2-1 4
1 2 9 28 PHASE_CPU2
VW PHASE2 PQ32
PR151 13K_0402_1% 10 27 UGATE_CPU2-1 PL11
COMP UGATE2 SI7686DP-T1-E3_SO8 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR152
1 2

5
6
7
8

5
6
7
8

1
DROOP

PC126 1000P_0402_50V7K 2.2_0603_5% PC127

6.8_1206_5%
12 FB2 NC 25 2 3
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR154
PR153 6.81K_0402_1% 0.22U_0603_10V7K PQ34

3.65K_0805_1%
GND

VDD
RTN

DFB

1
VIN
VO

10K_0402_1%
1 2 AO4456_SO8

PR157

PR155
PQ33
1 2 AO4456_SO8 PR156
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4 4 1_0402_5%
PC128 1000P_0402_50V7K @ PR159

2
PC129
ISEN1 0_0603_5%

680P_0402_50V7K
ISEN2 1 2

2
2

0_0402_5%

1K_0402_1%

PR160 97.6K_0402_1% PC130 470P_0402_50V7K 1 2 +5VS

3
2
1

3
2
1
1
@ PR161

1 2 2 1 PR158 1_0603_5% VSUM

1
PR162

1 2
PC133 220P_0402_50V7K PC131
1 2 1U_0402_6.3V6K PC132
1

LGATE_CPU2

LGATE_CPU2
0.22U_0603_10V7K
2

VCC_PRM
PR163 PR164 ISEN2
255_0402_1% PC134 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

1 2 PC135
PR165 1K_0402_1% 0.1U_0603_25V7K
PR166
2

0_0402_5% PC136 820P_0402_50V7K

[5] VCCSENSE 1 2 1 2
VSUM
1

PR167
1

20_0402_5% @PC137
@PC137 PC138
+CPU_CORE 1 2 0.022U_0603_50V7K 0.01U_0603_50V7K PR168
2

PR169 2.61K_0402_1%
2

0_0402_5%
[5] VSSSENSE 1 2
2
1

PC139 180P_0402_50V8J
11K_0402_1%
2

PR171

1 2
2

PR170
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR172 1K_0402_1% PR173 3.83K +-1% 0402

1

VCC_PRM
PC140
0.1U_0402_16V7K
1 2

2 1
2

PC141 0.22U_0402_6.3V6K
PC142
A 0.22U_0603_10V7K A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 43 of 45
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D

C 8 C

10

11

12

13

14

15
B B

16

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/28 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1-
Date: Friday, April 24, 2009 Sheet 45 of 45
5 4 3 2 1
 5 4 3 2 1

PCB
ZZZ

LA-5272P MB Rev0: DA60000DW00

D D
PCB 08Y LA-5271P REV1 M/B

North Bridge

U21

GL40 GL40: SA00002Q8N0

S IC AC82GL40 SLGGM A1 FCBGA1329 GL ABO

GL40@

MEDIA_LED NUM_LED CAPS_LED PROJECT ID (KALG1_H0+)

1 2
R146 10K_0402_5% KALH0@
2

1 2
R380 10K_0402_5% KALH0@
C R6 R7 R9 1 2 C
453_0402_1% 150_0402_1% 150_0402_1% R399 10K_0402_5% KALH0@
KAL90_90+@ KAL90_90+@ KAL90_90+@
1

PROJECT ID (KALG1_90+)
1 2
R156 10K_0402_5% KAL90_90+@
1 2
R380 10K_0402_5% KAL90_90+@
ON/OFF LED Risiter 1 2
R399 10K_0402_5% KAL90_90+@

LEFT RIGHT DOWN

2

R3 R4 R16
220_0402_5% 220_0402_5% 220_0402_5%
KAL90_90+@ KAL90_90+@ KAL90_90+@
1

Enlightener LED
2

R1 R15
300_0402_5% 300_0402_5%
KAL90_90+@ KAL90_90+@
Page 36
1

B B

LED11 LED11
KAL90_90+@ KALH0@

2 YG 1 2 YG 1

4 A 3 4 A 3

HT-297DQ-GQ_AMB-YG HT-297DQ-GQ_AMB-YG

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/08/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Option Component
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KALG1
Date: Friday, April 24, 2009 Sheet 46 of 46
5 4 3 2 1