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Little Panda Academy ZYNQ Teaching Documentation

Using the clock IP core

------ Based on ZYNQ MINI development board

Writers: Teacher Yang, Teacher Wu

Date of writing final draft: 2022.10.12

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Table of contents

1. Document Implementation Function Introduction................................... ................................................... ..................................3

2. ZYNQ project establishment............ ................................................... ................................................... .............. 3 3.

Clock module IP calling and realization................... ................................................... ................................................3

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1. Document Implementation Function Introduction

This document implements creating a new FPGA development project under VIVADO, and then calling the clock phase-locked loop IP through the input 50M

The clock generates a clock source of 100M or even higher. While learning the use of the 7 series always phase-locked loop IP, learn how to use it under VIVADO

Call the IP core. Achievement effect: PLL clock output, and finally drive the water lamp module. For the method of creating a new project, please refer to the document "Development Software

Software Installation and Introduction/Introduction to VIVADO and New ZYNQ Project Tutorial under the Software".

2. ZYNQ project establishment

Start page (or file->Project->New) Create a new project (CreateNewProject)

Wizard start page Click Next->

ProjectName (project name) Project name: fpga_04_pll_clock

Project path: (choose by yourself, try not to have a Chinese path)

Check CreateProjectSubdirectory, click Next->

AddSource (add design source file) Click Next->

AddExsixtingIP (add existing IP) Click Next->

AddConstraints (add existing constraint files) Click Next->

DefaultPart (default configuration, chip selection) Family->Zynq-7000

Package->clg400

Speed->7010 selection-1,7020

selection-2 7010 version selection target device:

xc7z010clg400-1 7020 version selection target device: xc7z020clg400-2

Click Next->

NewProjectSummary (new project overview) Confirm project information, type selection, etc., click Finish to complete

3. Clock module IP call and implementation

ÿ Click Add Sources in the project management bar to add a new file: pll_clock_top.v, module name pll_clock_top, after the addition is

completed, click IP Catalog under PROJECT MANAGER in the project management bar:

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Call the IP core. We adjust the window layout and maximize the newly pop-up IP Catalog window. When

using VIVADO, readers should familiarize themselves with the software interface. In many cases, the interface

layout, toolbar, and function navigation interface are somewhat different from the traditional ones. What's novel, just

use it more. We enter clock in the IP Catalog, find the clocking wizard on the pull-down interface and double-click it

to open the IP configuration interface:

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Modify the configuration to be consistent with the following figure:

The output clock configuration is as follows, only output one clock, 100M frequency:

Pull down the interface on the right, set the reset signal as low effective at the bottom, and finally click OK to complete the configuration:

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A dialog box pops up, click OK:

Finally, generate the output file dialog box, we click Generate

When we go back to the Sources interface, we can see that the IP core of clk_wiz_0 has been added to Design Sources. Click the arrow of

the IP core on the left to open the architecture of the IP.

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Click OK in the pop-up dialog box:

A top-level .v file of a clock module appears under the IP core of Design Sources under Sources. we double click

Open it, you can see the name of the module and the interface signal. We instantiate this clock module into pll_clock_top.v.

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Finally, the entire pll_top_top.v file code is as follows:

module pll_clock_top(
output reg [3:0] led, // LED4 --- LED1, 1 on, 0 off input
clk, // FPGA PLreset
clock,input
pin 50 MHz input rst_n // FPGA

);

reg [31:0] cnt;

reg [1:0] led_on_number;

wire clk_out1;
parameter CLOCK_FREQ =100000000;
parameter COUNTER_MAX_CNT=CLOCK_FREQ/2-1;//change time 0.5s

//clock pll inst

clk_wiz_0 clk_wiz_0_inst

( .clk_out1(clk_out1), .resetn(rst_n), .locked(), .clk_in1(clk) );

always @(posedge clk_out1, negedge rst_n) begin if(!rst_n) begin
cnt <= 32'd0;

led_on_number <= 2'd0; end

else begin
cnt <= cnt + 1'b1;

if(cnt == COUNTER_MAX_CNT) begin//ÿÿ0.5s cnt <=

32'd0;

led_on_number <= led_on_number + 1'b1; end

end
end

always @(led_on_number) begin

case(led_on_number) 0: led <=
4'b0001;
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1: led <= 4'b0010; 2:

led <= 4'b0100; 3: led
<= 4'b1000;
endcase
end
endmodule

Synthesize first, then bind pins, and save the pin constraint file name pll_test_top. Finally, the comprehensive layout and routing generates

a bit file, which we download to the board. We can see that the running water lamp is twice as fast as our previous experiment. Because our clock is

multiplied at 100M speed, while the clock of the running water lamp used the external crystal oscillator directly, and the speed was 50M.