22m1145 Vlsidesign 2

VLSI design
Assignment 2
Roll no : 22M1145
Question 1 :
Q–1 Simulate a 2 input XOR gate implemented in CPL logic style.
Load the final XOR and XNOR outputs with load capacitances of
100+nn fF, where nn are the last two digits of your roll number.
a) For this part, do not use the leakage reducing pMOS feedback in
your circuit. Plot the voltages at the output of the switch matrix and
the final XOR and XNOR outputs using transient analysis to show
functionality of the gate. Also, plot the current drawn from VDD and
evaluate its average over the simulation period. Explain the wave
forms seen.
b) Now add minimum sized pMOS transistors as the leakage
reduction feedback. Observe and explain the voltage and current
waveforms.
c) Next, add an additional 2 ns to the initial wait time for the wave
forms for Abar and Bbar, keeping everything else the same as in the
part above. (This describes the non-ideal case where signals and
their complements are not strictly simultaneous). Re-simulate the
circuit and describe what you observe.
d) To see the pseudo nMOS effect when feedback is used, use an
exaggerated width for the feedback pMOS (say 4 times the minimum
width) and see what happens. (Don’t put the extra delay for Abar
and Bbar for this part).
Answer 1(a) :
Code :
* Switch Matrix
.subckt swmat In1 In2 In3 In4 con conbar Out1 Out2
MN1 In1 con Out1 0 cmosn
+ L=0.18U W=0.24U AD = 86.4fF AS = 86.4fF PD = 1.2U PS = 1.2U
MN2 In2 conbar Out1 0 cmosn
* Device under test
* Loads representing wiring capacitance
C1 Out1 0 50fF
C2 Out2 0 50fF
.ends
x1 B Bbar Bbar B A Abar Out_1 Out_2 swmat
* Unit Inverter
* This subcircuit defines a CMOS inverter with equal n and p widths
MP1 Output1 Out_1 Supply Supply cmosp
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
MN5 Output1 Out_1 0 0 cmosn
+ L=0.18U W=0.445U AD = 0.1602P AS = 0.1602P PD = 1.610U PS =
1.610U
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
vdd Supply 0 dc 1.8
* Load Capacitor
C3 Output1 0 145fF
C4 Output2 0 145fF
.include models-180nm
.param Trep1= 40n
.param Trep2 = {Trep1/2.0}
.param Trf = {Trep1/20.0}
.param Tw1 = {Trep1/2.0 - Trf}
.param hival=1.6
.param loval=0.2
V1 A 0 DC 0 PULSE({loval} {hival} {Tw1} {Trf} {Trf} {Tw1} {Trep1})
V2 Abar 0 DC 0 PULSE({hival} {loval} {Tw1} {Trf} {Trf} {Tw1} {Trep1})
V3 B 0 DC 0 PULSE({loval} {hival} {Tw2} {Trf} {Trf} {Tw2} {Trep2})
V4 Bbar 0 DC 0 PULSE({hival} {loval} {Tw2} {Trf} {Trf} {Tw2} {Trep2})
.tran 1pS {3*Trep1} 0nS
.control
run
*plot V(A)+2 V(Abar)+2 V(B) V(Bbar)
plot V(A)+10 V(B)+8 V(Out_1)+6 V(Out_2)+4 V(Output1)+2
V(Output2)
plot i(Vdd)
meas tran iavg AVG i(Vdd) from=0 to=3*Trep1
.endc
1 ) waveform for output voltages with respect to input voltage

2 ) wavefrom for current
Observation :
-> In the waveforms got in the above , for the different A and B
values we got output waveforms at CPL gate .
-> but at the transition periods at A and B waveforms , we got gliches
in the output of CPL gates.
-> because at the time ,both inputs are at the same level voltage
value.
->In the waveforms of the outputs of the CMOS inverters , the fall
time of the outputs are larger compared to rise time.
-> this is because of the leakage current through the pmos in the
CMOS inverters .
->for the current ‘Id’ through Vdd , we got -ve sign . because we are
taking current into the Vdd in PMOS.
-> we got peaks in current at 10ns ,30ns ,50ns and so on.
-> this is because of at every interval we gave above , the PMOS in
the inverter is changes from ‘OFF’ to ‘ON’ ,it draws large current
from Vdd to capacitor at output for very small interval. After the
small interval capacitor is fully charged.
-> average value of Id = -5.4926e-05 from t=0e-07 to 1.2e-07
Result :
-> so, we plotted waveforms for XOR and XNOR logic for A and B
waveforms using CPL gate with CMOS inverter .
Question 1(b):
Code :
* Switch Matrix
* Device under test
C1 Out1 0 50fF
C2 Out2 0 50fF
.ends
* Unit Inverter
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
MP3 Out_1 Output1 Supply Supply cmosp
vdd Supply 0 dc 1.8
* Load Capacitor
C3 Output1 0 145fF
C4 Output2 0 145fF
.param Trep1= 40n
.param hival=1.6
.param loval=0.2
.control
run
plot V(A)+10 V(B)+8 V(Out_1)+6 V(Out_2)+4 V(Output1)+2
V(Output2)
plot i(Vdd)
.endc
1 ) waveforms for output voltages
2 ) waveform for current into Vdd
Observation :
-> compared to the voltage levels of the outputs at CPL gate in the
1(b) with 1(a),we got high voltage level in the 1(b).
-> this is because of the feedback PMOS connection between CPL
gate ouput and CMOS output.
-> feedback PMOS nullify the leakage current through the PMOS in
inverter and increase the Vdd – Vtn to Vdd – Vtp .
-> in this result, the fall time of the CMOS output is reduced compare
to 1(a).
-> the average value for current in the waveform 1(b) is
Id=-2.9266e-05 from t=0e-07 to t=1.2e-07
Result :
So, we plotted output waveforms for XOR and XNOR gates using CPL
gate with CMOS inverter using feedback PMOS.
Question 1(c):
Code :
* Switch Matrix
* Device under test
C1 Out1 0 50fF
C2 Out2 0 50fF
.ends
* Unit Inverter
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
vdd Supply 0 dc 1.8
* Load Capacitor
C3 Output1 0 145fF
C4 Output2 0 145fF
.param Trep1= 40n
.param hival=1.6
.param loval=0.2
V2 Abar 0 DC 0 PULSE({hival} {loval} {Tw1+2n} {Trf} {Trf} {Tw1}
{Trep1})
V4 Bbar 0 DC 0 PULSE({hival} {loval} {Tw2+2n} {Trf} {Trf} {Tw2}
{Trep2})
.control
run
plot V(A)+6 V(Abar)+4 V(B)+2 V(Bbar)
plot V(Out_1)+6 V(Out_2)+4 V(Output1)+2 V(Output2)
plot i(Vdd)
.endc
1 ) waveforms for inputs
2 ) waveforms for outputs

3 ) waveform for current
Observation :
-> in this question , we add delay time of 2ns only for Abar and Bbar
.
-> for this conditions , we got transition levels in the outputs of the
CPL gates at regular intervals.
-> so, we got high level glithes in the outputs of the CMOS inverter.
-> avg current Id=-4.2343e-05.
Result :
So, we plotted XOR and XNOR outputs using CPL gate with CMOS
inverter using feedback PMOS.
Question 1(d):
Code :
* Switch Matrix
* Device under test
C1 Out1 0 50fF
C2 Out2 0 50fF
.ends
* Unit Inverter
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
1.610U
+ L=0.18U W=0.96U AD = 345.6fF AS = 345.6fF PD = 2.644U PS =
2.644U
+ L=0.18U W=0.96U AD = 345.6fF AS = 345.6fF PD = 2.644U PS =
2.644U
vdd Supply 0 dc 1.8
* Load Capacitor
C3 Output1 0 145fF
C4 Output2 0 145fF
.param Trep1= 40n
.param hival=1.6
.param loval=0.2
.control
run
plot V(A)+6 V(B)+4 V(Output1)+2 V(Output2)
plot i(Vdd)
.endc
1 ) waveforms for outputs

Observation :
-> when we increase the width of a feedback PMOS in the logic
circuit , the circuit becomes the ‘strong pseudo NMOS logic circuit’.
-> so, the inputs of the CMOS inverter are always high .
-> it results in the outputs of the CMOS inverter are always low.
-> average current id = -1.115e-04
Result :
So, we plotted XOR and XNOR outputs for feedback PMOS with
equivalent width = 4*W .
Question 2 :
Code :
**CVSL logic **
Vdd supply 0 dc 1.8
MP1 out outbar supply supply CMOSP
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
MP2 outbar out supply supply CMOSP
+ L=0.18U W=1.3667U AD = 0.492012P AS = 0.492012P PD = 3.4534U
PS = 3.4534U
MN1 out A 1 1 CMOSN
+ L=0.18U W=0.89U AD = 0.3204P AS = 0.3204P PD = 2.5U PS = 2.5U
MN2 out Bbar 1 1 CMOSN
MN3 1 Abar 0 0 CMOSN
MN4 1 B 0 0 CMOSN
+L=0.18U W=0.89U AD = 0.3204P AS = 0.3204P PD = 2.5U PS = 2.5U
MN5 outbar A 2 2 CMOSN
MN6 outbar Abar 3 3 CMOSN
MN7 2 Bbar 0 0 CMOSN
MN8 3 B 0 0 CMOSN
.param Trep1= 40n
.param hival=1.6
.param loval=0.2
.control
run
*plot V(A)+6 V(B)+4 V(dout)+2 V(doutbar)
*plot V(A)+6 V(B)+4 V(xor)+2 V(xnor)
plot i(Vdd)
plot V(out)+2 V(outbar) V(A)+4 V(B)+6
.endc
1 ) waveforms

Observation :
-> in the previous question1(d) ,we have problem with the feedback
PMOS width. When we increase the width, the outputs of the CMOS
inverters are always low .
-> to avoid this, we use CVSL gates .
-> from the plots of the question2 , when we compare with the
previous ones , we have little gliches and less fall time.
-> average current Id = -1.6e-05 .
Result :
So, we plotted outputs of XOR and XNOR gates for CVSL gates.

22m1145 Vlsidesign 2

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22m1145 Vlsidesign 2

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VLSI design

1 ) waveform for output voltages with respect to input voltage

2 ) waveforms for outputs

1 ) waveforms for outputs

2 ) waveform for current

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