Laboratory nr.

6
CONTROLLED RECTIFIERS

1. THE PURPOSES of the laboratory work are:

a. To present the power circuit topologies and the control possibilities of the
single-phased controlled rectifiers
b. To present simple applications that can be included in control systems.

2. TEHNICAL SUPPORT consists of a series of dedicated circuits: a power circuit that

permits the implementation of different topologies for controlled rectifiers (L8.1) other
control circuits (L.3) from the laboratory nr.3.

3. THEORETICAL SUPPORT:

Electrical power generation and distribution is usually accomplished in the

form of alternating current due to simplicity and economy. However, many types of
electrical equipment operate from direct current sources. There are multiple
applications for controlled rectifiers like: DC motors, battery charger etc. The A.C.
voltage must be therefore rectified and in most cases filtered to provide a desired D.C.
output voltage at a required current or power level. The A.C. input may be single
phase for low to medium power requirements or three-phase for medium to high
power requirements. There are multiple applications for controlled rectifiers like: DC
motors, battery charger, galvanization process, electrolysis process etc.

A controlled rectifier is based on thyristors or other controlled devices. In

contrast to a diode, a thyristor does not turn on automatically at the beginning of the
positive half-cycle. After it has become forward-biased, it waits until a gate pulse is
applied on its gate terminal. A controlled rectifier is based on phase-angle strategy
and has a control circuit to generate the “gate firing pulses”. Control of the D.C.
output voltage is achieved by adjusting the delay time of the gate firing pulse. In other
words, we adjust the phase (   0  t f ) of the gate firing pulse with respect to a
reference instant. For each thyristor the reference is the instant at which it starts to get
forward biased. Of course, (tf) is the moment of the thyristor switching, with
T0
0tf 
2
and T0  20m sec for 50 Hz. For (   0 ), the circuit operates like a rectifier
based on diodes.

Semi-controlled rectifiers contain controlled switches-thyristors, GTO-s, etc.

but also diodes. These rectifiers are used primarily for reasons of economy in
situations that do not demand a fully controlled rectifier.
The controlled rectifiers based on thyristors (or other controlled electronic power
switches) are known as Naturally Commutated Converters because the switching-OFF
(commutation) is facilitated by the main line voltage which, periodically passes
through zero. Moreover, the transfer of the current from one device to other occurs
naturally because of the presence of these A.C. voltages.
 In the process of electrical rectification the bi-directional (A.C.) current is converted
to a unidirectional (D.C.) form. In accord to phase number of the A.C.-supply are
used:
 simple-phase rectifiers (small power range),
 three-phase rectifiers (middle power range),
 multiphase rectifiers (great power range).
In the plane ( V0 , I 0 ) of the middle-values (averaged values) of the load (output)
voltage and current, the operating mode of the rectifiers can be described in various
quadrants:
 one-quadrant operation: with ( V0  0 , I 0  0 ); electrical energy is transferred only from
the power supply to the load and the converter is a typical rectifier;
 two-quadrant operation with the possibility to work either in the first quadrant ( V0  0 ,
I 0  0 ) as in the previous case or in the fourth quadrant ( V0  0 , I 0  0 ) if the load
comprises an equivalent D.C.-supply (“active load”); the electrical energy is reversed
from the active load to the power supply; the output voltage ( V0 ) can be reversed by a
proper selection of the delay-angle () of the controlled rectifiers but the load current
remains positive; the converter becomes an inverter;
 four-quadrant operation if both the output voltage and current can be reversed; in fact
are used two back-to-back connected converters; if the first converter is operated as
rectifier (in the first quadrant) the second converter is operated as inverter (in the second
quadrant) and the output voltage (load voltage) is positive; to reverse the load voltage, the
first converter is operated as inverter (in the fourth quadrant) while the second converter
operates as rectifier (in the third quadrant).

Single-phase rectifier topologies and parameters

a) Single-phase semi-controlled bridges rectifiers

Figure 6.1. Single-phase full-wave semi-controlled rectifier

The circuit arrangement is shown in figure 6.1.a with two controlled (T1,T2) and two
uncontrolled (d1,d2) rectifiers. For resistive or resistive-inductive load the average of the load
voltage computed by equation :
 2 2  1  cosα   1  cosα 
V   Va  0,9 V
0 π  2   2  a
The r.m.s. output voltage equation is :

 
V
0 r.m.s.
V 
0
π  α  0,5
π
V
a
(6.3.2.)

The output voltage V0(t), besides the D.C. components V0 contains also high order
harmonics whose amplitudes and phases depend in the first line on the delay phase-angle () .
The harmonics have to be smoothed (”filtered” ) to obtain a quasi-ideal (A.C.-D.C.) converter
with a “pure” (D.C.) output voltage .
The output current depend on delay angle () and on the load –character, figure
6.3.1.b .(iOR: resistive load , IORL: resistive- inductive load ). On the A.C. side the current ia(t)
is also harmonics–rich and disturbs the main line. This is the main problem of the usual
rectifiers that are using the delay-angle control strategy .

b) Single-phase full-controlled bridge converter

The circuit topology is presented in figure 6.2.a. The load current will be transferred from
thyristors (T1 ;T2) during the positive half-cycle to thyristors (T3 ;T4) in the negative half-
cycle . The advantages of the full controlled converter can be fully exploited only by
inductive resistive load with ( τ L  L L R L ). Figure 6.2.b shows the voltage and current for
LL (L) as an idealized limit case. The average output voltage is :
2 2
V   cosα  V  0,9  cosα  V
0 π a a
as in figure 6.2.d.

If (LL >>), the load current is constant and the rectifiers is in continuous conduction mode
of operation :
i 0 t   I 0  V0 R L .
For pure resistive load (LL=0) results the load time constant ( τ L  L L R L  0 ). The average
output voltage was given by the equation:
1  cosα
V  0,9 V
0 2 a
while for pure inductive load (RL=0)and
τ L  LL R L  
It results
V 0  0,9cosα  V
a.
The two boundary static characteristic of the rectifying circuits are shows in figure 6.2.d and
results that, for inductive load and for    2 , the average output voltage can be negative. In
practice, this is possible only if the load is “active”, containing are external (equivalent)
power supply (eb) as we will see further.
For α  0  π 2 , V 0  I 0  0 and the convertor operates as rectifier. The electrical power flows
from the supply to the load. The operating point ( V 0 , I 0 ) is placed in the first quadrant figure
6.2.c.
Figure 6.2. Single-phase full-wave controlled converter

For α  π 2   and an active load figure 6.3 (eb, ZL) the average of the output voltage ( V 0 )
is negative. The converter operates as inverter in the fourth quadrant. The local current can be
controlled by changing the delay angle () ” beyond 2 “. The converter can operate only if
e  2  V . When the converter is operated as inverter and accidentally the A.C. voltage
b a
disappears, the load current i0(t) can not be more controlled by angle (), being given by the
equation: i  e R . This is practically a short-circuit and this situation must be avoided .
0 b L

eb
 4. EXPERIMENT PROCESS:

As a first step it is necessary to identify the dedicated circuits L8.1.

 The resistors (ro=2Ω) as a shunt for current measurement and visualization
 4 power thyristors (T6N10) denoted by (Thy1 – Thy4) and 4 snubber circuits
 4 power diodes 6SI10
 4 auxiliary thyristors of type K105 to control the power thyristors
The controlled rectifier is supplied from the AC power supply (SMP 2x17 Vrms).
All the controlled rectifier topologies will be implemented and tested.

Figure 4.