Q.

1 Let t1 and t2 are the time taken by the quick sort for inputs [1234] and [4321] respectively. Which of the following
holds?
(a) t1=t2 (b) t1>t2 (c) t1=t2+log5 (d) t1<t2
Q.2 Solve the following recurrence relations with T(1) = 1;
1.T(n) = 2T(n/2)+1 2. T(n) = 2T(n/2)+n-1 3. T(n)= T( /n ) + 1 4. T(n) = T(n-1)+n 5. T(2k)=3T(2k-1)+1;
Q.3 Find the value of ‘x’ after the execution of the following
1. x=0;i=n; while(i>2){ x=x+1; i= / i; }
2. x=0; for(i=1 to n){ for(j=1 to i) { for( k=1 to j) { x=x+1; }}}
Q.4 What structure is represented
in following binary tree? How
to delete key 5 so that the
structure is preserved?
Q.5 An array A contains n integers in non-decreasing order. Write a linear time algorithm to find i,j such that A[i] + A[j]
= a given integer M, if such i,j exist.
Q.6 Draw the min-heap that results from insertion of following elements in order into an initially empty min-heap:
7,6,5,4,3,2,1. Show the result after the deletion of root of the heap.
Q.7 The main memory has 2cm blocks, while the cache has 2c blocks, if the cache uses the set associative mapping
scheme with 2 blocks per set, then block k of the main memory maps to the set
(a) (k mod m) of the cache (b) (k mod c) of the cache (c) (k mod 2c) of the cache (d) (k mod 2cm) of the cache
Q.8 Arrange the following configuration for CPU in decreasing order of operating speed; Hard wired, Vertical,
horizontal microprog.
(a) H.W, Vertical, horizontal (b) H.W, horizontal, vertical
(c) Horizontal, vertical, hardwired (d) vertical, horizontal, hardwired
Q.9 Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but
identical CPU, we can say that
(a) T1<=T2 (b) T1>=T2 (c) T1<T2 (d) None
Q.10 Let G be a undirected graph with distinct edge weight. Let emax be the edge with max. weight and emin the edge
with min. weight. Which of the following statement is false?
(a) Every min span tree of G must contain emin.
(b) If emax is in min span tree, then its removal must disconnect 'G'
(c) No min span. tree contains emax
(d) 'G' has a unique min span tree
Q.11 Which of the following requires a device deriver
(a) Register (b) cache (c) Main-memory (d) Disk
Q.12 A CPU has 32 bit memory address and 256 KB cache memory. The cache is organized as a G-way Set-associative
cache with cache block size of 16 byte
(a) What is the no. of sets in the cache ?
(b) What is the size (in bits) of tag field per cache block ?
(c) What is the number & size of comparators required for tag matching.
(d) How many address bits are required to find the byte offset within a cache block ?
Q.13 The performance of a pipelined processor suffers if
(a) The pipeline stages have different delays
(b) Consecutive instructions are dependent on each other
(c) Pipeline stages shares hardware resources
(d) All of the above
Q.14 Horizontal micro programming
(a) Does not require use of signal decoders (b) Results in larger sized microinstr. than vertical
(c) Use one bit for each control signal (d) All of the above.
Q.15 Using expanding opcode encoding for instructions, is it possible to encode all of following in an instruction format
shown below? Justify your answer.
14- double address instructions,
127- single address instructions,
60- zero address instructions.
Q.16 A block set associative cache memory consists of 128 blocks divided into four block sets. The main memory
consists of 16384 blocks and each block contains 256 words. How many bits are
Q.17 Consider the following pseudo code.
x := 1;
i := 1;
while (x<=1000)
begin
x := 2x ;
i := i + 1;
end;
What is the value of i at the end of the pseudocode?
(A) 4 (B) 5 (C) 6 (D) 7 (E) 8
Q.18 Let T (n ) be defined by T (1 ) = 7 and T(n +1) = 3 n + T(n) for all integers n ≥1. Which of the following
represents the order of growth of T (n) as a function of n ?
(A) (n ) (B) (n log n) (C) (n 2) (D) (n2 log n ) (E) (2 n)
Q.19 Below is a precedence graph for a set of tasks to be executed on a parallel processing system S.

Efficiency is defined as the ratio between the speedup and the number of processors. (The speedup is defined as
the ratio of the time taken to perform a set of tasks on a single processor to the time taken to perform the same set of
tasks on a parallel processor.)

System S has four processors (CPU’s). If each of the tasks T 1, . . . ,T8 takes the same time, what is the efficiency of
this precedence graph on S ?
(A) 25% (B) 33 1 % (C) 50% (D) 100% (E) 125%
3
Q.20 Let k be an integer greater than 1. Which of the following represents the order of growth of the expression

as a function of n ?

(A) (k n) (B) θ (k n log n) (C) θ (k n log n) (D) θ (k2kn) (E) θ (n k + 1)

Q.21 Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves.
Which of the following data structures will allow mergesort to work in O (n log n) time?
I. A singly linked list
II. A doubly linked list
 III. An array
(A) None (B) III only (C) I and II only (D) II and III only (E) I, II, and III
Q.22 Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a
clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which
of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
(A) I only (B) II only (C) I and III only (D) II and III only (E) I, II, and III
Q.23 Consider any array representation of an n element binary heap where the elements are stored from index 1 to index
n of the array. For the element stored at index i of the array (i≤n), the index of the parent is
Q.24 A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative
cache with cache block size of 16 bytes.

a) What is the number of sets in the cache?

b) What is the size (in bits) of the tag field per cache block?
c) What is the number and size of comparators required for tag matching?
d) How many address bits are required to find the byte offset within a cache block?
e) What is the total amount of extra memory (in bytes) required for the tag bits?
Q.25 Consider a 5-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute),
MEM (Memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock
cycle and writes occur in the first phase of the clock
cycle. Consider the execution of the following instruction sequence:
11: sub r2, r3, r4; /* r2 r3 - r4 */
12: sub r4, r2, r3; /* r4 r2 - r3 */
13: sw r2, 100(r1) /* M[r1+100] r2 */
14: sub r3, r4, r2; /* r3 r4 - r2 */

a) Show all data dependencies between the four instructions.

b) Identify the data hazards.
Q.26 The performance of a pipelined processor suffers if

a) The pipeline stages have different delays (b) Consecutive instructions are dependent on each other

b) The pipeline stages share hardware resources (c) All of the above
Q.27 Horizontal microprogramming
a) Does not require use of signal decoders
b) Results in larger sized microinstructions than vertical microprogramming
c) Uses one bit for each control signal
d) all of the above
Q.28 The elements 32, 15, 20, 30, 12, 25, 16, are inserted one by in the given order into a maxHeap. The resultant
maxHeap is
Q.29 A 4-stage pipeline has the stage delays as 150, 120,160 and 140 nanoseconds respectively. Registers that are used
between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to
process 1000 items on this pipeline will be
(a) 120.4 microseconds (b) 160.5 microseconds (c) 165.5 microseconds (d) 590.0 microseconds
Q.30 A Priority-Queue is implemented as a Max-Heap. Initially, it has 5 elements. The level-order traversal of the heap is
given below:
10, 8, 5, 3, 2
Two new elements '1' and '7' are inserted in the heap in that order. The level-order traversal of the heap after the
insertion of the elements is:
(a) 10, 8, 7, 5, 3, 2, 1 (b) 10, 8, 7, 2, 3, 1, 5 (c) 10, 8, 7, 1, 2, 3, 5 (d) 10, 8, 7, 3, 2, 1, 5
Q.31 Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit address
the number of bits needed for cache indexing and the number of tag bits are respectively.
(a) 10, 17 (b) 10, 22 (c) 15, 17 (d) 5, 17
Q.32 A 5 stage pipelined CPU has the following sequence of stages:
IF - Instruction fetch from instruction memory.
RD - Instruction decode and register read.
EX - Execute: ALU operation for data and address computation.
MA - Data memory access - for write access, the register read at RD state is used.
WB - Register write back.
Consider the following sequence of instructions:
I1: L R0, loc 1; R0 < = M[loc1]
12: A R0, R0 1; R0 < = R0+R0
I3: S R2, R0 1; R2 < = R2 - R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to completer the above sequence of instruction starting from the fetch of I 1 ?
(a) 8 (b) 10 (c) 12 (d) 15

Q33 We are given ‘9’ tasks (for job sequencing with deadline problem) T1, T2,-----T9.
Task T1 T2 T3 T4 T5 T6 T7 T8 T9

Profit 15 20 30 18 18 10 23 16 25

Deadline 7 2 5 3 4 5 2 7 3

(A) Are all tasks completed in the schedule that gives maximum profit?
(a) All tasks are completed (b) T1 and T6 are left out (c) T1 and T8 are left out (d) T4 and T6 are left out
(B) What is the maximum profit earned?
(a) 147 (b) 165 (c) 167 (d) 175
Q.34 A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the
pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage
of the pipeline. the processor stops fetching new instructions following a conditional branch until the branch
outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each
instruction takes on cycle to complete on average, the total execution time of the program is:
(A) 1.0 second (B) 1.2 seconds (C) 1.4 seconds (D) 1.6 seconds
Q.35 Consider the following recurrence:

Which one of the following is true?

(A) T (n) = θ (loglogn) (B) T (n) = θ (log n)

(C) T (n) = θ ( ) (D) T (n) = θ (n)

Q.36 Consider two cache organization: The first one is 32KB 2-way set associative with 32byte block size, the second
one is same but direct mapped. The size of address is 32 bits in both the cases. A 2x1 multiplexer has a latency of
0.6nS while K-bit comparator has a latency K/10 nS.
(A) The value of hit latency in set associative case is;
(A) 2.4 ns (B) 2.3 ns (C) 1.8 ns (D) 1.7 ns
(B) The value of hit latency in direct mapping case is;
(A) 2.4 ns (B) 2.3 ns (C) 1.8 ns (D) 1.7 ns
Q.37 Which one of the following is a valid sequence of elements in an array representing 3-ary max heap?
(A) 1, 3, 5, 6, 8, 9 (B) 9, 6, 3, 1, 8, 5 (C) 9, 3, 6, 8, 5, 1 (D) 9, 5, 6, 8, 3, 1
Q.38 Suppose the elements 7,2,10 and 4 are inserted, in that order, into the valid 3-ary max heap found in the above
question,. Which one of the following is the sequence of items in the array representing the resultant heap?
(A) 10, 7, 9, 8, 3, 1, 5, 2, 6, 4 (B) 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
(C) 10, 9, 4, 5, 7, 6, 8, 2, 1, 3 (D) 10, 8, 6, 9, 7, 2, 3, 4, 1, 5
Q.39 Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a
20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively:
(A) 9, 6, 5 (B) 7, 7, 6 (C) 7, 5, 8 (D) 9, 5, 6
Q.40 Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the
EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction
needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of
clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 R1 + R0
MUL R4, R3, R2 R4 R3 * R2
SUB R6, R5, R4 R6 R5 - R4
Q.41 Consider the process of inserting an element into a Max Heap, where the Max Heap is represented by an array.
Suppose we perform a binary search on the path from the new leaf to the root to find the position for the newly
inserted element, the number of comparisons performed is:

Q. 42 We have a binary heap on n elements and wish to insert n more elements (not necessarily one after another) into
this heap. The total time required for this is
Q.43 The performance of a pipeline processor suffers if
(A) The pipeline stages have different delays (B) Consecutive instructions are dependent on each other
(C) The pipeline stages share hardware resources (D) All of the above
Q.44 If the following elements, 5, 3, 4, 2, 6, 7 and 1, are inserted into a heap then what is printed for an in order traversal
of the heap
(A) 2, 5, 3, 7, 4, 6, 1 (B) 3, 5, 2, 7, 4, 6, 1 (C) 4, 6, 3, 7, 2, 5, 1 (D) 4, 6, 3, 7, 1, 5, 2
Q. 45 Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns,
iOns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the
average access time of the system ignoring the search time within the cache?
(A) 13.0 ns (B) 12.8 ns (C) 12.6 ns (D) 12.4 ns
Q. 46 We have two designs Di and D2 for a synchronous pipeline processor. Di has 5 pipeline stages with execution times
of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution
time. How much time can be saved using design D2 over design Di for executing 100 instructions?
(A 214 nsec (B) 202 nsec (C) 86 nsec (D)-200 nsec
Q. 47 An instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as
follows:
Group 1: 20 signals, Group 2: 70 signals, Group 3: 2 signals, Group 4: 10 signals, Group 5: 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal
microprogramming?
(A) 0 (B) 103 (C) 22 (D) 55
Q.48 Consider a 4 stage pipeline processor. The number of cycle needed by the four instructions I1, I2, I3, I4 in stages
S1, S2, S3, S4 is shown below:
S1 S2 S3 S4
11 2 1 1 1
12 1 3 2 2
13 2 1 1 3
14 1 2 2 2
What is the number of cycles needed to execute the following loop?
for (i=1 to 2) {I1;I2;I3;I4;}
(A) 16 (B) 23 (C) 28 (D) 30
Q.49 Which one of the following array represents a binary max-heap?
(A) {25, 12, 16, 13, 10, 8, 14} (B) {25, 14, 13, 16, 10, 8, 12}
(C) {25, 14, 16, 13, 10, 8, 12} (D) {25, 14, 12, 13, 10, 8, 16}
Q.50 What is the content of the array after two delete operations on the correct answer to the previous question?
(A) {14, 13, 12, 10, 8} (B) {14, 12, 13, 8, 10} (C) {14, 13, 8, 12, 10} (D) {14, 13, 12, 8, 10}