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  • 8-to-3 Encoder Design Using Verilog

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    Tanima Bal
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    This document describes designing an 8 to 3 encoder using Xilinx Vivado and a Digilent Nexys 4 board. The encoder uses an if-else statement to assign a unique 3-bit code to each of the 8 possible input values. A testbench is also provided that applies sample input patterns to validate the encoder's functionality through simulation.

    Original Description:

    Combinational circuit

    Original Title

    combinational_2

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    This document describes designing an 8 to 3 encoder using Xilinx Vivado and a Digilent Nexys 4 board. The encoder uses an if-else statement to assign a unique 3-bit code to each of the 8 possible input values. A testbench is also provided that applies sample input patterns to validate the encoder's functionality through simulation.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    4 views3 pages

    8-to-3 Encoder Design Using Verilog

    Uploaded by

    Tanima Bal
    This document describes designing an 8 to 3 encoder using Xilinx Vivado and a Digilent Nexys 4 board. The encoder uses an if-else statement to assign a unique 3-bit code to each of the 8 possible input values. A testbench is also provided that applies sample input patterns to validate the encoder's functionality through simulation.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    COMBINATIONAL CIRCUITS

    3.1 ENCODER
    AIM: To design 8 to 3 encoder

    TOOL USED: Xilinx Vivado, Digilent Nexys 4

    CODE:

    module encoder_ifelse(

    input [7:0] data,

    output [2:0] code

    );

    reg [2:0] code;

    always@(data)

    begin

    if(data==8'b00000001) code=3'b000;

    else if(data==8'b00000010) code=3'b001;

    else if(data==8'b00000100) code=3'b010;

    else if(data==8'b00001000) code=3'b011;

    else if(data==8'b00010000) code=3'b100;

    else if(data==8'b00100000) code=3'b101;

    else if(data==8'b01000000) code=3'b110;

    else if(data==8'b10000000) code=3'b111;

    else code=3'bxxx;

    end

    endmodule

    TESTBENCH:
    module encoder_tb( );
    reg [7:0] data;

    wire valid_data;

    wire [2:0] code;

    pencoder_casex dut (.data(data),.valid_data(valid_data),.code(code));

    initial

    begin

    data=8'b01000000;

    #10 data=8'b00000100;

    #10 data=8'b10000000;

    #10 data=8'b00000010;

    end

    endmodule

    RTL NETLIST:

    SYNTHESIZED DESIGN:

    SIMULATION:

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