P8748H/P8749H

8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
MICROCONTROLLER
• High Performance HMOS II • Programmable ROMs Using 21V
• Interval Time/Event Counter • Easily Expandable Memory and I/O
• Two Single Level Interrupts • Up to 1.36 (J-s Instruction Cycle All
• Single 5-Volt Supply Instructions 1 or 2 Cycles
• Over 96 Instructions; 90% Single Byte
The Intel MCS®-48 family are totally self-sufficient. 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The family contains 27 I/O lines, an 8-bit timer/counter. and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and ROMless versions as well as a new version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
times and code risks.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly single byte instructions and no instruc-
tions over 2 bytes in length.
Device Internal Memory RAM STANDBY
8050AH 4Kx8 ROM 256x8RAM yes
8049AH 2Kx8ROM 128 x8 RAM yes
8048AH 1K xB ROM 64xBRAM yes
8040AHL None 256x8 RAM yes
8039AHL None 128x8RAM yes
B035AHL None 64xBRAM yes
P8749H 2K x 8 Programmable ROM 12Bx8 RAM no
P8748H 1K x 8 Programmable ROM 64x8RAM no

HAL {

_
1'17_
1'17_
-....
_AH
_L
....
1035......

_ ....L

270053-1
Figure 1. Block Diagram
270053-2

Figure 2. Logic Symbol

August 1989
Order Number: 270053-003 1-27
 MCS®-48

WAVEFORMS

INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY

MEMORY

.. LE
I-
I--'LL ---j .....FC2 r
.Cy-----I
. . __-,

270053-5

270053-4

WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS

ALE
...._ _-_--1..,tlAFC1 r uv ------,
X:.:::
....V - - - - - - ' ,
TEST POtNTS:::
;x=::::=
-
270053-7
kC, testing inputs are driven at 2AV lor a logic "1" and O,45V for
WR
a logic "0", Output liming measurements are made at 2.0V for a
ADDRESS IWO logic "1" and 0.6V for a logic "0",
FLOATING

270053-6

PORT 1/PORT 2 TIMING

,1STCYC~E I 2ND
CYCl.E
II
"LE

PSEN I I
-..i I-'LP \ ~ __----!V
i i
P20-23
OUTPUT

P24-27
]X~_-:-- _PCH
_ _ _ _ _-J, x po.;-:
'-._ _ _ R_T_20-_23_D_AT_A_---'X NEW P20-n DATA

~~~~T -;1_ _ _~-PO-R-T-2.---21-,-PO-R-T-'-O--'-'-DA-T-A-~------~'--_ _ _ _N_E_W_P_O_R_T~~...

_T_..__
I
'--l r-
i
IlP
EXPANDER II-- I A l + - "'.0 - - - 1 - - -
PORT "
~------i.
OUTPUT PCH

EXPANDER
PORT
INPUT PCH

PROG

270053-6

I
1-35
 MCS®-48

Table 1. Pin Description (Continued)

Pin
Symbol Function Device
No.
Tl 39 Input pin testable using the JT1. and JNT1 instructions. Can be All
designated the timer/counter input using the STAT CNT instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is All
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
AD 8 Output strobe activated during a BUS read. Can be used to enable All
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
AESET 4 Input which is used to initialize the processor. (Active low) (Non TTL All
VIH)
Used during power down. 8048AH
8035AHL
8049AH
8039AHL
8050AH
8040AHL
Used during programming. P8748H
P8749H
Used during ROM verification. 8048AH
P8748H
8049AH
P8749H
8050AH
WR 10 Output strobe during a bus write. (Active low) All
Used as write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each cycle and is All
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
PSEN 9 Program store enable. This output occurs only during a fetch to All
external program memory. (Active low)
58 5 Single step input can be used in conjunction with ALE to "single step" All
the processor through each instruction.
(Active low) Used in sync mode. 8048AH
8035AHL
8049AH
8039AHL
8050AH
8040AHL
EA 7 External access input which forces all program memory fetches to All
reference external memory. Useful for emulation and debug. (Active
high)
Used during (18V) programming. P8748H
P8749H
Used during ROM verification (12V). 8048AH
8049AH
8050AH
XTAL1 2 One side of crystal input for internal oscillator. Also input for external AU
source. (Non TTL VIH)
XTAL2 3 Other side of crystal input. All

I
1-29
MCS®-48

Table 2. Instruction Set

Accumulator Input/Output
Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles
ADDA,R Add register to A 1 1 INA,P Input port to A 2
ADD A, @R Add data memory PUTLP,A Output A to port 1 2
toA ANLP, #data And immediate to 2 2
ADD A, #data .l\dd immediate to A 2 2 port
ADDCA, R Add register with PRL P, #data Or immediate to 2 2
carry port
AD DC A, @R Add data memory INS A, BUS Input BUS to A 2
with carry OUTL BUS, A Output A to BUS 1 2
ADDC A, # data Add immediate with 2 2 ANL BUS, #data And immediate to 2 2
carry BUS
ANLA, R And register to A ORl BUS, #data Or immediate to 2 2
ANLA, @R And data memory BUS
to A MOVD A, P Input expander port 2
ANLA, #data And immediate to A 2 2 toA
ORLA, R Or register to A MOVDP,A Output A to 2
ORLA, @R Or data memory expander port
to A ANLD P,A And A to expander 2
ORLA, #data Or immediate to A 2 2 port
XRLA, R Exclusive or register ORLDP, A Or A to expander 2
toA port
XRLA,@R Exclusive or data
memory to A
XRL A, #data Exclusive or 2 2 Registers
Immediate to A
Mnemonic Description Bytes Cycles
INCA Increment A
DECA Decrement A INCR Increment register
CLRA Clear A INC@R Increment data memory
CPLA Complement A DECR Decrement register
DAA Decimal adjust A
SWAP A Swap nibbles of A Branch
RLA Rotate A left
RLCA Rotate A left Mnemonic Description Bytes Cycles
through carry
RRA Rotate A right JMP addr Jump unconditional 2 2
JMPP @A Jump indirect 1 2
RRCA Rotate A right
through carry DJNZ R, addr Decrement register 2 2
and skip
JC addr Jump on carry = 1 2 2
JNC addr Jump on carry = 0 2 2
JZ addr Jump on A zero 2 2
JNZaddr Jump on A not zero 2 2
JTO addr Jump on TO = 1 2 2
JNTO addr Jump on TO = 0 2 2
JT1 addr JumponT1 = 1 2 2
JNT1 addr Jump on T1 = 0 2 2
JFO addr Jump on FO = 1 2 2
JF1 addr Jump on F1 = 1 2 2
JTF addr Jump on timer flag 2 2
JNI addr Jump on INT = 0 2 2
JBb addr Jump on accumulator 2 2
bit

1-30

I
 MCS®-48

Table 2. Instruction Set (Continued)

r-----------------------------------~ r----------------------------------~
Subroutine Timer/Counter

Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles

CALLaddr Jump to subroutine 2 2 MOVA.T Read timer/counter 1 1
RET Return 1 2 MOVT.A Load timer I counter 1 1
RETR Return and restore 1 2 STRTT Start timer 1 1
status STRTCNT Start counter 1 1
STOP TCNT Stop timer I counter 1
EN TCNTI Enable timer I 1
Flags counter interrupt
DIS TCNTI Disable timerI
Mnemonic Description Bytes Cycles counter interrupt
CLRC Clear carry 1 1
CPLC Complement carry 1 1
CLR FO Clear flag 0 1 1 Control
CPLFO Complement flag 0 1 1
Mnemonic Description Bytes Cycles
CLRF1 Clear flag 1 1 1
CPLF1 Complement flag 1 1 1 ENI Enable external 1 1
interrupt
DISI Disable external
Data Moves interrupt
Mnemonic Description Bytes Cycles SELRBO Select register bank 0
SELRB1 Select register bank 1
MOVA.R Move register to A 1 1 SElMBO Select memory bank 0
MOVA.@R Move data memory 1 1 Select memory bank 1
SELMB1
toA
ENTOCLK Enable clock output
MOV A. II data Move immediate to 2 2
A onTO
MOV R. A Move A to register
MOV @R. A Move A to data Mnemonic Description Bytes Cycles
memory
MOV R. IIdata Move immediate to 2 2 NOP No operation 1
register
MOV @R. IIdata Move immediate to 2 2
data memory
MOV A. PSW Move PSW to A
MOV PSW. A Move A to PSW
XCH A. R Exchange A and
register
XCH A. @R Exchange A and
data memory
XCHD A. @R Exchange nibble of
A and data memory
MOVX A. @R Move external data 2
memorytoA
MOVX @R. A Move A to external 2
data memory
MOVP A. @A Move to A from 2
current page
MOVP3 A. @A Move to A from 2
page 3

I
1-31
ABSOLUTE MAXIMUM RATINGS·
Case Temperature Under Bias ....... O·C to + 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on any Pin with Respect
to Ground ...................... - 0.5V to + 7V
Power Dissipation .......................... 1.5W
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operating Conditions"
may affect device reliabl1ity.

D.C. CHARACTERISTICS TA = O"Cto +70"C;Vce = Voo = 5V ±10%;Vss = OV

Uml.s
Symbol Parameter Unit Test Conditions Device
Min Typ Max
Vil Input Low VoHage (All -0.5 0.8 V All
ExceptRESET,X1,X2)
VIL1 Input Low Voltage -0.5 0.6 V All
(RESET, X1, X2)
VIH Input High Voltage 2.0 Vee V All
(All Except XTAL1,
XTAL2, RESET)
VIH1 Input High Voltage 3.8 Vee V All
(X1, X2, RESEn
VOL Output Low Voltage 0,45 V IOl = 2.0mA All
(BUS)
VOL1 Output Low Voltage 0.45 V IOl = 1.8 rnA All
(RD, WR, PSEN, ALE)
VOL2 Output Low Voltage 0,45 V IOl = 1.0 rnA All
(PROG)
VOl3 Output Low Voltage 0.45 V IOl = 1.6mA All
(AU Other Outputs)
VOH Output High Voltage 2.4 V IOH = - 400 IJoA All
(BUS)
VOH1 Output High Voltage 2.4 V IOH = -100 IJoA All
(RD, WR, PSEN, ALE)
VOH2 Output High Voltage 2.4 V IOH = -40~ All
(All Other Outputs)

I
1-32
 MCS®-48

D.C. CHARACTERISTICS TA = OOCto +700C;Vcc = voo = 5V ±10%;Vss = OV(Continued)

Umlt.
Symbol Parameter Unit Test Conditions Device
Min Typ Max
1L1 Leakage Current ±10 /J- A Vss :$; VIN :$; Vcc All
(T1.1m')
ILl1 Input Leakage Current -500 /J- A Vss + 0.45 :$; VIN :$; Vee All
(P10-P17. P20-P27,
EA,~)

IU2 Input Leakage Current -10 -300 p.A Vss :$; VIN :$; 3.8 All
AESET
iLO Leakage Current ±10 p.A Vss :$; VIN :$; Vee All
(BUS, TO) (High
Impedance State)
100 Voo Supply Current 3 5 mA 8048AH
(RAM Standby) 8035AHL
4 7 mA 8049AH
8039AHL
5 10 rnA 8050AH
8040AHL
100 + Total Supply Current- 30 65 rnA 8048AH
Icc 8035AHL
35 70 rnA 8049AH
8039AHL
40 80 rnA 8050AH
8040AHL
30 100 rnA P8748H
50 110 rnA P8749H
Voo RAM Standby Voltage 2.2 5.5 V Standby Mode Reset 8048AH
:$;VIL1 8035AH
2.2 5.5 V 8049AH
8039AH
2.2 5.5 V 8050AH
8040AHL
'Icc + 100 are measured with aft outputs In !heir high impedance state; R£SET low; 11 MHz crystal applied; INT, SS, and EA floalong.

1-33

I
MCS®-48

A.C. CHARACTERISTICS T A = O·C to + 70·C; Vee = Voo = 5V ± 10%; VSS = OV

f (t) 11 MHz Conditions

Symbol Parameter Unit
(Note 3) Min Max (Note 1)
t Clock Period 1/xtal fraq 90.9 1000 ns (Note 3)
tll ALE Pulse Width 3.5t-170 150 ns
tAL Addr Setup to ALE 2t-110 70 ns (Note 2)
tLA Addr Hold from ALE t-40 50 ns

tcCl Control Pulse Width (RD, WR) 7.5t-200 480 ns

tcC2 Control Pulse Width (PSEN) 6t-200 350 ns

tow Data Setup before WR 6.5t-200 390 ns
two Data Hold after WR t-50 40 ns
tOR Data Hold (RD, PSEN) 1.5t-30 0 110 ns
tROl RDto Data in 6t-170 375 ns
tR02 PSEN to Data in 4.5t-170 240 ns
tAW Addr Setup to WR 5t-150 300 ns
tADl Addr Setup to Data (RD) 10.5t-220 730 ns
tAD2 Addr Setup to Data (PSEN) 7.5t-200 460 ns
tAFCl Addr Float to RD. WR 2t-40 140 ns (Note 2)
tAFC2 Addr Float to PSEN 0.5t-40 10 ns (Note 2)

tLAFCl ALE to Control (RD. WR) 3t-75 200 ns

tlAFC2 ALE to Control (PSEN) 1.5t-75 60 ns
tCAl Control to ALE (RD. WR. PROG) t-65 25 ns
tCA2 Control to ALE (PSEN) 4t-70 290 ns
tcp Port Control Setup to PROG 1.5t-80 50 ns
tpc Port Control Hold to PROG 4t-260 100 ns
tpR PROG to P2 Input Valid 8.5t-120 650 ns
tpF Input Data Hold from PROG 1.5t 0 140 ns
top Output Data Setup 6t-290 250 ns
tpo Output Data Hold 1.5t-90 40 ns
tpp PROG Pulse Width 10.5t-250 700 ns
tpl Port 2 1/0 Setup to ALE 4t-200 160 ns
tlP Port 2 1/0 Hold to ALE 0.5t-30 15 ns
tpv Port Output from ALE 4.5t+ 100 5.0 ns
tOPRR TO Rep Rate 3t 270 ns
tCY Cycle Time 15t 1.36 15.0 ,...s

NOTES:
1. Control outputs: C L = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance load 20 pF
3. fIt) assumes 50% duty cycle on Xl, X2. Max clock period is for a 1 MHz crystal input.

I
1-34
 MCS®-48

WAVEFORMS

INSTRUCTION FETCH FROM PROGRAM READ FROM EXTERNAL DATA MEMORY

MEMORY

I>
ALE
I--'ll ---j "-A.C.' 'Cy-----I
,-__-,

270053-5

270053-4

WRITE TO EXTERNAL DATA MEMORY INPUT AND OUTPUT FOR A.C. TESTS

ALE
.--_ _--_-i,tLAFC1 r O.45V
____~X:.::
uv -------
. .
TEST POtHTS=::
:x=:=
-
270053-7
AG. testing inputs are driven at 2.4V lor a logic "1" and 0.45V for
WR
a logic "0". Output timing measurements are made at 2.0V for a
ADDRESS 'wo logic "1" and O.BV for a logic "0".
FLOATING

270053-6

PORT 1/PORT 2 TIMING

,1STCYC~E I .ND
CYCl.E
II
ALE

PIlEN I I
--i l>'lP \ ~------!I/ ---II-- 'lP
i i
P20-23
OUTPUT ]X ~_-:-_PC
_ .._ _ _ _.J_
X '- POT:R_T_20-_23_D_AT_A_--->X
____ NEW P20-23 DATA
~
P24-27 I
ri~~T _~I_ _ _~_P_D_R_T_"_-_21_,_PO_R_T_'_O-_'_7_DA_T_A_-7_ _ _ _ _ _--1'--_ _ _ _N_E_W_P_O_R_T~~A_T_A__
I
---1 r-
i
'lP
EXPANDER
PORT
II--
"
t A L + - "-A ---1----
~---___i
OUTPUT PCH

EXPANDER
PORT
tNPUT PCH

PRDG

270053-6

I
1-35
MCS®-48

CRYSTAL OSCILLATOR MODE CERAMIC RESONATOR MODE

Cl

~
t----'_ _ _"-_ _2-1 ICTAl1

~~~
~ :----,-----T-L--_. --: 3
XTAL2
C3
270053-9 270053-10
Cl ~ 5 pF +'1. pF + (STRAY < 5 pF)
C2 ~ (CRYSTAL + STAY) < S pF
C3 ~ 20 pF ± 1 pF + (STRAY < 5 pF)
Crystal series resistance should be less than 30n at 11 MHz; less
than 75{l at 6 MHz; less than 180n at 3.6 MHz.

DRIVING FROM EXTERNAL SOURCE

~. ._ _ _ _2--j' ICTAl1

~o'=~ ~
GATES Y 1470 I II

3 XTAl2

270053-11
For XTAl1 and XTAL2 define "high" as voltages above LSVand
"low" as voltages below I.SV. The duty cycle requirements for
externally driving XTAL1 and XTAL2 using the circuits shown
above are as follows: XTALI must be high 35-65% of the period
and XTAL2 must be high 35-65% of the period. Rise and fall nmes
must be faster than 20 ns.

I
1-36
 MCS®-48

PROGRAMMING AND VERIFYING THE WARNING:

P8749H/48H PROGRAMMABLE ROM An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
Programming Verification of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
In brief, the programming process consists of: acti- used to disable the programmer.
vating the program mode, applying an address,
latching the address, applying data, and applying a The Program/Verify sequence is:
programming pulse. Each word is programmed com- 1. Voo = 5V, Clock applied or internal oscillator
pletely before moving on to the next and is followed operating, RESET = OV. TO = 5V, EA = 5V.
by a verification step. The following is a list of the BUS and PROG floating. P10 and P11 must be
pins used for programming and a description of their tied to ground.
functions:
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)
Pin Function
4. EA = 18V (activate program mode)
XTAl1 Clock Input (3 to 4.0 MHz)
5. Address applied to BUS and P20-22
XTAL2
6. RESET = 5V (latch address)
RESET Initialization and Address Latching
TO Selection of Program or Verifying Mode 7. Data applied to BUS
EA Activation of ProgramlVerify Modes 8. Voo = 21V (programming power)
BUS Address and Data Input 9. PROG = Vee or float followed by one 50 ms
Data Output During Verify pulse to 18V
P20-P22 Address Input 10. Voo = 5V
Voo Programming Power Supply
11. TO = 5V (verify mode)
PROG Program Pulse Input
12. Read and verify data on BUS
13. TO = OV
14. RESET = OV and repeat from step 5
15. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.

NOTE:
Once programmed the P8749H/48H cannot be
erased.

1-37

l
MCS®-48

A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY

TA = 25C C ±5C C; vee = 5V ±5%; voo = 21 ±0.5V
Symbol Parameter Min Max Unit Test Conditions
tAW Address Setup Time to RESET 4tcy
tWA Address Hold Time After RESET 4tcy
tow Data in Setup Time to PROG 4tcy
two Data in Hold Time After PROG 4tcy
tpH RESET Hold Time to Verify 4tcv
tvoow Voo Hold Time Before PROG 0 1.0 ms
tVOOH Voo Hold Time After PROG 0 1.0 ms
tpw Program Pulse Width 50 60 ms
tTW TO Setup Time for Program Mode 4tcy
tWT TO Hold Time After Program Mode 4tcy
too TO to Data Out Delay 4tcy
tww RESET Pulse Width to Latch Address 4tcy
t r• tf Voo and PROG Rise and Fall Times 0.5 100 ,...s
tey CPU Operation Cycle Time 3.75 5 ,...s
tRE RESET Setup Time before EA 4tcy

NOTE:
If Test 0 is high, too can be triggered by RESET.

D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY

T A = 25 c C ± 5°C; Vee = 5V ± 5%; Voo = 21 ± 0.5V
Symbol Parameter Min Max Unit Test Conditions
VOOH Voo Program Voltage High Level 20.5 21.5 V
VOOL Voo Voltage Low Level 4.75 5.25 V
VPH PROG Program Voltage High Level 17.5 18.5 V
~PL PROG Voltage Low Level 4.0 Vee V
VEAH EA Program or Verify Voltage High Level 17.5 18.5 V
100 VOO High Voltage Supply Current 20.0 mA
IpROG PROG High Voltage Supply Current 1.0 mA
lEA EA High Voltage Supply Current 1.0 mA

I
1-38
 MCS®-48

SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY

INITIAL ROM DUMP CYCLE SUBSEQUENT ROM DUMP CYCLES

ALE
(NOTE 1) : (OUTPUT)

EA --.:J I
: (INPUT)
I

DB ADDRESS

(INPUT,
H ROM DATA

(OUTPUT)
H I
ADDRESS

(INPUT)
~ DATA
(OUTPUT,:

,
RESET I I
I
(INPUT)

P20-P23 ADDRESS
H I
I
(INPUT,
ADDRESS

270053-12
50H Vee ~ Voo ~ +5V
Vss ~ OV
Al0 ADDR
All ADDR

NOTE:
ALE is function of Xi, X2 inputs.

COMBINATION PROGRAM/VERIFY MODE (PROGRAMMABLE ROMS ONLY)

~IRE.}
Vee II
TO vee=1L-ITW-~ PROGRAM-----+-~C WM"~!""'----PflOGRAM
:~~ -----~----------~---------------------------------~-- -
RESET
'----- '------~/
~
VIL1 -
-l---+---+-
DATA TO BE
PROGRAMMED VALID

LAST NEXT
ADDRESS ADDRESS

V,,:" -- ----- tvDDW1,t:JJr., ~~

Vee J' i I ~~--------------------------------------------------
VPH _... _
PRO~PL_____________
-. - - - -
====rrlJ DW
_
•
"
: I two
_.i ____________________ .
270053-13

I
1-39