Intro to Digital Logic, Lab 3

Digital Design using FPGAs

Lab Objectives
Now that you know how to develop Verilog designs and load them into the DE1-SoC board, we can now
start looking at more complex designs.

Task #1 – Multi-level logic on the FPGA

The customer service department at Nordstrom (the department store) wants an electronic detector
device for processing returns. Its goal is to both detect discounted items, so that the proper rebates can
be calculated, as well as help find shoplifters returning their ill-gotten gains.
There are six products being sold. Table 1 shows the Universal Product Code (UPC), whether it was ever
on sale (i.e., sold at a discounted price), and whether it is expensive for each item.

Since there are only 6 items, not all UPC codes are used. The behavior of your circuit for these
situations is unimportant (i.e., Don’t Care).

Nordstrom has a special method for finding shoplifters. Whenever they sell an expensive item, they put
a secret mark on it at checkout. Thus, expensive items that are purchased are specially marked, while
stolen expensive items will not be so marked (inexpensive items are never marked, since it is too
expensive to mark everything sold). When there is a return, we want to make sure someone didn’t steal
the item, then return the stolen item for money. Therefore, there are the following four cases to
consider for whether or not an item was stolen:
• An expensive, marked item is not stolen.
• An expensive, unmarked item is stolen.
• An inexpensive, unmarked item is not stolen.
• An inexpensive, marked item should never occur, so treat it as a Don’t Care.

Item Name UPC Discounted? Expensive?

Shoes No Yes
Costume Jewelry No No
Christmas Ornament Yes No
Business Suit No Yes
Winter Coat Yes Yes
Socks Yes No
Table 1: List of products being sold as well as their UPCs and shopping classifications.

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You will be given the UPC of the item under test (signals “ ”, “ ”, and “ ” for simplicity), and a detector
will check for a secret mark (“ ”). Your circuit should have one “ ” light that lights up
whenever a discounted item’s UPC is supplied, as well as a “ ” light that lights up whenever a
theft is detected (Figure 1).

Figure 1: Schematic of Lab 3 circuit design.

1) Create a circuit design by hand for each output. Use K-Maps or Boolean algebra to optimize the
design (K-Maps will likely be easiest).
2) Write the corresponding Verilog code in Quartus Prime and simulate it, using the available
switches and lights on the FPGA as inputs and outputs.
3) Download the design to the FPGA and test/debug it.
4) Once you have the design working on the FPGA, draw out the finalized schematic for
submission.

Lab Grading
Working Design: 50 points for correctness, style, and testing.
Logic Minimization: Up to 10 points for using as few logic gates as possible.
You are only allowed to use standard gates (AND, OR, NAND, NOR, NOT, XOR, XNOR).
Each gate appearing in your hand-drawn circuit diagram counts the same, and gates (other
than NOT) can have as many inputs as you want. Unlike Lab 2, there are no “free” gates, so
every gate in your schematic is counted.

Lab Demonstration/Turn-In Requirements

Lab Report (before Wednesday section, submit as PDF on Gradescope)
• The K-maps or Boolean simplification you did to create your design ( and ).
• Your circuit diagrams (separate) for and .
• A screenshot of the ModelSim simulation with explanation.
• How many hours (estimated) it took to complete this lab in total, including reading, planning,
designing, coding, debugging, and testing.
• As a separate file, upload the Verilog code for your design.

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In-Person Demo (during your demo slot)
• Demonstrate your UPC code circuit working in simulation in ModelSim.
• Demonstrate your UPC code circuit working on the DE1 board.
• Be prepared to answer questions on both the theoretical and practical parts of the lab.

Lab 3 Rubric
Grading Criteria Points

Q1: Logic simplification work 5 pts

Q2: Circuit diagrams 5 pts

▪ Logic minimization ( ) 4 pts

▪ Logic minimization ( ) 6 pts

Q3: ModelSim screenshot of Nordstrom circuit 3 pts

▪ Explanation of waveforms 5 pts

Time spent 2 pts

Verilog code uploaded 5 pts

LAB DEMO 25 pts

60 pts