2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 1

FPGA Implementation of Hybrid Han-Carlson Adder

Swapna Gedam Pravin Zode Pradnya Zode
Deptt. of Electronics Engineering Assistant Professor Assistant Professor
Y.C. College of Engg, Nagpur Deptt. of Electronics Engineering Deptt. of Electronics Engineering
India- 441110 Y.C. College of Engg, Nagpur Y.C. College of Engg, Nagpur
India- 441110 India- 441110

Abstract- In this paper a modified parallel prefix adder, more inverters to buffer the outputs. Zero or more
Hybrid Han-Carlson adder is proposed which uses different inverters are added to each prefix cell output to minimize
stages of Brent-Kung and Kogge-Stone adders. Binary
addition is one of the primitive and most commonly used the delay based on this model, buffers are individually
application in computer arithmetic. Parallel prefix adders sized to minimize the delay, buffers are used to minimize
offer a highly efficient solution to the binary addition the fanout and loading on gates since high fanout causes
problem and are well suited for FPGA implementation. poor performance. A modified Han-Carlson adder uses
Carry propagation in binary addition can be efficiently fewer number of prefix operations by adjusting the
expressed as a prefix computation. Modified Hybrid Han-
Carlson adder reduces the complexity, area and power number of stages amongst Kogge-Stone and Brent-kung
consumption significantly. adder and thus reduces the area required by the adder
circuitry. The two different designs Han-Carlson adder
Index Terms - Parallel Prefix Adders; Han-Carlson
adder; Hybrid Han-Carlson Adder; prefix computation. and the Hybrid Han-Carlson adder is shown in fig.1 and
fig.2 respectively. The nodes (black circular cell)
I. INTRODUCTION represents the prefix operation.
VLSI binary adders are critically important elements in
processor chips, they are used in floating-point arithmetic
units, ALUs, memory addresses program counter update
and magnitude comparator [1, 2]. Adders are extensively
used as a part of the filter such as DSP lattice filter [3].
Ripple carry adder is the first and most fundamental adder
that is capable of performing binary number addition.
Since its latency is proportional to the length of its input
operands, it is not very useful. To speed up the addition,
carry look ahead adder is introduced. The requirement of
the adder is that it is fast and secondly efficient in terms of Fig.1: Graph representation of 32-bit Han-Carlson Adder [4]
power consumption and chip area. Parallel prefix adders
provide a good theoretical basis to make a wide range of
design trade-offs in terms of delay, area and power.
The adders with the large complex gates will be
too slow for VLSI, so the design is modularized by
breaking it into trees of smaller and faster adders which
are more readily implemented. For large adders the delay
of passing the carry through the look-ahead stages
becomes dominated and therefore tree adders or parallel
prefix adders are used. High speed addition depends on the
previous carry to generate the present sum. In integer
addition any decrease in delay will directly relate to an
increase in throughput. In nanometer range, it is very Fig. 2: Graph representation of 32-bit Hybrid Han-Carlson Adder [4]
important to develop addition algorithm that provide high
performance while reducing power. The paper remainder of the paper is organized as
Parallel prefix adders are suitable for VLSI follows. Section 2 describes previous work related to
implementation since they rely on the use of simple cells parallel prefix adders. Section 3 Describes proposed work.
and maintain regular connection between them. We can Section 4 describes FPGA Implementation of Hybrid Han
define each prefix structures in terms of logic levels, Carlson Adder. The Experimental results are discussed in
fanout and wiring tracks. Prefix cells are constructed using section 5 and finally, concluding remarks are in section 6
CMOS gates and consist of a complex gate and zero or

978-1-4799-1356-5/14/$31.00 ©2014 IEEE

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 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 2

II. PREVIOUS WORK parameters and shows how parallel prefix adders are better
The different types of parallel prefix adders available choice as compared to the conventional adders.
are Kogge-Stone adder, Brent-kung adder, Sklansky adder,
Han-Carlson adder, Knowles adder and Ladner-Fischer Table 1 Comparison of Adders [7]

adder. These adders offer tradeoffs among the number of

stages of logic, the number of logic gates, fanout and Logic Max Fan-
Architecture Tracks Cells
Levels out
amount of wiring between stages. Kogge-Stone adder,
Carry-Ripple N-1 1 1 N
Brent-kung adder and Sklansky adder are the fundamental
adders. Brent-Kung uses minimal number of computation Carry-Skip N/4 + 5 2 1 1.25N
nodes which yields in reduced area but structure has Carry-Inc. N/4 + 2 4 1 2N
maximum depth which yields slight increase in latency. Brent-Kung 2log2N – 1 2 1 2N
Slansky reduces the delay at the expense of increased
fanout. Kogge-stone achieves high speed and low fanout Kogge- Stone log2N 2 N/2 Nlog2N
but produces complex circuitry with more numbers of Han-Carlson log2N + 1 2 N/4 0.5Nog2N
wiring tracks[5]. The Knowles trees are family of network
between between Kogge-Stone and sklansky with
increased fanout. Ladner Fischer introduced a network III. PROPOSED WORK
between Sklansky and Brent-Kung which provides a To design Parallel Prefix Hybrid Han-Carlson Adder. It
tradeoffs between logic levels and fanout. T. Han and D.A. differs from other adder is that it can be used for large
Carlson presented a hybrid construction of a parallel prefix word sizes. The proposed design reduces the number of
adder using two designs the Kogge-Stone construction prefix operation by using more number of Brent-Kung
having the best feature of higher speed and the Brent-kung stages and lesser number of Kogge-Stone stages. To
construction with best feature of low area requirement. A reduce the complexity, silicon area and power
modified Han-Carlson adder uses fewer number of prefix consumption significantly as compared to Han-Carlson
operations by adjusting the number of stages amongst adder. Later this Prefix Hybrid Han-Carlson is
Kogge-Stone and Brent-kung adder and thus reduces the implemented on FPGA.
area required by the adder circuitry.
Fig 3. below shows a 3-dimentional
taxonomy of tree adders[6]. There are three axis IV. IMPLEMENTATION
representing the fanout, wiring tracks and logic levels and Studied the structure of Hybrid Han-Carlson Adder
each tree is indicated by three integers (l, f, t) in the range and various design parameters. Also studied different
[0, L-1]. The tree adders lie on the plane l + f + t = L-1, Prefix cells that are being used in the design and their
where L= log2N and indicates the number of bits. Brent- equations [4] are shown below
Kung, Kogge-Stone and Sklansky represent the vertices of Square Cells : for pre-processing parallel prefix stage to
the cube (3, 0, 0),(0, 0, 3) and (0, 3, 0) respectively. Han- calculate generate and propagate .
Carlson, Ladner-Fischer and Knowles lie along the g= a and b & p= a xor b
diagonals.

Fig 4. Logic diagram for Black Square cell.

Fig 3. Taxonomy of prefix networks [6] Fig 5(a), 5(b). below shows the simulation result for
single black square cell.
Table 1 below shows the comparison of conventional
and parallel prefix adders in terms of design parameters
like logic levels, fanout, wiring tracks and number of cells
required. There is always a trade-off between these

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 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 3

Fig 7(b) Simulation result for Black circular cell

Fig 5(a). RTl view for Black Square cell Fig 8(a) and Fig 8(b) below shows the simulation results
for initial stage of 32-bit hybrid Han- Carlson adder.

Fig 8(a) Simulation result for initial stage of Hybrid Han-Carlson adder
Fig 5(b). Simulation result for Black Square cell

Circular cells: for computation of prefix operation [8,9]

Fig 8(b) RTL view for initial stage of Hybrid Han-Carlson adder
Fig 6. Logic diagram for Black circular cell [10]
V. RESULT
Fig 7a, 7b. below shows the simulation result for single
The simulation results of Han-Carlson and Modified
black circular cell
Hybrid Han-Carlson adder indicates that the number of
prefix operations required in a Hybrid Han-Carlson adder
is less since it uses more number of Brent-Kung stages and
fewer number of Kogge-Stone stages as compared to the
Han-Carlson design. Table 2. below gives the comparison
of these two designs and shows how the modified design
is better than the traditional design.
Table 2 Comparative results

Hybrid Han-Carlson
Parameters Han-Carlson adder
Adder
No. of bits 32 32

No. of gates 940 855

Area 1299.02 (x 10-10 m2) 1147.44 (x 10-10 m2)

Power 445.98 microwatts 405.23 microwatts

Fig 7(a) RTL view for Black circular cell

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 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 4

VI. CONCLUSION
From the above work, it is seen that the Hybrid
Han-Carlson adder presented a reduction in the complexity
and hence provides a tradeoffs for the construction of large
adders. These wide adders are useful in applications like
cryptography for security purpose, global unique
identifiers used as a identifier in computer software and
this wide adder also provides good speed.

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