A Comparative Study on 16-bit Digital Adders

Rahul Sajeeth Mohan Joseph James Jose K Joyes Mrs. Niji Mathews
Dept.of Electronics and Dept.of Electronics and Dept.of Electronics and Asst. Professor
Communications Engineering Communications Engineering Communications Engineering ECE Department
Viswajyothi College of Viswajyothi College of Viswajyothi College of Viswajyothi College of
Engineering & Technology Engineering & Technology Engineering & Technology Engineering & Technology
Vazhakulam, Muvattupuzha, Vazhakulam, Muvattupuzha, Vazhakulam, Muvattupuzha, Vazhakulam, Muvattupuzha,
Kerala, India Kerala, India Kerala, India Kerala, India
rahul.sajeeth@gmail.com josephjames253@gmail.com josekjoyes101@gmail.com niji@vjcet.org

Abstract - This report compares the area, delay, II. TYPES OF ADDERS
complexity (in terms of gate count), and the power
A. Ripple Carry Adder
consumption of various 16-bit serial and parallel
The simplest form of adder is the ripple-carry
adders. The adders that were chosen to be studied
adder[2]. An n-bit ripple carry adder consists of n one-bit
includes serial adders like Ripple Carry Adder, Carry
full adders connected in succession. The carry "ripples"
Look-Ahead Adder, and Carry Select Adder, and
from the least significant bit to the most significant bit and
parallel prefix adders like Kogge-Stone, Brent-Kung,
hence it gets its name. Since, the carry in at any stage
Ladner-Fischer, and Han-Carlson. The adders were
depends on the carry out from the previous stage, the
designed using the Verilog hardware description
delay of ripple carry adders is O(N) and increases linearly
language and then simulated, synthesised, and
as the size of the operand is increased. Thus it is essential
virtually implemented using the Xilinx Vivado Design
to look for other alternatives.
Suite. The performance comparision of the adders was
done in Cadence SoC Encounter and all the adders
were virtually implemented on the ZedBoard Zynq
Evaluation and Development Board.
Keywords - Ripple Carry Adder, Carry Look-
Ahead Adder, Carry Select Adder, Kogge-Stone
Adder, Brent-Kung Adder, Ladner-Fischer Adder,
Han-Carlson Adder Fig 1. 4-bit Ripple Carry Adder

I. INTRODUCTION B. Carry Select Adder

Adders play an important role in almost all digital
systems[1], and the choice of adder changes from one
design to another based on a few performance parameters
such as
Power Consumption
Power Dissipation
Speed of Operation
Area Occupied
Circuit Complexity
Cost etc.
Since a single adder is not able to exhibit all of the
above mentioned parameters, certain adders usurp others,
based on the requirement of the user. Adders have become
a requisite component in most cognitive systems. Usage of
adders in any circuit, reduces the number of transistors
used. Digital adders are mostly used in a computer's ALU
to compute addition. Digital calculators use adders for
arithmetic addition. Microcontrollers use adders in
program counters, timers, etc. Every device that uses some
kind of increment, decrement, or arithmetic process
contains adders.
Carry select adders consists of two ripple carry
adders and a multiplexer. Addition of two n-bit numbers is
done with two adders: one time with the assumption that
the carry in is zero, and the other assuming that the carry
is one[3]. After the two results are calculated, the correct
sum and the correct carry is selected with the multiplexer
once the correct carry of previous stage is known. The
number of bits in each carry select block can be uniform,
or variable. In the uniform case, the optimal delay occurs
for a block size of √N, where N is the size of the operands.
The carry select adders are simple, but rather fast
compared to the ripple carry adders having a delay of
O (√N).
C. Carry Look-Ahead Adder
The higher delay in the case of ripple carry adders is
due to the carry chain[4]. In carry look-ahead adders, the
carry signals are calculated in advance, based on the input
signals. For any bit position i, a carry will be generated if
the corresponding input bits are ‘1’ or if the carry-in to
that bit was a ‘1’ and at least one of the input bits is ‘1’.
From this, a recurrence relation is derived that expresses
carry in to any bit position in terms of the relevant addend
and augend digits and some lower-adder carry. This can
result in considerable gain in speed.
Fig 2. 4-bit Carry Select Adder
Fig 3. 4-bit Carry Look-Ahead Adder
D. Kogge-Stone Adder
Kogge-Stone[5] uses a technique called recursive
doubling in an algorithm for solving a large class of
recurrence problems on parallel computers. Recursive
doubling involves the splitting of the computation of a
function into two equally complex sub functions whose
evaluation can be performed simultaneously. The Kogge-
Stone adder has log 2N stages and a fanout of 2 at each
stage. This comes at the cost of many long wires that must
be routed between stages.
Fig 4. 16-bit Kogge-Stone Adder
E. Brent-Kung Adder
Brent-Kung[6] is a simple parallel adder with regular
design. It takes into account the problem of connecting the
gates in an economical and regular way to minimize chip
area and design costs along with delay and complexity. It
uses the same idea as Ladner-Fischer but is not directly
applicable because they ignored fan-out restriction. Brent-
Kung assumes existence of gates that compute a logical
function of two inputs in constant time and an output
signal can be divided into two signals in constant time.
Fig 5. 16-bit Brent-Kung Adder
F. Ladner-Fischer Adder
Ladner-Fischer[7] provides a general method for
deriving efficient parallel solutions to the fixed-length
version of any problem solved by a finite state transducer.
The Ladner-Fischer adder computes prefixes for the odd
numbered bits and uses one more stage to ripple into the
even positions. Cells at high-fanout nodes must still be
sized or ganged appropriately to achieve good speed.
Fig 6. 16-bit Ladner-Fischer Adder
G. Han-Carlson Adder
Han-Carlson[8] is a new graph representation for
prefix computation that leads to the design of a fast, area-
efficient binary adder. The new graph is a combination of
Brent-Kung and Kogge-Stone for prefix computation, and
its area is close to known lower bounds on the VLSI area
of parallel prefix graphs. HanCarlson adders perform
Kogge-Stone on the odd numbered bits, and then use one
more stage to ripple into the even positions. They claim it
to be the fastest possible area-efficient VLSI adder.
 Fig 9. Synthesis Result of Ripple Carry Adder

Fig 7. 16-bit Han-Carlson Adder

III. SYNTHESIS AND SIMULATION RESULTS

This section deals with the synthesis and simulation

results of each of the adders mentioned in Section II.
Synthesis and simulation were both done on the Xilinx
Vivado Design Suite software. Two testbenches were
considered for all the adders to check the design code and
obtain the simulation results. The testbenches used were,
a = 1010 1010 1010 1010
b = 1111 0000 1111 0000
cin = 0
a = 1010 1010 1010 1010
b = 1111 0000 1111 0000
cin = 1
The expected results for testbench case 1 were,
sum = 1001 1011 1001 1010
cout = 1
The expected results for testbench case 2 were, Fig 10. Synthesis Result of Carry Select Adder
sum = 1001 1011 1001 1011
cout = 1
The simulation results are shown in Fig. 8. After
successful simulation of the designs, they were
synthesised onto the ZedBoard Zynq Development and
Evaluation Board. The synthesis results are shown in
Figs. 9, 10, 11, 12, 13, 14, 15.

Fig 11. Synthesis Result of Carry Look-Ahead Adder

Fig 8. Simulation Results

 IV. PERFORMANCE ANALYSIS RESULTS
This section deals with the performance analysis
results of the various adders mentioned in Section II.
Performance analysis of the adders was done using
Cadence SoC Encounter software. The result of the
performance analysis is shown in Tables I, II, III, IV.

TABLE I
PRE- & POST-APR DELAY COMPARISION

Fig 12. Synthesis Result of Kogge-Stone Adder TABLE II

GATE COUNT COMPARISION

TABLE III
AREA OF LAYOUT COMPARISION

Fig 13. Synthesis Result of Brent-Kung Adder

TABLE IV
POWER CONSUMPTION COMPARISION

Fig 14. Synthesis Result of Ladner-Fischer Adder

Fig 15. Synthesis Result of Han-Carlson Adder

 V. CONCLUSIONS
Among all the adders studied, the ripple carry adder
was found to have the highest delay and the lowest gate
count, which is to be expected as the ripple carry adder is
the simplest form of an adder. The delay of the carry
select adder and the carry look-ahead adder was found to
be considerably lower than that of the ripple carry adder.
This is to be expected as both these adders are upgrades
made upon the simple ripple carry adder. However, both
these adders have more complex circuits since it uses two
blocks of ripple carry adders to perform addition and they
also have a multiplexer to choose the correct sum and
carry. Parallel-prefix adders were found to have
significantly lower delays than their serial adder
counterparts. Among the parallel adders, the Kogge-Stone
adder was found to have the least delay. However, the
Kogge-Stone adder occupies the most area and also has
the highest complexity amongst the parallel adders. This is
to be expected as the Kogge-Stone adder has the most
parallel prefix operations. The Brent-Kung adder occupies
the least area because it has very few parallel prefix
operations, however, it is found to have the worst delay
amongst the parallel adders, as it has the most
computation stages. The Han-Carlson and Ladner-Fischer
adders have delays and areas between that of the Kogge-
Stone and Brent-Kung adders. The delay of Han-Carlson
and Ladner-Fischer adders is almost the same even though
the Han-Carlson adder has an extra computational stage.
The area occupied by the Han-Carlson adder is slightly
less than the Ladner-Fischer adder.
As a result, we can conclude that, the Kogge-Stone
adder should be used if delay needs to be minimised with
no constraint on area. The Brent-Kung adder should be
used if area needs to be minimised but some delay is
tolerable. If delay and area both needs to be optimised,
then the Han-Carlson adder needs to be used. These
results support the statement that the Han-Carlson adder is
the fastest possible area efficient adder.
REFERENCES
[1] ‘Digital Design : Principles and Practices’, John F. Walkerly,
Third Edition, Published by Pearson Education, 2003
[2] ‘Ripple Carry Adder Design Using Universal Logic Gates’,
Patel Chandrahash and C.S. Veena, Department of ECE,
Technocrats Institute of Technology, Bhopal, MP INDIA,
Research Journal of Engineering Sciences, Vol. 3(11), 1-5,
November (2014), ISSN 2278 – 9472
[3] ‘Design of High-Speed Ladner-Fischer Based Carry Select
Adder’, Pakkiraiah Chakali, Madhu Kumar Patnala,
International Journal of Soft Computing and Engineering
(IJSCE), ISSN: 2231-2307, Volume-3, Issue-1, March 2013
[4] ‘Area Efficient Design Analysis of Carry-Look Ahead
Adder’, Anku Bala, Rajesh Mehra, International Journal of
Computer Applications (0975 – 8887), Volume 119 – No.20,
June 2015
[6] P. M. Kogge and H. S. Stone, “A Parallel Algorithm for the
Efficient Solution of a General Class of Recurrence
Equations,” IEEE Transactions on Computers, Vol. C-22,
No. 8, pp. 783-791, August 1973
[7] R. P. Brent and H. T. Kung, “A Regular Layout for Parallel
Adders,” IEEE Transactions on Computers, Vol. C-31, No.
3, March 1982
[8] R. E. Lardner and M. J. Fischer, “Parallel Prefix
Computation,” Journal of the ACM, Vol. 27, No. 4, pp. 831-
838, October 1980
[9] T. Han and D.A. Carlson, “Fast Area-Efficient VLSI
Adders,” 1987 IEEE 8th Symposium on Computer
Arithmetic, pp.49-56, May 1987
Niji Mathews was born in Kerala,
India. She obtained her Bachelor
of Technology (BTech) from
Cochin University in 2004. She
did her post-graduation from Anna
University, Coimbatore in 2010.
Currently, she is working as Asst. Professor,
Department of Electronics and Communication
Engineering, Viswajyothi College of Engineering
and Technology, Vazhakulam, India. Her special
fields of interest include VLSI and image
processing.
Rahul Sajeeth Mohan was born
in Dubai, UAE. He is currently
doing his Bachelor of Technology
(BTech) in Electronics &
Communications Engineering at
Viswajyothi College of Engin-
eering and Technology, Vazhakulam, India.
 Joseph James was born in
Kerala, India. He is currently
doing his Bachelor of Technology
(BTech) in Electronics &
Communications Engineering at
Viswajyothi College of Engin-
eering and Technology, Vazhakulam, India.

Jose K Joyes was born in Kerala,

India. He is currently doing his
Bachelor of Technology (BTech)
in Electronics & Communications
Engineering at Viswajyothi
College of Engineering &
Tec- India.
hnology, Vazhakulam,