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A0 6V10bit1MS Smonoto Tabilizerin0 13
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A 0.6 v 10 bit 1 MS/s monotonic switching SAR ADC with common mode
stabilizer in 0.13 μm CMOS
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A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer
in 0.13 m CMOS
Lü Wei(吕伟)1 , Luo Duona(罗多纳)1 , Mei Fengcheng(梅逢城)1 , Yang Jiaqi(杨家琪)1 ,
Yao Libin(姚立斌)2 , He Lin(贺林)1; , and Lin Fujiang(林福江)1
1 Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China
2 Kunming Institute of Physics, Kunming 650223, China
Abstract: This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to
the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and
power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the
associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional
constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode
stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified
through both simulation and measurement results. Fabricated with 1P8M 0.13 m CMOS technology, the proposed
SAR ADC consumes 6.3 W at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency
and FOM of 21 fJ/conversion-step. The core area is only 120 300 m2 .
Key words: SAR ADC; monotonic switching; common mode stabilizer; comparator offset
DOI: 10.1088/1674-4926/35/5/055006 EEACC: 2570
* Project supported by the National Natural Science Foundation of China (No. 61204033) and the Natural Science Foundation of Jiangsu
Province (No. BK2012214).
† Corresponding author. Email: helin77@ustc.edu.cn
Received 21 October 2013, revised manuscript received 5 November 2013 © 2014 Chinese Institute of Electronics
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Fig. 1. Block diagram of SAR ADC based on monotonic switching (MS) scheme.
turned on and all the bottom plates are reset to VDD . Since 2.3. Architecture of the proposed SAR ADC
the S/H switches turn off, the signal is sampled on the DAC,
Figure 3 shows the block diagram of the proposed SAR
and the conversion begins. At first, the comparator directly
ADC, which adds an additional CMS circuit to the existing MS
performs the first comparison without switching any capaci-
SAR ADC to stabilize the input CM of the dynamic amplifier.
tor. Then one of the MSB capacitors is switched from VDD to
The CMS circuit is actually a binary weighted capacitive array
ground, while the other one remains unchanged, according to
sharing the same top plates with the MS DAC. Each unit of the
the comparison result. This procedure is repeated until the LSB
CMS circuit contains two identical capacitors whose bottom
is resolved.
plates will experience a transition from VSS to VDD to compen-
Figure 2 shows the waveform of the MS procedure. After
sate for the CM drop of the MS DAC. The size of capacitors in
the comparison, only one side of the DAC is switched while the
the CMS array is half of their corresponding capacitors in the
other side stays unchanged, which causes not only a differential
MS DAC. The VSS to VDD transition is implemented by an OR
change of the DAC output, but also a gradual decreasing in
gate whose inputs are 1P–4P and 1N–4N, the control signals
the CM from 0.5VDD to VSS . This large CM shift leads to a
of the DAC. Since most of the CM variation happens around
significant variation of the offset in the dynamic comparator,
the MSB, only four bits of CMS are applied. The CM varia-
which is the main source of integral nonlinearity (INL) of the
tion after the fourth bit will cause negligible error in the ADC
SAR ADCŒ11 .
output. Figure 4 shows the first four bit-cycles waveform of
MS DAC with CMS applied. During the i th comparison, the
2.2. Common mode-dependent offset of the comparator
voltage swing on each side of the DAC is given by
In the MS structure, the offset variation in the comparator
degrades the performance of the ADC. Assume that the offset 2n i 1
Cu 2n i 2
Cu
voltage of the comparator is dominated by the preamplifier, VPi D Bi VDD C VDD ; (2)
CT CT
whose offset voltage can be expressed asŒ12
VGS VTH S R 2n i 1
Cu 2n i 2
Cu
Vos D VTH C C ; (1) VNi D .Bi 1/ VDD C VDD ; (3)
2 S R CT CT
where VTH is the threshold voltage mismatch of the input pair, where VPi and VNi are the i th voltage swing on the positive
S=S is the size mismatch of the input pair, and R=R is the and negative side of the DAC, Cu is the unit capacitance, CT
resistance mismatch of the loading pair. From Eq. (1), we can is the total capacitance of the DAC, and Bi is the ith compar-
find that the offset voltage is related to the device mismatches ison result. The first and second terms in Eq. (2) represent the
and bias conditions. The first term in Eq. (1) is a static error contributions from the MS network and the CMS network, re-
which does not affect the performance of the ADC. The second spectively. No matter what Bi is, the summation of VPi and
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J. Semicond. 2014, 35(5) Lü Wei et al.
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J. Semicond. 2014, 35(5) Lü Wei et al.
Fig. 9. Simulation results of (a) DNL and (b) INL with CMS.
Fig. 11. Measured (a) DNL and (b) INL of the proposed SAR ADC.
FFT of the ADC output for fin D 40.039 kHz and 489.2578
kHz at 1 MS/s. Figure 13 plots the measured SNDR and SFDR
versus the input frequency at 1 MS/s. At low input frequency,
the measured SNDR, SFDR and ENOB are 52.6 dB, 67.95
dB and 8.44 bit respectively. At near Nyquist frequency, the
SNDR and SFDR drop by 1.35 dB (loss of 0.22 bit ENOB)
and 1.5 dB, respectively. Figure 13 also shows the measure-
ment results of SNDR/SFDR against the sampling frequency
with the Nyquist rate input. The ENOB degradation is mainly
caused by the noise from the dynamic comparator.
The total power consumption of the SAR ADC is 6.3 W
at 0.6 V and 1 MS/s sampling rate. The analog power, including
the capacitive DAC array, CMS circuit is 2.1 W. The digital
Fig. 10. Die photograph of the proposed SAR ADC.
power, including clock generator and output register is 2.3 W.
The power of the comparator is 1.9 W. The proposed ADC
achieves 21 fJ/conversion-step at the Nyquist frequency with
4. Measurement results
1 MS/s.
The proposed ADC was fabricated using the 1P8M 0.13- The performance of the proposed SAR ADC is summa-
m CMOS process. A die photograph of the chip is shown rized in Table 2, and compared with several recently published
in Fig. 10. The chip was directly mounted on a printed circuit SAR ADCs. The proposed ADC achieved a comparable per-
board. The analog input signal and clock are both provided by formance to the published 0.6 V designs. The speed advantage
an Agilent 33250A function arbitrary waveform generator. The of our design over the time-domain comparator based approach
digital outputs of the proposed ADC are captured by an Agi- can also be clearly seen.
lent 1681A logic analyzer and processed using Matlab to obtain
their static and dynamic performance. 5. Conclusion
Figure 11 shows the measured DNL and INL. The
measured peak DNL and INL are 0:91/C1:58 LSB and This paper presents a 0.6 V 10 bit monotonic switching
1:15/C1:99 LSB, respectively. Figure 12 shows 16384 point SAR ADC with a novel common mode stabilizer to address
055006-5
J. Semicond. 2014, 35(5) Lü Wei et al.
Fig. 12. 16384 points of FFT spectrum at (a) fin D 40.039 kHz and (b) 489.2578 kHz.
Fig. 13. Measured (a) dynamic performance versus input frequency at 1 MS/s, (b) dynamic performance versus sampling frequency with Nyquist
rate input.
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J. Semicond. 2014, 35(5) Lü Wei et al.
[2] Verma N, Chandrakasan A P. An ultra low energy 12-bit rate- free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits,
resolution scalable SAR ADC for wireless sensor nodes. IEEE J 2010, 45(5): 1111
Solid-State Circuits, 2007, 42(6): 1196 [10] Ginsburg B P, Chandrakasan A P. An energy-efficient charge
[3] Yip M, Chandrakasan A P. A resolution-reconfigurable 5-to-10- recycling approach for a SAR converter with capacitive DAC.
bit 0.4-to-1 V power scalable SAR ADC for sensor applications. IEEE Int Symp Circuits and Systems (ISCAS), 2005: 184
IEEE J Solid-State Circuits, 2013, 48(6): 1453 [11] Liu C C, Chang S J, Huang G Y, et al. A 0.92 mW 10-bit 50-MS/s
[4] Harpe P, Dolmans G, Philips K, et al. A 0.7 V 7-to-10 bit 0- SAR ADC in 0.13 m CMOS process. Symposium on VLSI Cir-
to-2 MS/s flexible SAR ADC for ultra low-power wireless sen- cuits Digest of Technical Papers, 2009: 236
sor nodes. IEEE European Solid-State Circuits Conference (ES- [12] Razavi B. Design of analog CMOS integrated circuits. New York:
SCIRC), 2012: 373 McGraw-Hill, Inc, 2000
[5] Shikata A, Sekimoto R, Kuroda T, et al. A 0.5 V 1.1 MS/sec 6.3 [13] Schinkel D, Mensink E, Klumperink E, et al. A double-tail latch-
fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm type voltage sense amplifier with 18 ps Setup+Hold time. IEEE
CMOS. IEEE J Solid-State Circuits, 2012, 47(4): 1022 International Solid-State Circuits Conference Digest of Technical
[6] Lee S K, Park S J, Park H J, et al. A 1.3 W 0.6 V 8.7-ENOB Papers (ISSCC), 2007: 314
successive approximation ADC in a 0.18 m CMOS. Sympo- [14] Chen S M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asyn-
sium on VLSI Circuits Digest of Technical Papers, 2009: 242 chronous ADC in 0.13-m CMOS. IEEE J Solid-State Circuits,
[7] Lin G Y, Huang H Y, Hsieh C C, et al. A 0.05 mm2 0.6 V 500 kS/s 2006, 41(12): 2669
14.3 fJ/Conversion-step 11-bit two-step switching SAR ADC for [15] Promitzer G. 12-bit low-power fully differential noncalibrating
3-dimensional stacking CMOS imager. IEEE Asian Solid-State successive approximation ADC with 1 MS/s. IEEE J Solid-State
Circuits Conference (ASSCC), 2012: 165 Circuits, 2001, 36(7): 1138
[8] Liu C C, Chang S J, Huang G Y, et al. A 10-bit 50-MS/s SAR [16] Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8
ADC with a monotonic capacitor switching procedure. IEEE J W 100 kS/s SAR ADC with time-domain comparator. IEEE
Solid-State Circuits, 2010, 45(4): 731 International Solid-State Circuits Conference Digest of Technical
[9] Zhu Y, Chan C H, Chio U F, et al. A 10-bit 100-MS/s reference- Papers (ISSCC), 2008: 246
055006-7
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