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  • CH 07 Yc 1

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    RUBEN DARIO Sandoval
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    The document shows a block diagram of the luminance and chrominance signal paths in record and playback modes. In record mode, video signals enter from the front video input or tuner and are processed by chips JK4951 and JK3002 before being output. In playback mode, video signals enter the P4951 chip from memory and are processed by chips P3001, Q3009, and P4951 before being output.

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    The document shows a block diagram of the luminance and chrominance signal paths in record and playback modes. In record mode, video signals enter from the front video input or tuner and are processed by chips JK4951 and JK3002 before being output. In playback mode, video signals enter the P4951 chip from memory and are processed by chips P3001, Q3009, and P4951 before being output.

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    © All Rights Reserved
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    11 views1 page

    CH 07 Yc 1

    Uploaded by

    RUBEN DARIO Sandoval
    The document shows a block diagram of the luminance and chrominance signal paths in record and playback modes. In record mode, video signals enter from the front video input or tuner and are processed by chips JK4951 and JK3002 before being output. In playback mode, video signals enter the P4951 chip from memory and are processed by chips P3001, Q3009, and P4951 before being output.

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    of 1

    MAIN SIGNAL PATH IN REC MODE MAIN SIGNAL PATH IN PLAYBACK MODE

    JK4951

    P4951 P3001
    4 FRONT VIDEO IN
    5 1

    TUNER VIDEO
    TO/FROM
    TUNER
    RFC VIDEO OUT

    JK3002

    4 VIDEO IN

    8 VIDEO OUT

    TO/FROM VIDEO OUT Q3009


    SYSTEM
    CONTROL Y/C VIDEO OUT

    FROM
    SYSTEM ART V/H/N
    CONTROL

    NV-FJ630PM/PMP/ARU
    LUMINANCE & CHROMINANCE BLOCK DIAGRAM

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