PS1U5005 Dig Video

Subject: DIGITAL VIDEO OUTPUT PROTOCOLFOR COMPACT EYE ENGINE.
Doc. No. PS1U5005

Revision: See Revisions Page
Name Signature Date
Written Yaron Shamay Oct 2010
Revised Nimrod Streit Oct 2009
This document discloses data in which Opgal Inc. has proprietary rights. Neither the furnishing,
receipt, nor possession thereof confers upon or transfers any right to reproduce or disclose the
document, any part thereof, or any information therein except by written permission from, or
written agreement with, Opgal Inc.
OPGAL Proprietary
Commercial Confidential
Doc. Name: Doc. No. Revision:
Digital video outputs protocol for COMPACT EYE PS1U5005 A
engine.
Updates
Authorization's
Rev Change Description Authorization Date
Name
R01 YARON SHAMAY 5/10/2010
P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
Web site: www.opgal.com
OPGAL Proprietary
engine.
1. Electrical Pinout
Pin Number 1 OPGAL P/N: 800088LF

Manufacturer : HIROSE
P/N: DF20F-30DP-1V (59)
Pin # Signal Name Type I/O Signal Type Comment

1. TCK JTAG Out TTL 3.3v
2. Rx_out Communication In TTL 3.3v
3. TMS JTAG Out TTL 3.3v

TTL 3.3v
4. Tx_out Communication Out
TTL 3.3v
5. TDI JTAG Out

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
6. LVDS1P Digital Video Out LVDS 2.5V

7. TDO JTAG In TTL 3.3v
8. LVDS1N Digital Video Out LVDS 2.5V
9. DGND Power Out Power Output digital ground
for JTAG or discrete
only!
11. 3_3OUT Power Power Output 3.3 Volt
digital for JTAG or
discrete only!
13. DISCRETE 1 Discrete In TTL 3.3v See paragraph 5.3
15. DISCRETE 2 Discrete In TTL 3.3v See paragraph 5.3
17. DISCRETE3 Discrete In TTL 3.3v See paragraph 5.3
23. N.C.
25. DGND Power Out Power Output digital ground
for JTAG or discrete
only!
26. Vin Power In Power See paragraph 4.1
27. GNDin Power In Power
28. Vin Power In Power See paragraph 4.1
29. GNDin Power In Power
30. SHIELD Power

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
Digital video output's options:

a. RAW DATA – This output sent straight from the detector, before the
processing phase, and includes the detector's control pixels.
b. NUC & BPR – This output produced during the processing phase, after the
"Time domain filter", the "Nun-uniform correction" and the "Bad pixels
replacement" phases
c. PROCESSED – This output produced after the processing phase.

The digital video timing for each phase is illustrated in Error! Reference
source not found. Error! Reference source not found..
• The video timing were tested on compact FPGA v4.15
Digital video timing format :
Function Document Digital Number Number of pixels / Frames ( HZ )

Description format of bits lines
paragraph
RS-170 CCIR RS-170 CCIR RS-170 CCIR
Row 3a 4a LVDS 14
USB 14
NUC & 3b 4b LVDS 14 320 / 240 384 / 288 60 50

BPR
USB 14
Process 3c 4c LVDS 8
video
USB 8

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
2. RS170
In the RS170 video format, the pixel clock cycle is 20 MHz.
a) RAW DATA.
- The VD output show the field which consists of 240 lines during the high state, and
0 lines during the low state.
- The VD is pulsed low for 46.68 us. (See Time #1, Time #2 below)
- Each field period is 16.7 ms. (See Time #4)
- Each line is marked by one HD which contains valid 320 pixels. (See Time #5, #8)
- Each line takes 63.6 µs, including the 47.6 µs gap. (See Time #6 and #7)
Time 1 VD
Time 2 46.68us
Time 3
240lines
Time 4 16.7ms
Time 5 Valid
Time 6
47.6 us
Time 7 63.6us
Time 8 320Pixs
Figure 1 Timing diagram of Raw Data option, RS170 format

OPGAL Proprietary
Digital video outputs protocol for COMPACT EYE PS1F5005 A
engine.
b) NUC & BPR.

- The pixel clock cycle is 20 MHz.
- The timing for the NUC and BPR option in the RS170 format is given in Figure 2
below.
0 lines during the low state.
- The VD is pulsed low for 80 us. (See Time #1, Time #2 in figure 2 below)
- Each field period is 16. 7 ms. (See Time #3)
- Each line is marked by one HD which contains 320 valid pixels. (See Time #4 and
#7 below)
- Each line takes 63.6 µs, including the 47.6 µs gap. (See Time #5 and #6)
Time 1
VD
Time 2
80us
240lines
Time 3
16.7ms
Time 4
Valid
Time 5
47.6us
Time 6 63.6us
Time 7 320Pixs
Figure 2 Timing diagram of NUC & BPR option, RS170 format

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
c) PROCESSED VIDEO.
- The timing for the processed video option in the RS170 format is given in Figure 3
below.
- The VD output show the field which consists of 240 lines during the high state.
- The VD is pulsed low for 750 us. (See Time #2)
- Each field period is 16.7 ms. (See Time #4)
- Each line is marked by one HD which contains 320 pixels. (See Time #5, #8)
- Each line takes 63.6 µs to process, including the 47.6 µs gap. (See Time #6, #7)
Figure 3 Timing diagram of Processed option, RS170 format

Time 1
VD
Time 2
750us
Time 3
240lines
Time 4
16.7ms
Time 5
Valid
Time 6 47 .6us
63.6us
Time 7
Time 8 320Pixs

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
3. CCIR
In the CCIR format the pixel clock cycle is 5.9 MHz.
a) RAW DATA.
- The timing for the raw data option in the CCIR format is given in Figure 4 below.
0 lines during the low state (See Time #1, #4).
- The VD is pulsed low for 0.1 ms. (See Time #1, #2)
- Each field period is 20 ms. (See Time #3)
- Each line is marked by an HD which contains 384 pixels. (See Time #5, #8)
- Each line takes 68.2 µs, including the 49 µs gap. (See Time #6 and #7)
Time 1
Time 2
Time 3
Time 4
Time 5
Time 6
Time 7
Time 8
Figure 4 Timing diagram of Raw Data option, CCIR format

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
b) NUC & BPR.

- The timing for the processed video option in the CCIR format is given in Figure 5
below.
0 lines during the low state. (See Time #1)
- The VD is pulsed low for 0.1 ms. (See Time #1,#2)
- Each field period is 20 ms. (See Time #2, #3)
- Each line is marked by one HD which contains 384 pixels. (See Time #7)
- Each line takes 68.2 µs, including the 49 µs gap. (See Time #5 and #6)
Time 1
Time 2
Time 3
Time 4
Time 5
Time 6
Time 7
Figure 5 Timing diagram of NUC & BPR option, CCIR format

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
c) PROCESSED VIDEO.
- The timing for the processed video option in the CCIR format is given in Figure 6
below.
- The VD output show the field which consists of 288 lines during the high state.
Each line is marked by one HD each. (See Time #1, #4)
- The VD is pulsed low for 1 ms. (See Time #2)
- Each field period is 20 ms. (See Time #3)
- Each line is marked by one HD which contains 384 pixels. (See Time #5, #8)
- Each line takes 64 µs, including the 44.8 µs gap. (See Time #6, #7)
Time 1
VD
Time 2 1ms
Time 3
20ms
Time 4 288lines
Time 5 Valid
Time 6 44.8us
Time 7
64us
Time 8 384 Pixls
Figure 6 Timing diagram of Processed option, CCIR format

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
Camera Link protocol

LVDS based Video data serializer protocol.
In the current work mode, it Works in 20MHz parallel data rate and in 140MHz serialized
data rate.
Inputs Bit Assignment
Ports B6-C7- are not used in the current work mode.

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900
OPGAL Proprietary
engine.
Bits Serialization Order

Tel: 972-4-9953903 / 975 Fax: 972-4-9953900

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Subject: DIGITAL VIDEO OUTPUT PROTOCOLFOR COMPACT EYE ENGINE.

Doc. No. PS1U5005

Name Signature Date

Written Yaron Shamay Oct 2010

Revised Nimrod Streit Oct 2009

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Pin Number 1 OPGAL P/N: 800088LF

Pin # Signal Name Type I/O Signal Type Comment

3. TMS JTAG Out TTL 3.3v

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

6. LVDS1P Digital Video Out LVDS 2.5V

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Digital video output's options:

c. PROCESSED – This output produced after the processing phase.

• The video timing were tested on compact FPGA v4.15

Digital video timing format :

Function Document Digital Number Number of pixels / Frames ( HZ )

RS-170 CCIR RS-170 CCIR RS-170 CCIR

NUC & 3b 4b LVDS 14 320 / 240 384 / 288 60 50

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Figure 1 Timing diagram of Raw Data option, RS170 format

b) NUC & BPR.

Figure 2 Timing diagram of NUC & BPR option, RS170 format

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Figure 3 Timing diagram of Processed option, RS170 format

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Figure 4 Timing diagram of Raw Data option, CCIR format

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

b) NUC & BPR.

Figure 5 Timing diagram of NUC & BPR option, CCIR format

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Figure 6 Timing diagram of Processed option, CCIR format

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Camera Link protocol

Inputs Bit Assignment

Ports B6-C7- are not used in the current work mode.

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

Bits Serialization Order

P.O. Box 462, Industrial Area 5, Carmiel 20101, ISRAEL

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